2 * sleep.c - x86-specific ACPI sleep support.
4 * Copyright (C) 2001-2003 Patrick Mochel
5 * Copyright (C) 2001-2003 Pavel Machek <pavel@ucw.cz>
8 #include <linux/acpi.h>
9 #include <linux/bootmem.h>
10 #include <linux/memblock.h>
11 #include <linux/dmi.h>
12 #include <linux/cpumask.h>
13 #include <asm/segment.h>
15 #include <asm/pgtable.h>
16 #include <asm/cacheflush.h>
17 #include <asm/realmode.h>
19 #include "../../realmode/rm/wakeup.h"
22 unsigned long acpi_realmode_flags
;
24 #if defined(CONFIG_SMP) && defined(CONFIG_64BIT)
25 static char temp_stack
[4096];
29 * x86_acpi_suspend_lowlevel - save kernel state
31 * Create an identity mapped page table and copy the wakeup routine to
34 int x86_acpi_suspend_lowlevel(void)
36 struct wakeup_header
*header
=
37 (struct wakeup_header
*) __va(real_mode_header
->wakeup_header
);
39 if (header
->signature
!= WAKEUP_HEADER_SIGNATURE
) {
40 printk(KERN_ERR
"wakeup header does not match\n");
44 header
->video_mode
= saved_video_mode
;
46 header
->pmode_behavior
= 0;
49 native_store_gdt((struct desc_ptr
*)&header
->pmode_gdt
);
52 * We have to check that we can write back the value, and not
53 * just read it. At least on 90 nm Pentium M (Family 6, Model
54 * 13), reading an invalid MSR is not guaranteed to trap, see
55 * Erratum X4 in "Intel Pentium M Processor on 90 nm Process
56 * with 2-MB L2 Cache and IntelĀ® Processor A100 and A110 on 90
57 * nm process with 512-KB L2 Cache Specification Update".
59 if (!rdmsr_safe(MSR_EFER
,
60 &header
->pmode_efer_low
,
61 &header
->pmode_efer_high
) &&
63 header
->pmode_efer_low
,
64 header
->pmode_efer_high
))
65 header
->pmode_behavior
|= (1 << WAKEUP_BEHAVIOR_RESTORE_EFER
);
66 #endif /* !CONFIG_64BIT */
68 header
->pmode_cr0
= read_cr0();
69 if (__this_cpu_read(cpu_info
.cpuid_level
) >= 0) {
70 header
->pmode_cr4
= read_cr4();
71 header
->pmode_behavior
|= (1 << WAKEUP_BEHAVIOR_RESTORE_CR4
);
73 if (!rdmsr_safe(MSR_IA32_MISC_ENABLE
,
74 &header
->pmode_misc_en_low
,
75 &header
->pmode_misc_en_high
) &&
76 !wrmsr_safe(MSR_IA32_MISC_ENABLE
,
77 header
->pmode_misc_en_low
,
78 header
->pmode_misc_en_high
))
79 header
->pmode_behavior
|=
80 (1 << WAKEUP_BEHAVIOR_RESTORE_MISC_ENABLE
);
81 header
->realmode_flags
= acpi_realmode_flags
;
82 header
->real_magic
= 0x12345678;
85 header
->pmode_entry
= (u32
)&wakeup_pmode_return
;
86 header
->pmode_cr3
= (u32
)__pa_symbol(initial_page_table
);
87 saved_magic
= 0x12345678;
88 #else /* CONFIG_64BIT */
90 stack_start
= (unsigned long)temp_stack
+ sizeof(temp_stack
);
91 early_gdt_descr
.address
=
92 (unsigned long)get_cpu_gdt_table(smp_processor_id());
93 initial_gs
= per_cpu_offset(smp_processor_id());
95 initial_code
= (unsigned long)wakeup_long64
;
96 saved_magic
= 0x123456789abcdef0L
;
97 #endif /* CONFIG_64BIT */
99 do_suspend_lowlevel();
103 static int __init
acpi_sleep_setup(char *str
)
105 while ((str
!= NULL
) && (*str
!= '\0')) {
106 if (strncmp(str
, "s3_bios", 7) == 0)
107 acpi_realmode_flags
|= 1;
108 if (strncmp(str
, "s3_mode", 7) == 0)
109 acpi_realmode_flags
|= 2;
110 if (strncmp(str
, "s3_beep", 7) == 0)
111 acpi_realmode_flags
|= 4;
112 #ifdef CONFIG_HIBERNATION
113 if (strncmp(str
, "s4_nohwsig", 10) == 0)
114 acpi_no_s4_hw_signature();
116 if (strncmp(str
, "nonvs", 5) == 0)
118 if (strncmp(str
, "nonvs_s3", 8) == 0)
119 acpi_nvs_nosave_s3();
120 if (strncmp(str
, "old_ordering", 12) == 0)
121 acpi_old_suspend_ordering();
122 str
= strchr(str
, ',');
124 str
+= strspn(str
, ", \t");
129 __setup("acpi_sleep=", acpi_sleep_setup
);