arch/x86/kernel/cpu/perf_event.h

   1 /*
   2  * Performance events x86 architecture header
   3  *
   4  *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
   5  *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
   6  *  Copyright (C) 2009 Jaswinder Singh Rajput
   7  *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
   8  *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
   9  *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
  10  *  Copyright (C) 2009 Google, Inc., Stephane Eranian
  11  *
  12  *  For licencing details see kernel-base/COPYING
  13  */
  14
  15 #include <linux/perf_event.h>
  16
  17 #if 0
  18 #undef wrmsrl
  19 #define wrmsrl(msr, val)                                                \
  20 do {                                                                    \
  21         unsigned int _msr = (msr);                                      \
  22         u64 _val = (val);                                               \
  23         trace_printk("wrmsrl(%x, %Lx)\n", (unsigned int)(_msr),         \
  24                         (unsigned long long)(_val));                    \
  25         native_write_msr((_msr), (u32)(_val), (u32)(_val >> 32));       \
  26 } while (0)
  27 #endif
  28
  29 /*
  30  *          |   NHM/WSM    |      SNB     |
  31  * register -------------------------------
  32  *          |  HT  | no HT |  HT  | no HT |
  33  *-----------------------------------------
  34  * offcore  | core | core  | cpu  | core  |
  35  * lbr_sel  | core | core  | cpu  | core  |
  36  * ld_lat   | cpu  | core  | cpu  | core  |
  37  *-----------------------------------------
  38  *
  39  * Given that there is a small number of shared regs,
  40  * we can pre-allocate their slot in the per-cpu
  41  * per-core reg tables.
  42  */
  43 enum extra_reg_type {
  44         EXTRA_REG_NONE  = -1,   /* not used */
  45
  46         EXTRA_REG_RSP_0 = 0,    /* offcore_response_0 */
  47         EXTRA_REG_RSP_1 = 1,    /* offcore_response_1 */
  48         EXTRA_REG_LBR   = 2,    /* lbr_select */
  49         EXTRA_REG_LDLAT = 3,    /* ld_lat_threshold */
  50
  51         EXTRA_REG_MAX           /* number of entries needed */
  52 };
  53
  54 struct event_constraint {
  55         union {
  56                 unsigned long   idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
  57                 u64             idxmsk64;
  58         };
  59         u64     code;
  60         u64     cmask;
  61         int     weight;
  62         int     overlap;
  63         int     flags;
  64 };
  65 /*
  66  * struct hw_perf_event.flags flags
  67  */
  68 #define PERF_X86_EVENT_PEBS_LDLAT       0x1 /* ld+ldlat data address sampling */
  69 #define PERF_X86_EVENT_PEBS_ST          0x2 /* st data address sampling */
  70 #define PERF_X86_EVENT_PEBS_ST_HSW      0x4 /* haswell style st data sampling */
  71 #define PERF_X86_EVENT_COMMITTED        0x8 /* event passed commit_txn */
  72
  73 struct amd_nb {
  74         int nb_id;  /* NorthBridge id */
  75         int refcnt; /* reference count */
  76         struct perf_event *owners[X86_PMC_IDX_MAX];
  77         struct event_constraint event_constraints[X86_PMC_IDX_MAX];
  78 };
  79
  80 /* The maximal number of PEBS events: */
  81 #define MAX_PEBS_EVENTS         8
  82
  83 /*
  84  * A debug store configuration.
  85  *
  86  * We only support architectures that use 64bit fields.
  87  */
  88 struct debug_store {
  89         u64     bts_buffer_base;
  90         u64     bts_index;
  91         u64     bts_absolute_maximum;
  92         u64     bts_interrupt_threshold;
  93         u64     pebs_buffer_base;
  94         u64     pebs_index;
  95         u64     pebs_absolute_maximum;
  96         u64     pebs_interrupt_threshold;
  97         u64     pebs_event_reset[MAX_PEBS_EVENTS];
  98 };
  99
 100 /*
 101  * Per register state.
 102  */
 103 struct er_account {
 104         raw_spinlock_t          lock;   /* per-core: protect structure */
 105         u64                 config;     /* extra MSR config */
 106         u64                 reg;        /* extra MSR number */
 107         atomic_t            ref;        /* reference count */
 108 };
 109
 110 /*
 111  * Per core/cpu state
 112  *
 113  * Used to coordinate shared registers between HT threads or
 114  * among events on a single PMU.
 115  */
 116 struct intel_shared_regs {
 117         struct er_account       regs[EXTRA_REG_MAX];
 118         int                     refcnt;         /* per-core: #HT threads */
 119         unsigned                core_id;        /* per-core: core id */
 120 };
 121
 122 #define MAX_LBR_ENTRIES         16
 123
 124 struct cpu_hw_events {
 125         /*
 126          * Generic x86 PMC bits
 127          */
 128         struct perf_event       *events[X86_PMC_IDX_MAX]; /* in counter order */
 129         unsigned long           active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 130         unsigned long           running[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 131         int                     enabled;
 132
 133         int                     n_events;
 134         int                     n_added;
 135         int                     n_txn;
 136         int                     assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
 137         u64                     tags[X86_PMC_IDX_MAX];
 138         struct perf_event       *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
 139
 140         unsigned int            group_flag;
 141         int                     is_fake;
 142
 143         /*
 144          * Intel DebugStore bits
 145          */
 146         struct debug_store      *ds;
 147         u64                     pebs_enabled;
 148
 149         /*
 150          * Intel LBR bits
 151          */
 152         int                             lbr_users;
 153         void                            *lbr_context;
 154         struct perf_branch_stack        lbr_stack;
 155         struct perf_branch_entry        lbr_entries[MAX_LBR_ENTRIES];
 156         struct er_account               *lbr_sel;
 157         u64                             br_sel;
 158
 159         /*
 160          * Intel host/guest exclude bits
 161          */
 162         u64                             intel_ctrl_guest_mask;
 163         u64                             intel_ctrl_host_mask;
 164         struct perf_guest_switch_msr    guest_switch_msrs[X86_PMC_IDX_MAX];
 165
 166         /*
 167          * manage shared (per-core, per-cpu) registers
 168          * used on Intel NHM/WSM/SNB
 169          */
 170         struct intel_shared_regs        *shared_regs;
 171
 172         /*
 173          * AMD specific bits
 174          */
 175         struct amd_nb                   *amd_nb;
 176         /* Inverted mask of bits to clear in the perf_ctr ctrl registers */
 177         u64                             perf_ctr_virt_mask;
 178
 179         void                            *kfree_on_online;
 180 };
 181
 182 #define __EVENT_CONSTRAINT(c, n, m, w, o, f) {\
 183         { .idxmsk64 = (n) },            \
 184         .code = (c),                    \
 185         .cmask = (m),                   \
 186         .weight = (w),                  \
 187         .overlap = (o),                 \
 188         .flags = f,                     \
 189 }
 190
 191 #define EVENT_CONSTRAINT(c, n, m)       \
 192         __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 0, 0)
 193
 194 /*
 195  * The overlap flag marks event constraints with overlapping counter
 196  * masks. This is the case if the counter mask of such an event is not
 197  * a subset of any other counter mask of a constraint with an equal or
 198  * higher weight, e.g.:
 199  *
 200  *  c_overlaps = EVENT_CONSTRAINT_OVERLAP(0, 0x09, 0);
 201  *  c_another1 = EVENT_CONSTRAINT(0, 0x07, 0);
 202  *  c_another2 = EVENT_CONSTRAINT(0, 0x38, 0);
 203  *
 204  * The event scheduler may not select the correct counter in the first
 205  * cycle because it needs to know which subsequent events will be
 206  * scheduled. It may fail to schedule the events then. So we set the
 207  * overlap flag for such constraints to give the scheduler a hint which
 208  * events to select for counter rescheduling.
 209  *
 210  * Care must be taken as the rescheduling algorithm is O(n!) which
 211  * will increase scheduling cycles for an over-commited system
 212  * dramatically.  The number of such EVENT_CONSTRAINT_OVERLAP() macros
 213  * and its counter masks must be kept at a minimum.
 214  */
 215 #define EVENT_CONSTRAINT_OVERLAP(c, n, m)       \
 216         __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 1, 0)
 217
 218 /*
 219  * Constraint on the Event code.
 220  */
 221 #define INTEL_EVENT_CONSTRAINT(c, n)    \
 222         EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
 223
 224 /*
 225  * Constraint on the Event code + UMask + fixed-mask
 226  *
 227  * filter mask to validate fixed counter events.
 228  * the following filters disqualify for fixed counters:
 229  *  - inv
 230  *  - edge
 231  *  - cnt-mask
 232  *  - in_tx
 233  *  - in_tx_checkpointed
 234  *  The other filters are supported by fixed counters.
 235  *  The any-thread option is supported starting with v3.
 236  */
 237 #define FIXED_EVENT_FLAGS (X86_RAW_EVENT_MASK|HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)
 238 #define FIXED_EVENT_CONSTRAINT(c, n)    \
 239         EVENT_CONSTRAINT(c, (1ULL << (32+n)), FIXED_EVENT_FLAGS)
 240
 241 /*
 242  * Constraint on the Event code + UMask
 243  */
 244 #define INTEL_UEVENT_CONSTRAINT(c, n)   \
 245         EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
 246
 247 #define INTEL_PLD_CONSTRAINT(c, n)      \
 248         __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK, \
 249                            HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LDLAT)
 250
 251 #define INTEL_PST_CONSTRAINT(c, n)      \
 252         __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK, \
 253                           HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST)
 254
 255 /* DataLA version of store sampling without extra enable bit. */
 256 #define INTEL_PST_HSW_CONSTRAINT(c, n)  \
 257         __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK, \
 258                           HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW)
 259
 260 #define EVENT_CONSTRAINT_END            \
 261         EVENT_CONSTRAINT(0, 0, 0)
 262
 263 #define for_each_event_constraint(e, c) \
 264         for ((e) = (c); (e)->weight; (e)++)
 265
 266 /*
 267  * Extra registers for specific events.
 268  *
 269  * Some events need large masks and require external MSRs.
 270  * Those extra MSRs end up being shared for all events on
 271  * a PMU and sometimes between PMU of sibling HT threads.
 272  * In either case, the kernel needs to handle conflicting
 273  * accesses to those extra, shared, regs. The data structure
 274  * to manage those registers is stored in cpu_hw_event.
 275  */
 276 struct extra_reg {
 277         unsigned int            event;
 278         unsigned int            msr;
 279         u64                     config_mask;
 280         u64                     valid_mask;
 281         int                     idx;  /* per_xxx->regs[] reg index */
 282 };
 283
 284 #define EVENT_EXTRA_REG(e, ms, m, vm, i) {      \
 285         .event = (e),           \
 286         .msr = (ms),            \
 287         .config_mask = (m),     \
 288         .valid_mask = (vm),     \
 289         .idx = EXTRA_REG_##i,   \
 290         }
 291
 292 #define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx)      \
 293         EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx)
 294
 295 #define INTEL_UEVENT_EXTRA_REG(event, msr, vm, idx) \
 296         EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT | \
 297                         ARCH_PERFMON_EVENTSEL_UMASK, vm, idx)
 298
 299 #define INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(c) \
 300         INTEL_UEVENT_EXTRA_REG(c, \
 301                                MSR_PEBS_LD_LAT_THRESHOLD, \
 302                                0xffff, \
 303                                LDLAT)
 304
 305 #define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0, RSP_0)
 306
 307 union perf_capabilities {
 308         struct {
 309                 u64     lbr_format:6;
 310                 u64     pebs_trap:1;
 311                 u64     pebs_arch_reg:1;
 312                 u64     pebs_format:4;
 313                 u64     smm_freeze:1;
 314                 /*
 315                  * PMU supports separate counter range for writing
 316                  * values > 32bit.
 317                  */
 318                 u64     full_width_write:1;
 319         };
 320         u64     capabilities;
 321 };
 322
 323 struct x86_pmu_quirk {
 324         struct x86_pmu_quirk *next;
 325         void (*func)(void);
 326 };
 327
 328 union x86_pmu_config {
 329         struct {
 330                 u64 event:8,
 331                     umask:8,
 332                     usr:1,
 333                     os:1,
 334                     edge:1,
 335                     pc:1,
 336                     interrupt:1,
 337                     __reserved1:1,
 338                     en:1,
 339                     inv:1,
 340                     cmask:8,
 341                     event2:4,
 342                     __reserved2:4,
 343                     go:1,
 344                     ho:1;
 345         } bits;
 346         u64 value;
 347 };
 348
 349 #define X86_CONFIG(args...) ((union x86_pmu_config){.bits = {args}}).value
 350
 351 /*
 352  * struct x86_pmu - generic x86 pmu
 353  */
 354 struct x86_pmu {
 355         /*
 356          * Generic x86 PMC bits
 357          */
 358         const char      *name;
 359         int             version;
 360         int             (*handle_irq)(struct pt_regs *);
 361         void            (*disable_all)(void);
 362         void            (*enable_all)(int added);
 363         void            (*enable)(struct perf_event *);
 364         void            (*disable)(struct perf_event *);
 365         int             (*hw_config)(struct perf_event *event);
 366         int             (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
 367         unsigned        eventsel;
 368         unsigned        perfctr;
 369         int             (*addr_offset)(int index, bool eventsel);
 370         int             (*rdpmc_index)(int index);
 371         u64             (*event_map)(int);
 372         int             max_events;
 373         int             num_counters;
 374         int             num_counters_fixed;
 375         int             cntval_bits;
 376         u64             cntval_mask;
 377         union {
 378                         unsigned long events_maskl;
 379                         unsigned long events_mask[BITS_TO_LONGS(ARCH_PERFMON_EVENTS_COUNT)];
 380         };
 381         int             events_mask_len;
 382         int             apic;
 383         u64             max_period;
 384         struct event_constraint *
 385                         (*get_event_constraints)(struct cpu_hw_events *cpuc,
 386                                                  struct perf_event *event);
 387
 388         void            (*put_event_constraints)(struct cpu_hw_events *cpuc,
 389                                                  struct perf_event *event);
 390         struct event_constraint *event_constraints;
 391         struct x86_pmu_quirk *quirks;
 392         int             perfctr_second_write;
 393         bool            late_ack;
 394
 395         /*
 396          * sysfs attrs
 397          */
 398         int             attr_rdpmc;
 399         struct attribute **format_attrs;
 400         struct attribute **event_attrs;
 401
 402         ssize_t         (*events_sysfs_show)(char *page, u64 config);
 403         struct attribute **cpu_events;
 404
 405         /*
 406          * CPU Hotplug hooks
 407          */
 408         int             (*cpu_prepare)(int cpu);
 409         void            (*cpu_starting)(int cpu);
 410         void            (*cpu_dying)(int cpu);
 411         void            (*cpu_dead)(int cpu);
 412
 413         void            (*check_microcode)(void);
 414         void            (*flush_branch_stack)(void);
 415
 416         /*
 417          * Intel Arch Perfmon v2+
 418          */
 419         u64                     intel_ctrl;
 420         union perf_capabilities intel_cap;
 421
 422         /*
 423          * Intel DebugStore bits
 424          */
 425         unsigned int    bts             :1,
 426                         bts_active      :1,
 427                         pebs            :1,
 428                         pebs_active     :1,
 429                         pebs_broken     :1;
 430         int             pebs_record_size;
 431         void            (*drain_pebs)(struct pt_regs *regs);
 432         struct event_constraint *pebs_constraints;
 433         void            (*pebs_aliases)(struct perf_event *event);
 434         int             max_pebs_events;
 435
 436         /*
 437          * Intel LBR
 438          */
 439         unsigned long   lbr_tos, lbr_from, lbr_to; /* MSR base regs       */
 440         int             lbr_nr;                    /* hardware stack size */
 441         u64             lbr_sel_mask;              /* LBR_SELECT valid bits */
 442         const int       *lbr_sel_map;              /* lbr_select mappings */
 443
 444         /*
 445          * Extra registers for events
 446          */
 447         struct extra_reg *extra_regs;
 448         unsigned int er_flags;
 449
 450         /*
 451          * Intel host/guest support (KVM)
 452          */
 453         struct perf_guest_switch_msr *(*guest_get_msrs)(int *nr);
 454 };
 455
 456 #define x86_add_quirk(func_)                                            \
 457 do {                                                                    \
 458         static struct x86_pmu_quirk __quirk __initdata = {              \
 459                 .func = func_,                                          \
 460         };                                                              \
 461         __quirk.next = x86_pmu.quirks;                                  \
 462         x86_pmu.quirks = &__quirk;                                      \
 463 } while (0)
 464
 465 #define ERF_NO_HT_SHARING       1
 466 #define ERF_HAS_RSP_1           2
 467
 468 #define EVENT_VAR(_id)  event_attr_##_id
 469 #define EVENT_PTR(_id) &event_attr_##_id.attr.attr
 470
 471 #define EVENT_ATTR(_name, _id)                                          \
 472 static struct perf_pmu_events_attr EVENT_VAR(_id) = {                   \
 473         .attr           = __ATTR(_name, 0444, events_sysfs_show, NULL), \
 474         .id             = PERF_COUNT_HW_##_id,                          \
 475         .event_str      = NULL,                                         \
 476 };
 477
 478 #define EVENT_ATTR_STR(_name, v, str)                                   \
 479 static struct perf_pmu_events_attr event_attr_##v = {                   \
 480         .attr           = __ATTR(_name, 0444, events_sysfs_show, NULL), \
 481         .id             = 0,                                            \
 482         .event_str      = str,                                          \
 483 };
 484
 485 extern struct x86_pmu x86_pmu __read_mostly;
 486
 487 DECLARE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
 488
 489 int x86_perf_event_set_period(struct perf_event *event);
 490
 491 /*
 492  * Generalized hw caching related hw_event table, filled
 493  * in on a per model basis. A value of 0 means
 494  * 'not supported', -1 means 'hw_event makes no sense on
 495  * this CPU', any other value means the raw hw_event
 496  * ID.
 497  */
 498
 499 #define C(x) PERF_COUNT_HW_CACHE_##x
 500
 501 extern u64 __read_mostly hw_cache_event_ids
 502                                 [PERF_COUNT_HW_CACHE_MAX]
 503                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 504                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
 505 extern u64 __read_mostly hw_cache_extra_regs
 506                                 [PERF_COUNT_HW_CACHE_MAX]
 507                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 508                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
 509
 510 u64 x86_perf_event_update(struct perf_event *event);
 511
 512 static inline unsigned int x86_pmu_config_addr(int index)
 513 {
 514         return x86_pmu.eventsel + (x86_pmu.addr_offset ?
 515                                    x86_pmu.addr_offset(index, true) : index);
 516 }
 517
 518 static inline unsigned int x86_pmu_event_addr(int index)
 519 {
 520         return x86_pmu.perfctr + (x86_pmu.addr_offset ?
 521                                   x86_pmu.addr_offset(index, false) : index);
 522 }
 523
 524 static inline int x86_pmu_rdpmc_index(int index)
 525 {
 526         return x86_pmu.rdpmc_index ? x86_pmu.rdpmc_index(index) : index;
 527 }
 528
 529 int x86_setup_perfctr(struct perf_event *event);
 530
 531 int x86_pmu_hw_config(struct perf_event *event);
 532
 533 void x86_pmu_disable_all(void);
 534
 535 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
 536                                           u64 enable_mask)
 537 {
 538         u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask);
 539
 540         if (hwc->extra_reg.reg)
 541                 wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config);
 542         wrmsrl(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask);
 543 }
 544
 545 void x86_pmu_enable_all(int added);
 546
 547 int perf_assign_events(struct perf_event **events, int n,
 548                         int wmin, int wmax, int *assign);
 549 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign);
 550
 551 void x86_pmu_stop(struct perf_event *event, int flags);
 552
 553 static inline void x86_pmu_disable_event(struct perf_event *event)
 554 {
 555         struct hw_perf_event *hwc = &event->hw;
 556
 557         wrmsrl(hwc->config_base, hwc->config);
 558 }
 559
 560 void x86_pmu_enable_event(struct perf_event *event);
 561
 562 int x86_pmu_handle_irq(struct pt_regs *regs);
 563
 564 extern struct event_constraint emptyconstraint;
 565
 566 extern struct event_constraint unconstrained;
 567
 568 static inline bool kernel_ip(unsigned long ip)
 569 {
 570 #ifdef CONFIG_X86_32
 571         return ip > PAGE_OFFSET;
 572 #else
 573         return (long)ip < 0;
 574 #endif
 575 }
 576
 577 /*
 578  * Not all PMUs provide the right context information to place the reported IP
 579  * into full context. Specifically segment registers are typically not
 580  * supplied.
 581  *
 582  * Assuming the address is a linear address (it is for IBS), we fake the CS and
 583  * vm86 mode using the known zero-based code segment and 'fix up' the registers
 584  * to reflect this.
 585  *
 586  * Intel PEBS/LBR appear to typically provide the effective address, nothing
 587  * much we can do about that but pray and treat it like a linear address.
 588  */
 589 static inline void set_linear_ip(struct pt_regs *regs, unsigned long ip)
 590 {
 591         regs->cs = kernel_ip(ip) ? __KERNEL_CS : __USER_CS;
 592         if (regs->flags & X86_VM_MASK)
 593                 regs->flags ^= (PERF_EFLAGS_VM | X86_VM_MASK);
 594         regs->ip = ip;
 595 }
 596
 597 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event);
 598 ssize_t intel_event_sysfs_show(char *page, u64 config);
 599
 600 #ifdef CONFIG_CPU_SUP_AMD
 601
 602 int amd_pmu_init(void);
 603
 604 #else /* CONFIG_CPU_SUP_AMD */
 605
 606 static inline int amd_pmu_init(void)
 607 {
 608         return 0;
 609 }
 610
 611 #endif /* CONFIG_CPU_SUP_AMD */
 612
 613 #ifdef CONFIG_CPU_SUP_INTEL
 614
 615 int intel_pmu_save_and_restart(struct perf_event *event);
 616
 617 struct event_constraint *
 618 x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event);
 619
 620 struct intel_shared_regs *allocate_shared_regs(int cpu);
 621
 622 int intel_pmu_init(void);
 623
 624 void init_debug_store_on_cpu(int cpu);
 625
 626 void fini_debug_store_on_cpu(int cpu);
 627
 628 void release_ds_buffers(void);
 629
 630 void reserve_ds_buffers(void);
 631
 632 extern struct event_constraint bts_constraint;
 633
 634 void intel_pmu_enable_bts(u64 config);
 635
 636 void intel_pmu_disable_bts(void);
 637
 638 int intel_pmu_drain_bts_buffer(void);
 639
 640 extern struct event_constraint intel_core2_pebs_event_constraints[];
 641
 642 extern struct event_constraint intel_atom_pebs_event_constraints[];
 643
 644 extern struct event_constraint intel_slm_pebs_event_constraints[];
 645
 646 extern struct event_constraint intel_nehalem_pebs_event_constraints[];
 647
 648 extern struct event_constraint intel_westmere_pebs_event_constraints[];
 649
 650 extern struct event_constraint intel_snb_pebs_event_constraints[];
 651
 652 extern struct event_constraint intel_ivb_pebs_event_constraints[];
 653
 654 extern struct event_constraint intel_hsw_pebs_event_constraints[];
 655
 656 struct event_constraint *intel_pebs_constraints(struct perf_event *event);
 657
 658 void intel_pmu_pebs_enable(struct perf_event *event);
 659
 660 void intel_pmu_pebs_disable(struct perf_event *event);
 661
 662 void intel_pmu_pebs_enable_all(void);
 663
 664 void intel_pmu_pebs_disable_all(void);
 665
 666 void intel_ds_init(void);
 667
 668 void intel_pmu_lbr_reset(void);
 669
 670 void intel_pmu_lbr_enable(struct perf_event *event);
 671
 672 void intel_pmu_lbr_disable(struct perf_event *event);
 673
 674 void intel_pmu_lbr_enable_all(void);
 675
 676 void intel_pmu_lbr_disable_all(void);
 677
 678 void intel_pmu_lbr_read(void);
 679
 680 void intel_pmu_lbr_init_core(void);
 681
 682 void intel_pmu_lbr_init_nhm(void);
 683
 684 void intel_pmu_lbr_init_atom(void);
 685
 686 void intel_pmu_lbr_init_snb(void);
 687
 688 int intel_pmu_setup_lbr_filter(struct perf_event *event);
 689
 690 int p4_pmu_init(void);
 691
 692 int p6_pmu_init(void);
 693
 694 int knc_pmu_init(void);
 695
 696 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr,
 697                           char *page);
 698
 699 #else /* CONFIG_CPU_SUP_INTEL */
 700
 701 static inline void reserve_ds_buffers(void)
 702 {
 703 }
 704
 705 static inline void release_ds_buffers(void)
 706 {
 707 }
 708
 709 static inline int intel_pmu_init(void)
 710 {
 711         return 0;
 712 }
 713
 714 static inline struct intel_shared_regs *allocate_shared_regs(int cpu)
 715 {
 716         return NULL;
 717 }
 718
 719 #endif /* CONFIG_CPU_SUP_INTEL */