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x86/efi: Enforce CONFIG_RELOCATABLE for EFI boot stub
[linux/fpc-iii.git] / arch / x86 / kernel / cpu / perf_event_intel.c
blobaa4b5c132c663c47c7b10dc62619e0e815d3c322
1 /*
2 * Per core/cpu state
3 *
4 * Used to coordinate shared registers between HT threads or
5 * among events on a single PMU.
6 */
7
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
10 #include <linux/stddef.h>
11 #include <linux/types.h>
12 #include <linux/init.h>
13 #include <linux/slab.h>
14 #include <linux/export.h>
15
16 #include <asm/cpufeature.h>
17 #include <asm/hardirq.h>
18 #include <asm/apic.h>
19
20 #include "perf_event.h"
21
22 /*
23 * Intel PerfMon, used on Core and later.
24 */
25 static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
26 {
27 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
28 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
29 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
30 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
31 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
32 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
33 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
34 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */
35 };
36
37 static struct event_constraint intel_core_event_constraints[] __read_mostly =
38 {
39 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
40 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
41 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
42 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
43 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
44 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
45 EVENT_CONSTRAINT_END
46 };
47
48 static struct event_constraint intel_core2_event_constraints[] __read_mostly =
49 {
50 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
51 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
52 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
53 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
54 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
55 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
56 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
57 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
58 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
59 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
60 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
61 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
62 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
63 EVENT_CONSTRAINT_END
64 };
65
66 static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
67 {
68 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
69 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
70 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
71 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
72 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
73 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
74 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
75 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
76 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
77 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
78 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
79 EVENT_CONSTRAINT_END
80 };
81
82 static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
83 {
84 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
85 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
86 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
87 EVENT_EXTRA_END
88 };
89
90 static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
91 {
92 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
93 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
94 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
95 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
96 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
97 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
98 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
99 EVENT_CONSTRAINT_END
100 };
101
102 static struct event_constraint intel_snb_event_constraints[] __read_mostly =
103 {
104 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
105 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
106 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
107 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
108 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
109 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
110 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
111 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
112 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
113 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
114 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
115 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
116 EVENT_CONSTRAINT_END
117 };
118
119 static struct event_constraint intel_ivb_event_constraints[] __read_mostly =
120 {
121 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
122 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
123 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
124 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */
125 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMTPY */
126 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */
127 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */
128 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
129 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
130 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */
131 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
132 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
133 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
134 /*
135 * Errata BV98 -- MEM_*_RETIRED events can leak between counters of SMT
136 * siblings; disable these events because they can corrupt unrelated
137 * counters.
138 */
139 INTEL_EVENT_CONSTRAINT(0xd0, 0x0), /* MEM_UOPS_RETIRED.* */
140 INTEL_EVENT_CONSTRAINT(0xd1, 0x0), /* MEM_LOAD_UOPS_RETIRED.* */
141 INTEL_EVENT_CONSTRAINT(0xd2, 0x0), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
142 INTEL_EVENT_CONSTRAINT(0xd3, 0x0), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
143 EVENT_CONSTRAINT_END
144 };
145
146 static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
147 {
148 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
149 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
150 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
151 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
152 EVENT_EXTRA_END
153 };
154
155 static struct event_constraint intel_v1_event_constraints[] __read_mostly =
156 {
157 EVENT_CONSTRAINT_END
158 };
159
160 static struct event_constraint intel_gen_event_constraints[] __read_mostly =
161 {
162 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
163 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
164 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
165 EVENT_CONSTRAINT_END
166 };
167
168 static struct event_constraint intel_slm_event_constraints[] __read_mostly =
169 {
170 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
171 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
172 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF */
173 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
174 EVENT_CONSTRAINT_END
175 };
176
177 static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
178 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
179 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
180 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1),
181 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
182 EVENT_EXTRA_END
183 };
184
185 static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {
186 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
187 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
188 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
189 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
190 EVENT_EXTRA_END
191 };
192
193 EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3");
194 EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3");
195 EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2");
196
197 struct attribute *nhm_events_attrs[] = {
198 EVENT_PTR(mem_ld_nhm),
199 NULL,
200 };
201
202 struct attribute *snb_events_attrs[] = {
203 EVENT_PTR(mem_ld_snb),
204 EVENT_PTR(mem_st_snb),
205 NULL,
206 };
207
208 static struct event_constraint intel_hsw_event_constraints[] = {
209 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
210 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
211 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
212 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.* */
213 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
214 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
215 /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
216 INTEL_EVENT_CONSTRAINT(0x08a3, 0x4),
217 /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
218 INTEL_EVENT_CONSTRAINT(0x0ca3, 0x4),
219 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
220 INTEL_EVENT_CONSTRAINT(0x04a3, 0xf),
221 EVENT_CONSTRAINT_END
222 };
223
224 static u64 intel_pmu_event_map(int hw_event)
225 {
226 return intel_perfmon_event_map[hw_event];
227 }
228
229 #define SNB_DMND_DATA_RD (1ULL << 0)
230 #define SNB_DMND_RFO (1ULL << 1)
231 #define SNB_DMND_IFETCH (1ULL << 2)
232 #define SNB_DMND_WB (1ULL << 3)
233 #define SNB_PF_DATA_RD (1ULL << 4)
234 #define SNB_PF_RFO (1ULL << 5)
235 #define SNB_PF_IFETCH (1ULL << 6)
236 #define SNB_LLC_DATA_RD (1ULL << 7)
237 #define SNB_LLC_RFO (1ULL << 8)
238 #define SNB_LLC_IFETCH (1ULL << 9)
239 #define SNB_BUS_LOCKS (1ULL << 10)
240 #define SNB_STRM_ST (1ULL << 11)
241 #define SNB_OTHER (1ULL << 15)
242 #define SNB_RESP_ANY (1ULL << 16)
243 #define SNB_NO_SUPP (1ULL << 17)
244 #define SNB_LLC_HITM (1ULL << 18)
245 #define SNB_LLC_HITE (1ULL << 19)
246 #define SNB_LLC_HITS (1ULL << 20)
247 #define SNB_LLC_HITF (1ULL << 21)
248 #define SNB_LOCAL (1ULL << 22)
249 #define SNB_REMOTE (0xffULL << 23)
250 #define SNB_SNP_NONE (1ULL << 31)
251 #define SNB_SNP_NOT_NEEDED (1ULL << 32)
252 #define SNB_SNP_MISS (1ULL << 33)
253 #define SNB_NO_FWD (1ULL << 34)
254 #define SNB_SNP_FWD (1ULL << 35)
255 #define SNB_HITM (1ULL << 36)
256 #define SNB_NON_DRAM (1ULL << 37)
257
258 #define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
259 #define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO)
260 #define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
261
262 #define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
263 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
264 SNB_HITM)
265
266 #define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
267 #define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY)
268
269 #define SNB_L3_ACCESS SNB_RESP_ANY
270 #define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM)
271
272 static __initconst const u64 snb_hw_cache_extra_regs
273 [PERF_COUNT_HW_CACHE_MAX]
274 [PERF_COUNT_HW_CACHE_OP_MAX]
275 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
276 {
277 [ C(LL ) ] = {
278 [ C(OP_READ) ] = {
279 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
280 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS,
281 },
282 [ C(OP_WRITE) ] = {
283 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
284 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS,
285 },
286 [ C(OP_PREFETCH) ] = {
287 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
288 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
289 },
290 },
291 [ C(NODE) ] = {
292 [ C(OP_READ) ] = {
293 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
294 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
295 },
296 [ C(OP_WRITE) ] = {
297 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
298 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
299 },
300 [ C(OP_PREFETCH) ] = {
301 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
302 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
303 },
304 },
305 };
306
307 static __initconst const u64 snb_hw_cache_event_ids
308 [PERF_COUNT_HW_CACHE_MAX]
309 [PERF_COUNT_HW_CACHE_OP_MAX]
310 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
311 {
312 [ C(L1D) ] = {
313 [ C(OP_READ) ] = {
314 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
315 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */
316 },
317 [ C(OP_WRITE) ] = {
318 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
319 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
320 },
321 [ C(OP_PREFETCH) ] = {
322 [ C(RESULT_ACCESS) ] = 0x0,
323 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
324 },
325 },
326 [ C(L1I ) ] = {
327 [ C(OP_READ) ] = {
328 [ C(RESULT_ACCESS) ] = 0x0,
329 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */
330 },
331 [ C(OP_WRITE) ] = {
332 [ C(RESULT_ACCESS) ] = -1,
333 [ C(RESULT_MISS) ] = -1,
334 },
335 [ C(OP_PREFETCH) ] = {
336 [ C(RESULT_ACCESS) ] = 0x0,
337 [ C(RESULT_MISS) ] = 0x0,
338 },
339 },
340 [ C(LL ) ] = {
341 [ C(OP_READ) ] = {
342 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
343 [ C(RESULT_ACCESS) ] = 0x01b7,
344 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
345 [ C(RESULT_MISS) ] = 0x01b7,
346 },
347 [ C(OP_WRITE) ] = {
348 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
349 [ C(RESULT_ACCESS) ] = 0x01b7,
350 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
351 [ C(RESULT_MISS) ] = 0x01b7,
352 },
353 [ C(OP_PREFETCH) ] = {
354 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
355 [ C(RESULT_ACCESS) ] = 0x01b7,
356 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
357 [ C(RESULT_MISS) ] = 0x01b7,
358 },
359 },
360 [ C(DTLB) ] = {
361 [ C(OP_READ) ] = {
362 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
363 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
364 },
365 [ C(OP_WRITE) ] = {
366 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
367 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
368 },
369 [ C(OP_PREFETCH) ] = {
370 [ C(RESULT_ACCESS) ] = 0x0,
371 [ C(RESULT_MISS) ] = 0x0,
372 },
373 },
374 [ C(ITLB) ] = {
375 [ C(OP_READ) ] = {
376 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */
377 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */
378 },
379 [ C(OP_WRITE) ] = {
380 [ C(RESULT_ACCESS) ] = -1,
381 [ C(RESULT_MISS) ] = -1,
382 },
383 [ C(OP_PREFETCH) ] = {
384 [ C(RESULT_ACCESS) ] = -1,
385 [ C(RESULT_MISS) ] = -1,
386 },
387 },
388 [ C(BPU ) ] = {
389 [ C(OP_READ) ] = {
390 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
391 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
392 },
393 [ C(OP_WRITE) ] = {
394 [ C(RESULT_ACCESS) ] = -1,
395 [ C(RESULT_MISS) ] = -1,
396 },
397 [ C(OP_PREFETCH) ] = {
398 [ C(RESULT_ACCESS) ] = -1,
399 [ C(RESULT_MISS) ] = -1,
400 },
401 },
402 [ C(NODE) ] = {
403 [ C(OP_READ) ] = {
404 [ C(RESULT_ACCESS) ] = 0x01b7,
405 [ C(RESULT_MISS) ] = 0x01b7,
406 },
407 [ C(OP_WRITE) ] = {
408 [ C(RESULT_ACCESS) ] = 0x01b7,
409 [ C(RESULT_MISS) ] = 0x01b7,
410 },
411 [ C(OP_PREFETCH) ] = {
412 [ C(RESULT_ACCESS) ] = 0x01b7,
413 [ C(RESULT_MISS) ] = 0x01b7,
414 },
415 },
416
417 };
418
419 static __initconst const u64 westmere_hw_cache_event_ids
420 [PERF_COUNT_HW_CACHE_MAX]
421 [PERF_COUNT_HW_CACHE_OP_MAX]
422 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
423 {
424 [ C(L1D) ] = {
425 [ C(OP_READ) ] = {
426 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
427 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
428 },
429 [ C(OP_WRITE) ] = {
430 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
431 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
432 },
433 [ C(OP_PREFETCH) ] = {
434 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
435 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
436 },
437 },
438 [ C(L1I ) ] = {
439 [ C(OP_READ) ] = {
440 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
441 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
442 },
443 [ C(OP_WRITE) ] = {
444 [ C(RESULT_ACCESS) ] = -1,
445 [ C(RESULT_MISS) ] = -1,
446 },
447 [ C(OP_PREFETCH) ] = {
448 [ C(RESULT_ACCESS) ] = 0x0,
449 [ C(RESULT_MISS) ] = 0x0,
450 },
451 },
452 [ C(LL ) ] = {
453 [ C(OP_READ) ] = {
454 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
455 [ C(RESULT_ACCESS) ] = 0x01b7,
456 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
457 [ C(RESULT_MISS) ] = 0x01b7,
458 },
459 /*
460 * Use RFO, not WRITEBACK, because a write miss would typically occur
461 * on RFO.
462 */
463 [ C(OP_WRITE) ] = {
464 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
465 [ C(RESULT_ACCESS) ] = 0x01b7,
466 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
467 [ C(RESULT_MISS) ] = 0x01b7,
468 },
469 [ C(OP_PREFETCH) ] = {
470 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
471 [ C(RESULT_ACCESS) ] = 0x01b7,
472 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
473 [ C(RESULT_MISS) ] = 0x01b7,
474 },
475 },
476 [ C(DTLB) ] = {
477 [ C(OP_READ) ] = {
478 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
479 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
480 },
481 [ C(OP_WRITE) ] = {
482 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
483 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
484 },
485 [ C(OP_PREFETCH) ] = {
486 [ C(RESULT_ACCESS) ] = 0x0,
487 [ C(RESULT_MISS) ] = 0x0,
488 },
489 },
490 [ C(ITLB) ] = {
491 [ C(OP_READ) ] = {
492 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
493 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
494 },
495 [ C(OP_WRITE) ] = {
496 [ C(RESULT_ACCESS) ] = -1,
497 [ C(RESULT_MISS) ] = -1,
498 },
499 [ C(OP_PREFETCH) ] = {
500 [ C(RESULT_ACCESS) ] = -1,
501 [ C(RESULT_MISS) ] = -1,
502 },
503 },
504 [ C(BPU ) ] = {
505 [ C(OP_READ) ] = {
506 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
507 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
508 },
509 [ C(OP_WRITE) ] = {
510 [ C(RESULT_ACCESS) ] = -1,
511 [ C(RESULT_MISS) ] = -1,
512 },
513 [ C(OP_PREFETCH) ] = {
514 [ C(RESULT_ACCESS) ] = -1,
515 [ C(RESULT_MISS) ] = -1,
516 },
517 },
518 [ C(NODE) ] = {
519 [ C(OP_READ) ] = {
520 [ C(RESULT_ACCESS) ] = 0x01b7,
521 [ C(RESULT_MISS) ] = 0x01b7,
522 },
523 [ C(OP_WRITE) ] = {
524 [ C(RESULT_ACCESS) ] = 0x01b7,
525 [ C(RESULT_MISS) ] = 0x01b7,
526 },
527 [ C(OP_PREFETCH) ] = {
528 [ C(RESULT_ACCESS) ] = 0x01b7,
529 [ C(RESULT_MISS) ] = 0x01b7,
530 },
531 },
532 };
533
534 /*
535 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
536 * See IA32 SDM Vol 3B 30.6.1.3
537 */
538
539 #define NHM_DMND_DATA_RD (1 << 0)
540 #define NHM_DMND_RFO (1 << 1)
541 #define NHM_DMND_IFETCH (1 << 2)
542 #define NHM_DMND_WB (1 << 3)
543 #define NHM_PF_DATA_RD (1 << 4)
544 #define NHM_PF_DATA_RFO (1 << 5)
545 #define NHM_PF_IFETCH (1 << 6)
546 #define NHM_OFFCORE_OTHER (1 << 7)
547 #define NHM_UNCORE_HIT (1 << 8)
548 #define NHM_OTHER_CORE_HIT_SNP (1 << 9)
549 #define NHM_OTHER_CORE_HITM (1 << 10)
550 /* reserved */
551 #define NHM_REMOTE_CACHE_FWD (1 << 12)
552 #define NHM_REMOTE_DRAM (1 << 13)
553 #define NHM_LOCAL_DRAM (1 << 14)
554 #define NHM_NON_DRAM (1 << 15)
555
556 #define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)
557 #define NHM_REMOTE (NHM_REMOTE_DRAM)
558
559 #define NHM_DMND_READ (NHM_DMND_DATA_RD)
560 #define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB)
561 #define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
562
563 #define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
564 #define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)
565 #define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS)
566
567 static __initconst const u64 nehalem_hw_cache_extra_regs
568 [PERF_COUNT_HW_CACHE_MAX]
569 [PERF_COUNT_HW_CACHE_OP_MAX]
570 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
571 {
572 [ C(LL ) ] = {
573 [ C(OP_READ) ] = {
574 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
575 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
576 },
577 [ C(OP_WRITE) ] = {
578 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
579 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
580 },
581 [ C(OP_PREFETCH) ] = {
582 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
583 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
584 },
585 },
586 [ C(NODE) ] = {
587 [ C(OP_READ) ] = {
588 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
589 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE,
590 },
591 [ C(OP_WRITE) ] = {
592 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
593 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE,
594 },
595 [ C(OP_PREFETCH) ] = {
596 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
597 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE,
598 },
599 },
600 };
601
602 static __initconst const u64 nehalem_hw_cache_event_ids
603 [PERF_COUNT_HW_CACHE_MAX]
604 [PERF_COUNT_HW_CACHE_OP_MAX]
605 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
606 {
607 [ C(L1D) ] = {
608 [ C(OP_READ) ] = {
609 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
610 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
611 },
612 [ C(OP_WRITE) ] = {
613 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
614 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
615 },
616 [ C(OP_PREFETCH) ] = {
617 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
618 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
619 },
620 },
621 [ C(L1I ) ] = {
622 [ C(OP_READ) ] = {
623 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
624 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
625 },
626 [ C(OP_WRITE) ] = {
627 [ C(RESULT_ACCESS) ] = -1,
628 [ C(RESULT_MISS) ] = -1,
629 },
630 [ C(OP_PREFETCH) ] = {
631 [ C(RESULT_ACCESS) ] = 0x0,
632 [ C(RESULT_MISS) ] = 0x0,
633 },
634 },
635 [ C(LL ) ] = {
636 [ C(OP_READ) ] = {
637 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
638 [ C(RESULT_ACCESS) ] = 0x01b7,
639 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
640 [ C(RESULT_MISS) ] = 0x01b7,
641 },
642 /*
643 * Use RFO, not WRITEBACK, because a write miss would typically occur
644 * on RFO.
645 */
646 [ C(OP_WRITE) ] = {
647 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
648 [ C(RESULT_ACCESS) ] = 0x01b7,
649 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
650 [ C(RESULT_MISS) ] = 0x01b7,
651 },
652 [ C(OP_PREFETCH) ] = {
653 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
654 [ C(RESULT_ACCESS) ] = 0x01b7,
655 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
656 [ C(RESULT_MISS) ] = 0x01b7,
657 },
658 },
659 [ C(DTLB) ] = {
660 [ C(OP_READ) ] = {
661 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
662 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
663 },
664 [ C(OP_WRITE) ] = {
665 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
666 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
667 },
668 [ C(OP_PREFETCH) ] = {
669 [ C(RESULT_ACCESS) ] = 0x0,
670 [ C(RESULT_MISS) ] = 0x0,
671 },
672 },
673 [ C(ITLB) ] = {
674 [ C(OP_READ) ] = {
675 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
676 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
677 },
678 [ C(OP_WRITE) ] = {
679 [ C(RESULT_ACCESS) ] = -1,
680 [ C(RESULT_MISS) ] = -1,
681 },
682 [ C(OP_PREFETCH) ] = {
683 [ C(RESULT_ACCESS) ] = -1,
684 [ C(RESULT_MISS) ] = -1,
685 },
686 },
687 [ C(BPU ) ] = {
688 [ C(OP_READ) ] = {
689 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
690 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
691 },
692 [ C(OP_WRITE) ] = {
693 [ C(RESULT_ACCESS) ] = -1,
694 [ C(RESULT_MISS) ] = -1,
695 },
696 [ C(OP_PREFETCH) ] = {
697 [ C(RESULT_ACCESS) ] = -1,
698 [ C(RESULT_MISS) ] = -1,
699 },
700 },
701 [ C(NODE) ] = {
702 [ C(OP_READ) ] = {
703 [ C(RESULT_ACCESS) ] = 0x01b7,
704 [ C(RESULT_MISS) ] = 0x01b7,
705 },
706 [ C(OP_WRITE) ] = {
707 [ C(RESULT_ACCESS) ] = 0x01b7,
708 [ C(RESULT_MISS) ] = 0x01b7,
709 },
710 [ C(OP_PREFETCH) ] = {
711 [ C(RESULT_ACCESS) ] = 0x01b7,
712 [ C(RESULT_MISS) ] = 0x01b7,
713 },
714 },
715 };
716
717 static __initconst const u64 core2_hw_cache_event_ids
718 [PERF_COUNT_HW_CACHE_MAX]
719 [PERF_COUNT_HW_CACHE_OP_MAX]
720 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
721 {
722 [ C(L1D) ] = {
723 [ C(OP_READ) ] = {
724 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
725 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
726 },
727 [ C(OP_WRITE) ] = {
728 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
729 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
730 },
731 [ C(OP_PREFETCH) ] = {
732 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
733 [ C(RESULT_MISS) ] = 0,
734 },
735 },
736 [ C(L1I ) ] = {
737 [ C(OP_READ) ] = {
738 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
739 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
740 },
741 [ C(OP_WRITE) ] = {
742 [ C(RESULT_ACCESS) ] = -1,
743 [ C(RESULT_MISS) ] = -1,
744 },
745 [ C(OP_PREFETCH) ] = {
746 [ C(RESULT_ACCESS) ] = 0,
747 [ C(RESULT_MISS) ] = 0,
748 },
749 },
750 [ C(LL ) ] = {
751 [ C(OP_READ) ] = {
752 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
753 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
754 },
755 [ C(OP_WRITE) ] = {
756 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
757 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
758 },
759 [ C(OP_PREFETCH) ] = {
760 [ C(RESULT_ACCESS) ] = 0,
761 [ C(RESULT_MISS) ] = 0,
762 },
763 },
764 [ C(DTLB) ] = {
765 [ C(OP_READ) ] = {
766 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
767 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
768 },
769 [ C(OP_WRITE) ] = {
770 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
771 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
772 },
773 [ C(OP_PREFETCH) ] = {
774 [ C(RESULT_ACCESS) ] = 0,
775 [ C(RESULT_MISS) ] = 0,
776 },
777 },
778 [ C(ITLB) ] = {
779 [ C(OP_READ) ] = {
780 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
781 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
782 },
783 [ C(OP_WRITE) ] = {
784 [ C(RESULT_ACCESS) ] = -1,
785 [ C(RESULT_MISS) ] = -1,
786 },
787 [ C(OP_PREFETCH) ] = {
788 [ C(RESULT_ACCESS) ] = -1,
789 [ C(RESULT_MISS) ] = -1,
790 },
791 },
792 [ C(BPU ) ] = {
793 [ C(OP_READ) ] = {
794 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
795 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
796 },
797 [ C(OP_WRITE) ] = {
798 [ C(RESULT_ACCESS) ] = -1,
799 [ C(RESULT_MISS) ] = -1,
800 },
801 [ C(OP_PREFETCH) ] = {
802 [ C(RESULT_ACCESS) ] = -1,
803 [ C(RESULT_MISS) ] = -1,
804 },
805 },
806 };
807
808 static __initconst const u64 atom_hw_cache_event_ids
809 [PERF_COUNT_HW_CACHE_MAX]
810 [PERF_COUNT_HW_CACHE_OP_MAX]
811 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
812 {
813 [ C(L1D) ] = {
814 [ C(OP_READ) ] = {
815 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
816 [ C(RESULT_MISS) ] = 0,
817 },
818 [ C(OP_WRITE) ] = {
819 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
820 [ C(RESULT_MISS) ] = 0,
821 },
822 [ C(OP_PREFETCH) ] = {
823 [ C(RESULT_ACCESS) ] = 0x0,
824 [ C(RESULT_MISS) ] = 0,
825 },
826 },
827 [ C(L1I ) ] = {
828 [ C(OP_READ) ] = {
829 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
830 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
831 },
832 [ C(OP_WRITE) ] = {
833 [ C(RESULT_ACCESS) ] = -1,
834 [ C(RESULT_MISS) ] = -1,
835 },
836 [ C(OP_PREFETCH) ] = {
837 [ C(RESULT_ACCESS) ] = 0,
838 [ C(RESULT_MISS) ] = 0,
839 },
840 },
841 [ C(LL ) ] = {
842 [ C(OP_READ) ] = {
843 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
844 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
845 },
846 [ C(OP_WRITE) ] = {
847 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
848 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
849 },
850 [ C(OP_PREFETCH) ] = {
851 [ C(RESULT_ACCESS) ] = 0,
852 [ C(RESULT_MISS) ] = 0,
853 },
854 },
855 [ C(DTLB) ] = {
856 [ C(OP_READ) ] = {
857 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
858 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
859 },
860 [ C(OP_WRITE) ] = {
861 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
862 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
863 },
864 [ C(OP_PREFETCH) ] = {
865 [ C(RESULT_ACCESS) ] = 0,
866 [ C(RESULT_MISS) ] = 0,
867 },
868 },
869 [ C(ITLB) ] = {
870 [ C(OP_READ) ] = {
871 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
872 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
873 },
874 [ C(OP_WRITE) ] = {
875 [ C(RESULT_ACCESS) ] = -1,
876 [ C(RESULT_MISS) ] = -1,
877 },
878 [ C(OP_PREFETCH) ] = {
879 [ C(RESULT_ACCESS) ] = -1,
880 [ C(RESULT_MISS) ] = -1,
881 },
882 },
883 [ C(BPU ) ] = {
884 [ C(OP_READ) ] = {
885 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
886 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
887 },
888 [ C(OP_WRITE) ] = {
889 [ C(RESULT_ACCESS) ] = -1,
890 [ C(RESULT_MISS) ] = -1,
891 },
892 [ C(OP_PREFETCH) ] = {
893 [ C(RESULT_ACCESS) ] = -1,
894 [ C(RESULT_MISS) ] = -1,
895 },
896 },
897 };
898
899 static struct extra_reg intel_slm_extra_regs[] __read_mostly =
900 {
901 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
902 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0),
903 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x768005ffffull, RSP_1),
904 EVENT_EXTRA_END
905 };
906
907 #define SLM_DMND_READ SNB_DMND_DATA_RD
908 #define SLM_DMND_WRITE SNB_DMND_RFO
909 #define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
910
911 #define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM)
912 #define SLM_LLC_ACCESS SNB_RESP_ANY
913 #define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM)
914
915 static __initconst const u64 slm_hw_cache_extra_regs
916 [PERF_COUNT_HW_CACHE_MAX]
917 [PERF_COUNT_HW_CACHE_OP_MAX]
918 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
919 {
920 [ C(LL ) ] = {
921 [ C(OP_READ) ] = {
922 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS,
923 [ C(RESULT_MISS) ] = SLM_DMND_READ|SLM_LLC_MISS,
924 },
925 [ C(OP_WRITE) ] = {
926 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS,
927 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS,
928 },
929 [ C(OP_PREFETCH) ] = {
930 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS,
931 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS,
932 },
933 },
934 };
935
936 static __initconst const u64 slm_hw_cache_event_ids
937 [PERF_COUNT_HW_CACHE_MAX]
938 [PERF_COUNT_HW_CACHE_OP_MAX]
939 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
940 {
941 [ C(L1D) ] = {
942 [ C(OP_READ) ] = {
943 [ C(RESULT_ACCESS) ] = 0,
944 [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */
945 },
946 [ C(OP_WRITE) ] = {
947 [ C(RESULT_ACCESS) ] = 0,
948 [ C(RESULT_MISS) ] = 0,
949 },
950 [ C(OP_PREFETCH) ] = {
951 [ C(RESULT_ACCESS) ] = 0,
952 [ C(RESULT_MISS) ] = 0,
953 },
954 },
955 [ C(L1I ) ] = {
956 [ C(OP_READ) ] = {
957 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */
958 [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */
959 },
960 [ C(OP_WRITE) ] = {
961 [ C(RESULT_ACCESS) ] = -1,
962 [ C(RESULT_MISS) ] = -1,
963 },
964 [ C(OP_PREFETCH) ] = {
965 [ C(RESULT_ACCESS) ] = 0,
966 [ C(RESULT_MISS) ] = 0,
967 },
968 },
969 [ C(LL ) ] = {
970 [ C(OP_READ) ] = {
971 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
972 [ C(RESULT_ACCESS) ] = 0x01b7,
973 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
974 [ C(RESULT_MISS) ] = 0x01b7,
975 },
976 [ C(OP_WRITE) ] = {
977 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
978 [ C(RESULT_ACCESS) ] = 0x01b7,
979 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
980 [ C(RESULT_MISS) ] = 0x01b7,
981 },
982 [ C(OP_PREFETCH) ] = {
983 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
984 [ C(RESULT_ACCESS) ] = 0x01b7,
985 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
986 [ C(RESULT_MISS) ] = 0x01b7,
987 },
988 },
989 [ C(DTLB) ] = {
990 [ C(OP_READ) ] = {
991 [ C(RESULT_ACCESS) ] = 0,
992 [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */
993 },
994 [ C(OP_WRITE) ] = {
995 [ C(RESULT_ACCESS) ] = 0,
996 [ C(RESULT_MISS) ] = 0,
997 },
998 [ C(OP_PREFETCH) ] = {
999 [ C(RESULT_ACCESS) ] = 0,
1000 [ C(RESULT_MISS) ] = 0,
1001 },
1002 },
1003 [ C(ITLB) ] = {
1004 [ C(OP_READ) ] = {
1005 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1006 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
1007 },
1008 [ C(OP_WRITE) ] = {
1009 [ C(RESULT_ACCESS) ] = -1,
1010 [ C(RESULT_MISS) ] = -1,
1011 },
1012 [ C(OP_PREFETCH) ] = {
1013 [ C(RESULT_ACCESS) ] = -1,
1014 [ C(RESULT_MISS) ] = -1,
1015 },
1016 },
1017 [ C(BPU ) ] = {
1018 [ C(OP_READ) ] = {
1019 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1020 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1021 },
1022 [ C(OP_WRITE) ] = {
1023 [ C(RESULT_ACCESS) ] = -1,
1024 [ C(RESULT_MISS) ] = -1,
1025 },
1026 [ C(OP_PREFETCH) ] = {
1027 [ C(RESULT_ACCESS) ] = -1,
1028 [ C(RESULT_MISS) ] = -1,
1029 },
1030 },
1031 };
1032
1033 static inline bool intel_pmu_needs_lbr_smpl(struct perf_event *event)
1034 {
1035 /* user explicitly requested branch sampling */
1036 if (has_branch_stack(event))
1037 return true;
1038
1039 /* implicit branch sampling to correct PEBS skid */
1040 if (x86_pmu.intel_cap.pebs_trap && event->attr.precise_ip > 1 &&
1041 x86_pmu.intel_cap.pebs_format < 2)
1042 return true;
1043
1044 return false;
1045 }
1046
1047 static void intel_pmu_disable_all(void)
1048 {
1049 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1050
1051 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
1052
1053 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
1054 intel_pmu_disable_bts();
1055
1056 intel_pmu_pebs_disable_all();
1057 intel_pmu_lbr_disable_all();
1058 }
1059
1060 static void intel_pmu_enable_all(int added)
1061 {
1062 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1063
1064 intel_pmu_pebs_enable_all();
1065 intel_pmu_lbr_enable_all();
1066 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
1067 x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
1068
1069 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
1070 struct perf_event *event =
1071 cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
1072
1073 if (WARN_ON_ONCE(!event))
1074 return;
1075
1076 intel_pmu_enable_bts(event->hw.config);
1077 }
1078 }
1079
1080 /*
1081 * Workaround for:
1082 * Intel Errata AAK100 (model 26)
1083 * Intel Errata AAP53 (model 30)
1084 * Intel Errata BD53 (model 44)
1085 *
1086 * The official story:
1087 * These chips need to be 'reset' when adding counters by programming the
1088 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
1089 * in sequence on the same PMC or on different PMCs.
1090 *
1091 * In practise it appears some of these events do in fact count, and
1092 * we need to programm all 4 events.
1093 */
1094 static void intel_pmu_nhm_workaround(void)
1095 {
1096 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1097 static const unsigned long nhm_magic[4] = {
1098 0x4300B5,
1099 0x4300D2,
1100 0x4300B1,
1101 0x4300B1
1102 };
1103 struct perf_event *event;
1104 int i;
1105
1106 /*
1107 * The Errata requires below steps:
1108 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
1109 * 2) Configure 4 PERFEVTSELx with the magic events and clear
1110 * the corresponding PMCx;
1111 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
1112 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
1113 * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
1114 */
1115
1116 /*
1117 * The real steps we choose are a little different from above.
1118 * A) To reduce MSR operations, we don't run step 1) as they
1119 * are already cleared before this function is called;
1120 * B) Call x86_perf_event_update to save PMCx before configuring
1121 * PERFEVTSELx with magic number;
1122 * C) With step 5), we do clear only when the PERFEVTSELx is
1123 * not used currently.
1124 * D) Call x86_perf_event_set_period to restore PMCx;
1125 */
1126
1127 /* We always operate 4 pairs of PERF Counters */
1128 for (i = 0; i < 4; i++) {
1129 event = cpuc->events[i];
1130 if (event)
1131 x86_perf_event_update(event);
1132 }
1133
1134 for (i = 0; i < 4; i++) {
1135 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
1136 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
1137 }
1138
1139 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
1140 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
1141
1142 for (i = 0; i < 4; i++) {
1143 event = cpuc->events[i];
1144
1145 if (event) {
1146 x86_perf_event_set_period(event);
1147 __x86_pmu_enable_event(&event->hw,
1148 ARCH_PERFMON_EVENTSEL_ENABLE);
1149 } else
1150 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
1151 }
1152 }
1153
1154 static void intel_pmu_nhm_enable_all(int added)
1155 {
1156 if (added)
1157 intel_pmu_nhm_workaround();
1158 intel_pmu_enable_all(added);
1159 }
1160
1161 static inline u64 intel_pmu_get_status(void)
1162 {
1163 u64 status;
1164
1165 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1166
1167 return status;
1168 }
1169
1170 static inline void intel_pmu_ack_status(u64 ack)
1171 {
1172 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
1173 }
1174
1175 static void intel_pmu_disable_fixed(struct hw_perf_event *hwc)
1176 {
1177 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
1178 u64 ctrl_val, mask;
1179
1180 mask = 0xfULL << (idx * 4);
1181
1182 rdmsrl(hwc->config_base, ctrl_val);
1183 ctrl_val &= ~mask;
1184 wrmsrl(hwc->config_base, ctrl_val);
1185 }
1186
1187 static void intel_pmu_disable_event(struct perf_event *event)
1188 {
1189 struct hw_perf_event *hwc = &event->hw;
1190 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1191
1192 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
1193 intel_pmu_disable_bts();
1194 intel_pmu_drain_bts_buffer();
1195 return;
1196 }
1197
1198 cpuc->intel_ctrl_guest_mask &= ~(1ull << hwc->idx);
1199 cpuc->intel_ctrl_host_mask &= ~(1ull << hwc->idx);
1200
1201 /*
1202 * must disable before any actual event
1203 * because any event may be combined with LBR
1204 */
1205 if (intel_pmu_needs_lbr_smpl(event))
1206 intel_pmu_lbr_disable(event);
1207
1208 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
1209 intel_pmu_disable_fixed(hwc);
1210 return;
1211 }
1212
1213 x86_pmu_disable_event(event);
1214
1215 if (unlikely(event->attr.precise_ip))
1216 intel_pmu_pebs_disable(event);
1217 }
1218
1219 static void intel_pmu_enable_fixed(struct hw_perf_event *hwc)
1220 {
1221 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
1222 u64 ctrl_val, bits, mask;
1223
1224 /*
1225 * Enable IRQ generation (0x8),
1226 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
1227 * if requested:
1228 */
1229 bits = 0x8ULL;
1230 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
1231 bits |= 0x2;
1232 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
1233 bits |= 0x1;
1234
1235 /*
1236 * ANY bit is supported in v3 and up
1237 */
1238 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
1239 bits |= 0x4;
1240
1241 bits <<= (idx * 4);
1242 mask = 0xfULL << (idx * 4);
1243
1244 rdmsrl(hwc->config_base, ctrl_val);
1245 ctrl_val &= ~mask;
1246 ctrl_val |= bits;
1247 wrmsrl(hwc->config_base, ctrl_val);
1248 }
1249
1250 static void intel_pmu_enable_event(struct perf_event *event)
1251 {
1252 struct hw_perf_event *hwc = &event->hw;
1253 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1254
1255 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
1256 if (!__this_cpu_read(cpu_hw_events.enabled))
1257 return;
1258
1259 intel_pmu_enable_bts(hwc->config);
1260 return;
1261 }
1262 /*
1263 * must enabled before any actual event
1264 * because any event may be combined with LBR
1265 */
1266 if (intel_pmu_needs_lbr_smpl(event))
1267 intel_pmu_lbr_enable(event);
1268
1269 if (event->attr.exclude_host)
1270 cpuc->intel_ctrl_guest_mask |= (1ull << hwc->idx);
1271 if (event->attr.exclude_guest)
1272 cpuc->intel_ctrl_host_mask |= (1ull << hwc->idx);
1273
1274 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
1275 intel_pmu_enable_fixed(hwc);
1276 return;
1277 }
1278
1279 if (unlikely(event->attr.precise_ip))
1280 intel_pmu_pebs_enable(event);
1281
1282 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
1283 }
1284
1285 /*
1286 * Save and restart an expired event. Called by NMI contexts,
1287 * so it has to be careful about preempting normal event ops:
1288 */
1289 int intel_pmu_save_and_restart(struct perf_event *event)
1290 {
1291 x86_perf_event_update(event);
1292 return x86_perf_event_set_period(event);
1293 }
1294
1295 static void intel_pmu_reset(void)
1296 {
1297 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
1298 unsigned long flags;
1299 int idx;
1300
1301 if (!x86_pmu.num_counters)
1302 return;
1303
1304 local_irq_save(flags);
1305
1306 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
1307
1308 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1309 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull);
1310 wrmsrl_safe(x86_pmu_event_addr(idx), 0ull);
1311 }
1312 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++)
1313 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
1314
1315 if (ds)
1316 ds->bts_index = ds->bts_buffer_base;
1317
1318 local_irq_restore(flags);
1319 }
1320
1321 /*
1322 * This handler is triggered by the local APIC, so the APIC IRQ handling
1323 * rules apply:
1324 */
1325 static int intel_pmu_handle_irq(struct pt_regs *regs)
1326 {
1327 struct perf_sample_data data;
1328 struct cpu_hw_events *cpuc;
1329 int bit, loops;
1330 u64 status;
1331 int handled;
1332
1333 cpuc = &__get_cpu_var(cpu_hw_events);
1334
1335 /*
1336 * No known reason to not always do late ACK,
1337 * but just in case do it opt-in.
1338 */
1339 if (!x86_pmu.late_ack)
1340 apic_write(APIC_LVTPC, APIC_DM_NMI);
1341 intel_pmu_disable_all();
1342 handled = intel_pmu_drain_bts_buffer();
1343 status = intel_pmu_get_status();
1344 if (!status) {
1345 intel_pmu_enable_all(0);
1346 return handled;
1347 }
1348
1349 loops = 0;
1350 again:
1351 intel_pmu_ack_status(status);
1352 if (++loops > 100) {
1353 static bool warned = false;
1354 if (!warned) {
1355 WARN(1, "perfevents: irq loop stuck!\n");
1356 perf_event_print_debug();
1357 warned = true;
1358 }
1359 intel_pmu_reset();
1360 goto done;
1361 }
1362
1363 inc_irq_stat(apic_perf_irqs);
1364
1365 intel_pmu_lbr_read();
1366
1367 /*
1368 * CondChgd bit 63 doesn't mean any overflow status. Ignore
1369 * and clear the bit.
1370 */
1371 if (__test_and_clear_bit(63, (unsigned long *)&status)) {
1372 if (!status)
1373 goto done;
1374 }
1375
1376 /*
1377 * PEBS overflow sets bit 62 in the global status register
1378 */
1379 if (__test_and_clear_bit(62, (unsigned long *)&status)) {
1380 handled++;
1381 x86_pmu.drain_pebs(regs);
1382 }
1383
1384 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
1385 struct perf_event *event = cpuc->events[bit];
1386
1387 handled++;
1388
1389 if (!test_bit(bit, cpuc->active_mask))
1390 continue;
1391
1392 if (!intel_pmu_save_and_restart(event))
1393 continue;
1394
1395 perf_sample_data_init(&data, 0, event->hw.last_period);
1396
1397 if (has_branch_stack(event))
1398 data.br_stack = &cpuc->lbr_stack;
1399
1400 if (perf_event_overflow(event, &data, regs))
1401 x86_pmu_stop(event, 0);
1402 }
1403
1404 /*
1405 * Repeat if there is more work to be done:
1406 */
1407 status = intel_pmu_get_status();
1408 if (status)
1409 goto again;
1410
1411 done:
1412 intel_pmu_enable_all(0);
1413 /*
1414 * Only unmask the NMI after the overflow counters
1415 * have been reset. This avoids spurious NMIs on
1416 * Haswell CPUs.
1417 */
1418 if (x86_pmu.late_ack)
1419 apic_write(APIC_LVTPC, APIC_DM_NMI);
1420 return handled;
1421 }
1422
1423 static struct event_constraint *
1424 intel_bts_constraints(struct perf_event *event)
1425 {
1426 struct hw_perf_event *hwc = &event->hw;
1427 unsigned int hw_event, bts_event;
1428
1429 if (event->attr.freq)
1430 return NULL;
1431
1432 hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
1433 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
1434
1435 if (unlikely(hw_event == bts_event && hwc->sample_period == 1))
1436 return &bts_constraint;
1437
1438 return NULL;
1439 }
1440
1441 static int intel_alt_er(int idx)
1442 {
1443 if (!(x86_pmu.er_flags & ERF_HAS_RSP_1))
1444 return idx;
1445
1446 if (idx == EXTRA_REG_RSP_0)
1447 return EXTRA_REG_RSP_1;
1448
1449 if (idx == EXTRA_REG_RSP_1)
1450 return EXTRA_REG_RSP_0;
1451
1452 return idx;
1453 }
1454
1455 static void intel_fixup_er(struct perf_event *event, int idx)
1456 {
1457 event->hw.extra_reg.idx = idx;
1458
1459 if (idx == EXTRA_REG_RSP_0) {
1460 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
1461 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_0].event;
1462 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
1463 } else if (idx == EXTRA_REG_RSP_1) {
1464 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
1465 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_1].event;
1466 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
1467 }
1468 }
1469
1470 /*
1471 * manage allocation of shared extra msr for certain events
1472 *
1473 * sharing can be:
1474 * per-cpu: to be shared between the various events on a single PMU
1475 * per-core: per-cpu + shared by HT threads
1476 */
1477 static struct event_constraint *
1478 __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
1479 struct perf_event *event,
1480 struct hw_perf_event_extra *reg)
1481 {
1482 struct event_constraint *c = &emptyconstraint;
1483 struct er_account *era;
1484 unsigned long flags;
1485 int idx = reg->idx;
1486
1487 /*
1488 * reg->alloc can be set due to existing state, so for fake cpuc we
1489 * need to ignore this, otherwise we might fail to allocate proper fake
1490 * state for this extra reg constraint. Also see the comment below.
1491 */
1492 if (reg->alloc && !cpuc->is_fake)
1493 return NULL; /* call x86_get_event_constraint() */
1494
1495 again:
1496 era = &cpuc->shared_regs->regs[idx];
1497 /*
1498 * we use spin_lock_irqsave() to avoid lockdep issues when
1499 * passing a fake cpuc
1500 */
1501 raw_spin_lock_irqsave(&era->lock, flags);
1502
1503 if (!atomic_read(&era->ref) || era->config == reg->config) {
1504
1505 /*
1506 * If its a fake cpuc -- as per validate_{group,event}() we
1507 * shouldn't touch event state and we can avoid doing so
1508 * since both will only call get_event_constraints() once
1509 * on each event, this avoids the need for reg->alloc.
1510 *
1511 * Not doing the ER fixup will only result in era->reg being
1512 * wrong, but since we won't actually try and program hardware
1513 * this isn't a problem either.
1514 */
1515 if (!cpuc->is_fake) {
1516 if (idx != reg->idx)
1517 intel_fixup_er(event, idx);
1518
1519 /*
1520 * x86_schedule_events() can call get_event_constraints()
1521 * multiple times on events in the case of incremental
1522 * scheduling(). reg->alloc ensures we only do the ER
1523 * allocation once.
1524 */
1525 reg->alloc = 1;
1526 }
1527
1528 /* lock in msr value */
1529 era->config = reg->config;
1530 era->reg = reg->reg;
1531
1532 /* one more user */
1533 atomic_inc(&era->ref);
1534
1535 /*
1536 * need to call x86_get_event_constraint()
1537 * to check if associated event has constraints
1538 */
1539 c = NULL;
1540 } else {
1541 idx = intel_alt_er(idx);
1542 if (idx != reg->idx) {
1543 raw_spin_unlock_irqrestore(&era->lock, flags);
1544 goto again;
1545 }
1546 }
1547 raw_spin_unlock_irqrestore(&era->lock, flags);
1548
1549 return c;
1550 }
1551
1552 static void
1553 __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
1554 struct hw_perf_event_extra *reg)
1555 {
1556 struct er_account *era;
1557
1558 /*
1559 * Only put constraint if extra reg was actually allocated. Also takes
1560 * care of event which do not use an extra shared reg.
1561 *
1562 * Also, if this is a fake cpuc we shouldn't touch any event state
1563 * (reg->alloc) and we don't care about leaving inconsistent cpuc state
1564 * either since it'll be thrown out.
1565 */
1566 if (!reg->alloc || cpuc->is_fake)
1567 return;
1568
1569 era = &cpuc->shared_regs->regs[reg->idx];
1570
1571 /* one fewer user */
1572 atomic_dec(&era->ref);
1573
1574 /* allocate again next time */
1575 reg->alloc = 0;
1576 }
1577
1578 static struct event_constraint *
1579 intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
1580 struct perf_event *event)
1581 {
1582 struct event_constraint *c = NULL, *d;
1583 struct hw_perf_event_extra *xreg, *breg;
1584
1585 xreg = &event->hw.extra_reg;
1586 if (xreg->idx != EXTRA_REG_NONE) {
1587 c = __intel_shared_reg_get_constraints(cpuc, event, xreg);
1588 if (c == &emptyconstraint)
1589 return c;
1590 }
1591 breg = &event->hw.branch_reg;
1592 if (breg->idx != EXTRA_REG_NONE) {
1593 d = __intel_shared_reg_get_constraints(cpuc, event, breg);
1594 if (d == &emptyconstraint) {
1595 __intel_shared_reg_put_constraints(cpuc, xreg);
1596 c = d;
1597 }
1598 }
1599 return c;
1600 }
1601
1602 struct event_constraint *
1603 x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1604 {
1605 struct event_constraint *c;
1606
1607 if (x86_pmu.event_constraints) {
1608 for_each_event_constraint(c, x86_pmu.event_constraints) {
1609 if ((event->hw.config & c->cmask) == c->code) {
1610 event->hw.flags |= c->flags;
1611 return c;
1612 }
1613 }
1614 }
1615
1616 return &unconstrained;
1617 }
1618
1619 static struct event_constraint *
1620 intel_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1621 {
1622 struct event_constraint *c;
1623
1624 c = intel_bts_constraints(event);
1625 if (c)
1626 return c;
1627
1628 c = intel_pebs_constraints(event);
1629 if (c)
1630 return c;
1631
1632 c = intel_shared_regs_constraints(cpuc, event);
1633 if (c)
1634 return c;
1635
1636 return x86_get_event_constraints(cpuc, event);
1637 }
1638
1639 static void
1640 intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
1641 struct perf_event *event)
1642 {
1643 struct hw_perf_event_extra *reg;
1644
1645 reg = &event->hw.extra_reg;
1646 if (reg->idx != EXTRA_REG_NONE)
1647 __intel_shared_reg_put_constraints(cpuc, reg);
1648
1649 reg = &event->hw.branch_reg;
1650 if (reg->idx != EXTRA_REG_NONE)
1651 __intel_shared_reg_put_constraints(cpuc, reg);
1652 }
1653
1654 static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
1655 struct perf_event *event)
1656 {
1657 intel_put_shared_regs_event_constraints(cpuc, event);
1658 }
1659
1660 static void intel_pebs_aliases_core2(struct perf_event *event)
1661 {
1662 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
1663 /*
1664 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
1665 * (0x003c) so that we can use it with PEBS.
1666 *
1667 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
1668 * PEBS capable. However we can use INST_RETIRED.ANY_P
1669 * (0x00c0), which is a PEBS capable event, to get the same
1670 * count.
1671 *
1672 * INST_RETIRED.ANY_P counts the number of cycles that retires
1673 * CNTMASK instructions. By setting CNTMASK to a value (16)
1674 * larger than the maximum number of instructions that can be
1675 * retired per cycle (4) and then inverting the condition, we
1676 * count all cycles that retire 16 or less instructions, which
1677 * is every cycle.
1678 *
1679 * Thereby we gain a PEBS capable cycle counter.
1680 */
1681 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
1682
1683 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
1684 event->hw.config = alt_config;
1685 }
1686 }
1687
1688 static void intel_pebs_aliases_snb(struct perf_event *event)
1689 {
1690 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
1691 /*
1692 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
1693 * (0x003c) so that we can use it with PEBS.
1694 *
1695 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
1696 * PEBS capable. However we can use UOPS_RETIRED.ALL
1697 * (0x01c2), which is a PEBS capable event, to get the same
1698 * count.
1699 *
1700 * UOPS_RETIRED.ALL counts the number of cycles that retires
1701 * CNTMASK micro-ops. By setting CNTMASK to a value (16)
1702 * larger than the maximum number of micro-ops that can be
1703 * retired per cycle (4) and then inverting the condition, we
1704 * count all cycles that retire 16 or less micro-ops, which
1705 * is every cycle.
1706 *
1707 * Thereby we gain a PEBS capable cycle counter.
1708 */
1709 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16);
1710
1711 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
1712 event->hw.config = alt_config;
1713 }
1714 }
1715
1716 static int intel_pmu_hw_config(struct perf_event *event)
1717 {
1718 int ret = x86_pmu_hw_config(event);
1719
1720 if (ret)
1721 return ret;
1722
1723 if (event->attr.precise_ip && x86_pmu.pebs_aliases)
1724 x86_pmu.pebs_aliases(event);
1725
1726 if (intel_pmu_needs_lbr_smpl(event)) {
1727 ret = intel_pmu_setup_lbr_filter(event);
1728 if (ret)
1729 return ret;
1730 }
1731
1732 if (event->attr.type != PERF_TYPE_RAW)
1733 return 0;
1734
1735 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
1736 return 0;
1737
1738 if (x86_pmu.version < 3)
1739 return -EINVAL;
1740
1741 if (perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN))
1742 return -EACCES;
1743
1744 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
1745
1746 return 0;
1747 }
1748
1749 struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
1750 {
1751 if (x86_pmu.guest_get_msrs)
1752 return x86_pmu.guest_get_msrs(nr);
1753 *nr = 0;
1754 return NULL;
1755 }
1756 EXPORT_SYMBOL_GPL(perf_guest_get_msrs);
1757
1758 static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr)
1759 {
1760 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1761 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
1762
1763 arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL;
1764 arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask;
1765 arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask;
1766 /*
1767 * If PMU counter has PEBS enabled it is not enough to disable counter
1768 * on a guest entry since PEBS memory write can overshoot guest entry
1769 * and corrupt guest memory. Disabling PEBS solves the problem.
1770 */
1771 arr[1].msr = MSR_IA32_PEBS_ENABLE;
1772 arr[1].host = cpuc->pebs_enabled;
1773 arr[1].guest = 0;
1774
1775 *nr = 2;
1776 return arr;
1777 }
1778
1779 static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr)
1780 {
1781 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1782 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
1783 int idx;
1784
1785 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1786 struct perf_event *event = cpuc->events[idx];
1787
1788 arr[idx].msr = x86_pmu_config_addr(idx);
1789 arr[idx].host = arr[idx].guest = 0;
1790
1791 if (!test_bit(idx, cpuc->active_mask))
1792 continue;
1793
1794 arr[idx].host = arr[idx].guest =
1795 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
1796
1797 if (event->attr.exclude_host)
1798 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
1799 else if (event->attr.exclude_guest)
1800 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
1801 }
1802
1803 *nr = x86_pmu.num_counters;
1804 return arr;
1805 }
1806
1807 static void core_pmu_enable_event(struct perf_event *event)
1808 {
1809 if (!event->attr.exclude_host)
1810 x86_pmu_enable_event(event);
1811 }
1812
1813 static void core_pmu_enable_all(int added)
1814 {
1815 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1816 int idx;
1817
1818 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1819 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
1820
1821 if (!test_bit(idx, cpuc->active_mask) ||
1822 cpuc->events[idx]->attr.exclude_host)
1823 continue;
1824
1825 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
1826 }
1827 }
1828
1829 static int hsw_hw_config(struct perf_event *event)
1830 {
1831 int ret = intel_pmu_hw_config(event);
1832
1833 if (ret)
1834 return ret;
1835 if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE))
1836 return 0;
1837 event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED);
1838
1839 /*
1840 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with
1841 * PEBS or in ANY thread mode. Since the results are non-sensical forbid
1842 * this combination.
1843 */
1844 if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) &&
1845 ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) ||
1846 event->attr.precise_ip > 0))
1847 return -EOPNOTSUPP;
1848
1849 return 0;
1850 }
1851
1852 static struct event_constraint counter2_constraint =
1853 EVENT_CONSTRAINT(0, 0x4, 0);
1854
1855 static struct event_constraint *
1856 hsw_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1857 {
1858 struct event_constraint *c = intel_get_event_constraints(cpuc, event);
1859
1860 /* Handle special quirk on in_tx_checkpointed only in counter 2 */
1861 if (event->hw.config & HSW_IN_TX_CHECKPOINTED) {
1862 if (c->idxmsk64 & (1U << 2))
1863 return &counter2_constraint;
1864 return &emptyconstraint;
1865 }
1866
1867 return c;
1868 }
1869
1870 PMU_FORMAT_ATTR(event, "config:0-7" );
1871 PMU_FORMAT_ATTR(umask, "config:8-15" );
1872 PMU_FORMAT_ATTR(edge, "config:18" );
1873 PMU_FORMAT_ATTR(pc, "config:19" );
1874 PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */
1875 PMU_FORMAT_ATTR(inv, "config:23" );
1876 PMU_FORMAT_ATTR(cmask, "config:24-31" );
1877 PMU_FORMAT_ATTR(in_tx, "config:32");
1878 PMU_FORMAT_ATTR(in_tx_cp, "config:33");
1879
1880 static struct attribute *intel_arch_formats_attr[] = {
1881 &format_attr_event.attr,
1882 &format_attr_umask.attr,
1883 &format_attr_edge.attr,
1884 &format_attr_pc.attr,
1885 &format_attr_inv.attr,
1886 &format_attr_cmask.attr,
1887 NULL,
1888 };
1889
1890 ssize_t intel_event_sysfs_show(char *page, u64 config)
1891 {
1892 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT);
1893
1894 return x86_event_sysfs_show(page, config, event);
1895 }
1896
1897 static __initconst const struct x86_pmu core_pmu = {
1898 .name = "core",
1899 .handle_irq = x86_pmu_handle_irq,
1900 .disable_all = x86_pmu_disable_all,
1901 .enable_all = core_pmu_enable_all,
1902 .enable = core_pmu_enable_event,
1903 .disable = x86_pmu_disable_event,
1904 .hw_config = x86_pmu_hw_config,
1905 .schedule_events = x86_schedule_events,
1906 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
1907 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
1908 .event_map = intel_pmu_event_map,
1909 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
1910 .apic = 1,
1911 /*
1912 * Intel PMCs cannot be accessed sanely above 32 bit width,
1913 * so we install an artificial 1<<31 period regardless of
1914 * the generic event period:
1915 */
1916 .max_period = (1ULL << 31) - 1,
1917 .get_event_constraints = intel_get_event_constraints,
1918 .put_event_constraints = intel_put_event_constraints,
1919 .event_constraints = intel_core_event_constraints,
1920 .guest_get_msrs = core_guest_get_msrs,
1921 .format_attrs = intel_arch_formats_attr,
1922 .events_sysfs_show = intel_event_sysfs_show,
1923 };
1924
1925 struct intel_shared_regs *allocate_shared_regs(int cpu)
1926 {
1927 struct intel_shared_regs *regs;
1928 int i;
1929
1930 regs = kzalloc_node(sizeof(struct intel_shared_regs),
1931 GFP_KERNEL, cpu_to_node(cpu));
1932 if (regs) {
1933 /*
1934 * initialize the locks to keep lockdep happy
1935 */
1936 for (i = 0; i < EXTRA_REG_MAX; i++)
1937 raw_spin_lock_init(&regs->regs[i].lock);
1938
1939 regs->core_id = -1;
1940 }
1941 return regs;
1942 }
1943
1944 static int intel_pmu_cpu_prepare(int cpu)
1945 {
1946 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1947
1948 if (!(x86_pmu.extra_regs || x86_pmu.lbr_sel_map))
1949 return NOTIFY_OK;
1950
1951 cpuc->shared_regs = allocate_shared_regs(cpu);
1952 if (!cpuc->shared_regs)
1953 return NOTIFY_BAD;
1954
1955 return NOTIFY_OK;
1956 }
1957
1958 static void intel_pmu_cpu_starting(int cpu)
1959 {
1960 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1961 int core_id = topology_core_id(cpu);
1962 int i;
1963
1964 init_debug_store_on_cpu(cpu);
1965 /*
1966 * Deal with CPUs that don't clear their LBRs on power-up.
1967 */
1968 intel_pmu_lbr_reset();
1969
1970 cpuc->lbr_sel = NULL;
1971
1972 if (!cpuc->shared_regs)
1973 return;
1974
1975 if (!(x86_pmu.er_flags & ERF_NO_HT_SHARING)) {
1976 for_each_cpu(i, topology_thread_cpumask(cpu)) {
1977 struct intel_shared_regs *pc;
1978
1979 pc = per_cpu(cpu_hw_events, i).shared_regs;
1980 if (pc && pc->core_id == core_id) {
1981 cpuc->kfree_on_online = cpuc->shared_regs;
1982 cpuc->shared_regs = pc;
1983 break;
1984 }
1985 }
1986 cpuc->shared_regs->core_id = core_id;
1987 cpuc->shared_regs->refcnt++;
1988 }
1989
1990 if (x86_pmu.lbr_sel_map)
1991 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
1992 }
1993
1994 static void intel_pmu_cpu_dying(int cpu)
1995 {
1996 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1997 struct intel_shared_regs *pc;
1998
1999 pc = cpuc->shared_regs;
2000 if (pc) {
2001 if (pc->core_id == -1 || --pc->refcnt == 0)
2002 kfree(pc);
2003 cpuc->shared_regs = NULL;
2004 }
2005
2006 fini_debug_store_on_cpu(cpu);
2007 }
2008
2009 static void intel_pmu_flush_branch_stack(void)
2010 {
2011 /*
2012 * Intel LBR does not tag entries with the
2013 * PID of the current task, then we need to
2014 * flush it on ctxsw
2015 * For now, we simply reset it
2016 */
2017 if (x86_pmu.lbr_nr)
2018 intel_pmu_lbr_reset();
2019 }
2020
2021 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
2022
2023 PMU_FORMAT_ATTR(ldlat, "config1:0-15");
2024
2025 static struct attribute *intel_arch3_formats_attr[] = {
2026 &format_attr_event.attr,
2027 &format_attr_umask.attr,
2028 &format_attr_edge.attr,
2029 &format_attr_pc.attr,
2030 &format_attr_any.attr,
2031 &format_attr_inv.attr,
2032 &format_attr_cmask.attr,
2033 &format_attr_in_tx.attr,
2034 &format_attr_in_tx_cp.attr,
2035
2036 &format_attr_offcore_rsp.attr, /* XXX do NHM/WSM + SNB breakout */
2037 &format_attr_ldlat.attr, /* PEBS load latency */
2038 NULL,
2039 };
2040
2041 static __initconst const struct x86_pmu intel_pmu = {
2042 .name = "Intel",
2043 .handle_irq = intel_pmu_handle_irq,
2044 .disable_all = intel_pmu_disable_all,
2045 .enable_all = intel_pmu_enable_all,
2046 .enable = intel_pmu_enable_event,
2047 .disable = intel_pmu_disable_event,
2048 .hw_config = intel_pmu_hw_config,
2049 .schedule_events = x86_schedule_events,
2050 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
2051 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
2052 .event_map = intel_pmu_event_map,
2053 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
2054 .apic = 1,
2055 /*
2056 * Intel PMCs cannot be accessed sanely above 32 bit width,
2057 * so we install an artificial 1<<31 period regardless of
2058 * the generic event period:
2059 */
2060 .max_period = (1ULL << 31) - 1,
2061 .get_event_constraints = intel_get_event_constraints,
2062 .put_event_constraints = intel_put_event_constraints,
2063 .pebs_aliases = intel_pebs_aliases_core2,
2064
2065 .format_attrs = intel_arch3_formats_attr,
2066 .events_sysfs_show = intel_event_sysfs_show,
2067
2068 .cpu_prepare = intel_pmu_cpu_prepare,
2069 .cpu_starting = intel_pmu_cpu_starting,
2070 .cpu_dying = intel_pmu_cpu_dying,
2071 .guest_get_msrs = intel_guest_get_msrs,
2072 .flush_branch_stack = intel_pmu_flush_branch_stack,
2073 };
2074
2075 static __init void intel_clovertown_quirk(void)
2076 {
2077 /*
2078 * PEBS is unreliable due to:
2079 *
2080 * AJ67 - PEBS may experience CPL leaks
2081 * AJ68 - PEBS PMI may be delayed by one event
2082 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
2083 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
2084 *
2085 * AJ67 could be worked around by restricting the OS/USR flags.
2086 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
2087 *
2088 * AJ106 could possibly be worked around by not allowing LBR
2089 * usage from PEBS, including the fixup.
2090 * AJ68 could possibly be worked around by always programming
2091 * a pebs_event_reset[0] value and coping with the lost events.
2092 *
2093 * But taken together it might just make sense to not enable PEBS on
2094 * these chips.
2095 */
2096 pr_warn("PEBS disabled due to CPU errata\n");
2097 x86_pmu.pebs = 0;
2098 x86_pmu.pebs_constraints = NULL;
2099 }
2100
2101 static int intel_snb_pebs_broken(int cpu)
2102 {
2103 u32 rev = UINT_MAX; /* default to broken for unknown models */
2104
2105 switch (cpu_data(cpu).x86_model) {
2106 case 42: /* SNB */
2107 rev = 0x28;
2108 break;
2109
2110 case 45: /* SNB-EP */
2111 switch (cpu_data(cpu).x86_mask) {
2112 case 6: rev = 0x618; break;
2113 case 7: rev = 0x70c; break;
2114 }
2115 }
2116
2117 return (cpu_data(cpu).microcode < rev);
2118 }
2119
2120 static void intel_snb_check_microcode(void)
2121 {
2122 int pebs_broken = 0;
2123 int cpu;
2124
2125 get_online_cpus();
2126 for_each_online_cpu(cpu) {
2127 if ((pebs_broken = intel_snb_pebs_broken(cpu)))
2128 break;
2129 }
2130 put_online_cpus();
2131
2132 if (pebs_broken == x86_pmu.pebs_broken)
2133 return;
2134
2135 /*
2136 * Serialized by the microcode lock..
2137 */
2138 if (x86_pmu.pebs_broken) {
2139 pr_info("PEBS enabled due to microcode update\n");
2140 x86_pmu.pebs_broken = 0;
2141 } else {
2142 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n");
2143 x86_pmu.pebs_broken = 1;
2144 }
2145 }
2146
2147 static __init void intel_sandybridge_quirk(void)
2148 {
2149 x86_pmu.check_microcode = intel_snb_check_microcode;
2150 intel_snb_check_microcode();
2151 }
2152
2153 static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
2154 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
2155 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
2156 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" },
2157 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" },
2158 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" },
2159 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" },
2160 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" },
2161 };
2162
2163 static __init void intel_arch_events_quirk(void)
2164 {
2165 int bit;
2166
2167 /* disable event that reported as not presend by cpuid */
2168 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
2169 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
2170 pr_warn("CPUID marked event: \'%s\' unavailable\n",
2171 intel_arch_events_map[bit].name);
2172 }
2173 }
2174
2175 static __init void intel_nehalem_quirk(void)
2176 {
2177 union cpuid10_ebx ebx;
2178
2179 ebx.full = x86_pmu.events_maskl;
2180 if (ebx.split.no_branch_misses_retired) {
2181 /*
2182 * Erratum AAJ80 detected, we work it around by using
2183 * the BR_MISP_EXEC.ANY event. This will over-count
2184 * branch-misses, but it's still much better than the
2185 * architectural event which is often completely bogus:
2186 */
2187 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
2188 ebx.split.no_branch_misses_retired = 0;
2189 x86_pmu.events_maskl = ebx.full;
2190 pr_info("CPU erratum AAJ80 worked around\n");
2191 }
2192 }
2193
2194 EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3");
2195 EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82")
2196
2197 static struct attribute *hsw_events_attrs[] = {
2198 EVENT_PTR(mem_ld_hsw),
2199 EVENT_PTR(mem_st_hsw),
2200 NULL
2201 };
2202
2203 __init int intel_pmu_init(void)
2204 {
2205 union cpuid10_edx edx;
2206 union cpuid10_eax eax;
2207 union cpuid10_ebx ebx;
2208 struct event_constraint *c;
2209 unsigned int unused;
2210 int version;
2211
2212 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
2213 switch (boot_cpu_data.x86) {
2214 case 0x6:
2215 return p6_pmu_init();
2216 case 0xb:
2217 return knc_pmu_init();
2218 case 0xf:
2219 return p4_pmu_init();
2220 }
2221 return -ENODEV;
2222 }
2223
2224 /*
2225 * Check whether the Architectural PerfMon supports
2226 * Branch Misses Retired hw_event or not.
2227 */
2228 cpuid(10, &eax.full, &ebx.full, &unused, &edx.full);
2229 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
2230 return -ENODEV;
2231
2232 version = eax.split.version_id;
2233 if (version < 2)
2234 x86_pmu = core_pmu;
2235 else
2236 x86_pmu = intel_pmu;
2237
2238 x86_pmu.version = version;
2239 x86_pmu.num_counters = eax.split.num_counters;
2240 x86_pmu.cntval_bits = eax.split.bit_width;
2241 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1;
2242
2243 x86_pmu.events_maskl = ebx.full;
2244 x86_pmu.events_mask_len = eax.split.mask_length;
2245
2246 x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters);
2247
2248 /*
2249 * Quirk: v2 perfmon does not report fixed-purpose events, so
2250 * assume at least 3 events:
2251 */
2252 if (version > 1)
2253 x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3);
2254
2255 /*
2256 * v2 and above have a perf capabilities MSR
2257 */
2258 if (version > 1) {
2259 u64 capabilities;
2260
2261 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
2262 x86_pmu.intel_cap.capabilities = capabilities;
2263 }
2264
2265 intel_ds_init();
2266
2267 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
2268
2269 /*
2270 * Install the hw-cache-events table:
2271 */
2272 switch (boot_cpu_data.x86_model) {
2273 case 14: /* 65 nm core solo/duo, "Yonah" */
2274 pr_cont("Core events, ");
2275 break;
2276
2277 case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
2278 x86_add_quirk(intel_clovertown_quirk);
2279 case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
2280 case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
2281 case 29: /* six-core 45 nm xeon "Dunnington" */
2282 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
2283 sizeof(hw_cache_event_ids));
2284
2285 intel_pmu_lbr_init_core();
2286
2287 x86_pmu.event_constraints = intel_core2_event_constraints;
2288 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
2289 pr_cont("Core2 events, ");
2290 break;
2291
2292 case 26: /* 45 nm nehalem, "Bloomfield" */
2293 case 30: /* 45 nm nehalem, "Lynnfield" */
2294 case 46: /* 45 nm nehalem-ex, "Beckton" */
2295 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
2296 sizeof(hw_cache_event_ids));
2297 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
2298 sizeof(hw_cache_extra_regs));
2299
2300 intel_pmu_lbr_init_nhm();
2301
2302 x86_pmu.event_constraints = intel_nehalem_event_constraints;
2303 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
2304 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
2305 x86_pmu.extra_regs = intel_nehalem_extra_regs;
2306
2307 x86_pmu.cpu_events = nhm_events_attrs;
2308
2309 /* UOPS_ISSUED.STALLED_CYCLES */
2310 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2311 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
2312 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
2313 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
2314 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
2315
2316 x86_add_quirk(intel_nehalem_quirk);
2317
2318 pr_cont("Nehalem events, ");
2319 break;
2320
2321 case 28: /* Atom */
2322 case 38: /* Lincroft */
2323 case 39: /* Penwell */
2324 case 53: /* Cloverview */
2325 case 54: /* Cedarview */
2326 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
2327 sizeof(hw_cache_event_ids));
2328
2329 intel_pmu_lbr_init_atom();
2330
2331 x86_pmu.event_constraints = intel_gen_event_constraints;
2332 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
2333 pr_cont("Atom events, ");
2334 break;
2335
2336 case 55: /* Atom 22nm "Silvermont" */
2337 case 77: /* Avoton "Silvermont" */
2338 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
2339 sizeof(hw_cache_event_ids));
2340 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,
2341 sizeof(hw_cache_extra_regs));
2342
2343 intel_pmu_lbr_init_atom();
2344
2345 x86_pmu.event_constraints = intel_slm_event_constraints;
2346 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
2347 x86_pmu.extra_regs = intel_slm_extra_regs;
2348 x86_pmu.er_flags |= ERF_HAS_RSP_1;
2349 pr_cont("Silvermont events, ");
2350 break;
2351
2352 case 37: /* 32 nm nehalem, "Clarkdale" */
2353 case 44: /* 32 nm nehalem, "Gulftown" */
2354 case 47: /* 32 nm Xeon E7 */
2355 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
2356 sizeof(hw_cache_event_ids));
2357 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
2358 sizeof(hw_cache_extra_regs));
2359
2360 intel_pmu_lbr_init_nhm();
2361
2362 x86_pmu.event_constraints = intel_westmere_event_constraints;
2363 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
2364 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
2365 x86_pmu.extra_regs = intel_westmere_extra_regs;
2366 x86_pmu.er_flags |= ERF_HAS_RSP_1;
2367
2368 x86_pmu.cpu_events = nhm_events_attrs;
2369
2370 /* UOPS_ISSUED.STALLED_CYCLES */
2371 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2372 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
2373 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
2374 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
2375 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
2376
2377 pr_cont("Westmere events, ");
2378 break;
2379
2380 case 42: /* SandyBridge */
2381 case 45: /* SandyBridge, "Romely-EP" */
2382 x86_add_quirk(intel_sandybridge_quirk);
2383 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
2384 sizeof(hw_cache_event_ids));
2385 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
2386 sizeof(hw_cache_extra_regs));
2387
2388 intel_pmu_lbr_init_snb();
2389
2390 x86_pmu.event_constraints = intel_snb_event_constraints;
2391 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
2392 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
2393 if (boot_cpu_data.x86_model == 45)
2394 x86_pmu.extra_regs = intel_snbep_extra_regs;
2395 else
2396 x86_pmu.extra_regs = intel_snb_extra_regs;
2397 /* all extra regs are per-cpu when HT is on */
2398 x86_pmu.er_flags |= ERF_HAS_RSP_1;
2399 x86_pmu.er_flags |= ERF_NO_HT_SHARING;
2400
2401 x86_pmu.cpu_events = snb_events_attrs;
2402
2403 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
2404 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2405 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
2406 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
2407 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
2408 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
2409
2410 pr_cont("SandyBridge events, ");
2411 break;
2412 case 58: /* IvyBridge */
2413 case 62: /* IvyBridge EP */
2414 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
2415 sizeof(hw_cache_event_ids));
2416 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
2417 sizeof(hw_cache_extra_regs));
2418
2419 intel_pmu_lbr_init_snb();
2420
2421 x86_pmu.event_constraints = intel_ivb_event_constraints;
2422 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
2423 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
2424 if (boot_cpu_data.x86_model == 62)
2425 x86_pmu.extra_regs = intel_snbep_extra_regs;
2426 else
2427 x86_pmu.extra_regs = intel_snb_extra_regs;
2428 /* all extra regs are per-cpu when HT is on */
2429 x86_pmu.er_flags |= ERF_HAS_RSP_1;
2430 x86_pmu.er_flags |= ERF_NO_HT_SHARING;
2431
2432 x86_pmu.cpu_events = snb_events_attrs;
2433
2434 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
2435 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2436 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
2437
2438 pr_cont("IvyBridge events, ");
2439 break;
2440
2441
2442 case 60: /* Haswell Client */
2443 case 70:
2444 case 71:
2445 case 63:
2446 case 69:
2447 x86_pmu.late_ack = true;
2448 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, sizeof(hw_cache_event_ids));
2449 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
2450
2451 intel_pmu_lbr_init_snb();
2452
2453 x86_pmu.event_constraints = intel_hsw_event_constraints;
2454 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
2455 x86_pmu.extra_regs = intel_snb_extra_regs;
2456 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
2457 /* all extra regs are per-cpu when HT is on */
2458 x86_pmu.er_flags |= ERF_HAS_RSP_1;
2459 x86_pmu.er_flags |= ERF_NO_HT_SHARING;
2460
2461 x86_pmu.hw_config = hsw_hw_config;
2462 x86_pmu.get_event_constraints = hsw_get_event_constraints;
2463 x86_pmu.cpu_events = hsw_events_attrs;
2464 pr_cont("Haswell events, ");
2465 break;
2466
2467 default:
2468 switch (x86_pmu.version) {
2469 case 1:
2470 x86_pmu.event_constraints = intel_v1_event_constraints;
2471 pr_cont("generic architected perfmon v1, ");
2472 break;
2473 default:
2474 /*
2475 * default constraints for v2 and up
2476 */
2477 x86_pmu.event_constraints = intel_gen_event_constraints;
2478 pr_cont("generic architected perfmon, ");
2479 break;
2480 }
2481 }
2482
2483 if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) {
2484 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
2485 x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC);
2486 x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC;
2487 }
2488 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
2489
2490 if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) {
2491 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
2492 x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED);
2493 x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED;
2494 }
2495
2496 x86_pmu.intel_ctrl |=
2497 ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED;
2498
2499 if (x86_pmu.event_constraints) {
2500 /*
2501 * event on fixed counter2 (REF_CYCLES) only works on this
2502 * counter, so do not extend mask to generic counters
2503 */
2504 for_each_event_constraint(c, x86_pmu.event_constraints) {
2505 if (c->cmask != FIXED_EVENT_FLAGS
2506 || c->idxmsk64 == INTEL_PMC_MSK_FIXED_REF_CYCLES) {
2507 continue;
2508 }
2509
2510 c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
2511 c->weight += x86_pmu.num_counters;
2512 }
2513 }
2514
2515 /* Support full width counters using alternative MSR range */
2516 if (x86_pmu.intel_cap.full_width_write) {
2517 x86_pmu.max_period = x86_pmu.cntval_mask;
2518 x86_pmu.perfctr = MSR_IA32_PMC0;
2519 pr_cont("full-width counters, ");
2520 }
2521
2522 return 0;
2523 }
Linux with added FPC-III support