arch/x86/kernel/irq.c

   1 /*
   2  * Common interrupt code for 32 and 64 bit
   3  */
   4 #include <linux/cpu.h>
   5 #include <linux/interrupt.h>
   6 #include <linux/kernel_stat.h>
   7 #include <linux/of.h>
   8 #include <linux/seq_file.h>
   9 #include <linux/smp.h>
  10 #include <linux/ftrace.h>
  11 #include <linux/delay.h>
  12 #include <linux/export.h>
  13
  14 #include <asm/apic.h>
  15 #include <asm/io_apic.h>
  16 #include <asm/irq.h>
  17 #include <asm/idle.h>
  18 #include <asm/mce.h>
  19 #include <asm/hw_irq.h>
  20
  21 #define CREATE_TRACE_POINTS
  22 #include <asm/trace/irq_vectors.h>
  23
  24 atomic_t irq_err_count;
  25
  26 /* Function pointer for generic interrupt vector handling */
  27 void (*x86_platform_ipi_callback)(void) = NULL;
  28
  29 /*
  30  * 'what should we do if we get a hw irq event on an illegal vector'.
  31  * each architecture has to answer this themselves.
  32  */
  33 void ack_bad_irq(unsigned int irq)
  34 {
  35         if (printk_ratelimit())
  36                 pr_err("unexpected IRQ trap at vector %02x\n", irq);
  37
  38         /*
  39          * Currently unexpected vectors happen only on SMP and APIC.
  40          * We _must_ ack these because every local APIC has only N
  41          * irq slots per priority level, and a 'hanging, unacked' IRQ
  42          * holds up an irq slot - in excessive cases (when multiple
  43          * unexpected vectors occur) that might lock up the APIC
  44          * completely.
  45          * But only ack when the APIC is enabled -AK
  46          */
  47         ack_APIC_irq();
  48 }
  49
  50 #define irq_stats(x)            (&per_cpu(irq_stat, x))
  51 /*
  52  * /proc/interrupts printing for arch specific interrupts
  53  */
  54 int arch_show_interrupts(struct seq_file *p, int prec)
  55 {
  56         int j;
  57
  58         seq_printf(p, "%*s: ", prec, "NMI");
  59         for_each_online_cpu(j)
  60                 seq_printf(p, "%10u ", irq_stats(j)->__nmi_count);
  61         seq_printf(p, "  Non-maskable interrupts\n");
  62 #ifdef CONFIG_X86_LOCAL_APIC
  63         seq_printf(p, "%*s: ", prec, "LOC");
  64         for_each_online_cpu(j)
  65                 seq_printf(p, "%10u ", irq_stats(j)->apic_timer_irqs);
  66         seq_printf(p, "  Local timer interrupts\n");
  67
  68         seq_printf(p, "%*s: ", prec, "SPU");
  69         for_each_online_cpu(j)
  70                 seq_printf(p, "%10u ", irq_stats(j)->irq_spurious_count);
  71         seq_printf(p, "  Spurious interrupts\n");
  72         seq_printf(p, "%*s: ", prec, "PMI");
  73         for_each_online_cpu(j)
  74                 seq_printf(p, "%10u ", irq_stats(j)->apic_perf_irqs);
  75         seq_printf(p, "  Performance monitoring interrupts\n");
  76         seq_printf(p, "%*s: ", prec, "IWI");
  77         for_each_online_cpu(j)
  78                 seq_printf(p, "%10u ", irq_stats(j)->apic_irq_work_irqs);
  79         seq_printf(p, "  IRQ work interrupts\n");
  80         seq_printf(p, "%*s: ", prec, "RTR");
  81         for_each_online_cpu(j)
  82                 seq_printf(p, "%10u ", irq_stats(j)->icr_read_retry_count);
  83         seq_printf(p, "  APIC ICR read retries\n");
  84 #endif
  85         if (x86_platform_ipi_callback) {
  86                 seq_printf(p, "%*s: ", prec, "PLT");
  87                 for_each_online_cpu(j)
  88                         seq_printf(p, "%10u ", irq_stats(j)->x86_platform_ipis);
  89                 seq_printf(p, "  Platform interrupts\n");
  90         }
  91 #ifdef CONFIG_SMP
  92         seq_printf(p, "%*s: ", prec, "RES");
  93         for_each_online_cpu(j)
  94                 seq_printf(p, "%10u ", irq_stats(j)->irq_resched_count);
  95         seq_printf(p, "  Rescheduling interrupts\n");
  96         seq_printf(p, "%*s: ", prec, "CAL");
  97         for_each_online_cpu(j)
  98                 seq_printf(p, "%10u ", irq_stats(j)->irq_call_count -
  99                                         irq_stats(j)->irq_tlb_count);
 100         seq_printf(p, "  Function call interrupts\n");
 101         seq_printf(p, "%*s: ", prec, "TLB");
 102         for_each_online_cpu(j)
 103                 seq_printf(p, "%10u ", irq_stats(j)->irq_tlb_count);
 104         seq_printf(p, "  TLB shootdowns\n");
 105 #endif
 106 #ifdef CONFIG_X86_THERMAL_VECTOR
 107         seq_printf(p, "%*s: ", prec, "TRM");
 108         for_each_online_cpu(j)
 109                 seq_printf(p, "%10u ", irq_stats(j)->irq_thermal_count);
 110         seq_printf(p, "  Thermal event interrupts\n");
 111 #endif
 112 #ifdef CONFIG_X86_MCE_THRESHOLD
 113         seq_printf(p, "%*s: ", prec, "THR");
 114         for_each_online_cpu(j)
 115                 seq_printf(p, "%10u ", irq_stats(j)->irq_threshold_count);
 116         seq_printf(p, "  Threshold APIC interrupts\n");
 117 #endif
 118 #ifdef CONFIG_X86_MCE
 119         seq_printf(p, "%*s: ", prec, "MCE");
 120         for_each_online_cpu(j)
 121                 seq_printf(p, "%10u ", per_cpu(mce_exception_count, j));
 122         seq_printf(p, "  Machine check exceptions\n");
 123         seq_printf(p, "%*s: ", prec, "MCP");
 124         for_each_online_cpu(j)
 125                 seq_printf(p, "%10u ", per_cpu(mce_poll_count, j));
 126         seq_printf(p, "  Machine check polls\n");
 127 #endif
 128         seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count));
 129 #if defined(CONFIG_X86_IO_APIC)
 130         seq_printf(p, "%*s: %10u\n", prec, "MIS", atomic_read(&irq_mis_count));
 131 #endif
 132         return 0;
 133 }
 134
 135 /*
 136  * /proc/stat helpers
 137  */
 138 u64 arch_irq_stat_cpu(unsigned int cpu)
 139 {
 140         u64 sum = irq_stats(cpu)->__nmi_count;
 141
 142 #ifdef CONFIG_X86_LOCAL_APIC
 143         sum += irq_stats(cpu)->apic_timer_irqs;
 144         sum += irq_stats(cpu)->irq_spurious_count;
 145         sum += irq_stats(cpu)->apic_perf_irqs;
 146         sum += irq_stats(cpu)->apic_irq_work_irqs;
 147         sum += irq_stats(cpu)->icr_read_retry_count;
 148 #endif
 149         if (x86_platform_ipi_callback)
 150                 sum += irq_stats(cpu)->x86_platform_ipis;
 151 #ifdef CONFIG_SMP
 152         sum += irq_stats(cpu)->irq_resched_count;
 153         sum += irq_stats(cpu)->irq_call_count;
 154 #endif
 155 #ifdef CONFIG_X86_THERMAL_VECTOR
 156         sum += irq_stats(cpu)->irq_thermal_count;
 157 #endif
 158 #ifdef CONFIG_X86_MCE_THRESHOLD
 159         sum += irq_stats(cpu)->irq_threshold_count;
 160 #endif
 161 #ifdef CONFIG_X86_MCE
 162         sum += per_cpu(mce_exception_count, cpu);
 163         sum += per_cpu(mce_poll_count, cpu);
 164 #endif
 165         return sum;
 166 }
 167
 168 u64 arch_irq_stat(void)
 169 {
 170         u64 sum = atomic_read(&irq_err_count);
 171         return sum;
 172 }
 173
 174
 175 /*
 176  * do_IRQ handles all normal device IRQ's (the special
 177  * SMP cross-CPU interrupts have their own specific
 178  * handlers).
 179  */
 180 __visible unsigned int __irq_entry do_IRQ(struct pt_regs *regs)
 181 {
 182         struct pt_regs *old_regs = set_irq_regs(regs);
 183
 184         /* high bit used in ret_from_ code  */
 185         unsigned vector = ~regs->orig_ax;
 186         unsigned irq;
 187
 188         irq_enter();
 189         exit_idle();
 190
 191         irq = __this_cpu_read(vector_irq[vector]);
 192
 193         if (!handle_irq(irq, regs)) {
 194                 ack_APIC_irq();
 195
 196                 if (printk_ratelimit())
 197                         pr_emerg("%s: %d.%d No irq handler for vector (irq %d)\n",
 198                                 __func__, smp_processor_id(), vector, irq);
 199         }
 200
 201         irq_exit();
 202
 203         set_irq_regs(old_regs);
 204         return 1;
 205 }
 206
 207 /*
 208  * Handler for X86_PLATFORM_IPI_VECTOR.
 209  */
 210 void __smp_x86_platform_ipi(void)
 211 {
 212         inc_irq_stat(x86_platform_ipis);
 213
 214         if (x86_platform_ipi_callback)
 215                 x86_platform_ipi_callback();
 216 }
 217
 218 __visible void smp_x86_platform_ipi(struct pt_regs *regs)
 219 {
 220         struct pt_regs *old_regs = set_irq_regs(regs);
 221
 222         entering_ack_irq();
 223         __smp_x86_platform_ipi();
 224         exiting_irq();
 225         set_irq_regs(old_regs);
 226 }
 227
 228 #ifdef CONFIG_HAVE_KVM
 229 /*
 230  * Handler for POSTED_INTERRUPT_VECTOR.
 231  */
 232 __visible void smp_kvm_posted_intr_ipi(struct pt_regs *regs)
 233 {
 234         struct pt_regs *old_regs = set_irq_regs(regs);
 235
 236         ack_APIC_irq();
 237
 238         irq_enter();
 239
 240         exit_idle();
 241
 242         inc_irq_stat(kvm_posted_intr_ipis);
 243
 244         irq_exit();
 245
 246         set_irq_regs(old_regs);
 247 }
 248 #endif
 249
 250 __visible void smp_trace_x86_platform_ipi(struct pt_regs *regs)
 251 {
 252         struct pt_regs *old_regs = set_irq_regs(regs);
 253
 254         entering_ack_irq();
 255         trace_x86_platform_ipi_entry(X86_PLATFORM_IPI_VECTOR);
 256         __smp_x86_platform_ipi();
 257         trace_x86_platform_ipi_exit(X86_PLATFORM_IPI_VECTOR);
 258         exiting_irq();
 259         set_irq_regs(old_regs);
 260 }
 261
 262 EXPORT_SYMBOL_GPL(vector_used_by_percpu_irq);
 263
 264 #ifdef CONFIG_HOTPLUG_CPU
 265 /* A cpu has been removed from cpu_online_mask.  Reset irq affinities. */
 266 void fixup_irqs(void)
 267 {
 268         unsigned int irq, vector;
 269         static int warned;
 270         struct irq_desc *desc;
 271         struct irq_data *data;
 272         struct irq_chip *chip;
 273
 274         for_each_irq_desc(irq, desc) {
 275                 int break_affinity = 0;
 276                 int set_affinity = 1;
 277                 const struct cpumask *affinity;
 278
 279                 if (!desc)
 280                         continue;
 281                 if (irq == 2)
 282                         continue;
 283
 284                 /* interrupt's are disabled at this point */
 285                 raw_spin_lock(&desc->lock);
 286
 287                 data = irq_desc_get_irq_data(desc);
 288                 affinity = data->affinity;
 289                 if (!irq_has_action(irq) || irqd_is_per_cpu(data) ||
 290                     cpumask_subset(affinity, cpu_online_mask)) {
 291                         raw_spin_unlock(&desc->lock);
 292                         continue;
 293                 }
 294
 295                 /*
 296                  * Complete the irq move. This cpu is going down and for
 297                  * non intr-remapping case, we can't wait till this interrupt
 298                  * arrives at this cpu before completing the irq move.
 299                  */
 300                 irq_force_complete_move(irq);
 301
 302                 if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids) {
 303                         break_affinity = 1;
 304                         affinity = cpu_online_mask;
 305                 }
 306
 307                 chip = irq_data_get_irq_chip(data);
 308                 if (!irqd_can_move_in_process_context(data) && chip->irq_mask)
 309                         chip->irq_mask(data);
 310
 311                 if (chip->irq_set_affinity)
 312                         chip->irq_set_affinity(data, affinity, true);
 313                 else if (!(warned++))
 314                         set_affinity = 0;
 315
 316                 /*
 317                  * We unmask if the irq was not marked masked by the
 318                  * core code. That respects the lazy irq disable
 319                  * behaviour.
 320                  */
 321                 if (!irqd_can_move_in_process_context(data) &&
 322                     !irqd_irq_masked(data) && chip->irq_unmask)
 323                         chip->irq_unmask(data);
 324
 325                 raw_spin_unlock(&desc->lock);
 326
 327                 if (break_affinity && set_affinity)
 328                         pr_notice("Broke affinity for irq %i\n", irq);
 329                 else if (!set_affinity)
 330                         pr_notice("Cannot set affinity for irq %i\n", irq);
 331         }
 332
 333         /*
 334          * We can remove mdelay() and then send spuriuous interrupts to
 335          * new cpu targets for all the irqs that were handled previously by
 336          * this cpu. While it works, I have seen spurious interrupt messages
 337          * (nothing wrong but still...).
 338          *
 339          * So for now, retain mdelay(1) and check the IRR and then send those
 340          * interrupts to new targets as this cpu is already offlined...
 341          */
 342         mdelay(1);
 343
 344         for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
 345                 unsigned int irr;
 346
 347                 if (__this_cpu_read(vector_irq[vector]) < 0)
 348                         continue;
 349
 350                 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
 351                 if (irr  & (1 << (vector % 32))) {
 352                         irq = __this_cpu_read(vector_irq[vector]);
 353
 354                         desc = irq_to_desc(irq);
 355                         data = irq_desc_get_irq_data(desc);
 356                         chip = irq_data_get_irq_chip(data);
 357                         raw_spin_lock(&desc->lock);
 358                         if (chip->irq_retrigger)
 359                                 chip->irq_retrigger(data);
 360                         raw_spin_unlock(&desc->lock);
 361                 }
 362                 __this_cpu_write(vector_irq[vector], -1);
 363         }
 364 }
 365 #endif