?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
x86/efi: Enforce CONFIG_RELOCATABLE for EFI boot stub
[linux/fpc-iii.git] / arch / x86 / kvm / emulate.c
blob3ee4472cef19d27012a93aae702a7d7b4ba0449d
1 /******************************************************************************
2 * emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
9 * privileged instructions:
10 *
11 * Copyright (C) 2006 Qumranet
12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
23 #include <linux/kvm_host.h>
24 #include "kvm_cache_regs.h"
25 #include <linux/module.h>
26 #include <asm/kvm_emulate.h>
27 #include <linux/stringify.h>
28
29 #include "x86.h"
30 #include "tss.h"
31
32 /*
33 * Operand types
34 */
35 #define OpNone 0ull
36 #define OpImplicit 1ull /* No generic decode */
37 #define OpReg 2ull /* Register */
38 #define OpMem 3ull /* Memory */
39 #define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
40 #define OpDI 5ull /* ES:DI/EDI/RDI */
41 #define OpMem64 6ull /* Memory, 64-bit */
42 #define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
43 #define OpDX 8ull /* DX register */
44 #define OpCL 9ull /* CL register (for shifts) */
45 #define OpImmByte 10ull /* 8-bit sign extended immediate */
46 #define OpOne 11ull /* Implied 1 */
47 #define OpImm 12ull /* Sign extended up to 32-bit immediate */
48 #define OpMem16 13ull /* Memory operand (16-bit). */
49 #define OpMem32 14ull /* Memory operand (32-bit). */
50 #define OpImmU 15ull /* Immediate operand, zero extended */
51 #define OpSI 16ull /* SI/ESI/RSI */
52 #define OpImmFAddr 17ull /* Immediate far address */
53 #define OpMemFAddr 18ull /* Far address in memory */
54 #define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
55 #define OpES 20ull /* ES */
56 #define OpCS 21ull /* CS */
57 #define OpSS 22ull /* SS */
58 #define OpDS 23ull /* DS */
59 #define OpFS 24ull /* FS */
60 #define OpGS 25ull /* GS */
61 #define OpMem8 26ull /* 8-bit zero extended memory operand */
62 #define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
63 #define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */
64 #define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */
65 #define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */
66
67 #define OpBits 5 /* Width of operand field */
68 #define OpMask ((1ull << OpBits) - 1)
69
70 /*
71 * Opcode effective-address decode tables.
72 * Note that we only emulate instructions that have at least one memory
73 * operand (excluding implicit stack references). We assume that stack
74 * references and instruction fetches will never occur in special memory
75 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
76 * not be handled.
77 */
78
79 /* Operand sizes: 8-bit operands or specified/overridden size. */
80 #define ByteOp (1<<0) /* 8-bit operands. */
81 /* Destination operand type. */
82 #define DstShift 1
83 #define ImplicitOps (OpImplicit << DstShift)
84 #define DstReg (OpReg << DstShift)
85 #define DstMem (OpMem << DstShift)
86 #define DstAcc (OpAcc << DstShift)
87 #define DstDI (OpDI << DstShift)
88 #define DstMem64 (OpMem64 << DstShift)
89 #define DstImmUByte (OpImmUByte << DstShift)
90 #define DstDX (OpDX << DstShift)
91 #define DstAccLo (OpAccLo << DstShift)
92 #define DstMask (OpMask << DstShift)
93 /* Source operand type. */
94 #define SrcShift 6
95 #define SrcNone (OpNone << SrcShift)
96 #define SrcReg (OpReg << SrcShift)
97 #define SrcMem (OpMem << SrcShift)
98 #define SrcMem16 (OpMem16 << SrcShift)
99 #define SrcMem32 (OpMem32 << SrcShift)
100 #define SrcImm (OpImm << SrcShift)
101 #define SrcImmByte (OpImmByte << SrcShift)
102 #define SrcOne (OpOne << SrcShift)
103 #define SrcImmUByte (OpImmUByte << SrcShift)
104 #define SrcImmU (OpImmU << SrcShift)
105 #define SrcSI (OpSI << SrcShift)
106 #define SrcXLat (OpXLat << SrcShift)
107 #define SrcImmFAddr (OpImmFAddr << SrcShift)
108 #define SrcMemFAddr (OpMemFAddr << SrcShift)
109 #define SrcAcc (OpAcc << SrcShift)
110 #define SrcImmU16 (OpImmU16 << SrcShift)
111 #define SrcImm64 (OpImm64 << SrcShift)
112 #define SrcDX (OpDX << SrcShift)
113 #define SrcMem8 (OpMem8 << SrcShift)
114 #define SrcAccHi (OpAccHi << SrcShift)
115 #define SrcMask (OpMask << SrcShift)
116 #define BitOp (1<<11)
117 #define MemAbs (1<<12) /* Memory operand is absolute displacement */
118 #define String (1<<13) /* String instruction (rep capable) */
119 #define Stack (1<<14) /* Stack instruction (push/pop) */
120 #define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
121 #define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
122 #define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
123 #define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
124 #define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
125 #define Escape (5<<15) /* Escape to coprocessor instruction */
126 #define Sse (1<<18) /* SSE Vector instruction */
127 /* Generic ModRM decode. */
128 #define ModRM (1<<19)
129 /* Destination is only written; never read. */
130 #define Mov (1<<20)
131 /* Misc flags */
132 #define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
133 #define VendorSpecific (1<<22) /* Vendor specific instruction */
134 #define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
135 #define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
136 #define Undefined (1<<25) /* No Such Instruction */
137 #define Lock (1<<26) /* lock prefix is allowed for the instruction */
138 #define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
139 #define No64 (1<<28)
140 #define PageTable (1 << 29) /* instruction used to write page table */
141 #define NotImpl (1 << 30) /* instruction is not implemented */
142 /* Source 2 operand type */
143 #define Src2Shift (31)
144 #define Src2None (OpNone << Src2Shift)
145 #define Src2Mem (OpMem << Src2Shift)
146 #define Src2CL (OpCL << Src2Shift)
147 #define Src2ImmByte (OpImmByte << Src2Shift)
148 #define Src2One (OpOne << Src2Shift)
149 #define Src2Imm (OpImm << Src2Shift)
150 #define Src2ES (OpES << Src2Shift)
151 #define Src2CS (OpCS << Src2Shift)
152 #define Src2SS (OpSS << Src2Shift)
153 #define Src2DS (OpDS << Src2Shift)
154 #define Src2FS (OpFS << Src2Shift)
155 #define Src2GS (OpGS << Src2Shift)
156 #define Src2Mask (OpMask << Src2Shift)
157 #define Mmx ((u64)1 << 40) /* MMX Vector instruction */
158 #define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
159 #define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
160 #define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
161 #define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
162 #define NoWrite ((u64)1 << 45) /* No writeback */
163 #define SrcWrite ((u64)1 << 46) /* Write back src operand */
164
165 #define DstXacc (DstAccLo | SrcAccHi | SrcWrite)
166
167 #define X2(x...) x, x
168 #define X3(x...) X2(x), x
169 #define X4(x...) X2(x), X2(x)
170 #define X5(x...) X4(x), x
171 #define X6(x...) X4(x), X2(x)
172 #define X7(x...) X4(x), X3(x)
173 #define X8(x...) X4(x), X4(x)
174 #define X16(x...) X8(x), X8(x)
175
176 #define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
177 #define FASTOP_SIZE 8
178
179 /*
180 * fastop functions have a special calling convention:
181 *
182 * dst: rax (in/out)
183 * src: rdx (in/out)
184 * src2: rcx (in)
185 * flags: rflags (in/out)
186 * ex: rsi (in:fastop pointer, out:zero if exception)
187 *
188 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
189 * different operand sizes can be reached by calculation, rather than a jump
190 * table (which would be bigger than the code).
191 *
192 * fastop functions are declared as taking a never-defined fastop parameter,
193 * so they can't be called from C directly.
194 */
195
196 struct fastop;
197
198 struct opcode {
199 u64 flags : 56;
200 u64 intercept : 8;
201 union {
202 int (*execute)(struct x86_emulate_ctxt *ctxt);
203 const struct opcode *group;
204 const struct group_dual *gdual;
205 const struct gprefix *gprefix;
206 const struct escape *esc;
207 void (*fastop)(struct fastop *fake);
208 } u;
209 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
210 };
211
212 struct group_dual {
213 struct opcode mod012[8];
214 struct opcode mod3[8];
215 };
216
217 struct gprefix {
218 struct opcode pfx_no;
219 struct opcode pfx_66;
220 struct opcode pfx_f2;
221 struct opcode pfx_f3;
222 };
223
224 struct escape {
225 struct opcode op[8];
226 struct opcode high[64];
227 };
228
229 /* EFLAGS bit definitions. */
230 #define EFLG_ID (1<<21)
231 #define EFLG_VIP (1<<20)
232 #define EFLG_VIF (1<<19)
233 #define EFLG_AC (1<<18)
234 #define EFLG_VM (1<<17)
235 #define EFLG_RF (1<<16)
236 #define EFLG_IOPL (3<<12)
237 #define EFLG_NT (1<<14)
238 #define EFLG_OF (1<<11)
239 #define EFLG_DF (1<<10)
240 #define EFLG_IF (1<<9)
241 #define EFLG_TF (1<<8)
242 #define EFLG_SF (1<<7)
243 #define EFLG_ZF (1<<6)
244 #define EFLG_AF (1<<4)
245 #define EFLG_PF (1<<2)
246 #define EFLG_CF (1<<0)
247
248 #define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
249 #define EFLG_RESERVED_ONE_MASK 2
250
251 static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
252 {
253 if (!(ctxt->regs_valid & (1 << nr))) {
254 ctxt->regs_valid |= 1 << nr;
255 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
256 }
257 return ctxt->_regs[nr];
258 }
259
260 static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
261 {
262 ctxt->regs_valid |= 1 << nr;
263 ctxt->regs_dirty |= 1 << nr;
264 return &ctxt->_regs[nr];
265 }
266
267 static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
268 {
269 reg_read(ctxt, nr);
270 return reg_write(ctxt, nr);
271 }
272
273 static void writeback_registers(struct x86_emulate_ctxt *ctxt)
274 {
275 unsigned reg;
276
277 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
278 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
279 }
280
281 static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
282 {
283 ctxt->regs_dirty = 0;
284 ctxt->regs_valid = 0;
285 }
286
287 /*
288 * These EFLAGS bits are restored from saved value during emulation, and
289 * any changes are written back to the saved value after emulation.
290 */
291 #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
292
293 #ifdef CONFIG_X86_64
294 #define ON64(x) x
295 #else
296 #define ON64(x)
297 #endif
298
299 static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
300
301 #define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t"
302 #define FOP_RET "ret \n\t"
303
304 #define FOP_START(op) \
305 extern void em_##op(struct fastop *fake); \
306 asm(".pushsection .text, \"ax\" \n\t" \
307 ".global em_" #op " \n\t" \
308 FOP_ALIGN \
309 "em_" #op ": \n\t"
310
311 #define FOP_END \
312 ".popsection")
313
314 #define FOPNOP() FOP_ALIGN FOP_RET
315
316 #define FOP1E(op, dst) \
317 FOP_ALIGN "10: " #op " %" #dst " \n\t" FOP_RET
318
319 #define FOP1EEX(op, dst) \
320 FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception)
321
322 #define FASTOP1(op) \
323 FOP_START(op) \
324 FOP1E(op##b, al) \
325 FOP1E(op##w, ax) \
326 FOP1E(op##l, eax) \
327 ON64(FOP1E(op##q, rax)) \
328 FOP_END
329
330 /* 1-operand, using src2 (for MUL/DIV r/m) */
331 #define FASTOP1SRC2(op, name) \
332 FOP_START(name) \
333 FOP1E(op, cl) \
334 FOP1E(op, cx) \
335 FOP1E(op, ecx) \
336 ON64(FOP1E(op, rcx)) \
337 FOP_END
338
339 /* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */
340 #define FASTOP1SRC2EX(op, name) \
341 FOP_START(name) \
342 FOP1EEX(op, cl) \
343 FOP1EEX(op, cx) \
344 FOP1EEX(op, ecx) \
345 ON64(FOP1EEX(op, rcx)) \
346 FOP_END
347
348 #define FOP2E(op, dst, src) \
349 FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET
350
351 #define FASTOP2(op) \
352 FOP_START(op) \
353 FOP2E(op##b, al, dl) \
354 FOP2E(op##w, ax, dx) \
355 FOP2E(op##l, eax, edx) \
356 ON64(FOP2E(op##q, rax, rdx)) \
357 FOP_END
358
359 /* 2 operand, word only */
360 #define FASTOP2W(op) \
361 FOP_START(op) \
362 FOPNOP() \
363 FOP2E(op##w, ax, dx) \
364 FOP2E(op##l, eax, edx) \
365 ON64(FOP2E(op##q, rax, rdx)) \
366 FOP_END
367
368 /* 2 operand, src is CL */
369 #define FASTOP2CL(op) \
370 FOP_START(op) \
371 FOP2E(op##b, al, cl) \
372 FOP2E(op##w, ax, cl) \
373 FOP2E(op##l, eax, cl) \
374 ON64(FOP2E(op##q, rax, cl)) \
375 FOP_END
376
377 #define FOP3E(op, dst, src, src2) \
378 FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET
379
380 /* 3-operand, word-only, src2=cl */
381 #define FASTOP3WCL(op) \
382 FOP_START(op) \
383 FOPNOP() \
384 FOP3E(op##w, ax, dx, cl) \
385 FOP3E(op##l, eax, edx, cl) \
386 ON64(FOP3E(op##q, rax, rdx, cl)) \
387 FOP_END
388
389 /* Special case for SETcc - 1 instruction per cc */
390 #define FOP_SETCC(op) ".align 4; " #op " %al; ret \n\t"
391
392 asm(".global kvm_fastop_exception \n"
393 "kvm_fastop_exception: xor %esi, %esi; ret");
394
395 FOP_START(setcc)
396 FOP_SETCC(seto)
397 FOP_SETCC(setno)
398 FOP_SETCC(setc)
399 FOP_SETCC(setnc)
400 FOP_SETCC(setz)
401 FOP_SETCC(setnz)
402 FOP_SETCC(setbe)
403 FOP_SETCC(setnbe)
404 FOP_SETCC(sets)
405 FOP_SETCC(setns)
406 FOP_SETCC(setp)
407 FOP_SETCC(setnp)
408 FOP_SETCC(setl)
409 FOP_SETCC(setnl)
410 FOP_SETCC(setle)
411 FOP_SETCC(setnle)
412 FOP_END;
413
414 FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET
415 FOP_END;
416
417 static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
418 enum x86_intercept intercept,
419 enum x86_intercept_stage stage)
420 {
421 struct x86_instruction_info info = {
422 .intercept = intercept,
423 .rep_prefix = ctxt->rep_prefix,
424 .modrm_mod = ctxt->modrm_mod,
425 .modrm_reg = ctxt->modrm_reg,
426 .modrm_rm = ctxt->modrm_rm,
427 .src_val = ctxt->src.val64,
428 .src_bytes = ctxt->src.bytes,
429 .dst_bytes = ctxt->dst.bytes,
430 .ad_bytes = ctxt->ad_bytes,
431 .next_rip = ctxt->eip,
432 };
433
434 return ctxt->ops->intercept(ctxt, &info, stage);
435 }
436
437 static void assign_masked(ulong *dest, ulong src, ulong mask)
438 {
439 *dest = (*dest & ~mask) | (src & mask);
440 }
441
442 static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
443 {
444 return (1UL << (ctxt->ad_bytes << 3)) - 1;
445 }
446
447 static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
448 {
449 u16 sel;
450 struct desc_struct ss;
451
452 if (ctxt->mode == X86EMUL_MODE_PROT64)
453 return ~0UL;
454 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
455 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
456 }
457
458 static int stack_size(struct x86_emulate_ctxt *ctxt)
459 {
460 return (__fls(stack_mask(ctxt)) + 1) >> 3;
461 }
462
463 /* Access/update address held in a register, based on addressing mode. */
464 static inline unsigned long
465 address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
466 {
467 if (ctxt->ad_bytes == sizeof(unsigned long))
468 return reg;
469 else
470 return reg & ad_mask(ctxt);
471 }
472
473 static inline unsigned long
474 register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
475 {
476 return address_mask(ctxt, reg);
477 }
478
479 static void masked_increment(ulong *reg, ulong mask, int inc)
480 {
481 assign_masked(reg, *reg + inc, mask);
482 }
483
484 static inline void
485 register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
486 {
487 ulong mask;
488
489 if (ctxt->ad_bytes == sizeof(unsigned long))
490 mask = ~0UL;
491 else
492 mask = ad_mask(ctxt);
493 masked_increment(reg, mask, inc);
494 }
495
496 static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
497 {
498 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
499 }
500
501 static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
502 {
503 register_address_increment(ctxt, &ctxt->_eip, rel);
504 }
505
506 static u32 desc_limit_scaled(struct desc_struct *desc)
507 {
508 u32 limit = get_desc_limit(desc);
509
510 return desc->g ? (limit << 12) | 0xfff : limit;
511 }
512
513 static void set_seg_override(struct x86_emulate_ctxt *ctxt, int seg)
514 {
515 ctxt->has_seg_override = true;
516 ctxt->seg_override = seg;
517 }
518
519 static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
520 {
521 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
522 return 0;
523
524 return ctxt->ops->get_cached_segment_base(ctxt, seg);
525 }
526
527 static unsigned seg_override(struct x86_emulate_ctxt *ctxt)
528 {
529 if (!ctxt->has_seg_override)
530 return 0;
531
532 return ctxt->seg_override;
533 }
534
535 static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
536 u32 error, bool valid)
537 {
538 ctxt->exception.vector = vec;
539 ctxt->exception.error_code = error;
540 ctxt->exception.error_code_valid = valid;
541 return X86EMUL_PROPAGATE_FAULT;
542 }
543
544 static int emulate_db(struct x86_emulate_ctxt *ctxt)
545 {
546 return emulate_exception(ctxt, DB_VECTOR, 0, false);
547 }
548
549 static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
550 {
551 return emulate_exception(ctxt, GP_VECTOR, err, true);
552 }
553
554 static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
555 {
556 return emulate_exception(ctxt, SS_VECTOR, err, true);
557 }
558
559 static int emulate_ud(struct x86_emulate_ctxt *ctxt)
560 {
561 return emulate_exception(ctxt, UD_VECTOR, 0, false);
562 }
563
564 static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
565 {
566 return emulate_exception(ctxt, TS_VECTOR, err, true);
567 }
568
569 static int emulate_de(struct x86_emulate_ctxt *ctxt)
570 {
571 return emulate_exception(ctxt, DE_VECTOR, 0, false);
572 }
573
574 static int emulate_nm(struct x86_emulate_ctxt *ctxt)
575 {
576 return emulate_exception(ctxt, NM_VECTOR, 0, false);
577 }
578
579 static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
580 {
581 u16 selector;
582 struct desc_struct desc;
583
584 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
585 return selector;
586 }
587
588 static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
589 unsigned seg)
590 {
591 u16 dummy;
592 u32 base3;
593 struct desc_struct desc;
594
595 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
596 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
597 }
598
599 /*
600 * x86 defines three classes of vector instructions: explicitly
601 * aligned, explicitly unaligned, and the rest, which change behaviour
602 * depending on whether they're AVX encoded or not.
603 *
604 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
605 * subject to the same check.
606 */
607 static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
608 {
609 if (likely(size < 16))
610 return false;
611
612 if (ctxt->d & Aligned)
613 return true;
614 else if (ctxt->d & Unaligned)
615 return false;
616 else if (ctxt->d & Avx)
617 return false;
618 else
619 return true;
620 }
621
622 static int __linearize(struct x86_emulate_ctxt *ctxt,
623 struct segmented_address addr,
624 unsigned size, bool write, bool fetch,
625 ulong *linear)
626 {
627 struct desc_struct desc;
628 bool usable;
629 ulong la;
630 u32 lim;
631 u16 sel;
632 unsigned cpl;
633
634 la = seg_base(ctxt, addr.seg) + addr.ea;
635 switch (ctxt->mode) {
636 case X86EMUL_MODE_PROT64:
637 if (((signed long)la << 16) >> 16 != la)
638 return emulate_gp(ctxt, 0);
639 break;
640 default:
641 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
642 addr.seg);
643 if (!usable)
644 goto bad;
645 /* code segment in protected mode or read-only data segment */
646 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
647 || !(desc.type & 2)) && write)
648 goto bad;
649 /* unreadable code segment */
650 if (!fetch && (desc.type & 8) && !(desc.type & 2))
651 goto bad;
652 lim = desc_limit_scaled(&desc);
653 if ((desc.type & 8) || !(desc.type & 4)) {
654 /* expand-up segment */
655 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
656 goto bad;
657 } else {
658 /* expand-down segment */
659 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
660 goto bad;
661 lim = desc.d ? 0xffffffff : 0xffff;
662 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
663 goto bad;
664 }
665 cpl = ctxt->ops->cpl(ctxt);
666 if (!(desc.type & 8)) {
667 /* data segment */
668 if (cpl > desc.dpl)
669 goto bad;
670 } else if ((desc.type & 8) && !(desc.type & 4)) {
671 /* nonconforming code segment */
672 if (cpl != desc.dpl)
673 goto bad;
674 } else if ((desc.type & 8) && (desc.type & 4)) {
675 /* conforming code segment */
676 if (cpl < desc.dpl)
677 goto bad;
678 }
679 break;
680 }
681 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
682 la &= (u32)-1;
683 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
684 return emulate_gp(ctxt, 0);
685 *linear = la;
686 return X86EMUL_CONTINUE;
687 bad:
688 if (addr.seg == VCPU_SREG_SS)
689 return emulate_ss(ctxt, sel);
690 else
691 return emulate_gp(ctxt, sel);
692 }
693
694 static int linearize(struct x86_emulate_ctxt *ctxt,
695 struct segmented_address addr,
696 unsigned size, bool write,
697 ulong *linear)
698 {
699 return __linearize(ctxt, addr, size, write, false, linear);
700 }
701
702
703 static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
704 struct segmented_address addr,
705 void *data,
706 unsigned size)
707 {
708 int rc;
709 ulong linear;
710
711 rc = linearize(ctxt, addr, size, false, &linear);
712 if (rc != X86EMUL_CONTINUE)
713 return rc;
714 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
715 }
716
717 /*
718 * Fetch the next byte of the instruction being emulated which is pointed to
719 * by ctxt->_eip, then increment ctxt->_eip.
720 *
721 * Also prefetch the remaining bytes of the instruction without crossing page
722 * boundary if they are not in fetch_cache yet.
723 */
724 static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest)
725 {
726 struct fetch_cache *fc = &ctxt->fetch;
727 int rc;
728 int size, cur_size;
729
730 if (ctxt->_eip == fc->end) {
731 unsigned long linear;
732 struct segmented_address addr = { .seg = VCPU_SREG_CS,
733 .ea = ctxt->_eip };
734 cur_size = fc->end - fc->start;
735 size = min(15UL - cur_size,
736 PAGE_SIZE - offset_in_page(ctxt->_eip));
737 rc = __linearize(ctxt, addr, size, false, true, &linear);
738 if (unlikely(rc != X86EMUL_CONTINUE))
739 return rc;
740 rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size,
741 size, &ctxt->exception);
742 if (unlikely(rc != X86EMUL_CONTINUE))
743 return rc;
744 fc->end += size;
745 }
746 *dest = fc->data[ctxt->_eip - fc->start];
747 ctxt->_eip++;
748 return X86EMUL_CONTINUE;
749 }
750
751 static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
752 void *dest, unsigned size)
753 {
754 int rc;
755
756 /* x86 instructions are limited to 15 bytes. */
757 if (unlikely(ctxt->_eip + size - ctxt->eip > 15))
758 return X86EMUL_UNHANDLEABLE;
759 while (size--) {
760 rc = do_insn_fetch_byte(ctxt, dest++);
761 if (rc != X86EMUL_CONTINUE)
762 return rc;
763 }
764 return X86EMUL_CONTINUE;
765 }
766
767 /* Fetch next part of the instruction being emulated. */
768 #define insn_fetch(_type, _ctxt) \
769 ({ unsigned long _x; \
770 rc = do_insn_fetch(_ctxt, &_x, sizeof(_type)); \
771 if (rc != X86EMUL_CONTINUE) \
772 goto done; \
773 (_type)_x; \
774 })
775
776 #define insn_fetch_arr(_arr, _size, _ctxt) \
777 ({ rc = do_insn_fetch(_ctxt, _arr, (_size)); \
778 if (rc != X86EMUL_CONTINUE) \
779 goto done; \
780 })
781
782 /*
783 * Given the 'reg' portion of a ModRM byte, and a register block, return a
784 * pointer into the block that addresses the relevant register.
785 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
786 */
787 static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
788 int highbyte_regs)
789 {
790 void *p;
791
792 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
793 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
794 else
795 p = reg_rmw(ctxt, modrm_reg);
796 return p;
797 }
798
799 static int read_descriptor(struct x86_emulate_ctxt *ctxt,
800 struct segmented_address addr,
801 u16 *size, unsigned long *address, int op_bytes)
802 {
803 int rc;
804
805 if (op_bytes == 2)
806 op_bytes = 3;
807 *address = 0;
808 rc = segmented_read_std(ctxt, addr, size, 2);
809 if (rc != X86EMUL_CONTINUE)
810 return rc;
811 addr.ea += 2;
812 rc = segmented_read_std(ctxt, addr, address, op_bytes);
813 return rc;
814 }
815
816 FASTOP2(add);
817 FASTOP2(or);
818 FASTOP2(adc);
819 FASTOP2(sbb);
820 FASTOP2(and);
821 FASTOP2(sub);
822 FASTOP2(xor);
823 FASTOP2(cmp);
824 FASTOP2(test);
825
826 FASTOP1SRC2(mul, mul_ex);
827 FASTOP1SRC2(imul, imul_ex);
828 FASTOP1SRC2EX(div, div_ex);
829 FASTOP1SRC2EX(idiv, idiv_ex);
830
831 FASTOP3WCL(shld);
832 FASTOP3WCL(shrd);
833
834 FASTOP2W(imul);
835
836 FASTOP1(not);
837 FASTOP1(neg);
838 FASTOP1(inc);
839 FASTOP1(dec);
840
841 FASTOP2CL(rol);
842 FASTOP2CL(ror);
843 FASTOP2CL(rcl);
844 FASTOP2CL(rcr);
845 FASTOP2CL(shl);
846 FASTOP2CL(shr);
847 FASTOP2CL(sar);
848
849 FASTOP2W(bsf);
850 FASTOP2W(bsr);
851 FASTOP2W(bt);
852 FASTOP2W(bts);
853 FASTOP2W(btr);
854 FASTOP2W(btc);
855
856 FASTOP2(xadd);
857
858 static u8 test_cc(unsigned int condition, unsigned long flags)
859 {
860 u8 rc;
861 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
862
863 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
864 asm("push %[flags]; popf; call *%[fastop]"
865 : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags));
866 return rc;
867 }
868
869 static void fetch_register_operand(struct operand *op)
870 {
871 switch (op->bytes) {
872 case 1:
873 op->val = *(u8 *)op->addr.reg;
874 break;
875 case 2:
876 op->val = *(u16 *)op->addr.reg;
877 break;
878 case 4:
879 op->val = *(u32 *)op->addr.reg;
880 break;
881 case 8:
882 op->val = *(u64 *)op->addr.reg;
883 break;
884 }
885 }
886
887 static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
888 {
889 ctxt->ops->get_fpu(ctxt);
890 switch (reg) {
891 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
892 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
893 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
894 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
895 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
896 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
897 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
898 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
899 #ifdef CONFIG_X86_64
900 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
901 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
902 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
903 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
904 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
905 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
906 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
907 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
908 #endif
909 default: BUG();
910 }
911 ctxt->ops->put_fpu(ctxt);
912 }
913
914 static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
915 int reg)
916 {
917 ctxt->ops->get_fpu(ctxt);
918 switch (reg) {
919 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
920 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
921 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
922 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
923 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
924 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
925 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
926 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
927 #ifdef CONFIG_X86_64
928 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
929 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
930 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
931 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
932 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
933 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
934 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
935 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
936 #endif
937 default: BUG();
938 }
939 ctxt->ops->put_fpu(ctxt);
940 }
941
942 static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
943 {
944 ctxt->ops->get_fpu(ctxt);
945 switch (reg) {
946 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
947 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
948 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
949 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
950 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
951 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
952 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
953 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
954 default: BUG();
955 }
956 ctxt->ops->put_fpu(ctxt);
957 }
958
959 static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
960 {
961 ctxt->ops->get_fpu(ctxt);
962 switch (reg) {
963 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
964 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
965 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
966 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
967 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
968 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
969 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
970 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
971 default: BUG();
972 }
973 ctxt->ops->put_fpu(ctxt);
974 }
975
976 static int em_fninit(struct x86_emulate_ctxt *ctxt)
977 {
978 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
979 return emulate_nm(ctxt);
980
981 ctxt->ops->get_fpu(ctxt);
982 asm volatile("fninit");
983 ctxt->ops->put_fpu(ctxt);
984 return X86EMUL_CONTINUE;
985 }
986
987 static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
988 {
989 u16 fcw;
990
991 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
992 return emulate_nm(ctxt);
993
994 ctxt->ops->get_fpu(ctxt);
995 asm volatile("fnstcw %0": "+m"(fcw));
996 ctxt->ops->put_fpu(ctxt);
997
998 /* force 2 byte destination */
999 ctxt->dst.bytes = 2;
1000 ctxt->dst.val = fcw;
1001
1002 return X86EMUL_CONTINUE;
1003 }
1004
1005 static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
1006 {
1007 u16 fsw;
1008
1009 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1010 return emulate_nm(ctxt);
1011
1012 ctxt->ops->get_fpu(ctxt);
1013 asm volatile("fnstsw %0": "+m"(fsw));
1014 ctxt->ops->put_fpu(ctxt);
1015
1016 /* force 2 byte destination */
1017 ctxt->dst.bytes = 2;
1018 ctxt->dst.val = fsw;
1019
1020 return X86EMUL_CONTINUE;
1021 }
1022
1023 static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
1024 struct operand *op)
1025 {
1026 unsigned reg = ctxt->modrm_reg;
1027 int highbyte_regs = ctxt->rex_prefix == 0;
1028
1029 if (!(ctxt->d & ModRM))
1030 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1031
1032 if (ctxt->d & Sse) {
1033 op->type = OP_XMM;
1034 op->bytes = 16;
1035 op->addr.xmm = reg;
1036 read_sse_reg(ctxt, &op->vec_val, reg);
1037 return;
1038 }
1039 if (ctxt->d & Mmx) {
1040 reg &= 7;
1041 op->type = OP_MM;
1042 op->bytes = 8;
1043 op->addr.mm = reg;
1044 return;
1045 }
1046
1047 op->type = OP_REG;
1048 if (ctxt->d & ByteOp) {
1049 op->addr.reg = decode_register(ctxt, reg, highbyte_regs);
1050 op->bytes = 1;
1051 } else {
1052 op->addr.reg = decode_register(ctxt, reg, 0);
1053 op->bytes = ctxt->op_bytes;
1054 }
1055 fetch_register_operand(op);
1056 op->orig_val = op->val;
1057 }
1058
1059 static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1060 {
1061 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1062 ctxt->modrm_seg = VCPU_SREG_SS;
1063 }
1064
1065 static int decode_modrm(struct x86_emulate_ctxt *ctxt,
1066 struct operand *op)
1067 {
1068 u8 sib;
1069 int index_reg = 0, base_reg = 0, scale;
1070 int rc = X86EMUL_CONTINUE;
1071 ulong modrm_ea = 0;
1072
1073 if (ctxt->rex_prefix) {
1074 ctxt->modrm_reg = (ctxt->rex_prefix & 4) << 1; /* REX.R */
1075 index_reg = (ctxt->rex_prefix & 2) << 2; /* REX.X */
1076 ctxt->modrm_rm = base_reg = (ctxt->rex_prefix & 1) << 3; /* REG.B */
1077 }
1078
1079 ctxt->modrm_mod |= (ctxt->modrm & 0xc0) >> 6;
1080 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
1081 ctxt->modrm_rm |= (ctxt->modrm & 0x07);
1082 ctxt->modrm_seg = VCPU_SREG_DS;
1083
1084 if (ctxt->modrm_mod == 3) {
1085 int highbyte_regs = ctxt->rex_prefix == 0;
1086
1087 op->type = OP_REG;
1088 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1089 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm,
1090 highbyte_regs && (ctxt->d & ByteOp));
1091 if (ctxt->d & Sse) {
1092 op->type = OP_XMM;
1093 op->bytes = 16;
1094 op->addr.xmm = ctxt->modrm_rm;
1095 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1096 return rc;
1097 }
1098 if (ctxt->d & Mmx) {
1099 op->type = OP_MM;
1100 op->bytes = 8;
1101 op->addr.xmm = ctxt->modrm_rm & 7;
1102 return rc;
1103 }
1104 fetch_register_operand(op);
1105 return rc;
1106 }
1107
1108 op->type = OP_MEM;
1109
1110 if (ctxt->ad_bytes == 2) {
1111 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1112 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1113 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1114 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1115
1116 /* 16-bit ModR/M decode. */
1117 switch (ctxt->modrm_mod) {
1118 case 0:
1119 if (ctxt->modrm_rm == 6)
1120 modrm_ea += insn_fetch(u16, ctxt);
1121 break;
1122 case 1:
1123 modrm_ea += insn_fetch(s8, ctxt);
1124 break;
1125 case 2:
1126 modrm_ea += insn_fetch(u16, ctxt);
1127 break;
1128 }
1129 switch (ctxt->modrm_rm) {
1130 case 0:
1131 modrm_ea += bx + si;
1132 break;
1133 case 1:
1134 modrm_ea += bx + di;
1135 break;
1136 case 2:
1137 modrm_ea += bp + si;
1138 break;
1139 case 3:
1140 modrm_ea += bp + di;
1141 break;
1142 case 4:
1143 modrm_ea += si;
1144 break;
1145 case 5:
1146 modrm_ea += di;
1147 break;
1148 case 6:
1149 if (ctxt->modrm_mod != 0)
1150 modrm_ea += bp;
1151 break;
1152 case 7:
1153 modrm_ea += bx;
1154 break;
1155 }
1156 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1157 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1158 ctxt->modrm_seg = VCPU_SREG_SS;
1159 modrm_ea = (u16)modrm_ea;
1160 } else {
1161 /* 32/64-bit ModR/M decode. */
1162 if ((ctxt->modrm_rm & 7) == 4) {
1163 sib = insn_fetch(u8, ctxt);
1164 index_reg |= (sib >> 3) & 7;
1165 base_reg |= sib & 7;
1166 scale = sib >> 6;
1167
1168 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
1169 modrm_ea += insn_fetch(s32, ctxt);
1170 else {
1171 modrm_ea += reg_read(ctxt, base_reg);
1172 adjust_modrm_seg(ctxt, base_reg);
1173 }
1174 if (index_reg != 4)
1175 modrm_ea += reg_read(ctxt, index_reg) << scale;
1176 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
1177 if (ctxt->mode == X86EMUL_MODE_PROT64)
1178 ctxt->rip_relative = 1;
1179 } else {
1180 base_reg = ctxt->modrm_rm;
1181 modrm_ea += reg_read(ctxt, base_reg);
1182 adjust_modrm_seg(ctxt, base_reg);
1183 }
1184 switch (ctxt->modrm_mod) {
1185 case 0:
1186 if (ctxt->modrm_rm == 5)
1187 modrm_ea += insn_fetch(s32, ctxt);
1188 break;
1189 case 1:
1190 modrm_ea += insn_fetch(s8, ctxt);
1191 break;
1192 case 2:
1193 modrm_ea += insn_fetch(s32, ctxt);
1194 break;
1195 }
1196 }
1197 op->addr.mem.ea = modrm_ea;
1198 done:
1199 return rc;
1200 }
1201
1202 static int decode_abs(struct x86_emulate_ctxt *ctxt,
1203 struct operand *op)
1204 {
1205 int rc = X86EMUL_CONTINUE;
1206
1207 op->type = OP_MEM;
1208 switch (ctxt->ad_bytes) {
1209 case 2:
1210 op->addr.mem.ea = insn_fetch(u16, ctxt);
1211 break;
1212 case 4:
1213 op->addr.mem.ea = insn_fetch(u32, ctxt);
1214 break;
1215 case 8:
1216 op->addr.mem.ea = insn_fetch(u64, ctxt);
1217 break;
1218 }
1219 done:
1220 return rc;
1221 }
1222
1223 static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
1224 {
1225 long sv = 0, mask;
1226
1227 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
1228 mask = ~(ctxt->dst.bytes * 8 - 1);
1229
1230 if (ctxt->src.bytes == 2)
1231 sv = (s16)ctxt->src.val & (s16)mask;
1232 else if (ctxt->src.bytes == 4)
1233 sv = (s32)ctxt->src.val & (s32)mask;
1234
1235 ctxt->dst.addr.mem.ea += (sv >> 3);
1236 }
1237
1238 /* only subword offset */
1239 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
1240 }
1241
1242 static int read_emulated(struct x86_emulate_ctxt *ctxt,
1243 unsigned long addr, void *dest, unsigned size)
1244 {
1245 int rc;
1246 struct read_cache *mc = &ctxt->mem_read;
1247
1248 if (mc->pos < mc->end)
1249 goto read_cached;
1250
1251 WARN_ON((mc->end + size) >= sizeof(mc->data));
1252
1253 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1254 &ctxt->exception);
1255 if (rc != X86EMUL_CONTINUE)
1256 return rc;
1257
1258 mc->end += size;
1259
1260 read_cached:
1261 memcpy(dest, mc->data + mc->pos, size);
1262 mc->pos += size;
1263 return X86EMUL_CONTINUE;
1264 }
1265
1266 static int segmented_read(struct x86_emulate_ctxt *ctxt,
1267 struct segmented_address addr,
1268 void *data,
1269 unsigned size)
1270 {
1271 int rc;
1272 ulong linear;
1273
1274 rc = linearize(ctxt, addr, size, false, &linear);
1275 if (rc != X86EMUL_CONTINUE)
1276 return rc;
1277 return read_emulated(ctxt, linear, data, size);
1278 }
1279
1280 static int segmented_write(struct x86_emulate_ctxt *ctxt,
1281 struct segmented_address addr,
1282 const void *data,
1283 unsigned size)
1284 {
1285 int rc;
1286 ulong linear;
1287
1288 rc = linearize(ctxt, addr, size, true, &linear);
1289 if (rc != X86EMUL_CONTINUE)
1290 return rc;
1291 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1292 &ctxt->exception);
1293 }
1294
1295 static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1296 struct segmented_address addr,
1297 const void *orig_data, const void *data,
1298 unsigned size)
1299 {
1300 int rc;
1301 ulong linear;
1302
1303 rc = linearize(ctxt, addr, size, true, &linear);
1304 if (rc != X86EMUL_CONTINUE)
1305 return rc;
1306 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1307 size, &ctxt->exception);
1308 }
1309
1310 static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
1311 unsigned int size, unsigned short port,
1312 void *dest)
1313 {
1314 struct read_cache *rc = &ctxt->io_read;
1315
1316 if (rc->pos == rc->end) { /* refill pio read ahead */
1317 unsigned int in_page, n;
1318 unsigned int count = ctxt->rep_prefix ?
1319 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
1320 in_page = (ctxt->eflags & EFLG_DF) ?
1321 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1322 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
1323 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1324 count);
1325 if (n == 0)
1326 n = 1;
1327 rc->pos = rc->end = 0;
1328 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
1329 return 0;
1330 rc->end = n * size;
1331 }
1332
1333 if (ctxt->rep_prefix && !(ctxt->eflags & EFLG_DF)) {
1334 ctxt->dst.data = rc->data + rc->pos;
1335 ctxt->dst.type = OP_MEM_STR;
1336 ctxt->dst.count = (rc->end - rc->pos) / size;
1337 rc->pos = rc->end;
1338 } else {
1339 memcpy(dest, rc->data + rc->pos, size);
1340 rc->pos += size;
1341 }
1342 return 1;
1343 }
1344
1345 static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1346 u16 index, struct desc_struct *desc)
1347 {
1348 struct desc_ptr dt;
1349 ulong addr;
1350
1351 ctxt->ops->get_idt(ctxt, &dt);
1352
1353 if (dt.size < index * 8 + 7)
1354 return emulate_gp(ctxt, index << 3 | 0x2);
1355
1356 addr = dt.address + index * 8;
1357 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1358 &ctxt->exception);
1359 }
1360
1361 static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
1362 u16 selector, struct desc_ptr *dt)
1363 {
1364 const struct x86_emulate_ops *ops = ctxt->ops;
1365
1366 if (selector & 1 << 2) {
1367 struct desc_struct desc;
1368 u16 sel;
1369
1370 memset (dt, 0, sizeof *dt);
1371 if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR))
1372 return;
1373
1374 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1375 dt->address = get_desc_base(&desc);
1376 } else
1377 ops->get_gdt(ctxt, dt);
1378 }
1379
1380 /* allowed just for 8 bytes segments */
1381 static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1382 u16 selector, struct desc_struct *desc,
1383 ulong *desc_addr_p)
1384 {
1385 struct desc_ptr dt;
1386 u16 index = selector >> 3;
1387 ulong addr;
1388
1389 get_descriptor_table_ptr(ctxt, selector, &dt);
1390
1391 if (dt.size < index * 8 + 7)
1392 return emulate_gp(ctxt, selector & 0xfffc);
1393
1394 *desc_addr_p = addr = dt.address + index * 8;
1395 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1396 &ctxt->exception);
1397 }
1398
1399 /* allowed just for 8 bytes segments */
1400 static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1401 u16 selector, struct desc_struct *desc)
1402 {
1403 struct desc_ptr dt;
1404 u16 index = selector >> 3;
1405 ulong addr;
1406
1407 get_descriptor_table_ptr(ctxt, selector, &dt);
1408
1409 if (dt.size < index * 8 + 7)
1410 return emulate_gp(ctxt, selector & 0xfffc);
1411
1412 addr = dt.address + index * 8;
1413 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1414 &ctxt->exception);
1415 }
1416
1417 /* Does not support long mode */
1418 static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1419 u16 selector, int seg)
1420 {
1421 struct desc_struct seg_desc, old_desc;
1422 u8 dpl, rpl, cpl;
1423 unsigned err_vec = GP_VECTOR;
1424 u32 err_code = 0;
1425 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1426 ulong desc_addr;
1427 int ret;
1428 u16 dummy;
1429
1430 memset(&seg_desc, 0, sizeof seg_desc);
1431
1432 if (ctxt->mode == X86EMUL_MODE_REAL) {
1433 /* set real mode segment descriptor (keep limit etc. for
1434 * unreal mode) */
1435 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
1436 set_desc_base(&seg_desc, selector << 4);
1437 goto load;
1438 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
1439 /* VM86 needs a clean new segment descriptor */
1440 set_desc_base(&seg_desc, selector << 4);
1441 set_desc_limit(&seg_desc, 0xffff);
1442 seg_desc.type = 3;
1443 seg_desc.p = 1;
1444 seg_desc.s = 1;
1445 seg_desc.dpl = 3;
1446 goto load;
1447 }
1448
1449 rpl = selector & 3;
1450 cpl = ctxt->ops->cpl(ctxt);
1451
1452 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1453 if ((seg == VCPU_SREG_CS
1454 || (seg == VCPU_SREG_SS
1455 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1456 || seg == VCPU_SREG_TR)
1457 && null_selector)
1458 goto exception;
1459
1460 /* TR should be in GDT only */
1461 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1462 goto exception;
1463
1464 if (null_selector) /* for NULL selector skip all following checks */
1465 goto load;
1466
1467 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
1468 if (ret != X86EMUL_CONTINUE)
1469 return ret;
1470
1471 err_code = selector & 0xfffc;
1472 err_vec = GP_VECTOR;
1473
1474 /* can't load system descriptor into segment selector */
1475 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1476 goto exception;
1477
1478 if (!seg_desc.p) {
1479 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1480 goto exception;
1481 }
1482
1483 dpl = seg_desc.dpl;
1484
1485 switch (seg) {
1486 case VCPU_SREG_SS:
1487 /*
1488 * segment is not a writable data segment or segment
1489 * selector's RPL != CPL or segment selector's RPL != CPL
1490 */
1491 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1492 goto exception;
1493 break;
1494 case VCPU_SREG_CS:
1495 if (!(seg_desc.type & 8))
1496 goto exception;
1497
1498 if (seg_desc.type & 4) {
1499 /* conforming */
1500 if (dpl > cpl)
1501 goto exception;
1502 } else {
1503 /* nonconforming */
1504 if (rpl > cpl || dpl != cpl)
1505 goto exception;
1506 }
1507 /* CS(RPL) <- CPL */
1508 selector = (selector & 0xfffc) | cpl;
1509 break;
1510 case VCPU_SREG_TR:
1511 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1512 goto exception;
1513 old_desc = seg_desc;
1514 seg_desc.type |= 2; /* busy */
1515 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1516 sizeof(seg_desc), &ctxt->exception);
1517 if (ret != X86EMUL_CONTINUE)
1518 return ret;
1519 break;
1520 case VCPU_SREG_LDTR:
1521 if (seg_desc.s || seg_desc.type != 2)
1522 goto exception;
1523 break;
1524 default: /* DS, ES, FS, or GS */
1525 /*
1526 * segment is not a data or readable code segment or
1527 * ((segment is a data or nonconforming code segment)
1528 * and (both RPL and CPL > DPL))
1529 */
1530 if ((seg_desc.type & 0xa) == 0x8 ||
1531 (((seg_desc.type & 0xc) != 0xc) &&
1532 (rpl > dpl && cpl > dpl)))
1533 goto exception;
1534 break;
1535 }
1536
1537 if (seg_desc.s) {
1538 /* mark segment as accessed */
1539 seg_desc.type |= 1;
1540 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
1541 if (ret != X86EMUL_CONTINUE)
1542 return ret;
1543 }
1544 load:
1545 ctxt->ops->set_segment(ctxt, selector, &seg_desc, 0, seg);
1546 return X86EMUL_CONTINUE;
1547 exception:
1548 emulate_exception(ctxt, err_vec, err_code, true);
1549 return X86EMUL_PROPAGATE_FAULT;
1550 }
1551
1552 static void write_register_operand(struct operand *op)
1553 {
1554 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1555 switch (op->bytes) {
1556 case 1:
1557 *(u8 *)op->addr.reg = (u8)op->val;
1558 break;
1559 case 2:
1560 *(u16 *)op->addr.reg = (u16)op->val;
1561 break;
1562 case 4:
1563 *op->addr.reg = (u32)op->val;
1564 break; /* 64b: zero-extend */
1565 case 8:
1566 *op->addr.reg = op->val;
1567 break;
1568 }
1569 }
1570
1571 static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
1572 {
1573 int rc;
1574
1575 switch (op->type) {
1576 case OP_REG:
1577 write_register_operand(op);
1578 break;
1579 case OP_MEM:
1580 if (ctxt->lock_prefix)
1581 rc = segmented_cmpxchg(ctxt,
1582 op->addr.mem,
1583 &op->orig_val,
1584 &op->val,
1585 op->bytes);
1586 else
1587 rc = segmented_write(ctxt,
1588 op->addr.mem,
1589 &op->val,
1590 op->bytes);
1591 if (rc != X86EMUL_CONTINUE)
1592 return rc;
1593 break;
1594 case OP_MEM_STR:
1595 rc = segmented_write(ctxt,
1596 op->addr.mem,
1597 op->data,
1598 op->bytes * op->count);
1599 if (rc != X86EMUL_CONTINUE)
1600 return rc;
1601 break;
1602 case OP_XMM:
1603 write_sse_reg(ctxt, &op->vec_val, op->addr.xmm);
1604 break;
1605 case OP_MM:
1606 write_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
1607 break;
1608 case OP_NONE:
1609 /* no writeback */
1610 break;
1611 default:
1612 break;
1613 }
1614 return X86EMUL_CONTINUE;
1615 }
1616
1617 static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
1618 {
1619 struct segmented_address addr;
1620
1621 rsp_increment(ctxt, -bytes);
1622 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
1623 addr.seg = VCPU_SREG_SS;
1624
1625 return segmented_write(ctxt, addr, data, bytes);
1626 }
1627
1628 static int em_push(struct x86_emulate_ctxt *ctxt)
1629 {
1630 /* Disable writeback. */
1631 ctxt->dst.type = OP_NONE;
1632 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
1633 }
1634
1635 static int emulate_pop(struct x86_emulate_ctxt *ctxt,
1636 void *dest, int len)
1637 {
1638 int rc;
1639 struct segmented_address addr;
1640
1641 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
1642 addr.seg = VCPU_SREG_SS;
1643 rc = segmented_read(ctxt, addr, dest, len);
1644 if (rc != X86EMUL_CONTINUE)
1645 return rc;
1646
1647 rsp_increment(ctxt, len);
1648 return rc;
1649 }
1650
1651 static int em_pop(struct x86_emulate_ctxt *ctxt)
1652 {
1653 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
1654 }
1655
1656 static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1657 void *dest, int len)
1658 {
1659 int rc;
1660 unsigned long val, change_mask;
1661 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1662 int cpl = ctxt->ops->cpl(ctxt);
1663
1664 rc = emulate_pop(ctxt, &val, len);
1665 if (rc != X86EMUL_CONTINUE)
1666 return rc;
1667
1668 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1669 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
1670
1671 switch(ctxt->mode) {
1672 case X86EMUL_MODE_PROT64:
1673 case X86EMUL_MODE_PROT32:
1674 case X86EMUL_MODE_PROT16:
1675 if (cpl == 0)
1676 change_mask |= EFLG_IOPL;
1677 if (cpl <= iopl)
1678 change_mask |= EFLG_IF;
1679 break;
1680 case X86EMUL_MODE_VM86:
1681 if (iopl < 3)
1682 return emulate_gp(ctxt, 0);
1683 change_mask |= EFLG_IF;
1684 break;
1685 default: /* real mode */
1686 change_mask |= (EFLG_IOPL | EFLG_IF);
1687 break;
1688 }
1689
1690 *(unsigned long *)dest =
1691 (ctxt->eflags & ~change_mask) | (val & change_mask);
1692
1693 return rc;
1694 }
1695
1696 static int em_popf(struct x86_emulate_ctxt *ctxt)
1697 {
1698 ctxt->dst.type = OP_REG;
1699 ctxt->dst.addr.reg = &ctxt->eflags;
1700 ctxt->dst.bytes = ctxt->op_bytes;
1701 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
1702 }
1703
1704 static int em_enter(struct x86_emulate_ctxt *ctxt)
1705 {
1706 int rc;
1707 unsigned frame_size = ctxt->src.val;
1708 unsigned nesting_level = ctxt->src2.val & 31;
1709 ulong rbp;
1710
1711 if (nesting_level)
1712 return X86EMUL_UNHANDLEABLE;
1713
1714 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1715 rc = push(ctxt, &rbp, stack_size(ctxt));
1716 if (rc != X86EMUL_CONTINUE)
1717 return rc;
1718 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
1719 stack_mask(ctxt));
1720 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1721 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
1722 stack_mask(ctxt));
1723 return X86EMUL_CONTINUE;
1724 }
1725
1726 static int em_leave(struct x86_emulate_ctxt *ctxt)
1727 {
1728 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
1729 stack_mask(ctxt));
1730 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
1731 }
1732
1733 static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
1734 {
1735 int seg = ctxt->src2.val;
1736
1737 ctxt->src.val = get_segment_selector(ctxt, seg);
1738
1739 return em_push(ctxt);
1740 }
1741
1742 static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
1743 {
1744 int seg = ctxt->src2.val;
1745 unsigned long selector;
1746 int rc;
1747
1748 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
1749 if (rc != X86EMUL_CONTINUE)
1750 return rc;
1751
1752 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
1753 return rc;
1754 }
1755
1756 static int em_pusha(struct x86_emulate_ctxt *ctxt)
1757 {
1758 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
1759 int rc = X86EMUL_CONTINUE;
1760 int reg = VCPU_REGS_RAX;
1761
1762 while (reg <= VCPU_REGS_RDI) {
1763 (reg == VCPU_REGS_RSP) ?
1764 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
1765
1766 rc = em_push(ctxt);
1767 if (rc != X86EMUL_CONTINUE)
1768 return rc;
1769
1770 ++reg;
1771 }
1772
1773 return rc;
1774 }
1775
1776 static int em_pushf(struct x86_emulate_ctxt *ctxt)
1777 {
1778 ctxt->src.val = (unsigned long)ctxt->eflags;
1779 return em_push(ctxt);
1780 }
1781
1782 static int em_popa(struct x86_emulate_ctxt *ctxt)
1783 {
1784 int rc = X86EMUL_CONTINUE;
1785 int reg = VCPU_REGS_RDI;
1786
1787 while (reg >= VCPU_REGS_RAX) {
1788 if (reg == VCPU_REGS_RSP) {
1789 rsp_increment(ctxt, ctxt->op_bytes);
1790 --reg;
1791 }
1792
1793 rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes);
1794 if (rc != X86EMUL_CONTINUE)
1795 break;
1796 --reg;
1797 }
1798 return rc;
1799 }
1800
1801 static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
1802 {
1803 const struct x86_emulate_ops *ops = ctxt->ops;
1804 int rc;
1805 struct desc_ptr dt;
1806 gva_t cs_addr;
1807 gva_t eip_addr;
1808 u16 cs, eip;
1809
1810 /* TODO: Add limit checks */
1811 ctxt->src.val = ctxt->eflags;
1812 rc = em_push(ctxt);
1813 if (rc != X86EMUL_CONTINUE)
1814 return rc;
1815
1816 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1817
1818 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
1819 rc = em_push(ctxt);
1820 if (rc != X86EMUL_CONTINUE)
1821 return rc;
1822
1823 ctxt->src.val = ctxt->_eip;
1824 rc = em_push(ctxt);
1825 if (rc != X86EMUL_CONTINUE)
1826 return rc;
1827
1828 ops->get_idt(ctxt, &dt);
1829
1830 eip_addr = dt.address + (irq << 2);
1831 cs_addr = dt.address + (irq << 2) + 2;
1832
1833 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
1834 if (rc != X86EMUL_CONTINUE)
1835 return rc;
1836
1837 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
1838 if (rc != X86EMUL_CONTINUE)
1839 return rc;
1840
1841 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
1842 if (rc != X86EMUL_CONTINUE)
1843 return rc;
1844
1845 ctxt->_eip = eip;
1846
1847 return rc;
1848 }
1849
1850 int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
1851 {
1852 int rc;
1853
1854 invalidate_registers(ctxt);
1855 rc = __emulate_int_real(ctxt, irq);
1856 if (rc == X86EMUL_CONTINUE)
1857 writeback_registers(ctxt);
1858 return rc;
1859 }
1860
1861 static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
1862 {
1863 switch(ctxt->mode) {
1864 case X86EMUL_MODE_REAL:
1865 return __emulate_int_real(ctxt, irq);
1866 case X86EMUL_MODE_VM86:
1867 case X86EMUL_MODE_PROT16:
1868 case X86EMUL_MODE_PROT32:
1869 case X86EMUL_MODE_PROT64:
1870 default:
1871 /* Protected mode interrupts unimplemented yet */
1872 return X86EMUL_UNHANDLEABLE;
1873 }
1874 }
1875
1876 static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
1877 {
1878 int rc = X86EMUL_CONTINUE;
1879 unsigned long temp_eip = 0;
1880 unsigned long temp_eflags = 0;
1881 unsigned long cs = 0;
1882 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1883 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1884 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1885 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
1886
1887 /* TODO: Add stack limit check */
1888
1889 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
1890
1891 if (rc != X86EMUL_CONTINUE)
1892 return rc;
1893
1894 if (temp_eip & ~0xffff)
1895 return emulate_gp(ctxt, 0);
1896
1897 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1898
1899 if (rc != X86EMUL_CONTINUE)
1900 return rc;
1901
1902 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
1903
1904 if (rc != X86EMUL_CONTINUE)
1905 return rc;
1906
1907 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
1908
1909 if (rc != X86EMUL_CONTINUE)
1910 return rc;
1911
1912 ctxt->_eip = temp_eip;
1913
1914
1915 if (ctxt->op_bytes == 4)
1916 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
1917 else if (ctxt->op_bytes == 2) {
1918 ctxt->eflags &= ~0xffff;
1919 ctxt->eflags |= temp_eflags;
1920 }
1921
1922 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1923 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1924
1925 return rc;
1926 }
1927
1928 static int em_iret(struct x86_emulate_ctxt *ctxt)
1929 {
1930 switch(ctxt->mode) {
1931 case X86EMUL_MODE_REAL:
1932 return emulate_iret_real(ctxt);
1933 case X86EMUL_MODE_VM86:
1934 case X86EMUL_MODE_PROT16:
1935 case X86EMUL_MODE_PROT32:
1936 case X86EMUL_MODE_PROT64:
1937 default:
1938 /* iret from protected mode unimplemented yet */
1939 return X86EMUL_UNHANDLEABLE;
1940 }
1941 }
1942
1943 static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
1944 {
1945 int rc;
1946 unsigned short sel;
1947
1948 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
1949
1950 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
1951 if (rc != X86EMUL_CONTINUE)
1952 return rc;
1953
1954 ctxt->_eip = 0;
1955 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
1956 return X86EMUL_CONTINUE;
1957 }
1958
1959 static int em_grp45(struct x86_emulate_ctxt *ctxt)
1960 {
1961 int rc = X86EMUL_CONTINUE;
1962
1963 switch (ctxt->modrm_reg) {
1964 case 2: /* call near abs */ {
1965 long int old_eip;
1966 old_eip = ctxt->_eip;
1967 ctxt->_eip = ctxt->src.val;
1968 ctxt->src.val = old_eip;
1969 rc = em_push(ctxt);
1970 break;
1971 }
1972 case 4: /* jmp abs */
1973 ctxt->_eip = ctxt->src.val;
1974 break;
1975 case 5: /* jmp far */
1976 rc = em_jmp_far(ctxt);
1977 break;
1978 case 6: /* push */
1979 rc = em_push(ctxt);
1980 break;
1981 }
1982 return rc;
1983 }
1984
1985 static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
1986 {
1987 u64 old = ctxt->dst.orig_val64;
1988
1989 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
1990 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
1991 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
1992 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
1993 ctxt->eflags &= ~EFLG_ZF;
1994 } else {
1995 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
1996 (u32) reg_read(ctxt, VCPU_REGS_RBX);
1997
1998 ctxt->eflags |= EFLG_ZF;
1999 }
2000 return X86EMUL_CONTINUE;
2001 }
2002
2003 static int em_ret(struct x86_emulate_ctxt *ctxt)
2004 {
2005 ctxt->dst.type = OP_REG;
2006 ctxt->dst.addr.reg = &ctxt->_eip;
2007 ctxt->dst.bytes = ctxt->op_bytes;
2008 return em_pop(ctxt);
2009 }
2010
2011 static int em_ret_far(struct x86_emulate_ctxt *ctxt)
2012 {
2013 int rc;
2014 unsigned long cs;
2015 int cpl = ctxt->ops->cpl(ctxt);
2016
2017 rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes);
2018 if (rc != X86EMUL_CONTINUE)
2019 return rc;
2020 if (ctxt->op_bytes == 4)
2021 ctxt->_eip = (u32)ctxt->_eip;
2022 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
2023 if (rc != X86EMUL_CONTINUE)
2024 return rc;
2025 /* Outer-privilege level return is not implemented */
2026 if (ctxt->mode >= X86EMUL_MODE_PROT16 && (cs & 3) > cpl)
2027 return X86EMUL_UNHANDLEABLE;
2028 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
2029 return rc;
2030 }
2031
2032 static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt)
2033 {
2034 int rc;
2035
2036 rc = em_ret_far(ctxt);
2037 if (rc != X86EMUL_CONTINUE)
2038 return rc;
2039 rsp_increment(ctxt, ctxt->src.val);
2040 return X86EMUL_CONTINUE;
2041 }
2042
2043 static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2044 {
2045 /* Save real source value, then compare EAX against destination. */
2046 ctxt->src.orig_val = ctxt->src.val;
2047 ctxt->src.val = reg_read(ctxt, VCPU_REGS_RAX);
2048 fastop(ctxt, em_cmp);
2049
2050 if (ctxt->eflags & EFLG_ZF) {
2051 /* Success: write back to memory. */
2052 ctxt->dst.val = ctxt->src.orig_val;
2053 } else {
2054 /* Failure: write the value we saw to EAX. */
2055 ctxt->dst.type = OP_REG;
2056 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
2057 }
2058 return X86EMUL_CONTINUE;
2059 }
2060
2061 static int em_lseg(struct x86_emulate_ctxt *ctxt)
2062 {
2063 int seg = ctxt->src2.val;
2064 unsigned short sel;
2065 int rc;
2066
2067 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
2068
2069 rc = load_segment_descriptor(ctxt, sel, seg);
2070 if (rc != X86EMUL_CONTINUE)
2071 return rc;
2072
2073 ctxt->dst.val = ctxt->src.val;
2074 return rc;
2075 }
2076
2077 static void
2078 setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
2079 struct desc_struct *cs, struct desc_struct *ss)
2080 {
2081 cs->l = 0; /* will be adjusted later */
2082 set_desc_base(cs, 0); /* flat segment */
2083 cs->g = 1; /* 4kb granularity */
2084 set_desc_limit(cs, 0xfffff); /* 4GB limit */
2085 cs->type = 0x0b; /* Read, Execute, Accessed */
2086 cs->s = 1;
2087 cs->dpl = 0; /* will be adjusted later */
2088 cs->p = 1;
2089 cs->d = 1;
2090 cs->avl = 0;
2091
2092 set_desc_base(ss, 0); /* flat segment */
2093 set_desc_limit(ss, 0xfffff); /* 4GB limit */
2094 ss->g = 1; /* 4kb granularity */
2095 ss->s = 1;
2096 ss->type = 0x03; /* Read/Write, Accessed */
2097 ss->d = 1; /* 32bit stack segment */
2098 ss->dpl = 0;
2099 ss->p = 1;
2100 ss->l = 0;
2101 ss->avl = 0;
2102 }
2103
2104 static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2105 {
2106 u32 eax, ebx, ecx, edx;
2107
2108 eax = ecx = 0;
2109 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2110 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
2111 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2112 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2113 }
2114
2115 static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2116 {
2117 const struct x86_emulate_ops *ops = ctxt->ops;
2118 u32 eax, ebx, ecx, edx;
2119
2120 /*
2121 * syscall should always be enabled in longmode - so only become
2122 * vendor specific (cpuid) if other modes are active...
2123 */
2124 if (ctxt->mode == X86EMUL_MODE_PROT64)
2125 return true;
2126
2127 eax = 0x00000000;
2128 ecx = 0x00000000;
2129 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2130 /*
2131 * Intel ("GenuineIntel")
2132 * remark: Intel CPUs only support "syscall" in 64bit
2133 * longmode. Also an 64bit guest with a
2134 * 32bit compat-app running will #UD !! While this
2135 * behaviour can be fixed (by emulating) into AMD
2136 * response - CPUs of AMD can't behave like Intel.
2137 */
2138 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2139 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2140 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2141 return false;
2142
2143 /* AMD ("AuthenticAMD") */
2144 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2145 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2146 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2147 return true;
2148
2149 /* AMD ("AMDisbetter!") */
2150 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2151 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2152 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2153 return true;
2154
2155 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2156 return false;
2157 }
2158
2159 static int em_syscall(struct x86_emulate_ctxt *ctxt)
2160 {
2161 const struct x86_emulate_ops *ops = ctxt->ops;
2162 struct desc_struct cs, ss;
2163 u64 msr_data;
2164 u16 cs_sel, ss_sel;
2165 u64 efer = 0;
2166
2167 /* syscall is not available in real mode */
2168 if (ctxt->mode == X86EMUL_MODE_REAL ||
2169 ctxt->mode == X86EMUL_MODE_VM86)
2170 return emulate_ud(ctxt);
2171
2172 if (!(em_syscall_is_enabled(ctxt)))
2173 return emulate_ud(ctxt);
2174
2175 ops->get_msr(ctxt, MSR_EFER, &efer);
2176 setup_syscalls_segments(ctxt, &cs, &ss);
2177
2178 if (!(efer & EFER_SCE))
2179 return emulate_ud(ctxt);
2180
2181 ops->get_msr(ctxt, MSR_STAR, &msr_data);
2182 msr_data >>= 32;
2183 cs_sel = (u16)(msr_data & 0xfffc);
2184 ss_sel = (u16)(msr_data + 8);
2185
2186 if (efer & EFER_LMA) {
2187 cs.d = 0;
2188 cs.l = 1;
2189 }
2190 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2191 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
2192
2193 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
2194 if (efer & EFER_LMA) {
2195 #ifdef CONFIG_X86_64
2196 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags & ~EFLG_RF;
2197
2198 ops->get_msr(ctxt,
2199 ctxt->mode == X86EMUL_MODE_PROT64 ?
2200 MSR_LSTAR : MSR_CSTAR, &msr_data);
2201 ctxt->_eip = msr_data;
2202
2203 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
2204 ctxt->eflags &= ~(msr_data | EFLG_RF);
2205 #endif
2206 } else {
2207 /* legacy mode */
2208 ops->get_msr(ctxt, MSR_STAR, &msr_data);
2209 ctxt->_eip = (u32)msr_data;
2210
2211 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
2212 }
2213
2214 return X86EMUL_CONTINUE;
2215 }
2216
2217 static int em_sysenter(struct x86_emulate_ctxt *ctxt)
2218 {
2219 const struct x86_emulate_ops *ops = ctxt->ops;
2220 struct desc_struct cs, ss;
2221 u64 msr_data;
2222 u16 cs_sel, ss_sel;
2223 u64 efer = 0;
2224
2225 ops->get_msr(ctxt, MSR_EFER, &efer);
2226 /* inject #GP if in real mode */
2227 if (ctxt->mode == X86EMUL_MODE_REAL)
2228 return emulate_gp(ctxt, 0);
2229
2230 /*
2231 * Not recognized on AMD in compat mode (but is recognized in legacy
2232 * mode).
2233 */
2234 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
2235 && !vendor_intel(ctxt))
2236 return emulate_ud(ctxt);
2237
2238 /* XXX sysenter/sysexit have not been tested in 64bit mode.
2239 * Therefore, we inject an #UD.
2240 */
2241 if (ctxt->mode == X86EMUL_MODE_PROT64)
2242 return emulate_ud(ctxt);
2243
2244 setup_syscalls_segments(ctxt, &cs, &ss);
2245
2246 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
2247 switch (ctxt->mode) {
2248 case X86EMUL_MODE_PROT32:
2249 if ((msr_data & 0xfffc) == 0x0)
2250 return emulate_gp(ctxt, 0);
2251 break;
2252 case X86EMUL_MODE_PROT64:
2253 if (msr_data == 0x0)
2254 return emulate_gp(ctxt, 0);
2255 break;
2256 default:
2257 break;
2258 }
2259
2260 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
2261 cs_sel = (u16)msr_data;
2262 cs_sel &= ~SELECTOR_RPL_MASK;
2263 ss_sel = cs_sel + 8;
2264 ss_sel &= ~SELECTOR_RPL_MASK;
2265 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
2266 cs.d = 0;
2267 cs.l = 1;
2268 }
2269
2270 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2271 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
2272
2273 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
2274 ctxt->_eip = msr_data;
2275
2276 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
2277 *reg_write(ctxt, VCPU_REGS_RSP) = msr_data;
2278
2279 return X86EMUL_CONTINUE;
2280 }
2281
2282 static int em_sysexit(struct x86_emulate_ctxt *ctxt)
2283 {
2284 const struct x86_emulate_ops *ops = ctxt->ops;
2285 struct desc_struct cs, ss;
2286 u64 msr_data;
2287 int usermode;
2288 u16 cs_sel = 0, ss_sel = 0;
2289
2290 /* inject #GP if in real mode or Virtual 8086 mode */
2291 if (ctxt->mode == X86EMUL_MODE_REAL ||
2292 ctxt->mode == X86EMUL_MODE_VM86)
2293 return emulate_gp(ctxt, 0);
2294
2295 setup_syscalls_segments(ctxt, &cs, &ss);
2296
2297 if ((ctxt->rex_prefix & 0x8) != 0x0)
2298 usermode = X86EMUL_MODE_PROT64;
2299 else
2300 usermode = X86EMUL_MODE_PROT32;
2301
2302 cs.dpl = 3;
2303 ss.dpl = 3;
2304 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
2305 switch (usermode) {
2306 case X86EMUL_MODE_PROT32:
2307 cs_sel = (u16)(msr_data + 16);
2308 if ((msr_data & 0xfffc) == 0x0)
2309 return emulate_gp(ctxt, 0);
2310 ss_sel = (u16)(msr_data + 24);
2311 break;
2312 case X86EMUL_MODE_PROT64:
2313 cs_sel = (u16)(msr_data + 32);
2314 if (msr_data == 0x0)
2315 return emulate_gp(ctxt, 0);
2316 ss_sel = cs_sel + 8;
2317 cs.d = 0;
2318 cs.l = 1;
2319 break;
2320 }
2321 cs_sel |= SELECTOR_RPL_MASK;
2322 ss_sel |= SELECTOR_RPL_MASK;
2323
2324 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2325 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
2326
2327 ctxt->_eip = reg_read(ctxt, VCPU_REGS_RDX);
2328 *reg_write(ctxt, VCPU_REGS_RSP) = reg_read(ctxt, VCPU_REGS_RCX);
2329
2330 return X86EMUL_CONTINUE;
2331 }
2332
2333 static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
2334 {
2335 int iopl;
2336 if (ctxt->mode == X86EMUL_MODE_REAL)
2337 return false;
2338 if (ctxt->mode == X86EMUL_MODE_VM86)
2339 return true;
2340 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
2341 return ctxt->ops->cpl(ctxt) > iopl;
2342 }
2343
2344 static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
2345 u16 port, u16 len)
2346 {
2347 const struct x86_emulate_ops *ops = ctxt->ops;
2348 struct desc_struct tr_seg;
2349 u32 base3;
2350 int r;
2351 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
2352 unsigned mask = (1 << len) - 1;
2353 unsigned long base;
2354
2355 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
2356 if (!tr_seg.p)
2357 return false;
2358 if (desc_limit_scaled(&tr_seg) < 103)
2359 return false;
2360 base = get_desc_base(&tr_seg);
2361 #ifdef CONFIG_X86_64
2362 base |= ((u64)base3) << 32;
2363 #endif
2364 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
2365 if (r != X86EMUL_CONTINUE)
2366 return false;
2367 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
2368 return false;
2369 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
2370 if (r != X86EMUL_CONTINUE)
2371 return false;
2372 if ((perm >> bit_idx) & mask)
2373 return false;
2374 return true;
2375 }
2376
2377 static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
2378 u16 port, u16 len)
2379 {
2380 if (ctxt->perm_ok)
2381 return true;
2382
2383 if (emulator_bad_iopl(ctxt))
2384 if (!emulator_io_port_access_allowed(ctxt, port, len))
2385 return false;
2386
2387 ctxt->perm_ok = true;
2388
2389 return true;
2390 }
2391
2392 static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
2393 struct tss_segment_16 *tss)
2394 {
2395 tss->ip = ctxt->_eip;
2396 tss->flag = ctxt->eflags;
2397 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2398 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2399 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2400 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2401 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2402 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2403 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2404 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
2405
2406 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2407 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2408 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2409 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2410 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
2411 }
2412
2413 static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
2414 struct tss_segment_16 *tss)
2415 {
2416 int ret;
2417
2418 ctxt->_eip = tss->ip;
2419 ctxt->eflags = tss->flag | 2;
2420 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2421 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2422 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2423 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2424 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2425 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2426 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2427 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
2428
2429 /*
2430 * SDM says that segment selectors are loaded before segment
2431 * descriptors
2432 */
2433 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2434 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2435 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2436 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2437 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2438
2439 /*
2440 * Now load segment descriptors. If fault happens at this stage
2441 * it is handled in a context of new task
2442 */
2443 ret = load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR);
2444 if (ret != X86EMUL_CONTINUE)
2445 return ret;
2446 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
2447 if (ret != X86EMUL_CONTINUE)
2448 return ret;
2449 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
2450 if (ret != X86EMUL_CONTINUE)
2451 return ret;
2452 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
2453 if (ret != X86EMUL_CONTINUE)
2454 return ret;
2455 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
2456 if (ret != X86EMUL_CONTINUE)
2457 return ret;
2458
2459 return X86EMUL_CONTINUE;
2460 }
2461
2462 static int task_switch_16(struct x86_emulate_ctxt *ctxt,
2463 u16 tss_selector, u16 old_tss_sel,
2464 ulong old_tss_base, struct desc_struct *new_desc)
2465 {
2466 const struct x86_emulate_ops *ops = ctxt->ops;
2467 struct tss_segment_16 tss_seg;
2468 int ret;
2469 u32 new_tss_base = get_desc_base(new_desc);
2470
2471 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2472 &ctxt->exception);
2473 if (ret != X86EMUL_CONTINUE)
2474 /* FIXME: need to provide precise fault address */
2475 return ret;
2476
2477 save_state_to_tss16(ctxt, &tss_seg);
2478
2479 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2480 &ctxt->exception);
2481 if (ret != X86EMUL_CONTINUE)
2482 /* FIXME: need to provide precise fault address */
2483 return ret;
2484
2485 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
2486 &ctxt->exception);
2487 if (ret != X86EMUL_CONTINUE)
2488 /* FIXME: need to provide precise fault address */
2489 return ret;
2490
2491 if (old_tss_sel != 0xffff) {
2492 tss_seg.prev_task_link = old_tss_sel;
2493
2494 ret = ops->write_std(ctxt, new_tss_base,
2495 &tss_seg.prev_task_link,
2496 sizeof tss_seg.prev_task_link,
2497 &ctxt->exception);
2498 if (ret != X86EMUL_CONTINUE)
2499 /* FIXME: need to provide precise fault address */
2500 return ret;
2501 }
2502
2503 return load_state_from_tss16(ctxt, &tss_seg);
2504 }
2505
2506 static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
2507 struct tss_segment_32 *tss)
2508 {
2509 tss->cr3 = ctxt->ops->get_cr(ctxt, 3);
2510 tss->eip = ctxt->_eip;
2511 tss->eflags = ctxt->eflags;
2512 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
2513 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
2514 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
2515 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
2516 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
2517 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
2518 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
2519 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
2520
2521 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2522 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2523 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2524 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2525 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2526 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
2527 tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR);
2528 }
2529
2530 static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
2531 struct tss_segment_32 *tss)
2532 {
2533 int ret;
2534
2535 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
2536 return emulate_gp(ctxt, 0);
2537 ctxt->_eip = tss->eip;
2538 ctxt->eflags = tss->eflags | 2;
2539
2540 /* General purpose registers */
2541 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
2542 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
2543 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
2544 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
2545 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
2546 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
2547 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
2548 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
2549
2550 /*
2551 * SDM says that segment selectors are loaded before segment
2552 * descriptors
2553 */
2554 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2555 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2556 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2557 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2558 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2559 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2560 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
2561
2562 /*
2563 * If we're switching between Protected Mode and VM86, we need to make
2564 * sure to update the mode before loading the segment descriptors so
2565 * that the selectors are interpreted correctly.
2566 *
2567 * Need to get rflags to the vcpu struct immediately because it
2568 * influences the CPL which is checked at least when loading the segment
2569 * descriptors and when pushing an error code to the new kernel stack.
2570 *
2571 * TODO Introduce a separate ctxt->ops->set_cpl callback
2572 */
2573 if (ctxt->eflags & X86_EFLAGS_VM)
2574 ctxt->mode = X86EMUL_MODE_VM86;
2575 else
2576 ctxt->mode = X86EMUL_MODE_PROT32;
2577
2578 ctxt->ops->set_rflags(ctxt, ctxt->eflags);
2579
2580 /*
2581 * Now load segment descriptors. If fault happenes at this stage
2582 * it is handled in a context of new task
2583 */
2584 ret = load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2585 if (ret != X86EMUL_CONTINUE)
2586 return ret;
2587 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
2588 if (ret != X86EMUL_CONTINUE)
2589 return ret;
2590 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
2591 if (ret != X86EMUL_CONTINUE)
2592 return ret;
2593 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
2594 if (ret != X86EMUL_CONTINUE)
2595 return ret;
2596 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
2597 if (ret != X86EMUL_CONTINUE)
2598 return ret;
2599 ret = load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS);
2600 if (ret != X86EMUL_CONTINUE)
2601 return ret;
2602 ret = load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS);
2603 if (ret != X86EMUL_CONTINUE)
2604 return ret;
2605
2606 return X86EMUL_CONTINUE;
2607 }
2608
2609 static int task_switch_32(struct x86_emulate_ctxt *ctxt,
2610 u16 tss_selector, u16 old_tss_sel,
2611 ulong old_tss_base, struct desc_struct *new_desc)
2612 {
2613 const struct x86_emulate_ops *ops = ctxt->ops;
2614 struct tss_segment_32 tss_seg;
2615 int ret;
2616 u32 new_tss_base = get_desc_base(new_desc);
2617
2618 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2619 &ctxt->exception);
2620 if (ret != X86EMUL_CONTINUE)
2621 /* FIXME: need to provide precise fault address */
2622 return ret;
2623
2624 save_state_to_tss32(ctxt, &tss_seg);
2625
2626 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2627 &ctxt->exception);
2628 if (ret != X86EMUL_CONTINUE)
2629 /* FIXME: need to provide precise fault address */
2630 return ret;
2631
2632 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
2633 &ctxt->exception);
2634 if (ret != X86EMUL_CONTINUE)
2635 /* FIXME: need to provide precise fault address */
2636 return ret;
2637
2638 if (old_tss_sel != 0xffff) {
2639 tss_seg.prev_task_link = old_tss_sel;
2640
2641 ret = ops->write_std(ctxt, new_tss_base,
2642 &tss_seg.prev_task_link,
2643 sizeof tss_seg.prev_task_link,
2644 &ctxt->exception);
2645 if (ret != X86EMUL_CONTINUE)
2646 /* FIXME: need to provide precise fault address */
2647 return ret;
2648 }
2649
2650 return load_state_from_tss32(ctxt, &tss_seg);
2651 }
2652
2653 static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
2654 u16 tss_selector, int idt_index, int reason,
2655 bool has_error_code, u32 error_code)
2656 {
2657 const struct x86_emulate_ops *ops = ctxt->ops;
2658 struct desc_struct curr_tss_desc, next_tss_desc;
2659 int ret;
2660 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
2661 ulong old_tss_base =
2662 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
2663 u32 desc_limit;
2664 ulong desc_addr;
2665
2666 /* FIXME: old_tss_base == ~0 ? */
2667
2668 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
2669 if (ret != X86EMUL_CONTINUE)
2670 return ret;
2671 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
2672 if (ret != X86EMUL_CONTINUE)
2673 return ret;
2674
2675 /* FIXME: check that next_tss_desc is tss */
2676
2677 /*
2678 * Check privileges. The three cases are task switch caused by...
2679 *
2680 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2681 * 2. Exception/IRQ/iret: No check is performed
2682 * 3. jmp/call to TSS: Check against DPL of the TSS
2683 */
2684 if (reason == TASK_SWITCH_GATE) {
2685 if (idt_index != -1) {
2686 /* Software interrupts */
2687 struct desc_struct task_gate_desc;
2688 int dpl;
2689
2690 ret = read_interrupt_descriptor(ctxt, idt_index,
2691 &task_gate_desc);
2692 if (ret != X86EMUL_CONTINUE)
2693 return ret;
2694
2695 dpl = task_gate_desc.dpl;
2696 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2697 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2698 }
2699 } else if (reason != TASK_SWITCH_IRET) {
2700 int dpl = next_tss_desc.dpl;
2701 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2702 return emulate_gp(ctxt, tss_selector);
2703 }
2704
2705
2706 desc_limit = desc_limit_scaled(&next_tss_desc);
2707 if (!next_tss_desc.p ||
2708 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2709 desc_limit < 0x2b)) {
2710 emulate_ts(ctxt, tss_selector & 0xfffc);
2711 return X86EMUL_PROPAGATE_FAULT;
2712 }
2713
2714 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2715 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2716 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
2717 }
2718
2719 if (reason == TASK_SWITCH_IRET)
2720 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2721
2722 /* set back link to prev task only if NT bit is set in eflags
2723 note that old_tss_sel is not used after this point */
2724 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2725 old_tss_sel = 0xffff;
2726
2727 if (next_tss_desc.type & 8)
2728 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
2729 old_tss_base, &next_tss_desc);
2730 else
2731 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
2732 old_tss_base, &next_tss_desc);
2733 if (ret != X86EMUL_CONTINUE)
2734 return ret;
2735
2736 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2737 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2738
2739 if (reason != TASK_SWITCH_IRET) {
2740 next_tss_desc.type |= (1 << 1); /* set busy flag */
2741 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
2742 }
2743
2744 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
2745 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
2746
2747 if (has_error_code) {
2748 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2749 ctxt->lock_prefix = 0;
2750 ctxt->src.val = (unsigned long) error_code;
2751 ret = em_push(ctxt);
2752 }
2753
2754 return ret;
2755 }
2756
2757 int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
2758 u16 tss_selector, int idt_index, int reason,
2759 bool has_error_code, u32 error_code)
2760 {
2761 int rc;
2762
2763 invalidate_registers(ctxt);
2764 ctxt->_eip = ctxt->eip;
2765 ctxt->dst.type = OP_NONE;
2766
2767 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
2768 has_error_code, error_code);
2769
2770 if (rc == X86EMUL_CONTINUE) {
2771 ctxt->eip = ctxt->_eip;
2772 writeback_registers(ctxt);
2773 }
2774
2775 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
2776 }
2777
2778 static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
2779 struct operand *op)
2780 {
2781 int df = (ctxt->eflags & EFLG_DF) ? -op->count : op->count;
2782
2783 register_address_increment(ctxt, reg_rmw(ctxt, reg), df * op->bytes);
2784 op->addr.mem.ea = register_address(ctxt, reg_read(ctxt, reg));
2785 }
2786
2787 static int em_das(struct x86_emulate_ctxt *ctxt)
2788 {
2789 u8 al, old_al;
2790 bool af, cf, old_cf;
2791
2792 cf = ctxt->eflags & X86_EFLAGS_CF;
2793 al = ctxt->dst.val;
2794
2795 old_al = al;
2796 old_cf = cf;
2797 cf = false;
2798 af = ctxt->eflags & X86_EFLAGS_AF;
2799 if ((al & 0x0f) > 9 || af) {
2800 al -= 6;
2801 cf = old_cf | (al >= 250);
2802 af = true;
2803 } else {
2804 af = false;
2805 }
2806 if (old_al > 0x99 || old_cf) {
2807 al -= 0x60;
2808 cf = true;
2809 }
2810
2811 ctxt->dst.val = al;
2812 /* Set PF, ZF, SF */
2813 ctxt->src.type = OP_IMM;
2814 ctxt->src.val = 0;
2815 ctxt->src.bytes = 1;
2816 fastop(ctxt, em_or);
2817 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2818 if (cf)
2819 ctxt->eflags |= X86_EFLAGS_CF;
2820 if (af)
2821 ctxt->eflags |= X86_EFLAGS_AF;
2822 return X86EMUL_CONTINUE;
2823 }
2824
2825 static int em_aam(struct x86_emulate_ctxt *ctxt)
2826 {
2827 u8 al, ah;
2828
2829 if (ctxt->src.val == 0)
2830 return emulate_de(ctxt);
2831
2832 al = ctxt->dst.val & 0xff;
2833 ah = al / ctxt->src.val;
2834 al %= ctxt->src.val;
2835
2836 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);
2837
2838 /* Set PF, ZF, SF */
2839 ctxt->src.type = OP_IMM;
2840 ctxt->src.val = 0;
2841 ctxt->src.bytes = 1;
2842 fastop(ctxt, em_or);
2843
2844 return X86EMUL_CONTINUE;
2845 }
2846
2847 static int em_aad(struct x86_emulate_ctxt *ctxt)
2848 {
2849 u8 al = ctxt->dst.val & 0xff;
2850 u8 ah = (ctxt->dst.val >> 8) & 0xff;
2851
2852 al = (al + (ah * ctxt->src.val)) & 0xff;
2853
2854 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
2855
2856 /* Set PF, ZF, SF */
2857 ctxt->src.type = OP_IMM;
2858 ctxt->src.val = 0;
2859 ctxt->src.bytes = 1;
2860 fastop(ctxt, em_or);
2861
2862 return X86EMUL_CONTINUE;
2863 }
2864
2865 static int em_call(struct x86_emulate_ctxt *ctxt)
2866 {
2867 long rel = ctxt->src.val;
2868
2869 ctxt->src.val = (unsigned long)ctxt->_eip;
2870 jmp_rel(ctxt, rel);
2871 return em_push(ctxt);
2872 }
2873
2874 static int em_call_far(struct x86_emulate_ctxt *ctxt)
2875 {
2876 u16 sel, old_cs;
2877 ulong old_eip;
2878 int rc;
2879
2880 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2881 old_eip = ctxt->_eip;
2882
2883 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
2884 if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
2885 return X86EMUL_CONTINUE;
2886
2887 ctxt->_eip = 0;
2888 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
2889
2890 ctxt->src.val = old_cs;
2891 rc = em_push(ctxt);
2892 if (rc != X86EMUL_CONTINUE)
2893 return rc;
2894
2895 ctxt->src.val = old_eip;
2896 return em_push(ctxt);
2897 }
2898
2899 static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2900 {
2901 int rc;
2902
2903 ctxt->dst.type = OP_REG;
2904 ctxt->dst.addr.reg = &ctxt->_eip;
2905 ctxt->dst.bytes = ctxt->op_bytes;
2906 rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
2907 if (rc != X86EMUL_CONTINUE)
2908 return rc;
2909 rsp_increment(ctxt, ctxt->src.val);
2910 return X86EMUL_CONTINUE;
2911 }
2912
2913 static int em_xchg(struct x86_emulate_ctxt *ctxt)
2914 {
2915 /* Write back the register source. */
2916 ctxt->src.val = ctxt->dst.val;
2917 write_register_operand(&ctxt->src);
2918
2919 /* Write back the memory destination with implicit LOCK prefix. */
2920 ctxt->dst.val = ctxt->src.orig_val;
2921 ctxt->lock_prefix = 1;
2922 return X86EMUL_CONTINUE;
2923 }
2924
2925 static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2926 {
2927 ctxt->dst.val = ctxt->src2.val;
2928 return fastop(ctxt, em_imul);
2929 }
2930
2931 static int em_cwd(struct x86_emulate_ctxt *ctxt)
2932 {
2933 ctxt->dst.type = OP_REG;
2934 ctxt->dst.bytes = ctxt->src.bytes;
2935 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
2936 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
2937
2938 return X86EMUL_CONTINUE;
2939 }
2940
2941 static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2942 {
2943 u64 tsc = 0;
2944
2945 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
2946 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
2947 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
2948 return X86EMUL_CONTINUE;
2949 }
2950
2951 static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
2952 {
2953 u64 pmc;
2954
2955 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
2956 return emulate_gp(ctxt, 0);
2957 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
2958 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
2959 return X86EMUL_CONTINUE;
2960 }
2961
2962 static int em_mov(struct x86_emulate_ctxt *ctxt)
2963 {
2964 memcpy(ctxt->dst.valptr, ctxt->src.valptr, ctxt->op_bytes);
2965 return X86EMUL_CONTINUE;
2966 }
2967
2968 static int em_cr_write(struct x86_emulate_ctxt *ctxt)
2969 {
2970 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
2971 return emulate_gp(ctxt, 0);
2972
2973 /* Disable writeback. */
2974 ctxt->dst.type = OP_NONE;
2975 return X86EMUL_CONTINUE;
2976 }
2977
2978 static int em_dr_write(struct x86_emulate_ctxt *ctxt)
2979 {
2980 unsigned long val;
2981
2982 if (ctxt->mode == X86EMUL_MODE_PROT64)
2983 val = ctxt->src.val & ~0ULL;
2984 else
2985 val = ctxt->src.val & ~0U;
2986
2987 /* #UD condition is already handled. */
2988 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
2989 return emulate_gp(ctxt, 0);
2990
2991 /* Disable writeback. */
2992 ctxt->dst.type = OP_NONE;
2993 return X86EMUL_CONTINUE;
2994 }
2995
2996 static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
2997 {
2998 u64 msr_data;
2999
3000 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3001 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3002 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
3003 return emulate_gp(ctxt, 0);
3004
3005 return X86EMUL_CONTINUE;
3006 }
3007
3008 static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3009 {
3010 u64 msr_data;
3011
3012 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
3013 return emulate_gp(ctxt, 0);
3014
3015 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3016 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
3017 return X86EMUL_CONTINUE;
3018 }
3019
3020 static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3021 {
3022 if (ctxt->modrm_reg > VCPU_SREG_GS)
3023 return emulate_ud(ctxt);
3024
3025 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
3026 return X86EMUL_CONTINUE;
3027 }
3028
3029 static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3030 {
3031 u16 sel = ctxt->src.val;
3032
3033 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
3034 return emulate_ud(ctxt);
3035
3036 if (ctxt->modrm_reg == VCPU_SREG_SS)
3037 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3038
3039 /* Disable writeback. */
3040 ctxt->dst.type = OP_NONE;
3041 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
3042 }
3043
3044 static int em_lldt(struct x86_emulate_ctxt *ctxt)
3045 {
3046 u16 sel = ctxt->src.val;
3047
3048 /* Disable writeback. */
3049 ctxt->dst.type = OP_NONE;
3050 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3051 }
3052
3053 static int em_ltr(struct x86_emulate_ctxt *ctxt)
3054 {
3055 u16 sel = ctxt->src.val;
3056
3057 /* Disable writeback. */
3058 ctxt->dst.type = OP_NONE;
3059 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3060 }
3061
3062 static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3063 {
3064 int rc;
3065 ulong linear;
3066
3067 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
3068 if (rc == X86EMUL_CONTINUE)
3069 ctxt->ops->invlpg(ctxt, linear);
3070 /* Disable writeback. */
3071 ctxt->dst.type = OP_NONE;
3072 return X86EMUL_CONTINUE;
3073 }
3074
3075 static int em_clts(struct x86_emulate_ctxt *ctxt)
3076 {
3077 ulong cr0;
3078
3079 cr0 = ctxt->ops->get_cr(ctxt, 0);
3080 cr0 &= ~X86_CR0_TS;
3081 ctxt->ops->set_cr(ctxt, 0, cr0);
3082 return X86EMUL_CONTINUE;
3083 }
3084
3085 static int em_vmcall(struct x86_emulate_ctxt *ctxt)
3086 {
3087 int rc;
3088
3089 if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1)
3090 return X86EMUL_UNHANDLEABLE;
3091
3092 rc = ctxt->ops->fix_hypercall(ctxt);
3093 if (rc != X86EMUL_CONTINUE)
3094 return rc;
3095
3096 /* Let the processor re-execute the fixed hypercall */
3097 ctxt->_eip = ctxt->eip;
3098 /* Disable writeback. */
3099 ctxt->dst.type = OP_NONE;
3100 return X86EMUL_CONTINUE;
3101 }
3102
3103 static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3104 void (*get)(struct x86_emulate_ctxt *ctxt,
3105 struct desc_ptr *ptr))
3106 {
3107 struct desc_ptr desc_ptr;
3108
3109 if (ctxt->mode == X86EMUL_MODE_PROT64)
3110 ctxt->op_bytes = 8;
3111 get(ctxt, &desc_ptr);
3112 if (ctxt->op_bytes == 2) {
3113 ctxt->op_bytes = 4;
3114 desc_ptr.address &= 0x00ffffff;
3115 }
3116 /* Disable writeback. */
3117 ctxt->dst.type = OP_NONE;
3118 return segmented_write(ctxt, ctxt->dst.addr.mem,
3119 &desc_ptr, 2 + ctxt->op_bytes);
3120 }
3121
3122 static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3123 {
3124 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3125 }
3126
3127 static int em_sidt(struct x86_emulate_ctxt *ctxt)
3128 {
3129 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3130 }
3131
3132 static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3133 {
3134 struct desc_ptr desc_ptr;
3135 int rc;
3136
3137 if (ctxt->mode == X86EMUL_MODE_PROT64)
3138 ctxt->op_bytes = 8;
3139 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
3140 &desc_ptr.size, &desc_ptr.address,
3141 ctxt->op_bytes);
3142 if (rc != X86EMUL_CONTINUE)
3143 return rc;
3144 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3145 /* Disable writeback. */
3146 ctxt->dst.type = OP_NONE;
3147 return X86EMUL_CONTINUE;
3148 }
3149
3150 static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
3151 {
3152 int rc;
3153
3154 rc = ctxt->ops->fix_hypercall(ctxt);
3155
3156 /* Disable writeback. */
3157 ctxt->dst.type = OP_NONE;
3158 return rc;
3159 }
3160
3161 static int em_lidt(struct x86_emulate_ctxt *ctxt)
3162 {
3163 struct desc_ptr desc_ptr;
3164 int rc;
3165
3166 if (ctxt->mode == X86EMUL_MODE_PROT64)
3167 ctxt->op_bytes = 8;
3168 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
3169 &desc_ptr.size, &desc_ptr.address,
3170 ctxt->op_bytes);
3171 if (rc != X86EMUL_CONTINUE)
3172 return rc;
3173 ctxt->ops->set_idt(ctxt, &desc_ptr);
3174 /* Disable writeback. */
3175 ctxt->dst.type = OP_NONE;
3176 return X86EMUL_CONTINUE;
3177 }
3178
3179 static int em_smsw(struct x86_emulate_ctxt *ctxt)
3180 {
3181 ctxt->dst.bytes = 2;
3182 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
3183 return X86EMUL_CONTINUE;
3184 }
3185
3186 static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3187 {
3188 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
3189 | (ctxt->src.val & 0x0f));
3190 ctxt->dst.type = OP_NONE;
3191 return X86EMUL_CONTINUE;
3192 }
3193
3194 static int em_loop(struct x86_emulate_ctxt *ctxt)
3195 {
3196 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX), -1);
3197 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
3198 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
3199 jmp_rel(ctxt, ctxt->src.val);
3200
3201 return X86EMUL_CONTINUE;
3202 }
3203
3204 static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3205 {
3206 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
3207 jmp_rel(ctxt, ctxt->src.val);
3208
3209 return X86EMUL_CONTINUE;
3210 }
3211
3212 static int em_in(struct x86_emulate_ctxt *ctxt)
3213 {
3214 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3215 &ctxt->dst.val))
3216 return X86EMUL_IO_NEEDED;
3217
3218 return X86EMUL_CONTINUE;
3219 }
3220
3221 static int em_out(struct x86_emulate_ctxt *ctxt)
3222 {
3223 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3224 &ctxt->src.val, 1);
3225 /* Disable writeback. */
3226 ctxt->dst.type = OP_NONE;
3227 return X86EMUL_CONTINUE;
3228 }
3229
3230 static int em_cli(struct x86_emulate_ctxt *ctxt)
3231 {
3232 if (emulator_bad_iopl(ctxt))
3233 return emulate_gp(ctxt, 0);
3234
3235 ctxt->eflags &= ~X86_EFLAGS_IF;
3236 return X86EMUL_CONTINUE;
3237 }
3238
3239 static int em_sti(struct x86_emulate_ctxt *ctxt)
3240 {
3241 if (emulator_bad_iopl(ctxt))
3242 return emulate_gp(ctxt, 0);
3243
3244 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3245 ctxt->eflags |= X86_EFLAGS_IF;
3246 return X86EMUL_CONTINUE;
3247 }
3248
3249 static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3250 {
3251 u32 eax, ebx, ecx, edx;
3252
3253 eax = reg_read(ctxt, VCPU_REGS_RAX);
3254 ecx = reg_read(ctxt, VCPU_REGS_RCX);
3255 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
3256 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3257 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3258 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3259 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
3260 return X86EMUL_CONTINUE;
3261 }
3262
3263 static int em_lahf(struct x86_emulate_ctxt *ctxt)
3264 {
3265 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3266 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
3267 return X86EMUL_CONTINUE;
3268 }
3269
3270 static int em_bswap(struct x86_emulate_ctxt *ctxt)
3271 {
3272 switch (ctxt->op_bytes) {
3273 #ifdef CONFIG_X86_64
3274 case 8:
3275 asm("bswap %0" : "+r"(ctxt->dst.val));
3276 break;
3277 #endif
3278 default:
3279 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3280 break;
3281 }
3282 return X86EMUL_CONTINUE;
3283 }
3284
3285 static bool valid_cr(int nr)
3286 {
3287 switch (nr) {
3288 case 0:
3289 case 2 ... 4:
3290 case 8:
3291 return true;
3292 default:
3293 return false;
3294 }
3295 }
3296
3297 static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3298 {
3299 if (!valid_cr(ctxt->modrm_reg))
3300 return emulate_ud(ctxt);
3301
3302 return X86EMUL_CONTINUE;
3303 }
3304
3305 static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3306 {
3307 u64 new_val = ctxt->src.val64;
3308 int cr = ctxt->modrm_reg;
3309 u64 efer = 0;
3310
3311 static u64 cr_reserved_bits[] = {
3312 0xffffffff00000000ULL,
3313 0, 0, 0, /* CR3 checked later */
3314 CR4_RESERVED_BITS,
3315 0, 0, 0,
3316 CR8_RESERVED_BITS,
3317 };
3318
3319 if (!valid_cr(cr))
3320 return emulate_ud(ctxt);
3321
3322 if (new_val & cr_reserved_bits[cr])
3323 return emulate_gp(ctxt, 0);
3324
3325 switch (cr) {
3326 case 0: {
3327 u64 cr4;
3328 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3329 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3330 return emulate_gp(ctxt, 0);
3331
3332 cr4 = ctxt->ops->get_cr(ctxt, 4);
3333 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3334
3335 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3336 !(cr4 & X86_CR4_PAE))
3337 return emulate_gp(ctxt, 0);
3338
3339 break;
3340 }
3341 case 3: {
3342 u64 rsvd = 0;
3343
3344 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3345 if (efer & EFER_LMA)
3346 rsvd = CR3_L_MODE_RESERVED_BITS;
3347 else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE)
3348 rsvd = CR3_PAE_RESERVED_BITS;
3349 else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG)
3350 rsvd = CR3_NONPAE_RESERVED_BITS;
3351
3352 if (new_val & rsvd)
3353 return emulate_gp(ctxt, 0);
3354
3355 break;
3356 }
3357 case 4: {
3358 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3359
3360 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3361 return emulate_gp(ctxt, 0);
3362
3363 break;
3364 }
3365 }
3366
3367 return X86EMUL_CONTINUE;
3368 }
3369
3370 static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3371 {
3372 unsigned long dr7;
3373
3374 ctxt->ops->get_dr(ctxt, 7, &dr7);
3375
3376 /* Check if DR7.Global_Enable is set */
3377 return dr7 & (1 << 13);
3378 }
3379
3380 static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3381 {
3382 int dr = ctxt->modrm_reg;
3383 u64 cr4;
3384
3385 if (dr > 7)
3386 return emulate_ud(ctxt);
3387
3388 cr4 = ctxt->ops->get_cr(ctxt, 4);
3389 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3390 return emulate_ud(ctxt);
3391
3392 if (check_dr7_gd(ctxt))
3393 return emulate_db(ctxt);
3394
3395 return X86EMUL_CONTINUE;
3396 }
3397
3398 static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3399 {
3400 u64 new_val = ctxt->src.val64;
3401 int dr = ctxt->modrm_reg;
3402
3403 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3404 return emulate_gp(ctxt, 0);
3405
3406 return check_dr_read(ctxt);
3407 }
3408
3409 static int check_svme(struct x86_emulate_ctxt *ctxt)
3410 {
3411 u64 efer;
3412
3413 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3414
3415 if (!(efer & EFER_SVME))
3416 return emulate_ud(ctxt);
3417
3418 return X86EMUL_CONTINUE;
3419 }
3420
3421 static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3422 {
3423 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
3424
3425 /* Valid physical address? */
3426 if (rax & 0xffff000000000000ULL)
3427 return emulate_gp(ctxt, 0);
3428
3429 return check_svme(ctxt);
3430 }
3431
3432 static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3433 {
3434 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
3435
3436 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
3437 return emulate_ud(ctxt);
3438
3439 return X86EMUL_CONTINUE;
3440 }
3441
3442 static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3443 {
3444 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
3445 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
3446
3447 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
3448 (rcx > 3))
3449 return emulate_gp(ctxt, 0);
3450
3451 return X86EMUL_CONTINUE;
3452 }
3453
3454 static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3455 {
3456 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3457 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
3458 return emulate_gp(ctxt, 0);
3459
3460 return X86EMUL_CONTINUE;
3461 }
3462
3463 static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3464 {
3465 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3466 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
3467 return emulate_gp(ctxt, 0);
3468
3469 return X86EMUL_CONTINUE;
3470 }
3471
3472 #define D(_y) { .flags = (_y) }
3473 #define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
3474 #define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
3475 .check_perm = (_p) }
3476 #define N D(NotImpl)
3477 #define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
3478 #define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3479 #define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
3480 #define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
3481 #define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
3482 #define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
3483 #define II(_f, _e, _i) \
3484 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
3485 #define IIP(_f, _e, _i, _p) \
3486 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
3487 .check_perm = (_p) }
3488 #define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
3489
3490 #define D2bv(_f) D((_f) | ByteOp), D(_f)
3491 #define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
3492 #define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
3493 #define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e)
3494 #define I2bvIP(_f, _e, _i, _p) \
3495 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
3496
3497 #define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3498 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3499 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
3500
3501 static const struct opcode group7_rm1[] = {
3502 DI(SrcNone | Priv, monitor),
3503 DI(SrcNone | Priv, mwait),
3504 N, N, N, N, N, N,
3505 };
3506
3507 static const struct opcode group7_rm3[] = {
3508 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
3509 II(SrcNone | Prot | VendorSpecific, em_vmmcall, vmmcall),
3510 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3511 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3512 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3513 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3514 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3515 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
3516 };
3517
3518 static const struct opcode group7_rm7[] = {
3519 N,
3520 DIP(SrcNone, rdtscp, check_rdtsc),
3521 N, N, N, N, N, N,
3522 };
3523
3524 static const struct opcode group1[] = {
3525 F(Lock, em_add),
3526 F(Lock | PageTable, em_or),
3527 F(Lock, em_adc),
3528 F(Lock, em_sbb),
3529 F(Lock | PageTable, em_and),
3530 F(Lock, em_sub),
3531 F(Lock, em_xor),
3532 F(NoWrite, em_cmp),
3533 };
3534
3535 static const struct opcode group1A[] = {
3536 I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N,
3537 };
3538
3539 static const struct opcode group2[] = {
3540 F(DstMem | ModRM, em_rol),
3541 F(DstMem | ModRM, em_ror),
3542 F(DstMem | ModRM, em_rcl),
3543 F(DstMem | ModRM, em_rcr),
3544 F(DstMem | ModRM, em_shl),
3545 F(DstMem | ModRM, em_shr),
3546 F(DstMem | ModRM, em_shl),
3547 F(DstMem | ModRM, em_sar),
3548 };
3549
3550 static const struct opcode group3[] = {
3551 F(DstMem | SrcImm | NoWrite, em_test),
3552 F(DstMem | SrcImm | NoWrite, em_test),
3553 F(DstMem | SrcNone | Lock, em_not),
3554 F(DstMem | SrcNone | Lock, em_neg),
3555 F(DstXacc | Src2Mem, em_mul_ex),
3556 F(DstXacc | Src2Mem, em_imul_ex),
3557 F(DstXacc | Src2Mem, em_div_ex),
3558 F(DstXacc | Src2Mem, em_idiv_ex),
3559 };
3560
3561 static const struct opcode group4[] = {
3562 F(ByteOp | DstMem | SrcNone | Lock, em_inc),
3563 F(ByteOp | DstMem | SrcNone | Lock, em_dec),
3564 N, N, N, N, N, N,
3565 };
3566
3567 static const struct opcode group5[] = {
3568 F(DstMem | SrcNone | Lock, em_inc),
3569 F(DstMem | SrcNone | Lock, em_dec),
3570 I(SrcMem | Stack, em_grp45),
3571 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
3572 I(SrcMem | Stack, em_grp45),
3573 I(SrcMemFAddr | ImplicitOps, em_grp45),
3574 I(SrcMem | Stack, em_grp45), D(Undefined),
3575 };
3576
3577 static const struct opcode group6[] = {
3578 DI(Prot, sldt),
3579 DI(Prot, str),
3580 II(Prot | Priv | SrcMem16, em_lldt, lldt),
3581 II(Prot | Priv | SrcMem16, em_ltr, ltr),
3582 N, N, N, N,
3583 };
3584
3585 static const struct group_dual group7 = { {
3586 II(Mov | DstMem | Priv, em_sgdt, sgdt),
3587 II(Mov | DstMem | Priv, em_sidt, sidt),
3588 II(SrcMem | Priv, em_lgdt, lgdt),
3589 II(SrcMem | Priv, em_lidt, lidt),
3590 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3591 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3592 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
3593 }, {
3594 I(SrcNone | Priv | VendorSpecific, em_vmcall),
3595 EXT(0, group7_rm1),
3596 N, EXT(0, group7_rm3),
3597 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3598 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3599 EXT(0, group7_rm7),
3600 } };
3601
3602 static const struct opcode group8[] = {
3603 N, N, N, N,
3604 F(DstMem | SrcImmByte | NoWrite, em_bt),
3605 F(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3606 F(DstMem | SrcImmByte | Lock, em_btr),
3607 F(DstMem | SrcImmByte | Lock | PageTable, em_btc),
3608 };
3609
3610 static const struct group_dual group9 = { {
3611 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
3612 }, {
3613 N, N, N, N, N, N, N, N,
3614 } };
3615
3616 static const struct opcode group11[] = {
3617 I(DstMem | SrcImm | Mov | PageTable, em_mov),
3618 X7(D(Undefined)),
3619 };
3620
3621 static const struct gprefix pfx_0f_6f_0f_7f = {
3622 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
3623 };
3624
3625 static const struct gprefix pfx_vmovntpx = {
3626 I(0, em_mov), N, N, N,
3627 };
3628
3629 static const struct escape escape_d9 = { {
3630 N, N, N, N, N, N, N, I(DstMem, em_fnstcw),
3631 }, {
3632 /* 0xC0 - 0xC7 */
3633 N, N, N, N, N, N, N, N,
3634 /* 0xC8 - 0xCF */
3635 N, N, N, N, N, N, N, N,
3636 /* 0xD0 - 0xC7 */
3637 N, N, N, N, N, N, N, N,
3638 /* 0xD8 - 0xDF */
3639 N, N, N, N, N, N, N, N,
3640 /* 0xE0 - 0xE7 */
3641 N, N, N, N, N, N, N, N,
3642 /* 0xE8 - 0xEF */
3643 N, N, N, N, N, N, N, N,
3644 /* 0xF0 - 0xF7 */
3645 N, N, N, N, N, N, N, N,
3646 /* 0xF8 - 0xFF */
3647 N, N, N, N, N, N, N, N,
3648 } };
3649
3650 static const struct escape escape_db = { {
3651 N, N, N, N, N, N, N, N,
3652 }, {
3653 /* 0xC0 - 0xC7 */
3654 N, N, N, N, N, N, N, N,
3655 /* 0xC8 - 0xCF */
3656 N, N, N, N, N, N, N, N,
3657 /* 0xD0 - 0xC7 */
3658 N, N, N, N, N, N, N, N,
3659 /* 0xD8 - 0xDF */
3660 N, N, N, N, N, N, N, N,
3661 /* 0xE0 - 0xE7 */
3662 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
3663 /* 0xE8 - 0xEF */
3664 N, N, N, N, N, N, N, N,
3665 /* 0xF0 - 0xF7 */
3666 N, N, N, N, N, N, N, N,
3667 /* 0xF8 - 0xFF */
3668 N, N, N, N, N, N, N, N,
3669 } };
3670
3671 static const struct escape escape_dd = { {
3672 N, N, N, N, N, N, N, I(DstMem, em_fnstsw),
3673 }, {
3674 /* 0xC0 - 0xC7 */
3675 N, N, N, N, N, N, N, N,
3676 /* 0xC8 - 0xCF */
3677 N, N, N, N, N, N, N, N,
3678 /* 0xD0 - 0xC7 */
3679 N, N, N, N, N, N, N, N,
3680 /* 0xD8 - 0xDF */
3681 N, N, N, N, N, N, N, N,
3682 /* 0xE0 - 0xE7 */
3683 N, N, N, N, N, N, N, N,
3684 /* 0xE8 - 0xEF */
3685 N, N, N, N, N, N, N, N,
3686 /* 0xF0 - 0xF7 */
3687 N, N, N, N, N, N, N, N,
3688 /* 0xF8 - 0xFF */
3689 N, N, N, N, N, N, N, N,
3690 } };
3691
3692 static const struct opcode opcode_table[256] = {
3693 /* 0x00 - 0x07 */
3694 F6ALU(Lock, em_add),
3695 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3696 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
3697 /* 0x08 - 0x0F */
3698 F6ALU(Lock | PageTable, em_or),
3699 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3700 N,
3701 /* 0x10 - 0x17 */
3702 F6ALU(Lock, em_adc),
3703 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3704 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
3705 /* 0x18 - 0x1F */
3706 F6ALU(Lock, em_sbb),
3707 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3708 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
3709 /* 0x20 - 0x27 */
3710 F6ALU(Lock | PageTable, em_and), N, N,
3711 /* 0x28 - 0x2F */
3712 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
3713 /* 0x30 - 0x37 */
3714 F6ALU(Lock, em_xor), N, N,
3715 /* 0x38 - 0x3F */
3716 F6ALU(NoWrite, em_cmp), N, N,
3717 /* 0x40 - 0x4F */
3718 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
3719 /* 0x50 - 0x57 */
3720 X8(I(SrcReg | Stack, em_push)),
3721 /* 0x58 - 0x5F */
3722 X8(I(DstReg | Stack, em_pop)),
3723 /* 0x60 - 0x67 */
3724 I(ImplicitOps | Stack | No64, em_pusha),
3725 I(ImplicitOps | Stack | No64, em_popa),
3726 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3727 N, N, N, N,
3728 /* 0x68 - 0x6F */
3729 I(SrcImm | Mov | Stack, em_push),
3730 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
3731 I(SrcImmByte | Mov | Stack, em_push),
3732 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
3733 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
3734 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
3735 /* 0x70 - 0x7F */
3736 X16(D(SrcImmByte)),
3737 /* 0x80 - 0x87 */
3738 G(ByteOp | DstMem | SrcImm, group1),
3739 G(DstMem | SrcImm, group1),
3740 G(ByteOp | DstMem | SrcImm | No64, group1),
3741 G(DstMem | SrcImmByte, group1),
3742 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
3743 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
3744 /* 0x88 - 0x8F */
3745 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
3746 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
3747 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
3748 D(ModRM | SrcMem | NoAccess | DstReg),
3749 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3750 G(0, group1A),
3751 /* 0x90 - 0x97 */
3752 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
3753 /* 0x98 - 0x9F */
3754 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
3755 I(SrcImmFAddr | No64, em_call_far), N,
3756 II(ImplicitOps | Stack, em_pushf, pushf),
3757 II(ImplicitOps | Stack, em_popf, popf), N, I(ImplicitOps, em_lahf),
3758 /* 0xA0 - 0xA7 */
3759 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
3760 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
3761 I2bv(SrcSI | DstDI | Mov | String, em_mov),
3762 F2bv(SrcSI | DstDI | String | NoWrite, em_cmp),
3763 /* 0xA8 - 0xAF */
3764 F2bv(DstAcc | SrcImm | NoWrite, em_test),
3765 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3766 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
3767 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp),
3768 /* 0xB0 - 0xB7 */
3769 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
3770 /* 0xB8 - 0xBF */
3771 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
3772 /* 0xC0 - 0xC7 */
3773 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
3774 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
3775 I(ImplicitOps | Stack, em_ret),
3776 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
3777 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
3778 G(ByteOp, group11), G(0, group11),
3779 /* 0xC8 - 0xCF */
3780 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
3781 I(ImplicitOps | Stack | SrcImmU16, em_ret_far_imm),
3782 I(ImplicitOps | Stack, em_ret_far),
3783 D(ImplicitOps), DI(SrcImmByte, intn),
3784 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
3785 /* 0xD0 - 0xD7 */
3786 G(Src2One | ByteOp, group2), G(Src2One, group2),
3787 G(Src2CL | ByteOp, group2), G(Src2CL, group2),
3788 I(DstAcc | SrcImmUByte | No64, em_aam),
3789 I(DstAcc | SrcImmUByte | No64, em_aad),
3790 F(DstAcc | ByteOp | No64, em_salc),
3791 I(DstAcc | SrcXLat | ByteOp, em_mov),
3792 /* 0xD8 - 0xDF */
3793 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
3794 /* 0xE0 - 0xE7 */
3795 X3(I(SrcImmByte, em_loop)),
3796 I(SrcImmByte, em_jcxz),
3797 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
3798 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
3799 /* 0xE8 - 0xEF */
3800 I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps),
3801 I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
3802 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
3803 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
3804 /* 0xF0 - 0xF7 */
3805 N, DI(ImplicitOps, icebp), N, N,
3806 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3807 G(ByteOp, group3), G(0, group3),
3808 /* 0xF8 - 0xFF */
3809 D(ImplicitOps), D(ImplicitOps),
3810 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
3811 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3812 };
3813
3814 static const struct opcode twobyte_table[256] = {
3815 /* 0x00 - 0x0F */
3816 G(0, group6), GD(0, &group7), N, N,
3817 N, I(ImplicitOps | VendorSpecific, em_syscall),
3818 II(ImplicitOps | Priv, em_clts, clts), N,
3819 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
3820 N, D(ImplicitOps | ModRM), N, N,
3821 /* 0x10 - 0x1F */
3822 N, N, N, N, N, N, N, N,
3823 D(ImplicitOps | ModRM), N, N, N, N, N, N, D(ImplicitOps | ModRM),
3824 /* 0x20 - 0x2F */
3825 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
3826 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
3827 IIP(ModRM | SrcMem | Priv | Op3264, em_cr_write, cr_write, check_cr_write),
3828 IIP(ModRM | SrcMem | Priv | Op3264, em_dr_write, dr_write, check_dr_write),
3829 N, N, N, N,
3830 N, N, N, GP(ModRM | DstMem | SrcReg | Sse | Mov | Aligned, &pfx_vmovntpx),
3831 N, N, N, N,
3832 /* 0x30 - 0x3F */
3833 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
3834 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
3835 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
3836 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
3837 I(ImplicitOps | VendorSpecific, em_sysenter),
3838 I(ImplicitOps | Priv | VendorSpecific, em_sysexit),
3839 N, N,
3840 N, N, N, N, N, N, N, N,
3841 /* 0x40 - 0x4F */
3842 X16(D(DstReg | SrcMem | ModRM | Mov)),
3843 /* 0x50 - 0x5F */
3844 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3845 /* 0x60 - 0x6F */
3846 N, N, N, N,
3847 N, N, N, N,
3848 N, N, N, N,
3849 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
3850 /* 0x70 - 0x7F */
3851 N, N, N, N,
3852 N, N, N, N,
3853 N, N, N, N,
3854 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
3855 /* 0x80 - 0x8F */
3856 X16(D(SrcImm)),
3857 /* 0x90 - 0x9F */
3858 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
3859 /* 0xA0 - 0xA7 */
3860 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
3861 II(ImplicitOps, em_cpuid, cpuid),
3862 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
3863 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
3864 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
3865 /* 0xA8 - 0xAF */
3866 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
3867 DI(ImplicitOps, rsm),
3868 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
3869 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
3870 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
3871 D(ModRM), F(DstReg | SrcMem | ModRM, em_imul),
3872 /* 0xB0 - 0xB7 */
3873 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
3874 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
3875 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
3876 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
3877 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
3878 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
3879 /* 0xB8 - 0xBF */
3880 N, N,
3881 G(BitOp, group8),
3882 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
3883 F(DstReg | SrcMem | ModRM, em_bsf), F(DstReg | SrcMem | ModRM, em_bsr),
3884 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
3885 /* 0xC0 - 0xC7 */
3886 F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd),
3887 N, D(DstMem | SrcReg | ModRM | Mov),
3888 N, N, N, GD(0, &group9),
3889 /* 0xC8 - 0xCF */
3890 X8(I(DstReg, em_bswap)),
3891 /* 0xD0 - 0xDF */
3892 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3893 /* 0xE0 - 0xEF */
3894 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3895 /* 0xF0 - 0xFF */
3896 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
3897 };
3898
3899 #undef D
3900 #undef N
3901 #undef G
3902 #undef GD
3903 #undef I
3904 #undef GP
3905 #undef EXT
3906
3907 #undef D2bv
3908 #undef D2bvIP
3909 #undef I2bv
3910 #undef I2bvIP
3911 #undef I6ALU
3912
3913 static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
3914 {
3915 unsigned size;
3916
3917 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3918 if (size == 8)
3919 size = 4;
3920 return size;
3921 }
3922
3923 static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
3924 unsigned size, bool sign_extension)
3925 {
3926 int rc = X86EMUL_CONTINUE;
3927
3928 op->type = OP_IMM;
3929 op->bytes = size;
3930 op->addr.mem.ea = ctxt->_eip;
3931 /* NB. Immediates are sign-extended as necessary. */
3932 switch (op->bytes) {
3933 case 1:
3934 op->val = insn_fetch(s8, ctxt);
3935 break;
3936 case 2:
3937 op->val = insn_fetch(s16, ctxt);
3938 break;
3939 case 4:
3940 op->val = insn_fetch(s32, ctxt);
3941 break;
3942 case 8:
3943 op->val = insn_fetch(s64, ctxt);
3944 break;
3945 }
3946 if (!sign_extension) {
3947 switch (op->bytes) {
3948 case 1:
3949 op->val &= 0xff;
3950 break;
3951 case 2:
3952 op->val &= 0xffff;
3953 break;
3954 case 4:
3955 op->val &= 0xffffffff;
3956 break;
3957 }
3958 }
3959 done:
3960 return rc;
3961 }
3962
3963 static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
3964 unsigned d)
3965 {
3966 int rc = X86EMUL_CONTINUE;
3967
3968 switch (d) {
3969 case OpReg:
3970 decode_register_operand(ctxt, op);
3971 break;
3972 case OpImmUByte:
3973 rc = decode_imm(ctxt, op, 1, false);
3974 break;
3975 case OpMem:
3976 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3977 mem_common:
3978 *op = ctxt->memop;
3979 ctxt->memopp = op;
3980 if ((ctxt->d & BitOp) && op == &ctxt->dst)
3981 fetch_bit_operand(ctxt);
3982 op->orig_val = op->val;
3983 break;
3984 case OpMem64:
3985 ctxt->memop.bytes = 8;
3986 goto mem_common;
3987 case OpAcc:
3988 op->type = OP_REG;
3989 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3990 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
3991 fetch_register_operand(op);
3992 op->orig_val = op->val;
3993 break;
3994 case OpAccLo:
3995 op->type = OP_REG;
3996 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes;
3997 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
3998 fetch_register_operand(op);
3999 op->orig_val = op->val;
4000 break;
4001 case OpAccHi:
4002 if (ctxt->d & ByteOp) {
4003 op->type = OP_NONE;
4004 break;
4005 }
4006 op->type = OP_REG;
4007 op->bytes = ctxt->op_bytes;
4008 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4009 fetch_register_operand(op);
4010 op->orig_val = op->val;
4011 break;
4012 case OpDI:
4013 op->type = OP_MEM;
4014 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4015 op->addr.mem.ea =
4016 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RDI));
4017 op->addr.mem.seg = VCPU_SREG_ES;
4018 op->val = 0;
4019 op->count = 1;
4020 break;
4021 case OpDX:
4022 op->type = OP_REG;
4023 op->bytes = 2;
4024 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4025 fetch_register_operand(op);
4026 break;
4027 case OpCL:
4028 op->bytes = 1;
4029 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4030 break;
4031 case OpImmByte:
4032 rc = decode_imm(ctxt, op, 1, true);
4033 break;
4034 case OpOne:
4035 op->bytes = 1;
4036 op->val = 1;
4037 break;
4038 case OpImm:
4039 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4040 break;
4041 case OpImm64:
4042 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
4043 break;
4044 case OpMem8:
4045 ctxt->memop.bytes = 1;
4046 if (ctxt->memop.type == OP_REG) {
4047 int highbyte_regs = ctxt->rex_prefix == 0;
4048
4049 ctxt->memop.addr.reg = decode_register(ctxt, ctxt->modrm_rm,
4050 highbyte_regs);
4051 fetch_register_operand(&ctxt->memop);
4052 }
4053 goto mem_common;
4054 case OpMem16:
4055 ctxt->memop.bytes = 2;
4056 goto mem_common;
4057 case OpMem32:
4058 ctxt->memop.bytes = 4;
4059 goto mem_common;
4060 case OpImmU16:
4061 rc = decode_imm(ctxt, op, 2, false);
4062 break;
4063 case OpImmU:
4064 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4065 break;
4066 case OpSI:
4067 op->type = OP_MEM;
4068 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4069 op->addr.mem.ea =
4070 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RSI));
4071 op->addr.mem.seg = seg_override(ctxt);
4072 op->val = 0;
4073 op->count = 1;
4074 break;
4075 case OpXLat:
4076 op->type = OP_MEM;
4077 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4078 op->addr.mem.ea =
4079 register_address(ctxt,
4080 reg_read(ctxt, VCPU_REGS_RBX) +
4081 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
4082 op->addr.mem.seg = seg_override(ctxt);
4083 op->val = 0;
4084 break;
4085 case OpImmFAddr:
4086 op->type = OP_IMM;
4087 op->addr.mem.ea = ctxt->_eip;
4088 op->bytes = ctxt->op_bytes + 2;
4089 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4090 break;
4091 case OpMemFAddr:
4092 ctxt->memop.bytes = ctxt->op_bytes + 2;
4093 goto mem_common;
4094 case OpES:
4095 op->val = VCPU_SREG_ES;
4096 break;
4097 case OpCS:
4098 op->val = VCPU_SREG_CS;
4099 break;
4100 case OpSS:
4101 op->val = VCPU_SREG_SS;
4102 break;
4103 case OpDS:
4104 op->val = VCPU_SREG_DS;
4105 break;
4106 case OpFS:
4107 op->val = VCPU_SREG_FS;
4108 break;
4109 case OpGS:
4110 op->val = VCPU_SREG_GS;
4111 break;
4112 case OpImplicit:
4113 /* Special instructions do their own operand decoding. */
4114 default:
4115 op->type = OP_NONE; /* Disable writeback. */
4116 break;
4117 }
4118
4119 done:
4120 return rc;
4121 }
4122
4123 int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
4124 {
4125 int rc = X86EMUL_CONTINUE;
4126 int mode = ctxt->mode;
4127 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
4128 bool op_prefix = false;
4129 struct opcode opcode;
4130
4131 ctxt->memop.type = OP_NONE;
4132 ctxt->memopp = NULL;
4133 ctxt->_eip = ctxt->eip;
4134 ctxt->fetch.start = ctxt->_eip;
4135 ctxt->fetch.end = ctxt->fetch.start + insn_len;
4136 if (insn_len > 0)
4137 memcpy(ctxt->fetch.data, insn, insn_len);
4138
4139 switch (mode) {
4140 case X86EMUL_MODE_REAL:
4141 case X86EMUL_MODE_VM86:
4142 case X86EMUL_MODE_PROT16:
4143 def_op_bytes = def_ad_bytes = 2;
4144 break;
4145 case X86EMUL_MODE_PROT32:
4146 def_op_bytes = def_ad_bytes = 4;
4147 break;
4148 #ifdef CONFIG_X86_64
4149 case X86EMUL_MODE_PROT64:
4150 def_op_bytes = 4;
4151 def_ad_bytes = 8;
4152 break;
4153 #endif
4154 default:
4155 return EMULATION_FAILED;
4156 }
4157
4158 ctxt->op_bytes = def_op_bytes;
4159 ctxt->ad_bytes = def_ad_bytes;
4160
4161 /* Legacy prefixes. */
4162 for (;;) {
4163 switch (ctxt->b = insn_fetch(u8, ctxt)) {
4164 case 0x66: /* operand-size override */
4165 op_prefix = true;
4166 /* switch between 2/4 bytes */
4167 ctxt->op_bytes = def_op_bytes ^ 6;
4168 break;
4169 case 0x67: /* address-size override */
4170 if (mode == X86EMUL_MODE_PROT64)
4171 /* switch between 4/8 bytes */
4172 ctxt->ad_bytes = def_ad_bytes ^ 12;
4173 else
4174 /* switch between 2/4 bytes */
4175 ctxt->ad_bytes = def_ad_bytes ^ 6;
4176 break;
4177 case 0x26: /* ES override */
4178 case 0x2e: /* CS override */
4179 case 0x36: /* SS override */
4180 case 0x3e: /* DS override */
4181 set_seg_override(ctxt, (ctxt->b >> 3) & 3);
4182 break;
4183 case 0x64: /* FS override */
4184 case 0x65: /* GS override */
4185 set_seg_override(ctxt, ctxt->b & 7);
4186 break;
4187 case 0x40 ... 0x4f: /* REX */
4188 if (mode != X86EMUL_MODE_PROT64)
4189 goto done_prefixes;
4190 ctxt->rex_prefix = ctxt->b;
4191 continue;
4192 case 0xf0: /* LOCK */
4193 ctxt->lock_prefix = 1;
4194 break;
4195 case 0xf2: /* REPNE/REPNZ */
4196 case 0xf3: /* REP/REPE/REPZ */
4197 ctxt->rep_prefix = ctxt->b;
4198 break;
4199 default:
4200 goto done_prefixes;
4201 }
4202
4203 /* Any legacy prefix after a REX prefix nullifies its effect. */
4204
4205 ctxt->rex_prefix = 0;
4206 }
4207
4208 done_prefixes:
4209
4210 /* REX prefix. */
4211 if (ctxt->rex_prefix & 8)
4212 ctxt->op_bytes = 8; /* REX.W */
4213
4214 /* Opcode byte(s). */
4215 opcode = opcode_table[ctxt->b];
4216 /* Two-byte opcode? */
4217 if (ctxt->b == 0x0f) {
4218 ctxt->twobyte = 1;
4219 ctxt->b = insn_fetch(u8, ctxt);
4220 opcode = twobyte_table[ctxt->b];
4221 }
4222 ctxt->d = opcode.flags;
4223
4224 if (ctxt->d & ModRM)
4225 ctxt->modrm = insn_fetch(u8, ctxt);
4226
4227 while (ctxt->d & GroupMask) {
4228 switch (ctxt->d & GroupMask) {
4229 case Group:
4230 goffset = (ctxt->modrm >> 3) & 7;
4231 opcode = opcode.u.group[goffset];
4232 break;
4233 case GroupDual:
4234 goffset = (ctxt->modrm >> 3) & 7;
4235 if ((ctxt->modrm >> 6) == 3)
4236 opcode = opcode.u.gdual->mod3[goffset];
4237 else
4238 opcode = opcode.u.gdual->mod012[goffset];
4239 break;
4240 case RMExt:
4241 goffset = ctxt->modrm & 7;
4242 opcode = opcode.u.group[goffset];
4243 break;
4244 case Prefix:
4245 if (ctxt->rep_prefix && op_prefix)
4246 return EMULATION_FAILED;
4247 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
4248 switch (simd_prefix) {
4249 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4250 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4251 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4252 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4253 }
4254 break;
4255 case Escape:
4256 if (ctxt->modrm > 0xbf)
4257 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
4258 else
4259 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
4260 break;
4261 default:
4262 return EMULATION_FAILED;
4263 }
4264
4265 ctxt->d &= ~(u64)GroupMask;
4266 ctxt->d |= opcode.flags;
4267 }
4268
4269 ctxt->execute = opcode.u.execute;
4270 ctxt->check_perm = opcode.check_perm;
4271 ctxt->intercept = opcode.intercept;
4272
4273 /* Unrecognised? */
4274 if (ctxt->d == 0 || (ctxt->d & NotImpl))
4275 return EMULATION_FAILED;
4276
4277 if (!(ctxt->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
4278 return EMULATION_FAILED;
4279
4280 if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
4281 ctxt->op_bytes = 8;
4282
4283 if (ctxt->d & Op3264) {
4284 if (mode == X86EMUL_MODE_PROT64)
4285 ctxt->op_bytes = 8;
4286 else
4287 ctxt->op_bytes = 4;
4288 }
4289
4290 if (ctxt->d & Sse)
4291 ctxt->op_bytes = 16;
4292 else if (ctxt->d & Mmx)
4293 ctxt->op_bytes = 8;
4294
4295 /* ModRM and SIB bytes. */
4296 if (ctxt->d & ModRM) {
4297 rc = decode_modrm(ctxt, &ctxt->memop);
4298 if (!ctxt->has_seg_override)
4299 set_seg_override(ctxt, ctxt->modrm_seg);
4300 } else if (ctxt->d & MemAbs)
4301 rc = decode_abs(ctxt, &ctxt->memop);
4302 if (rc != X86EMUL_CONTINUE)
4303 goto done;
4304
4305 if (!ctxt->has_seg_override)
4306 set_seg_override(ctxt, VCPU_SREG_DS);
4307
4308 ctxt->memop.addr.mem.seg = seg_override(ctxt);
4309
4310 if (ctxt->memop.type == OP_MEM && ctxt->ad_bytes != 8)
4311 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
4312
4313 /*
4314 * Decode and fetch the source operand: register, memory
4315 * or immediate.
4316 */
4317 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
4318 if (rc != X86EMUL_CONTINUE)
4319 goto done;
4320
4321 /*
4322 * Decode and fetch the second source operand: register, memory
4323 * or immediate.
4324 */
4325 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
4326 if (rc != X86EMUL_CONTINUE)
4327 goto done;
4328
4329 /* Decode and fetch the destination operand: register or memory. */
4330 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
4331
4332 done:
4333 if (ctxt->memopp && ctxt->memopp->type == OP_MEM && ctxt->rip_relative)
4334 ctxt->memopp->addr.mem.ea += ctxt->_eip;
4335
4336 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
4337 }
4338
4339 bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4340 {
4341 return ctxt->d & PageTable;
4342 }
4343
4344 static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4345 {
4346 /* The second termination condition only applies for REPE
4347 * and REPNE. Test if the repeat string operation prefix is
4348 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4349 * corresponding termination condition according to:
4350 * - if REPE/REPZ and ZF = 0 then done
4351 * - if REPNE/REPNZ and ZF = 1 then done
4352 */
4353 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4354 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4355 && (((ctxt->rep_prefix == REPE_PREFIX) &&
4356 ((ctxt->eflags & EFLG_ZF) == 0))
4357 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
4358 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
4359 return true;
4360
4361 return false;
4362 }
4363
4364 static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4365 {
4366 bool fault = false;
4367
4368 ctxt->ops->get_fpu(ctxt);
4369 asm volatile("1: fwait \n\t"
4370 "2: \n\t"
4371 ".pushsection .fixup,\"ax\" \n\t"
4372 "3: \n\t"
4373 "movb $1, %[fault] \n\t"
4374 "jmp 2b \n\t"
4375 ".popsection \n\t"
4376 _ASM_EXTABLE(1b, 3b)
4377 : [fault]"+qm"(fault));
4378 ctxt->ops->put_fpu(ctxt);
4379
4380 if (unlikely(fault))
4381 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4382
4383 return X86EMUL_CONTINUE;
4384 }
4385
4386 static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4387 struct operand *op)
4388 {
4389 if (op->type == OP_MM)
4390 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4391 }
4392
4393 static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
4394 {
4395 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
4396 if (!(ctxt->d & ByteOp))
4397 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
4398 asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
4399 : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags),
4400 [fastop]"+S"(fop)
4401 : "c"(ctxt->src2.val));
4402 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
4403 if (!fop) /* exception is returned in fop variable */
4404 return emulate_de(ctxt);
4405 return X86EMUL_CONTINUE;
4406 }
4407
4408 int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
4409 {
4410 const struct x86_emulate_ops *ops = ctxt->ops;
4411 int rc = X86EMUL_CONTINUE;
4412 int saved_dst_type = ctxt->dst.type;
4413
4414 ctxt->mem_read.pos = 0;
4415
4416 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
4417 (ctxt->d & Undefined)) {
4418 rc = emulate_ud(ctxt);
4419 goto done;
4420 }
4421
4422 /* LOCK prefix is allowed only with some instructions */
4423 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
4424 rc = emulate_ud(ctxt);
4425 goto done;
4426 }
4427
4428 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
4429 rc = emulate_ud(ctxt);
4430 goto done;
4431 }
4432
4433 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4434 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
4435 rc = emulate_ud(ctxt);
4436 goto done;
4437 }
4438
4439 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
4440 rc = emulate_nm(ctxt);
4441 goto done;
4442 }
4443
4444 if (ctxt->d & Mmx) {
4445 rc = flush_pending_x87_faults(ctxt);
4446 if (rc != X86EMUL_CONTINUE)
4447 goto done;
4448 /*
4449 * Now that we know the fpu is exception safe, we can fetch
4450 * operands from it.
4451 */
4452 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4453 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4454 if (!(ctxt->d & Mov))
4455 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4456 }
4457
4458 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4459 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4460 X86_ICPT_PRE_EXCEPT);
4461 if (rc != X86EMUL_CONTINUE)
4462 goto done;
4463 }
4464
4465 /* Privileged instruction can be executed only in CPL=0 */
4466 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
4467 rc = emulate_gp(ctxt, 0);
4468 goto done;
4469 }
4470
4471 /* Instruction can only be executed in protected mode */
4472 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
4473 rc = emulate_ud(ctxt);
4474 goto done;
4475 }
4476
4477 /* Do instruction specific permission checks */
4478 if (ctxt->check_perm) {
4479 rc = ctxt->check_perm(ctxt);
4480 if (rc != X86EMUL_CONTINUE)
4481 goto done;
4482 }
4483
4484 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4485 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4486 X86_ICPT_POST_EXCEPT);
4487 if (rc != X86EMUL_CONTINUE)
4488 goto done;
4489 }
4490
4491 if (ctxt->rep_prefix && (ctxt->d & String)) {
4492 /* All REP prefixes have the same first termination condition */
4493 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
4494 ctxt->eip = ctxt->_eip;
4495 goto done;
4496 }
4497 }
4498
4499 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4500 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4501 ctxt->src.valptr, ctxt->src.bytes);
4502 if (rc != X86EMUL_CONTINUE)
4503 goto done;
4504 ctxt->src.orig_val64 = ctxt->src.val64;
4505 }
4506
4507 if (ctxt->src2.type == OP_MEM) {
4508 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4509 &ctxt->src2.val, ctxt->src2.bytes);
4510 if (rc != X86EMUL_CONTINUE)
4511 goto done;
4512 }
4513
4514 if ((ctxt->d & DstMask) == ImplicitOps)
4515 goto special_insn;
4516
4517
4518 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
4519 /* optimisation - avoid slow emulated read if Mov */
4520 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4521 &ctxt->dst.val, ctxt->dst.bytes);
4522 if (rc != X86EMUL_CONTINUE)
4523 goto done;
4524 }
4525 ctxt->dst.orig_val = ctxt->dst.val;
4526
4527 special_insn:
4528
4529 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4530 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4531 X86_ICPT_POST_MEMACCESS);
4532 if (rc != X86EMUL_CONTINUE)
4533 goto done;
4534 }
4535
4536 if (ctxt->execute) {
4537 if (ctxt->d & Fastop) {
4538 void (*fop)(struct fastop *) = (void *)ctxt->execute;
4539 rc = fastop(ctxt, fop);
4540 if (rc != X86EMUL_CONTINUE)
4541 goto done;
4542 goto writeback;
4543 }
4544 rc = ctxt->execute(ctxt);
4545 if (rc != X86EMUL_CONTINUE)
4546 goto done;
4547 goto writeback;
4548 }
4549
4550 if (ctxt->twobyte)
4551 goto twobyte_insn;
4552
4553 switch (ctxt->b) {
4554 case 0x63: /* movsxd */
4555 if (ctxt->mode != X86EMUL_MODE_PROT64)
4556 goto cannot_emulate;
4557 ctxt->dst.val = (s32) ctxt->src.val;
4558 break;
4559 case 0x70 ... 0x7f: /* jcc (short) */
4560 if (test_cc(ctxt->b, ctxt->eflags))
4561 jmp_rel(ctxt, ctxt->src.val);
4562 break;
4563 case 0x8d: /* lea r16/r32, m */
4564 ctxt->dst.val = ctxt->src.addr.mem.ea;
4565 break;
4566 case 0x90 ... 0x97: /* nop / xchg reg, rax */
4567 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
4568 break;
4569 rc = em_xchg(ctxt);
4570 break;
4571 case 0x98: /* cbw/cwde/cdqe */
4572 switch (ctxt->op_bytes) {
4573 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4574 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4575 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
4576 }
4577 break;
4578 case 0xcc: /* int3 */
4579 rc = emulate_int(ctxt, 3);
4580 break;
4581 case 0xcd: /* int n */
4582 rc = emulate_int(ctxt, ctxt->src.val);
4583 break;
4584 case 0xce: /* into */
4585 if (ctxt->eflags & EFLG_OF)
4586 rc = emulate_int(ctxt, 4);
4587 break;
4588 case 0xe9: /* jmp rel */
4589 case 0xeb: /* jmp rel short */
4590 jmp_rel(ctxt, ctxt->src.val);
4591 ctxt->dst.type = OP_NONE; /* Disable writeback. */
4592 break;
4593 case 0xf4: /* hlt */
4594 ctxt->ops->halt(ctxt);
4595 break;
4596 case 0xf5: /* cmc */
4597 /* complement carry flag from eflags reg */
4598 ctxt->eflags ^= EFLG_CF;
4599 break;
4600 case 0xf8: /* clc */
4601 ctxt->eflags &= ~EFLG_CF;
4602 break;
4603 case 0xf9: /* stc */
4604 ctxt->eflags |= EFLG_CF;
4605 break;
4606 case 0xfc: /* cld */
4607 ctxt->eflags &= ~EFLG_DF;
4608 break;
4609 case 0xfd: /* std */
4610 ctxt->eflags |= EFLG_DF;
4611 break;
4612 default:
4613 goto cannot_emulate;
4614 }
4615
4616 if (rc != X86EMUL_CONTINUE)
4617 goto done;
4618
4619 writeback:
4620 if (!(ctxt->d & NoWrite)) {
4621 rc = writeback(ctxt, &ctxt->dst);
4622 if (rc != X86EMUL_CONTINUE)
4623 goto done;
4624 }
4625 if (ctxt->d & SrcWrite) {
4626 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR);
4627 rc = writeback(ctxt, &ctxt->src);
4628 if (rc != X86EMUL_CONTINUE)
4629 goto done;
4630 }
4631
4632 /*
4633 * restore dst type in case the decoding will be reused
4634 * (happens for string instruction )
4635 */
4636 ctxt->dst.type = saved_dst_type;
4637
4638 if ((ctxt->d & SrcMask) == SrcSI)
4639 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
4640
4641 if ((ctxt->d & DstMask) == DstDI)
4642 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
4643
4644 if (ctxt->rep_prefix && (ctxt->d & String)) {
4645 unsigned int count;
4646 struct read_cache *r = &ctxt->io_read;
4647 if ((ctxt->d & SrcMask) == SrcSI)
4648 count = ctxt->src.count;
4649 else
4650 count = ctxt->dst.count;
4651 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX),
4652 -count);
4653
4654 if (!string_insn_completed(ctxt)) {
4655 /*
4656 * Re-enter guest when pio read ahead buffer is empty
4657 * or, if it is not used, after each 1024 iteration.
4658 */
4659 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
4660 (r->end == 0 || r->end != r->pos)) {
4661 /*
4662 * Reset read cache. Usually happens before
4663 * decode, but since instruction is restarted
4664 * we have to do it here.
4665 */
4666 ctxt->mem_read.end = 0;
4667 writeback_registers(ctxt);
4668 return EMULATION_RESTART;
4669 }
4670 goto done; /* skip rip writeback */
4671 }
4672 }
4673
4674 ctxt->eip = ctxt->_eip;
4675
4676 done:
4677 if (rc == X86EMUL_PROPAGATE_FAULT)
4678 ctxt->have_exception = true;
4679 if (rc == X86EMUL_INTERCEPTED)
4680 return EMULATION_INTERCEPTED;
4681
4682 if (rc == X86EMUL_CONTINUE)
4683 writeback_registers(ctxt);
4684
4685 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
4686
4687 twobyte_insn:
4688 switch (ctxt->b) {
4689 case 0x09: /* wbinvd */
4690 (ctxt->ops->wbinvd)(ctxt);
4691 break;
4692 case 0x08: /* invd */
4693 case 0x0d: /* GrpP (prefetch) */
4694 case 0x18: /* Grp16 (prefetch/nop) */
4695 case 0x1f: /* nop */
4696 break;
4697 case 0x20: /* mov cr, reg */
4698 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
4699 break;
4700 case 0x21: /* mov from dr to reg */
4701 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
4702 break;
4703 case 0x40 ... 0x4f: /* cmov */
4704 ctxt->dst.val = ctxt->dst.orig_val = ctxt->src.val;
4705 if (!test_cc(ctxt->b, ctxt->eflags))
4706 ctxt->dst.type = OP_NONE; /* no writeback */
4707 break;
4708 case 0x80 ... 0x8f: /* jnz rel, etc*/
4709 if (test_cc(ctxt->b, ctxt->eflags))
4710 jmp_rel(ctxt, ctxt->src.val);
4711 break;
4712 case 0x90 ... 0x9f: /* setcc r/m8 */
4713 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
4714 break;
4715 case 0xae: /* clflush */
4716 break;
4717 case 0xb6 ... 0xb7: /* movzx */
4718 ctxt->dst.bytes = ctxt->op_bytes;
4719 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
4720 : (u16) ctxt->src.val;
4721 break;
4722 case 0xbe ... 0xbf: /* movsx */
4723 ctxt->dst.bytes = ctxt->op_bytes;
4724 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
4725 (s16) ctxt->src.val;
4726 break;
4727 case 0xc3: /* movnti */
4728 ctxt->dst.bytes = ctxt->op_bytes;
4729 ctxt->dst.val = (ctxt->op_bytes == 4) ? (u32) ctxt->src.val :
4730 (u64) ctxt->src.val;
4731 break;
4732 default:
4733 goto cannot_emulate;
4734 }
4735
4736 if (rc != X86EMUL_CONTINUE)
4737 goto done;
4738
4739 goto writeback;
4740
4741 cannot_emulate:
4742 return EMULATION_FAILED;
4743 }
4744
4745 void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
4746 {
4747 invalidate_registers(ctxt);
4748 }
4749
4750 void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
4751 {
4752 writeback_registers(ctxt);
4753 }
Linux with added FPC-III support