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ath9k_hw: clean up defines and variables from the ANI implementation split
[linux/fpc-iii.git] / drivers / net / wireless / ath / ath9k / ar9003_phy.c
blobec8a8d5c6db5f61aa5b58252dafa4a29aa244810
1 /*
2 * Copyright (c) 2010-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/export.h>
18 #include "hw.h"
19 #include "ar9003_phy.h"
20
21 static const int firstep_table[] =
22 /* level: 0 1 2 3 4 5 6 7 8 */
23 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */
24
25 static const int cycpwrThr1_table[] =
26 /* level: 0 1 2 3 4 5 6 7 8 */
27 { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */
28
29 /*
30 * register values to turn OFDM weak signal detection OFF
31 */
32 static const int m1ThreshLow_off = 127;
33 static const int m2ThreshLow_off = 127;
34 static const int m1Thresh_off = 127;
35 static const int m2Thresh_off = 127;
36 static const int m2CountThr_off = 31;
37 static const int m2CountThrLow_off = 63;
38 static const int m1ThreshLowExt_off = 127;
39 static const int m2ThreshLowExt_off = 127;
40 static const int m1ThreshExt_off = 127;
41 static const int m2ThreshExt_off = 127;
42
43 /**
44 * ar9003_hw_set_channel - set channel on single-chip device
45 * @ah: atheros hardware structure
46 * @chan:
47 *
48 * This is the function to change channel on single-chip devices, that is
49 * for AR9300 family of chipsets.
50 *
51 * This function takes the channel value in MHz and sets
52 * hardware channel value. Assumes writes have been enabled to analog bus.
53 *
54 * Actual Expression,
55 *
56 * For 2GHz channel,
57 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
58 * (freq_ref = 40MHz)
59 *
60 * For 5GHz channel,
61 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
62 * (freq_ref = 40MHz/(24>>amodeRefSel))
63 *
64 * For 5GHz channels which are 5MHz spaced,
65 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
66 * (freq_ref = 40MHz)
67 */
68 static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
69 {
70 u16 bMode, fracMode = 0, aModeRefSel = 0;
71 u32 freq, channelSel = 0, reg32 = 0;
72 struct chan_centers centers;
73 int loadSynthChannel;
74
75 ath9k_hw_get_channel_centers(ah, chan, &centers);
76 freq = centers.synth_center;
77
78 if (freq < 4800) { /* 2 GHz, fractional mode */
79 if (AR_SREV_9330(ah)) {
80 u32 chan_frac;
81 u32 div;
82
83 if (ah->is_clk_25mhz)
84 div = 75;
85 else
86 div = 120;
87
88 channelSel = (freq * 4) / div;
89 chan_frac = (((freq * 4) % div) * 0x20000) / div;
90 channelSel = (channelSel << 17) | chan_frac;
91 } else if (AR_SREV_9485(ah)) {
92 u32 chan_frac;
93
94 /*
95 * freq_ref = 40 / (refdiva >> amoderefsel); where refdiva=1 and amoderefsel=0
96 * ndiv = ((chan_mhz * 4) / 3) / freq_ref;
97 * chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000
98 */
99 channelSel = (freq * 4) / 120;
100 chan_frac = (((freq * 4) % 120) * 0x20000) / 120;
101 channelSel = (channelSel << 17) | chan_frac;
102 } else if (AR_SREV_9340(ah)) {
103 if (ah->is_clk_25mhz) {
104 u32 chan_frac;
105
106 channelSel = (freq * 2) / 75;
107 chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
108 channelSel = (channelSel << 17) | chan_frac;
109 } else
110 channelSel = CHANSEL_2G(freq) >> 1;
111 } else
112 channelSel = CHANSEL_2G(freq);
113 /* Set to 2G mode */
114 bMode = 1;
115 } else {
116 if (AR_SREV_9340(ah) && ah->is_clk_25mhz) {
117 u32 chan_frac;
118
119 channelSel = (freq * 2) / 75;
120 chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
121 channelSel = (channelSel << 17) | chan_frac;
122 } else {
123 channelSel = CHANSEL_5G(freq);
124 /* Doubler is ON, so, divide channelSel by 2. */
125 channelSel >>= 1;
126 }
127 /* Set to 5G mode */
128 bMode = 0;
129 }
130
131 /* Enable fractional mode for all channels */
132 fracMode = 1;
133 aModeRefSel = 0;
134 loadSynthChannel = 0;
135
136 reg32 = (bMode << 29);
137 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
138
139 /* Enable Long shift Select for Synthesizer */
140 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4,
141 AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1);
142
143 /* Program Synth. setting */
144 reg32 = (channelSel << 2) | (fracMode << 30) |
145 (aModeRefSel << 28) | (loadSynthChannel << 31);
146 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
147
148 /* Toggle Load Synth channel bit */
149 loadSynthChannel = 1;
150 reg32 = (channelSel << 2) | (fracMode << 30) |
151 (aModeRefSel << 28) | (loadSynthChannel << 31);
152 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
153
154 ah->curchan = chan;
155
156 return 0;
157 }
158
159 /**
160 * ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency
161 * @ah: atheros hardware structure
162 * @chan:
163 *
164 * For single-chip solutions. Converts to baseband spur frequency given the
165 * input channel frequency and compute register settings below.
166 *
167 * Spur mitigation for MRC CCK
168 */
169 static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
170 struct ath9k_channel *chan)
171 {
172 static const u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
173 int cur_bb_spur, negative = 0, cck_spur_freq;
174 int i;
175 int range, max_spur_cnts, synth_freq;
176 u8 *spur_fbin_ptr = NULL;
177
178 /*
179 * Need to verify range +/- 10 MHz in control channel, otherwise spur
180 * is out-of-band and can be ignored.
181 */
182
183 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah)) {
184 spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah,
185 IS_CHAN_2GHZ(chan));
186 if (spur_fbin_ptr[0] == 0) /* No spur */
187 return;
188 max_spur_cnts = 5;
189 if (IS_CHAN_HT40(chan)) {
190 range = 19;
191 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
192 AR_PHY_GC_DYN2040_PRI_CH) == 0)
193 synth_freq = chan->channel + 10;
194 else
195 synth_freq = chan->channel - 10;
196 } else {
197 range = 10;
198 synth_freq = chan->channel;
199 }
200 } else {
201 range = AR_SREV_9462(ah) ? 5 : 10;
202 max_spur_cnts = 4;
203 synth_freq = chan->channel;
204 }
205
206 for (i = 0; i < max_spur_cnts; i++) {
207 if (AR_SREV_9462(ah) && (i == 0 || i == 3))
208 continue;
209 negative = 0;
210 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah))
211 cur_bb_spur = ath9k_hw_fbin2freq(spur_fbin_ptr[i],
212 IS_CHAN_2GHZ(chan));
213 else
214 cur_bb_spur = spur_freq[i];
215
216 cur_bb_spur -= synth_freq;
217 if (cur_bb_spur < 0) {
218 negative = 1;
219 cur_bb_spur = -cur_bb_spur;
220 }
221 if (cur_bb_spur < range) {
222 cck_spur_freq = (int)((cur_bb_spur << 19) / 11);
223
224 if (negative == 1)
225 cck_spur_freq = -cck_spur_freq;
226
227 cck_spur_freq = cck_spur_freq & 0xfffff;
228
229 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
230 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7);
231 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
232 AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f);
233 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
234 AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE,
235 0x2);
236 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
237 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT,
238 0x1);
239 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
240 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ,
241 cck_spur_freq);
242
243 return;
244 }
245 }
246
247 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
248 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);
249 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
250 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0);
251 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
252 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0);
253 }
254
255 /* Clean all spur register fields */
256 static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah)
257 {
258 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
259 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0);
260 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
261 AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
262 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
263 AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
264 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
265 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0);
266 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
267 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0);
268 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
269 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0);
270 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
271 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0);
272 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
273 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0);
274 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
275 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0);
276
277 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
278 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0);
279 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
280 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0);
281 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
282 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0);
283 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
284 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0);
285 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
286 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0);
287 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
288 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0);
289 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
290 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0);
291 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
292 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0);
293 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
294 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0);
295 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
296 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);
297 }
298
299 static void ar9003_hw_spur_ofdm(struct ath_hw *ah,
300 int freq_offset,
301 int spur_freq_sd,
302 int spur_delta_phase,
303 int spur_subchannel_sd)
304 {
305 int mask_index = 0;
306
307 /* OFDM Spur mitigation */
308 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
309 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1);
310 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
311 AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
312 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
313 AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
314 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
315 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd);
316 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
317 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1);
318 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
319 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1);
320 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
321 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1);
322 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
323 AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);
324 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
325 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1);
326
327 if (REG_READ_FIELD(ah, AR_PHY_MODE,
328 AR_PHY_MODE_DYNAMIC) == 0x1)
329 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
330 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1);
331
332 mask_index = (freq_offset << 4) / 5;
333 if (mask_index < 0)
334 mask_index = mask_index - 1;
335
336 mask_index = mask_index & 0x7f;
337
338 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
339 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1);
340 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
341 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1);
342 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
343 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1);
344 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
345 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index);
346 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
347 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index);
348 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
349 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index);
350 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
351 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc);
352 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
353 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc);
354 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
355 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
356 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
357 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
358 }
359
360 static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah,
361 struct ath9k_channel *chan,
362 int freq_offset)
363 {
364 int spur_freq_sd = 0;
365 int spur_subchannel_sd = 0;
366 int spur_delta_phase = 0;
367
368 if (IS_CHAN_HT40(chan)) {
369 if (freq_offset < 0) {
370 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
371 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
372 spur_subchannel_sd = 1;
373 else
374 spur_subchannel_sd = 0;
375
376 spur_freq_sd = ((freq_offset + 10) << 9) / 11;
377
378 } else {
379 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
380 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
381 spur_subchannel_sd = 0;
382 else
383 spur_subchannel_sd = 1;
384
385 spur_freq_sd = ((freq_offset - 10) << 9) / 11;
386
387 }
388
389 spur_delta_phase = (freq_offset << 17) / 5;
390
391 } else {
392 spur_subchannel_sd = 0;
393 spur_freq_sd = (freq_offset << 9) /11;
394 spur_delta_phase = (freq_offset << 18) / 5;
395 }
396
397 spur_freq_sd = spur_freq_sd & 0x3ff;
398 spur_delta_phase = spur_delta_phase & 0xfffff;
399
400 ar9003_hw_spur_ofdm(ah,
401 freq_offset,
402 spur_freq_sd,
403 spur_delta_phase,
404 spur_subchannel_sd);
405 }
406
407 /* Spur mitigation for OFDM */
408 static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah,
409 struct ath9k_channel *chan)
410 {
411 int synth_freq;
412 int range = 10;
413 int freq_offset = 0;
414 int mode;
415 u8* spurChansPtr;
416 unsigned int i;
417 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
418
419 if (IS_CHAN_5GHZ(chan)) {
420 spurChansPtr = &(eep->modalHeader5G.spurChans[0]);
421 mode = 0;
422 }
423 else {
424 spurChansPtr = &(eep->modalHeader2G.spurChans[0]);
425 mode = 1;
426 }
427
428 if (spurChansPtr[0] == 0)
429 return; /* No spur in the mode */
430
431 if (IS_CHAN_HT40(chan)) {
432 range = 19;
433 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
434 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
435 synth_freq = chan->channel - 10;
436 else
437 synth_freq = chan->channel + 10;
438 } else {
439 range = 10;
440 synth_freq = chan->channel;
441 }
442
443 ar9003_hw_spur_ofdm_clear(ah);
444
445 for (i = 0; i < AR_EEPROM_MODAL_SPURS && spurChansPtr[i]; i++) {
446 freq_offset = ath9k_hw_fbin2freq(spurChansPtr[i], mode);
447 freq_offset -= synth_freq;
448 if (abs(freq_offset) < range) {
449 ar9003_hw_spur_ofdm_work(ah, chan, freq_offset);
450 break;
451 }
452 }
453 }
454
455 static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
456 struct ath9k_channel *chan)
457 {
458 ar9003_hw_spur_mitigate_mrc_cck(ah, chan);
459 ar9003_hw_spur_mitigate_ofdm(ah, chan);
460 }
461
462 static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
463 struct ath9k_channel *chan)
464 {
465 u32 pll;
466
467 pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
468
469 if (chan && IS_CHAN_HALF_RATE(chan))
470 pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
471 else if (chan && IS_CHAN_QUARTER_RATE(chan))
472 pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
473
474 pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
475
476 return pll;
477 }
478
479 static void ar9003_hw_set_channel_regs(struct ath_hw *ah,
480 struct ath9k_channel *chan)
481 {
482 u32 phymode;
483 u32 enableDacFifo = 0;
484
485 enableDacFifo =
486 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO);
487
488 /* Enable 11n HT, 20 MHz */
489 phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SINGLE_HT_LTF1 |
490 AR_PHY_GC_SHORT_GI_40 | enableDacFifo;
491
492 /* Configure baseband for dynamic 20/40 operation */
493 if (IS_CHAN_HT40(chan)) {
494 phymode |= AR_PHY_GC_DYN2040_EN;
495 /* Configure control (primary) channel at +-10MHz */
496 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
497 (chan->chanmode == CHANNEL_G_HT40PLUS))
498 phymode |= AR_PHY_GC_DYN2040_PRI_CH;
499
500 }
501
502 /* make sure we preserve INI settings */
503 phymode |= REG_READ(ah, AR_PHY_GEN_CTRL);
504 /* turn off Green Field detection for STA for now */
505 phymode &= ~AR_PHY_GC_GF_DETECT_EN;
506
507 REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);
508
509 /* Configure MAC for 20/40 operation */
510 ath9k_hw_set11nmac2040(ah);
511
512 /* global transmit timeout (25 TUs default)*/
513 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
514 /* carrier sense timeout */
515 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
516 }
517
518 static void ar9003_hw_init_bb(struct ath_hw *ah,
519 struct ath9k_channel *chan)
520 {
521 u32 synthDelay;
522
523 /*
524 * Wait for the frequency synth to settle (synth goes on
525 * via AR_PHY_ACTIVE_EN). Read the phy active delay register.
526 * Value is in 100ns increments.
527 */
528 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
529
530 /* Activate the PHY (includes baseband activate + synthesizer on) */
531 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
532 ath9k_hw_synth_delay(ah, chan, synthDelay);
533 }
534
535 static void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
536 {
537 switch (rx) {
538 case 0x5:
539 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
540 AR_PHY_SWAP_ALT_CHAIN);
541 case 0x3:
542 case 0x1:
543 case 0x2:
544 case 0x7:
545 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);
546 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);
547 break;
548 default:
549 break;
550 }
551
552 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7))
553 REG_WRITE(ah, AR_SELFGEN_MASK, 0x3);
554 else if (AR_SREV_9462(ah))
555 /* xxx only when MCI support is enabled */
556 REG_WRITE(ah, AR_SELFGEN_MASK, 0x3);
557 else
558 REG_WRITE(ah, AR_SELFGEN_MASK, tx);
559
560 if (tx == 0x5) {
561 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
562 AR_PHY_SWAP_ALT_CHAIN);
563 }
564 }
565
566 /*
567 * Override INI values with chip specific configuration.
568 */
569 static void ar9003_hw_override_ini(struct ath_hw *ah)
570 {
571 u32 val;
572
573 /*
574 * Set the RX_ABORT and RX_DIS and clear it only after
575 * RXE is set for MAC. This prevents frames with
576 * corrupted descriptor status.
577 */
578 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
579
580 /*
581 * For AR9280 and above, there is a new feature that allows
582 * Multicast search based on both MAC Address and Key ID. By default,
583 * this feature is enabled. But since the driver is not using this
584 * feature, we switch it off; otherwise multicast search based on
585 * MAC addr only will fail.
586 */
587 val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE);
588 REG_WRITE(ah, AR_PCU_MISC_MODE2,
589 val | AR_AGG_WEP_ENABLE_FIX | AR_AGG_WEP_ENABLE);
590
591 REG_SET_BIT(ah, AR_PHY_CCK_DETECT,
592 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
593 }
594
595 static void ar9003_hw_prog_ini(struct ath_hw *ah,
596 struct ar5416IniArray *iniArr,
597 int column)
598 {
599 unsigned int i, regWrites = 0;
600
601 /* New INI format: Array may be undefined (pre, core, post arrays) */
602 if (!iniArr->ia_array)
603 return;
604
605 /*
606 * New INI format: Pre, core, and post arrays for a given subsystem
607 * may be modal (> 2 columns) or non-modal (2 columns). Determine if
608 * the array is non-modal and force the column to 1.
609 */
610 if (column >= iniArr->ia_columns)
611 column = 1;
612
613 for (i = 0; i < iniArr->ia_rows; i++) {
614 u32 reg = INI_RA(iniArr, i, 0);
615 u32 val = INI_RA(iniArr, i, column);
616
617 REG_WRITE(ah, reg, val);
618
619 DO_DELAY(regWrites);
620 }
621 }
622
623 static int ar9003_hw_process_ini(struct ath_hw *ah,
624 struct ath9k_channel *chan)
625 {
626 unsigned int regWrites = 0, i;
627 u32 modesIndex;
628
629 switch (chan->chanmode) {
630 case CHANNEL_A:
631 case CHANNEL_A_HT20:
632 modesIndex = 1;
633 break;
634 case CHANNEL_A_HT40PLUS:
635 case CHANNEL_A_HT40MINUS:
636 modesIndex = 2;
637 break;
638 case CHANNEL_G:
639 case CHANNEL_G_HT20:
640 case CHANNEL_B:
641 modesIndex = 4;
642 break;
643 case CHANNEL_G_HT40PLUS:
644 case CHANNEL_G_HT40MINUS:
645 modesIndex = 3;
646 break;
647
648 default:
649 return -EINVAL;
650 }
651
652 for (i = 0; i < ATH_INI_NUM_SPLIT; i++) {
653 ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex);
654 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
655 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
656 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
657 if (i == ATH_INI_POST && AR_SREV_9462_20(ah))
658 ar9003_hw_prog_ini(ah,
659 &ah->ini_radio_post_sys2ant,
660 modesIndex);
661 }
662
663 REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
664 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
665
666 /*
667 * For 5GHz channels requiring Fast Clock, apply
668 * different modal values.
669 */
670 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
671 REG_WRITE_ARRAY(&ah->iniModesFastClock,
672 modesIndex, regWrites);
673
674 REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites);
675
676 if (chan->channel == 2484)
677 ar9003_hw_prog_ini(ah, &ah->ini_japan2484, 1);
678
679 if (AR_SREV_9462(ah))
680 REG_WRITE(ah, AR_GLB_SWREG_DISCONT_MODE,
681 AR_GLB_SWREG_DISCONT_EN_BT_WLAN);
682
683 ah->modes_index = modesIndex;
684 ar9003_hw_override_ini(ah);
685 ar9003_hw_set_channel_regs(ah, chan);
686 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
687 ath9k_hw_apply_txpower(ah, chan, false);
688
689 if (AR_SREV_9462(ah)) {
690 if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0,
691 AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL))
692 ah->enabled_cals |= TX_IQ_CAL;
693 else
694 ah->enabled_cals &= ~TX_IQ_CAL;
695
696 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE)
697 ah->enabled_cals |= TX_CL_CAL;
698 else
699 ah->enabled_cals &= ~TX_CL_CAL;
700 }
701
702 return 0;
703 }
704
705 static void ar9003_hw_set_rfmode(struct ath_hw *ah,
706 struct ath9k_channel *chan)
707 {
708 u32 rfMode = 0;
709
710 if (chan == NULL)
711 return;
712
713 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
714 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
715
716 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
717 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
718 if (IS_CHAN_QUARTER_RATE(chan))
719 rfMode |= AR_PHY_MODE_QUARTER;
720 if (IS_CHAN_HALF_RATE(chan))
721 rfMode |= AR_PHY_MODE_HALF;
722
723 if (rfMode & (AR_PHY_MODE_QUARTER | AR_PHY_MODE_HALF))
724 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,
725 AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW, 3);
726
727 REG_WRITE(ah, AR_PHY_MODE, rfMode);
728 }
729
730 static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah)
731 {
732 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
733 }
734
735 static void ar9003_hw_set_delta_slope(struct ath_hw *ah,
736 struct ath9k_channel *chan)
737 {
738 u32 coef_scaled, ds_coef_exp, ds_coef_man;
739 u32 clockMhzScaled = 0x64000000;
740 struct chan_centers centers;
741
742 /*
743 * half and quarter rate can divide the scaled clock by 2 or 4
744 * scale for selected channel bandwidth
745 */
746 if (IS_CHAN_HALF_RATE(chan))
747 clockMhzScaled = clockMhzScaled >> 1;
748 else if (IS_CHAN_QUARTER_RATE(chan))
749 clockMhzScaled = clockMhzScaled >> 2;
750
751 /*
752 * ALGO -> coef = 1e8/fcarrier*fclock/40;
753 * scaled coef to provide precision for this floating calculation
754 */
755 ath9k_hw_get_channel_centers(ah, chan, &centers);
756 coef_scaled = clockMhzScaled / centers.synth_center;
757
758 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
759 &ds_coef_exp);
760
761 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
762 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
763 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
764 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
765
766 /*
767 * For Short GI,
768 * scaled coeff is 9/10 that of normal coeff
769 */
770 coef_scaled = (9 * coef_scaled) / 10;
771
772 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
773 &ds_coef_exp);
774
775 /* for short gi */
776 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
777 AR_PHY_SGI_DSC_MAN, ds_coef_man);
778 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
779 AR_PHY_SGI_DSC_EXP, ds_coef_exp);
780 }
781
782 static bool ar9003_hw_rfbus_req(struct ath_hw *ah)
783 {
784 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
785 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
786 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
787 }
788
789 /*
790 * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN).
791 * Read the phy active delay register. Value is in 100ns increments.
792 */
793 static void ar9003_hw_rfbus_done(struct ath_hw *ah)
794 {
795 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
796
797 ath9k_hw_synth_delay(ah, ah->curchan, synthDelay);
798
799 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
800 }
801
802 static bool ar9003_hw_ani_control(struct ath_hw *ah,
803 enum ath9k_ani_cmd cmd, int param)
804 {
805 struct ath_common *common = ath9k_hw_common(ah);
806 struct ath9k_channel *chan = ah->curchan;
807 struct ar5416AniState *aniState = &chan->ani;
808 s32 value, value2;
809
810 switch (cmd & ah->ani_function) {
811 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
812 /*
813 * on == 1 means ofdm weak signal detection is ON
814 * on == 1 is the default, for less noise immunity
815 *
816 * on == 0 means ofdm weak signal detection is OFF
817 * on == 0 means more noise imm
818 */
819 u32 on = param ? 1 : 0;
820
821 if (on)
822 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
823 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
824 else
825 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
826 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
827
828 if (on != aniState->ofdmWeakSigDetect) {
829 ath_dbg(common, ANI,
830 "** ch %d: ofdm weak signal: %s=>%s\n",
831 chan->channel,
832 aniState->ofdmWeakSigDetect ?
833 "on" : "off",
834 on ? "on" : "off");
835 if (on)
836 ah->stats.ast_ani_ofdmon++;
837 else
838 ah->stats.ast_ani_ofdmoff++;
839 aniState->ofdmWeakSigDetect = on;
840 }
841 break;
842 }
843 case ATH9K_ANI_FIRSTEP_LEVEL:{
844 u32 level = param;
845
846 if (level >= ARRAY_SIZE(firstep_table)) {
847 ath_dbg(common, ANI,
848 "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n",
849 level, ARRAY_SIZE(firstep_table));
850 return false;
851 }
852
853 /*
854 * make register setting relative to default
855 * from INI file & cap value
856 */
857 value = firstep_table[level] -
858 firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
859 aniState->iniDef.firstep;
860 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
861 value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
862 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
863 value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
864 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
865 AR_PHY_FIND_SIG_FIRSTEP,
866 value);
867 /*
868 * we need to set first step low register too
869 * make register setting relative to default
870 * from INI file & cap value
871 */
872 value2 = firstep_table[level] -
873 firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
874 aniState->iniDef.firstepLow;
875 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
876 value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
877 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
878 value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;
879
880 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
881 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2);
882
883 if (level != aniState->firstepLevel) {
884 ath_dbg(common, ANI,
885 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
886 chan->channel,
887 aniState->firstepLevel,
888 level,
889 ATH9K_ANI_FIRSTEP_LVL,
890 value,
891 aniState->iniDef.firstep);
892 ath_dbg(common, ANI,
893 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
894 chan->channel,
895 aniState->firstepLevel,
896 level,
897 ATH9K_ANI_FIRSTEP_LVL,
898 value2,
899 aniState->iniDef.firstepLow);
900 if (level > aniState->firstepLevel)
901 ah->stats.ast_ani_stepup++;
902 else if (level < aniState->firstepLevel)
903 ah->stats.ast_ani_stepdown++;
904 aniState->firstepLevel = level;
905 }
906 break;
907 }
908 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
909 u32 level = param;
910
911 if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
912 ath_dbg(common, ANI,
913 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n",
914 level, ARRAY_SIZE(cycpwrThr1_table));
915 return false;
916 }
917 /*
918 * make register setting relative to default
919 * from INI file & cap value
920 */
921 value = cycpwrThr1_table[level] -
922 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
923 aniState->iniDef.cycpwrThr1;
924 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
925 value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
926 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
927 value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
928 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
929 AR_PHY_TIMING5_CYCPWR_THR1,
930 value);
931
932 /*
933 * set AR_PHY_EXT_CCA for extension channel
934 * make register setting relative to default
935 * from INI file & cap value
936 */
937 value2 = cycpwrThr1_table[level] -
938 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
939 aniState->iniDef.cycpwrThr1Ext;
940 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
941 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
942 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
943 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
944 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
945 AR_PHY_EXT_CYCPWR_THR1, value2);
946
947 if (level != aniState->spurImmunityLevel) {
948 ath_dbg(common, ANI,
949 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
950 chan->channel,
951 aniState->spurImmunityLevel,
952 level,
953 ATH9K_ANI_SPUR_IMMUNE_LVL,
954 value,
955 aniState->iniDef.cycpwrThr1);
956 ath_dbg(common, ANI,
957 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
958 chan->channel,
959 aniState->spurImmunityLevel,
960 level,
961 ATH9K_ANI_SPUR_IMMUNE_LVL,
962 value2,
963 aniState->iniDef.cycpwrThr1Ext);
964 if (level > aniState->spurImmunityLevel)
965 ah->stats.ast_ani_spurup++;
966 else if (level < aniState->spurImmunityLevel)
967 ah->stats.ast_ani_spurdown++;
968 aniState->spurImmunityLevel = level;
969 }
970 break;
971 }
972 case ATH9K_ANI_MRC_CCK:{
973 /*
974 * is_on == 1 means MRC CCK ON (default, less noise imm)
975 * is_on == 0 means MRC CCK is OFF (more noise imm)
976 */
977 bool is_on = param ? 1 : 0;
978 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
979 AR_PHY_MRC_CCK_ENABLE, is_on);
980 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
981 AR_PHY_MRC_CCK_MUX_REG, is_on);
982 if (!is_on != aniState->mrcCCKOff) {
983 ath_dbg(common, ANI, "** ch %d: MRC CCK: %s=>%s\n",
984 chan->channel,
985 !aniState->mrcCCKOff ? "on" : "off",
986 is_on ? "on" : "off");
987 if (is_on)
988 ah->stats.ast_ani_ccklow++;
989 else
990 ah->stats.ast_ani_cckhigh++;
991 aniState->mrcCCKOff = !is_on;
992 }
993 break;
994 }
995 case ATH9K_ANI_PRESENT:
996 break;
997 default:
998 ath_dbg(common, ANI, "invalid cmd %u\n", cmd);
999 return false;
1000 }
1001
1002 ath_dbg(common, ANI,
1003 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1004 aniState->spurImmunityLevel,
1005 aniState->ofdmWeakSigDetect ? "on" : "off",
1006 aniState->firstepLevel,
1007 !aniState->mrcCCKOff ? "on" : "off",
1008 aniState->listenTime,
1009 aniState->ofdmPhyErrCount,
1010 aniState->cckPhyErrCount);
1011 return true;
1012 }
1013
1014 static void ar9003_hw_do_getnf(struct ath_hw *ah,
1015 int16_t nfarray[NUM_NF_READINGS])
1016 {
1017 #define AR_PHY_CH_MINCCA_PWR 0x1FF00000
1018 #define AR_PHY_CH_MINCCA_PWR_S 20
1019 #define AR_PHY_CH_EXT_MINCCA_PWR 0x01FF0000
1020 #define AR_PHY_CH_EXT_MINCCA_PWR_S 16
1021
1022 int16_t nf;
1023 int i;
1024
1025 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1026 if (ah->rxchainmask & BIT(i)) {
1027 nf = MS(REG_READ(ah, ah->nf_regs[i]),
1028 AR_PHY_CH_MINCCA_PWR);
1029 nfarray[i] = sign_extend32(nf, 8);
1030
1031 if (IS_CHAN_HT40(ah->curchan)) {
1032 u8 ext_idx = AR9300_MAX_CHAINS + i;
1033
1034 nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]),
1035 AR_PHY_CH_EXT_MINCCA_PWR);
1036 nfarray[ext_idx] = sign_extend32(nf, 8);
1037 }
1038 }
1039 }
1040 }
1041
1042 static void ar9003_hw_set_nf_limits(struct ath_hw *ah)
1043 {
1044 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ;
1045 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ;
1046 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ;
1047 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ;
1048 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ;
1049 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ;
1050
1051 if (AR_SREV_9330(ah))
1052 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ;
1053
1054 if (AR_SREV_9462(ah)) {
1055 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ;
1056 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9462_2GHZ;
1057 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ;
1058 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9462_5GHZ;
1059 }
1060 }
1061
1062 /*
1063 * Initialize the ANI register values with default (ini) values.
1064 * This routine is called during a (full) hardware reset after
1065 * all the registers are initialised from the INI.
1066 */
1067 static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
1068 {
1069 struct ar5416AniState *aniState;
1070 struct ath_common *common = ath9k_hw_common(ah);
1071 struct ath9k_channel *chan = ah->curchan;
1072 struct ath9k_ani_default *iniDef;
1073 u32 val;
1074
1075 aniState = &ah->curchan->ani;
1076 iniDef = &aniState->iniDef;
1077
1078 ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz/0x%x\n",
1079 ah->hw_version.macVersion,
1080 ah->hw_version.macRev,
1081 ah->opmode,
1082 chan->channel,
1083 chan->channelFlags);
1084
1085 val = REG_READ(ah, AR_PHY_SFCORR);
1086 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
1087 iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
1088 iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
1089
1090 val = REG_READ(ah, AR_PHY_SFCORR_LOW);
1091 iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
1092 iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
1093 iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
1094
1095 val = REG_READ(ah, AR_PHY_SFCORR_EXT);
1096 iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
1097 iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
1098 iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
1099 iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
1100 iniDef->firstep = REG_READ_FIELD(ah,
1101 AR_PHY_FIND_SIG,
1102 AR_PHY_FIND_SIG_FIRSTEP);
1103 iniDef->firstepLow = REG_READ_FIELD(ah,
1104 AR_PHY_FIND_SIG_LOW,
1105 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW);
1106 iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1107 AR_PHY_TIMING5,
1108 AR_PHY_TIMING5_CYCPWR_THR1);
1109 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1110 AR_PHY_EXT_CCA,
1111 AR_PHY_EXT_CYCPWR_THR1);
1112
1113 /* these levels just got reset to defaults by the INI */
1114 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
1115 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
1116 aniState->ofdmWeakSigDetect = ATH9K_ANI_USE_OFDM_WEAK_SIG;
1117 aniState->mrcCCKOff = !ATH9K_ANI_ENABLE_MRC_CCK;
1118 }
1119
1120 static void ar9003_hw_set_radar_params(struct ath_hw *ah,
1121 struct ath_hw_radar_conf *conf)
1122 {
1123 u32 radar_0 = 0, radar_1 = 0;
1124
1125 if (!conf) {
1126 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
1127 return;
1128 }
1129
1130 radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
1131 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
1132 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
1133 radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
1134 radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
1135 radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
1136
1137 radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
1138 radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
1139 radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
1140 radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
1141 radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
1142
1143 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
1144 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
1145 if (conf->ext_channel)
1146 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1147 else
1148 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1149 }
1150
1151 static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
1152 {
1153 struct ath_hw_radar_conf *conf = &ah->radar_conf;
1154
1155 conf->fir_power = -28;
1156 conf->radar_rssi = 0;
1157 conf->pulse_height = 10;
1158 conf->pulse_rssi = 24;
1159 conf->pulse_inband = 8;
1160 conf->pulse_maxlen = 255;
1161 conf->pulse_inband_step = 12;
1162 conf->radar_inband = 8;
1163 }
1164
1165 static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah,
1166 struct ath_hw_antcomb_conf *antconf)
1167 {
1168 u32 regval;
1169
1170 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1171 antconf->main_lna_conf = (regval & AR_PHY_9485_ANT_DIV_MAIN_LNACONF) >>
1172 AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S;
1173 antconf->alt_lna_conf = (regval & AR_PHY_9485_ANT_DIV_ALT_LNACONF) >>
1174 AR_PHY_9485_ANT_DIV_ALT_LNACONF_S;
1175 antconf->fast_div_bias = (regval & AR_PHY_9485_ANT_FAST_DIV_BIAS) >>
1176 AR_PHY_9485_ANT_FAST_DIV_BIAS_S;
1177
1178 if (AR_SREV_9330_11(ah)) {
1179 antconf->lna1_lna2_delta = -9;
1180 antconf->div_group = 1;
1181 } else if (AR_SREV_9485(ah)) {
1182 antconf->lna1_lna2_delta = -9;
1183 antconf->div_group = 2;
1184 } else {
1185 antconf->lna1_lna2_delta = -3;
1186 antconf->div_group = 0;
1187 }
1188 }
1189
1190 static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah,
1191 struct ath_hw_antcomb_conf *antconf)
1192 {
1193 u32 regval;
1194
1195 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1196 regval &= ~(AR_PHY_9485_ANT_DIV_MAIN_LNACONF |
1197 AR_PHY_9485_ANT_DIV_ALT_LNACONF |
1198 AR_PHY_9485_ANT_FAST_DIV_BIAS |
1199 AR_PHY_9485_ANT_DIV_MAIN_GAINTB |
1200 AR_PHY_9485_ANT_DIV_ALT_GAINTB);
1201 regval |= ((antconf->main_lna_conf <<
1202 AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S)
1203 & AR_PHY_9485_ANT_DIV_MAIN_LNACONF);
1204 regval |= ((antconf->alt_lna_conf << AR_PHY_9485_ANT_DIV_ALT_LNACONF_S)
1205 & AR_PHY_9485_ANT_DIV_ALT_LNACONF);
1206 regval |= ((antconf->fast_div_bias << AR_PHY_9485_ANT_FAST_DIV_BIAS_S)
1207 & AR_PHY_9485_ANT_FAST_DIV_BIAS);
1208 regval |= ((antconf->main_gaintb << AR_PHY_9485_ANT_DIV_MAIN_GAINTB_S)
1209 & AR_PHY_9485_ANT_DIV_MAIN_GAINTB);
1210 regval |= ((antconf->alt_gaintb << AR_PHY_9485_ANT_DIV_ALT_GAINTB_S)
1211 & AR_PHY_9485_ANT_DIV_ALT_GAINTB);
1212
1213 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1214 }
1215
1216 static int ar9003_hw_fast_chan_change(struct ath_hw *ah,
1217 struct ath9k_channel *chan,
1218 u8 *ini_reloaded)
1219 {
1220 unsigned int regWrites = 0;
1221 u32 modesIndex;
1222
1223 switch (chan->chanmode) {
1224 case CHANNEL_A:
1225 case CHANNEL_A_HT20:
1226 modesIndex = 1;
1227 break;
1228 case CHANNEL_A_HT40PLUS:
1229 case CHANNEL_A_HT40MINUS:
1230 modesIndex = 2;
1231 break;
1232 case CHANNEL_G:
1233 case CHANNEL_G_HT20:
1234 case CHANNEL_B:
1235 modesIndex = 4;
1236 break;
1237 case CHANNEL_G_HT40PLUS:
1238 case CHANNEL_G_HT40MINUS:
1239 modesIndex = 3;
1240 break;
1241
1242 default:
1243 return -EINVAL;
1244 }
1245
1246 if (modesIndex == ah->modes_index) {
1247 *ini_reloaded = false;
1248 goto set_rfmode;
1249 }
1250
1251 ar9003_hw_prog_ini(ah, &ah->iniSOC[ATH_INI_POST], modesIndex);
1252 ar9003_hw_prog_ini(ah, &ah->iniMac[ATH_INI_POST], modesIndex);
1253 ar9003_hw_prog_ini(ah, &ah->iniBB[ATH_INI_POST], modesIndex);
1254 ar9003_hw_prog_ini(ah, &ah->iniRadio[ATH_INI_POST], modesIndex);
1255 if (AR_SREV_9462_20(ah))
1256 ar9003_hw_prog_ini(ah,
1257 &ah->ini_radio_post_sys2ant,
1258 modesIndex);
1259
1260 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1261
1262 /*
1263 * For 5GHz channels requiring Fast Clock, apply
1264 * different modal values.
1265 */
1266 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1267 REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, regWrites);
1268
1269 REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites);
1270
1271 ah->modes_index = modesIndex;
1272 *ini_reloaded = true;
1273
1274 set_rfmode:
1275 ar9003_hw_set_rfmode(ah, chan);
1276 return 0;
1277 }
1278
1279 void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
1280 {
1281 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1282 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
1283 static const u32 ar9300_cca_regs[6] = {
1284 AR_PHY_CCA_0,
1285 AR_PHY_CCA_1,
1286 AR_PHY_CCA_2,
1287 AR_PHY_EXT_CCA,
1288 AR_PHY_EXT_CCA_1,
1289 AR_PHY_EXT_CCA_2,
1290 };
1291
1292 priv_ops->rf_set_freq = ar9003_hw_set_channel;
1293 priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
1294 priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
1295 priv_ops->set_channel_regs = ar9003_hw_set_channel_regs;
1296 priv_ops->init_bb = ar9003_hw_init_bb;
1297 priv_ops->process_ini = ar9003_hw_process_ini;
1298 priv_ops->set_rfmode = ar9003_hw_set_rfmode;
1299 priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive;
1300 priv_ops->set_delta_slope = ar9003_hw_set_delta_slope;
1301 priv_ops->rfbus_req = ar9003_hw_rfbus_req;
1302 priv_ops->rfbus_done = ar9003_hw_rfbus_done;
1303 priv_ops->ani_control = ar9003_hw_ani_control;
1304 priv_ops->do_getnf = ar9003_hw_do_getnf;
1305 priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
1306 priv_ops->set_radar_params = ar9003_hw_set_radar_params;
1307 priv_ops->fast_chan_change = ar9003_hw_fast_chan_change;
1308
1309 ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get;
1310 ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set;
1311
1312 ar9003_hw_set_nf_limits(ah);
1313 ar9003_hw_set_radar_conf(ah);
1314 memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs));
1315 }
1316
1317 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah)
1318 {
1319 struct ath_common *common = ath9k_hw_common(ah);
1320 u32 idle_tmo_ms = ah->bb_watchdog_timeout_ms;
1321 u32 val, idle_count;
1322
1323 if (!idle_tmo_ms) {
1324 /* disable IRQ, disable chip-reset for BB panic */
1325 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1326 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) &
1327 ~(AR_PHY_WATCHDOG_RST_ENABLE |
1328 AR_PHY_WATCHDOG_IRQ_ENABLE));
1329
1330 /* disable watchdog in non-IDLE mode, disable in IDLE mode */
1331 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1332 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1) &
1333 ~(AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1334 AR_PHY_WATCHDOG_IDLE_ENABLE));
1335
1336 ath_dbg(common, RESET, "Disabled BB Watchdog\n");
1337 return;
1338 }
1339
1340 /* enable IRQ, disable chip-reset for BB watchdog */
1341 val = REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & AR_PHY_WATCHDOG_CNTL2_MASK;
1342 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1343 (val | AR_PHY_WATCHDOG_IRQ_ENABLE) &
1344 ~AR_PHY_WATCHDOG_RST_ENABLE);
1345
1346 /* bound limit to 10 secs */
1347 if (idle_tmo_ms > 10000)
1348 idle_tmo_ms = 10000;
1349
1350 /*
1351 * The time unit for watchdog event is 2^15 44/88MHz cycles.
1352 *
1353 * For HT20 we have a time unit of 2^15/44 MHz = .74 ms per tick
1354 * For HT40 we have a time unit of 2^15/88 MHz = .37 ms per tick
1355 *
1356 * Given we use fast clock now in 5 GHz, these time units should
1357 * be common for both 2 GHz and 5 GHz.
1358 */
1359 idle_count = (100 * idle_tmo_ms) / 74;
1360 if (ah->curchan && IS_CHAN_HT40(ah->curchan))
1361 idle_count = (100 * idle_tmo_ms) / 37;
1362
1363 /*
1364 * enable watchdog in non-IDLE mode, disable in IDLE mode,
1365 * set idle time-out.
1366 */
1367 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1368 AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1369 AR_PHY_WATCHDOG_IDLE_MASK |
1370 (AR_PHY_WATCHDOG_NON_IDLE_MASK & (idle_count << 2)));
1371
1372 ath_dbg(common, RESET, "Enabled BB Watchdog timeout (%u ms)\n",
1373 idle_tmo_ms);
1374 }
1375
1376 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah)
1377 {
1378 /*
1379 * we want to avoid printing in ISR context so we save the
1380 * watchdog status to be printed later in bottom half context.
1381 */
1382 ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS);
1383
1384 /*
1385 * the watchdog timer should reset on status read but to be sure
1386 * sure we write 0 to the watchdog status bit.
1387 */
1388 REG_WRITE(ah, AR_PHY_WATCHDOG_STATUS,
1389 ah->bb_watchdog_last_status & ~AR_PHY_WATCHDOG_STATUS_CLR);
1390 }
1391
1392 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah)
1393 {
1394 struct ath_common *common = ath9k_hw_common(ah);
1395 u32 status;
1396
1397 if (likely(!(common->debug_mask & ATH_DBG_RESET)))
1398 return;
1399
1400 status = ah->bb_watchdog_last_status;
1401 ath_dbg(common, RESET,
1402 "\n==== BB update: BB status=0x%08x ====\n", status);
1403 ath_dbg(common, RESET,
1404 "** BB state: wd=%u det=%u rdar=%u rOFDM=%d rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n",
1405 MS(status, AR_PHY_WATCHDOG_INFO),
1406 MS(status, AR_PHY_WATCHDOG_DET_HANG),
1407 MS(status, AR_PHY_WATCHDOG_RADAR_SM),
1408 MS(status, AR_PHY_WATCHDOG_RX_OFDM_SM),
1409 MS(status, AR_PHY_WATCHDOG_RX_CCK_SM),
1410 MS(status, AR_PHY_WATCHDOG_TX_OFDM_SM),
1411 MS(status, AR_PHY_WATCHDOG_TX_CCK_SM),
1412 MS(status, AR_PHY_WATCHDOG_AGC_SM),
1413 MS(status, AR_PHY_WATCHDOG_SRCH_SM));
1414
1415 ath_dbg(common, RESET, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n",
1416 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1),
1417 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2));
1418 ath_dbg(common, RESET, "** BB mode: BB_gen_controls=0x%08x **\n",
1419 REG_READ(ah, AR_PHY_GEN_CTRL));
1420
1421 #define PCT(_field) (common->cc_survey._field * 100 / common->cc_survey.cycles)
1422 if (common->cc_survey.cycles)
1423 ath_dbg(common, RESET,
1424 "** BB busy times: rx_clear=%d%%, rx_frame=%d%%, tx_frame=%d%% **\n",
1425 PCT(rx_busy), PCT(rx_frame), PCT(tx_frame));
1426
1427 ath_dbg(common, RESET, "==== BB update: done ====\n\n");
1428 }
1429 EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info);
1430
1431 void ar9003_hw_disable_phy_restart(struct ath_hw *ah)
1432 {
1433 u32 val;
1434
1435 /* While receiving unsupported rate frame rx state machine
1436 * gets into a state 0xb and if phy_restart happens in that
1437 * state, BB would go hang. If RXSM is in 0xb state after
1438 * first bb panic, ensure to disable the phy_restart.
1439 */
1440 if (!((MS(ah->bb_watchdog_last_status,
1441 AR_PHY_WATCHDOG_RX_OFDM_SM) == 0xb) ||
1442 ah->bb_hang_rx_ofdm))
1443 return;
1444
1445 ah->bb_hang_rx_ofdm = true;
1446 val = REG_READ(ah, AR_PHY_RESTART);
1447 val &= ~AR_PHY_RESTART_ENA;
1448
1449 REG_WRITE(ah, AR_PHY_RESTART, val);
1450 }
1451 EXPORT_SYMBOL(ar9003_hw_disable_phy_restart);
Linux with added FPC-III support