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Merge tag 'for-linus-20190706' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / iio / adc / ad7793.c
blobbbc41ecf0d2ffd3c0840ea8d0d28e39b17b47fb5
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * AD7785/AD7792/AD7793/AD7794/AD7795 SPI ADC driver
4 *
5 * Copyright 2011-2012 Analog Devices Inc.
6 */
7
8 #include <linux/interrupt.h>
9 #include <linux/device.h>
10 #include <linux/kernel.h>
11 #include <linux/slab.h>
12 #include <linux/sysfs.h>
13 #include <linux/spi/spi.h>
14 #include <linux/regulator/consumer.h>
15 #include <linux/err.h>
16 #include <linux/sched.h>
17 #include <linux/delay.h>
18 #include <linux/module.h>
19
20 #include <linux/iio/iio.h>
21 #include <linux/iio/sysfs.h>
22 #include <linux/iio/buffer.h>
23 #include <linux/iio/trigger.h>
24 #include <linux/iio/trigger_consumer.h>
25 #include <linux/iio/triggered_buffer.h>
26 #include <linux/iio/adc/ad_sigma_delta.h>
27 #include <linux/platform_data/ad7793.h>
28
29 /* Registers */
30 #define AD7793_REG_COMM 0 /* Communications Register (WO, 8-bit) */
31 #define AD7793_REG_STAT 0 /* Status Register (RO, 8-bit) */
32 #define AD7793_REG_MODE 1 /* Mode Register (RW, 16-bit */
33 #define AD7793_REG_CONF 2 /* Configuration Register (RW, 16-bit) */
34 #define AD7793_REG_DATA 3 /* Data Register (RO, 16-/24-bit) */
35 #define AD7793_REG_ID 4 /* ID Register (RO, 8-bit) */
36 #define AD7793_REG_IO 5 /* IO Register (RO, 8-bit) */
37 #define AD7793_REG_OFFSET 6 /* Offset Register (RW, 16-bit
38 * (AD7792)/24-bit (AD7793)) */
39 #define AD7793_REG_FULLSALE 7 /* Full-Scale Register
40 * (RW, 16-bit (AD7792)/24-bit (AD7793)) */
41
42 /* Communications Register Bit Designations (AD7793_REG_COMM) */
43 #define AD7793_COMM_WEN (1 << 7) /* Write Enable */
44 #define AD7793_COMM_WRITE (0 << 6) /* Write Operation */
45 #define AD7793_COMM_READ (1 << 6) /* Read Operation */
46 #define AD7793_COMM_ADDR(x) (((x) & 0x7) << 3) /* Register Address */
47 #define AD7793_COMM_CREAD (1 << 2) /* Continuous Read of Data Register */
48
49 /* Status Register Bit Designations (AD7793_REG_STAT) */
50 #define AD7793_STAT_RDY (1 << 7) /* Ready */
51 #define AD7793_STAT_ERR (1 << 6) /* Error (Overrange, Underrange) */
52 #define AD7793_STAT_CH3 (1 << 2) /* Channel 3 */
53 #define AD7793_STAT_CH2 (1 << 1) /* Channel 2 */
54 #define AD7793_STAT_CH1 (1 << 0) /* Channel 1 */
55
56 /* Mode Register Bit Designations (AD7793_REG_MODE) */
57 #define AD7793_MODE_SEL(x) (((x) & 0x7) << 13) /* Operation Mode Select */
58 #define AD7793_MODE_SEL_MASK (0x7 << 13) /* Operation Mode Select mask */
59 #define AD7793_MODE_CLKSRC(x) (((x) & 0x3) << 6) /* ADC Clock Source Select */
60 #define AD7793_MODE_RATE(x) ((x) & 0xF) /* Filter Update Rate Select */
61
62 #define AD7793_MODE_CONT 0 /* Continuous Conversion Mode */
63 #define AD7793_MODE_SINGLE 1 /* Single Conversion Mode */
64 #define AD7793_MODE_IDLE 2 /* Idle Mode */
65 #define AD7793_MODE_PWRDN 3 /* Power-Down Mode */
66 #define AD7793_MODE_CAL_INT_ZERO 4 /* Internal Zero-Scale Calibration */
67 #define AD7793_MODE_CAL_INT_FULL 5 /* Internal Full-Scale Calibration */
68 #define AD7793_MODE_CAL_SYS_ZERO 6 /* System Zero-Scale Calibration */
69 #define AD7793_MODE_CAL_SYS_FULL 7 /* System Full-Scale Calibration */
70
71 #define AD7793_CLK_INT 0 /* Internal 64 kHz Clock not
72 * available at the CLK pin */
73 #define AD7793_CLK_INT_CO 1 /* Internal 64 kHz Clock available
74 * at the CLK pin */
75 #define AD7793_CLK_EXT 2 /* External 64 kHz Clock */
76 #define AD7793_CLK_EXT_DIV2 3 /* External Clock divided by 2 */
77
78 /* Configuration Register Bit Designations (AD7793_REG_CONF) */
79 #define AD7793_CONF_VBIAS(x) (((x) & 0x3) << 14) /* Bias Voltage
80 * Generator Enable */
81 #define AD7793_CONF_BO_EN (1 << 13) /* Burnout Current Enable */
82 #define AD7793_CONF_UNIPOLAR (1 << 12) /* Unipolar/Bipolar Enable */
83 #define AD7793_CONF_BOOST (1 << 11) /* Boost Enable */
84 #define AD7793_CONF_GAIN(x) (((x) & 0x7) << 8) /* Gain Select */
85 #define AD7793_CONF_REFSEL(x) ((x) << 6) /* INT/EXT Reference Select */
86 #define AD7793_CONF_BUF (1 << 4) /* Buffered Mode Enable */
87 #define AD7793_CONF_CHAN(x) ((x) & 0xf) /* Channel select */
88 #define AD7793_CONF_CHAN_MASK 0xf /* Channel select mask */
89
90 #define AD7793_CH_AIN1P_AIN1M 0 /* AIN1(+) - AIN1(-) */
91 #define AD7793_CH_AIN2P_AIN2M 1 /* AIN2(+) - AIN2(-) */
92 #define AD7793_CH_AIN3P_AIN3M 2 /* AIN3(+) - AIN3(-) */
93 #define AD7793_CH_AIN1M_AIN1M 3 /* AIN1(-) - AIN1(-) */
94 #define AD7793_CH_TEMP 6 /* Temp Sensor */
95 #define AD7793_CH_AVDD_MONITOR 7 /* AVDD Monitor */
96
97 #define AD7795_CH_AIN4P_AIN4M 4 /* AIN4(+) - AIN4(-) */
98 #define AD7795_CH_AIN5P_AIN5M 5 /* AIN5(+) - AIN5(-) */
99 #define AD7795_CH_AIN6P_AIN6M 6 /* AIN6(+) - AIN6(-) */
100 #define AD7795_CH_AIN1M_AIN1M 8 /* AIN1(-) - AIN1(-) */
101
102 /* ID Register Bit Designations (AD7793_REG_ID) */
103 #define AD7785_ID 0x3
104 #define AD7792_ID 0xA
105 #define AD7793_ID 0xB
106 #define AD7794_ID 0xF
107 #define AD7795_ID 0xF
108 #define AD7796_ID 0xA
109 #define AD7797_ID 0xB
110 #define AD7798_ID 0x8
111 #define AD7799_ID 0x9
112 #define AD7793_ID_MASK 0xF
113
114 /* IO (Excitation Current Sources) Register Bit Designations (AD7793_REG_IO) */
115 #define AD7793_IO_IEXC1_IOUT1_IEXC2_IOUT2 0 /* IEXC1 connect to IOUT1,
116 * IEXC2 connect to IOUT2 */
117 #define AD7793_IO_IEXC1_IOUT2_IEXC2_IOUT1 1 /* IEXC1 connect to IOUT2,
118 * IEXC2 connect to IOUT1 */
119 #define AD7793_IO_IEXC1_IEXC2_IOUT1 2 /* Both current sources
120 * IEXC1,2 connect to IOUT1 */
121 #define AD7793_IO_IEXC1_IEXC2_IOUT2 3 /* Both current sources
122 * IEXC1,2 connect to IOUT2 */
123
124 #define AD7793_IO_IXCEN_10uA (1 << 0) /* Excitation Current 10uA */
125 #define AD7793_IO_IXCEN_210uA (2 << 0) /* Excitation Current 210uA */
126 #define AD7793_IO_IXCEN_1mA (3 << 0) /* Excitation Current 1mA */
127
128 /* NOTE:
129 * The AD7792/AD7793 features a dual use data out ready DOUT/RDY output.
130 * In order to avoid contentions on the SPI bus, it's therefore necessary
131 * to use spi bus locking.
132 *
133 * The DOUT/RDY output must also be wired to an interrupt capable GPIO.
134 */
135
136 #define AD7793_FLAG_HAS_CLKSEL BIT(0)
137 #define AD7793_FLAG_HAS_REFSEL BIT(1)
138 #define AD7793_FLAG_HAS_VBIAS BIT(2)
139 #define AD7793_HAS_EXITATION_CURRENT BIT(3)
140 #define AD7793_FLAG_HAS_GAIN BIT(4)
141 #define AD7793_FLAG_HAS_BUFFER BIT(5)
142
143 struct ad7793_chip_info {
144 unsigned int id;
145 const struct iio_chan_spec *channels;
146 unsigned int num_channels;
147 unsigned int flags;
148
149 const struct iio_info *iio_info;
150 const u16 *sample_freq_avail;
151 };
152
153 struct ad7793_state {
154 const struct ad7793_chip_info *chip_info;
155 struct regulator *reg;
156 u16 int_vref_mv;
157 u16 mode;
158 u16 conf;
159 u32 scale_avail[8][2];
160
161 struct ad_sigma_delta sd;
162
163 };
164
165 enum ad7793_supported_device_ids {
166 ID_AD7785,
167 ID_AD7792,
168 ID_AD7793,
169 ID_AD7794,
170 ID_AD7795,
171 ID_AD7796,
172 ID_AD7797,
173 ID_AD7798,
174 ID_AD7799,
175 };
176
177 static struct ad7793_state *ad_sigma_delta_to_ad7793(struct ad_sigma_delta *sd)
178 {
179 return container_of(sd, struct ad7793_state, sd);
180 }
181
182 static int ad7793_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
183 {
184 struct ad7793_state *st = ad_sigma_delta_to_ad7793(sd);
185
186 st->conf &= ~AD7793_CONF_CHAN_MASK;
187 st->conf |= AD7793_CONF_CHAN(channel);
188
189 return ad_sd_write_reg(&st->sd, AD7793_REG_CONF, 2, st->conf);
190 }
191
192 static int ad7793_set_mode(struct ad_sigma_delta *sd,
193 enum ad_sigma_delta_mode mode)
194 {
195 struct ad7793_state *st = ad_sigma_delta_to_ad7793(sd);
196
197 st->mode &= ~AD7793_MODE_SEL_MASK;
198 st->mode |= AD7793_MODE_SEL(mode);
199
200 return ad_sd_write_reg(&st->sd, AD7793_REG_MODE, 2, st->mode);
201 }
202
203 static const struct ad_sigma_delta_info ad7793_sigma_delta_info = {
204 .set_channel = ad7793_set_channel,
205 .set_mode = ad7793_set_mode,
206 .has_registers = true,
207 .addr_shift = 3,
208 .read_mask = BIT(6),
209 };
210
211 static const struct ad_sd_calib_data ad7793_calib_arr[6] = {
212 {AD7793_MODE_CAL_INT_ZERO, AD7793_CH_AIN1P_AIN1M},
213 {AD7793_MODE_CAL_INT_FULL, AD7793_CH_AIN1P_AIN1M},
214 {AD7793_MODE_CAL_INT_ZERO, AD7793_CH_AIN2P_AIN2M},
215 {AD7793_MODE_CAL_INT_FULL, AD7793_CH_AIN2P_AIN2M},
216 {AD7793_MODE_CAL_INT_ZERO, AD7793_CH_AIN3P_AIN3M},
217 {AD7793_MODE_CAL_INT_FULL, AD7793_CH_AIN3P_AIN3M}
218 };
219
220 static int ad7793_calibrate_all(struct ad7793_state *st)
221 {
222 return ad_sd_calibrate_all(&st->sd, ad7793_calib_arr,
223 ARRAY_SIZE(ad7793_calib_arr));
224 }
225
226 static int ad7793_check_platform_data(struct ad7793_state *st,
227 const struct ad7793_platform_data *pdata)
228 {
229 if ((pdata->current_source_direction == AD7793_IEXEC1_IEXEC2_IOUT1 ||
230 pdata->current_source_direction == AD7793_IEXEC1_IEXEC2_IOUT2) &&
231 ((pdata->exitation_current != AD7793_IX_10uA) &&
232 (pdata->exitation_current != AD7793_IX_210uA)))
233 return -EINVAL;
234
235 if (!(st->chip_info->flags & AD7793_FLAG_HAS_CLKSEL) &&
236 pdata->clock_src != AD7793_CLK_SRC_INT)
237 return -EINVAL;
238
239 if (!(st->chip_info->flags & AD7793_FLAG_HAS_REFSEL) &&
240 pdata->refsel != AD7793_REFSEL_REFIN1)
241 return -EINVAL;
242
243 if (!(st->chip_info->flags & AD7793_FLAG_HAS_VBIAS) &&
244 pdata->bias_voltage != AD7793_BIAS_VOLTAGE_DISABLED)
245 return -EINVAL;
246
247 if (!(st->chip_info->flags & AD7793_HAS_EXITATION_CURRENT) &&
248 pdata->exitation_current != AD7793_IX_DISABLED)
249 return -EINVAL;
250
251 return 0;
252 }
253
254 static int ad7793_setup(struct iio_dev *indio_dev,
255 const struct ad7793_platform_data *pdata,
256 unsigned int vref_mv)
257 {
258 struct ad7793_state *st = iio_priv(indio_dev);
259 int i, ret;
260 unsigned long long scale_uv;
261 u32 id;
262
263 ret = ad7793_check_platform_data(st, pdata);
264 if (ret)
265 return ret;
266
267 /* reset the serial interface */
268 ret = ad_sd_reset(&st->sd, 32);
269 if (ret < 0)
270 goto out;
271 usleep_range(500, 2000); /* Wait for at least 500us */
272
273 /* write/read test for device presence */
274 ret = ad_sd_read_reg(&st->sd, AD7793_REG_ID, 1, &id);
275 if (ret)
276 goto out;
277
278 id &= AD7793_ID_MASK;
279
280 if (id != st->chip_info->id) {
281 dev_err(&st->sd.spi->dev, "device ID query failed\n");
282 goto out;
283 }
284
285 st->mode = AD7793_MODE_RATE(1);
286 st->conf = 0;
287
288 if (st->chip_info->flags & AD7793_FLAG_HAS_CLKSEL)
289 st->mode |= AD7793_MODE_CLKSRC(pdata->clock_src);
290 if (st->chip_info->flags & AD7793_FLAG_HAS_REFSEL)
291 st->conf |= AD7793_CONF_REFSEL(pdata->refsel);
292 if (st->chip_info->flags & AD7793_FLAG_HAS_VBIAS)
293 st->conf |= AD7793_CONF_VBIAS(pdata->bias_voltage);
294 if (pdata->buffered || !(st->chip_info->flags & AD7793_FLAG_HAS_BUFFER))
295 st->conf |= AD7793_CONF_BUF;
296 if (pdata->boost_enable &&
297 (st->chip_info->flags & AD7793_FLAG_HAS_VBIAS))
298 st->conf |= AD7793_CONF_BOOST;
299 if (pdata->burnout_current)
300 st->conf |= AD7793_CONF_BO_EN;
301 if (pdata->unipolar)
302 st->conf |= AD7793_CONF_UNIPOLAR;
303
304 if (!(st->chip_info->flags & AD7793_FLAG_HAS_GAIN))
305 st->conf |= AD7793_CONF_GAIN(7);
306
307 ret = ad7793_set_mode(&st->sd, AD_SD_MODE_IDLE);
308 if (ret)
309 goto out;
310
311 ret = ad7793_set_channel(&st->sd, 0);
312 if (ret)
313 goto out;
314
315 if (st->chip_info->flags & AD7793_HAS_EXITATION_CURRENT) {
316 ret = ad_sd_write_reg(&st->sd, AD7793_REG_IO, 1,
317 pdata->exitation_current |
318 (pdata->current_source_direction << 2));
319 if (ret)
320 goto out;
321 }
322
323 ret = ad7793_calibrate_all(st);
324 if (ret)
325 goto out;
326
327 /* Populate available ADC input ranges */
328 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) {
329 scale_uv = ((u64)vref_mv * 100000000)
330 >> (st->chip_info->channels[0].scan_type.realbits -
331 (!!(st->conf & AD7793_CONF_UNIPOLAR) ? 0 : 1));
332 scale_uv >>= i;
333
334 st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10;
335 st->scale_avail[i][0] = scale_uv;
336 }
337
338 return 0;
339 out:
340 dev_err(&st->sd.spi->dev, "setup failed\n");
341 return ret;
342 }
343
344 static const u16 ad7793_sample_freq_avail[16] = {0, 470, 242, 123, 62, 50, 39,
345 33, 19, 17, 16, 12, 10, 8, 6, 4};
346
347 static const u16 ad7797_sample_freq_avail[16] = {0, 0, 0, 123, 62, 50, 0,
348 33, 0, 17, 16, 12, 10, 8, 6, 4};
349
350 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(
351 "470 242 123 62 50 39 33 19 17 16 12 10 8 6 4");
352
353 static IIO_CONST_ATTR_NAMED(sampling_frequency_available_ad7797,
354 sampling_frequency_available, "123 62 50 33 17 16 12 10 8 6 4");
355
356 static ssize_t ad7793_show_scale_available(struct device *dev,
357 struct device_attribute *attr, char *buf)
358 {
359 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
360 struct ad7793_state *st = iio_priv(indio_dev);
361 int i, len = 0;
362
363 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
364 len += sprintf(buf + len, "%d.%09u ", st->scale_avail[i][0],
365 st->scale_avail[i][1]);
366
367 len += sprintf(buf + len, "\n");
368
369 return len;
370 }
371
372 static IIO_DEVICE_ATTR_NAMED(in_m_in_scale_available,
373 in_voltage-voltage_scale_available, S_IRUGO,
374 ad7793_show_scale_available, NULL, 0);
375
376 static struct attribute *ad7793_attributes[] = {
377 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
378 &iio_dev_attr_in_m_in_scale_available.dev_attr.attr,
379 NULL
380 };
381
382 static const struct attribute_group ad7793_attribute_group = {
383 .attrs = ad7793_attributes,
384 };
385
386 static struct attribute *ad7797_attributes[] = {
387 &iio_const_attr_sampling_frequency_available_ad7797.dev_attr.attr,
388 NULL
389 };
390
391 static const struct attribute_group ad7797_attribute_group = {
392 .attrs = ad7797_attributes,
393 };
394
395 static int ad7793_read_raw(struct iio_dev *indio_dev,
396 struct iio_chan_spec const *chan,
397 int *val,
398 int *val2,
399 long m)
400 {
401 struct ad7793_state *st = iio_priv(indio_dev);
402 int ret;
403 unsigned long long scale_uv;
404 bool unipolar = !!(st->conf & AD7793_CONF_UNIPOLAR);
405
406 switch (m) {
407 case IIO_CHAN_INFO_RAW:
408 ret = ad_sigma_delta_single_conversion(indio_dev, chan, val);
409 if (ret < 0)
410 return ret;
411
412 return IIO_VAL_INT;
413
414 case IIO_CHAN_INFO_SCALE:
415 switch (chan->type) {
416 case IIO_VOLTAGE:
417 if (chan->differential) {
418 *val = st->
419 scale_avail[(st->conf >> 8) & 0x7][0];
420 *val2 = st->
421 scale_avail[(st->conf >> 8) & 0x7][1];
422 return IIO_VAL_INT_PLUS_NANO;
423 }
424 /* 1170mV / 2^23 * 6 */
425 scale_uv = (1170ULL * 1000000000ULL * 6ULL);
426 break;
427 case IIO_TEMP:
428 /* 1170mV / 0.81 mV/C / 2^23 */
429 scale_uv = 1444444444444444ULL;
430 break;
431 default:
432 return -EINVAL;
433 }
434
435 scale_uv >>= (chan->scan_type.realbits - (unipolar ? 0 : 1));
436 *val = 0;
437 *val2 = scale_uv;
438 return IIO_VAL_INT_PLUS_NANO;
439 case IIO_CHAN_INFO_OFFSET:
440 if (!unipolar)
441 *val = -(1 << (chan->scan_type.realbits - 1));
442 else
443 *val = 0;
444
445 /* Kelvin to Celsius */
446 if (chan->type == IIO_TEMP) {
447 unsigned long long offset;
448 unsigned int shift;
449
450 shift = chan->scan_type.realbits - (unipolar ? 0 : 1);
451 offset = 273ULL << shift;
452 do_div(offset, 1444);
453 *val -= offset;
454 }
455 return IIO_VAL_INT;
456 case IIO_CHAN_INFO_SAMP_FREQ:
457 *val = st->chip_info
458 ->sample_freq_avail[AD7793_MODE_RATE(st->mode)];
459 return IIO_VAL_INT;
460 }
461 return -EINVAL;
462 }
463
464 static int ad7793_write_raw(struct iio_dev *indio_dev,
465 struct iio_chan_spec const *chan,
466 int val,
467 int val2,
468 long mask)
469 {
470 struct ad7793_state *st = iio_priv(indio_dev);
471 int ret, i;
472 unsigned int tmp;
473
474 ret = iio_device_claim_direct_mode(indio_dev);
475 if (ret)
476 return ret;
477
478 switch (mask) {
479 case IIO_CHAN_INFO_SCALE:
480 ret = -EINVAL;
481 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
482 if (val2 == st->scale_avail[i][1]) {
483 ret = 0;
484 tmp = st->conf;
485 st->conf &= ~AD7793_CONF_GAIN(-1);
486 st->conf |= AD7793_CONF_GAIN(i);
487
488 if (tmp == st->conf)
489 break;
490
491 ad_sd_write_reg(&st->sd, AD7793_REG_CONF,
492 sizeof(st->conf), st->conf);
493 ad7793_calibrate_all(st);
494 break;
495 }
496 break;
497 case IIO_CHAN_INFO_SAMP_FREQ:
498 if (!val) {
499 ret = -EINVAL;
500 break;
501 }
502
503 for (i = 0; i < 16; i++)
504 if (val == st->chip_info->sample_freq_avail[i])
505 break;
506
507 if (i == 16) {
508 ret = -EINVAL;
509 break;
510 }
511
512 st->mode &= ~AD7793_MODE_RATE(-1);
513 st->mode |= AD7793_MODE_RATE(i);
514 ad_sd_write_reg(&st->sd, AD7793_REG_MODE, sizeof(st->mode),
515 st->mode);
516 break;
517 default:
518 ret = -EINVAL;
519 }
520
521 iio_device_release_direct_mode(indio_dev);
522 return ret;
523 }
524
525 static int ad7793_write_raw_get_fmt(struct iio_dev *indio_dev,
526 struct iio_chan_spec const *chan,
527 long mask)
528 {
529 return IIO_VAL_INT_PLUS_NANO;
530 }
531
532 static const struct iio_info ad7793_info = {
533 .read_raw = &ad7793_read_raw,
534 .write_raw = &ad7793_write_raw,
535 .write_raw_get_fmt = &ad7793_write_raw_get_fmt,
536 .attrs = &ad7793_attribute_group,
537 .validate_trigger = ad_sd_validate_trigger,
538 };
539
540 static const struct iio_info ad7797_info = {
541 .read_raw = &ad7793_read_raw,
542 .write_raw = &ad7793_write_raw,
543 .write_raw_get_fmt = &ad7793_write_raw_get_fmt,
544 .attrs = &ad7793_attribute_group,
545 .validate_trigger = ad_sd_validate_trigger,
546 };
547
548 #define DECLARE_AD7793_CHANNELS(_name, _b, _sb, _s) \
549 const struct iio_chan_spec _name##_channels[] = { \
550 AD_SD_DIFF_CHANNEL(0, 0, 0, AD7793_CH_AIN1P_AIN1M, (_b), (_sb), (_s)), \
551 AD_SD_DIFF_CHANNEL(1, 1, 1, AD7793_CH_AIN2P_AIN2M, (_b), (_sb), (_s)), \
552 AD_SD_DIFF_CHANNEL(2, 2, 2, AD7793_CH_AIN3P_AIN3M, (_b), (_sb), (_s)), \
553 AD_SD_SHORTED_CHANNEL(3, 0, AD7793_CH_AIN1M_AIN1M, (_b), (_sb), (_s)), \
554 AD_SD_TEMP_CHANNEL(4, AD7793_CH_TEMP, (_b), (_sb), (_s)), \
555 AD_SD_SUPPLY_CHANNEL(5, 3, AD7793_CH_AVDD_MONITOR, (_b), (_sb), (_s)), \
556 IIO_CHAN_SOFT_TIMESTAMP(6), \
557 }
558
559 #define DECLARE_AD7795_CHANNELS(_name, _b, _sb) \
560 const struct iio_chan_spec _name##_channels[] = { \
561 AD_SD_DIFF_CHANNEL(0, 0, 0, AD7793_CH_AIN1P_AIN1M, (_b), (_sb), 0), \
562 AD_SD_DIFF_CHANNEL(1, 1, 1, AD7793_CH_AIN2P_AIN2M, (_b), (_sb), 0), \
563 AD_SD_DIFF_CHANNEL(2, 2, 2, AD7793_CH_AIN3P_AIN3M, (_b), (_sb), 0), \
564 AD_SD_DIFF_CHANNEL(3, 3, 3, AD7795_CH_AIN4P_AIN4M, (_b), (_sb), 0), \
565 AD_SD_DIFF_CHANNEL(4, 4, 4, AD7795_CH_AIN5P_AIN5M, (_b), (_sb), 0), \
566 AD_SD_DIFF_CHANNEL(5, 5, 5, AD7795_CH_AIN6P_AIN6M, (_b), (_sb), 0), \
567 AD_SD_SHORTED_CHANNEL(6, 0, AD7795_CH_AIN1M_AIN1M, (_b), (_sb), 0), \
568 AD_SD_TEMP_CHANNEL(7, AD7793_CH_TEMP, (_b), (_sb), 0), \
569 AD_SD_SUPPLY_CHANNEL(8, 3, AD7793_CH_AVDD_MONITOR, (_b), (_sb), 0), \
570 IIO_CHAN_SOFT_TIMESTAMP(9), \
571 }
572
573 #define DECLARE_AD7797_CHANNELS(_name, _b, _sb) \
574 const struct iio_chan_spec _name##_channels[] = { \
575 AD_SD_DIFF_CHANNEL(0, 0, 0, AD7793_CH_AIN1P_AIN1M, (_b), (_sb), 0), \
576 AD_SD_SHORTED_CHANNEL(1, 0, AD7793_CH_AIN1M_AIN1M, (_b), (_sb), 0), \
577 AD_SD_TEMP_CHANNEL(2, AD7793_CH_TEMP, (_b), (_sb), 0), \
578 AD_SD_SUPPLY_CHANNEL(3, 3, AD7793_CH_AVDD_MONITOR, (_b), (_sb), 0), \
579 IIO_CHAN_SOFT_TIMESTAMP(4), \
580 }
581
582 #define DECLARE_AD7799_CHANNELS(_name, _b, _sb) \
583 const struct iio_chan_spec _name##_channels[] = { \
584 AD_SD_DIFF_CHANNEL(0, 0, 0, AD7793_CH_AIN1P_AIN1M, (_b), (_sb), 0), \
585 AD_SD_DIFF_CHANNEL(1, 1, 1, AD7793_CH_AIN2P_AIN2M, (_b), (_sb), 0), \
586 AD_SD_DIFF_CHANNEL(2, 2, 2, AD7793_CH_AIN3P_AIN3M, (_b), (_sb), 0), \
587 AD_SD_SHORTED_CHANNEL(3, 0, AD7793_CH_AIN1M_AIN1M, (_b), (_sb), 0), \
588 AD_SD_SUPPLY_CHANNEL(4, 3, AD7793_CH_AVDD_MONITOR, (_b), (_sb), 0), \
589 IIO_CHAN_SOFT_TIMESTAMP(5), \
590 }
591
592 static DECLARE_AD7793_CHANNELS(ad7785, 20, 32, 4);
593 static DECLARE_AD7793_CHANNELS(ad7792, 16, 32, 0);
594 static DECLARE_AD7793_CHANNELS(ad7793, 24, 32, 0);
595 static DECLARE_AD7795_CHANNELS(ad7794, 16, 32);
596 static DECLARE_AD7795_CHANNELS(ad7795, 24, 32);
597 static DECLARE_AD7797_CHANNELS(ad7796, 16, 16);
598 static DECLARE_AD7797_CHANNELS(ad7797, 24, 32);
599 static DECLARE_AD7799_CHANNELS(ad7798, 16, 16);
600 static DECLARE_AD7799_CHANNELS(ad7799, 24, 32);
601
602 static const struct ad7793_chip_info ad7793_chip_info_tbl[] = {
603 [ID_AD7785] = {
604 .id = AD7785_ID,
605 .channels = ad7785_channels,
606 .num_channels = ARRAY_SIZE(ad7785_channels),
607 .iio_info = &ad7793_info,
608 .sample_freq_avail = ad7793_sample_freq_avail,
609 .flags = AD7793_FLAG_HAS_CLKSEL |
610 AD7793_FLAG_HAS_REFSEL |
611 AD7793_FLAG_HAS_VBIAS |
612 AD7793_HAS_EXITATION_CURRENT |
613 AD7793_FLAG_HAS_GAIN |
614 AD7793_FLAG_HAS_BUFFER,
615 },
616 [ID_AD7792] = {
617 .id = AD7792_ID,
618 .channels = ad7792_channels,
619 .num_channels = ARRAY_SIZE(ad7792_channels),
620 .iio_info = &ad7793_info,
621 .sample_freq_avail = ad7793_sample_freq_avail,
622 .flags = AD7793_FLAG_HAS_CLKSEL |
623 AD7793_FLAG_HAS_REFSEL |
624 AD7793_FLAG_HAS_VBIAS |
625 AD7793_HAS_EXITATION_CURRENT |
626 AD7793_FLAG_HAS_GAIN |
627 AD7793_FLAG_HAS_BUFFER,
628 },
629 [ID_AD7793] = {
630 .id = AD7793_ID,
631 .channels = ad7793_channels,
632 .num_channels = ARRAY_SIZE(ad7793_channels),
633 .iio_info = &ad7793_info,
634 .sample_freq_avail = ad7793_sample_freq_avail,
635 .flags = AD7793_FLAG_HAS_CLKSEL |
636 AD7793_FLAG_HAS_REFSEL |
637 AD7793_FLAG_HAS_VBIAS |
638 AD7793_HAS_EXITATION_CURRENT |
639 AD7793_FLAG_HAS_GAIN |
640 AD7793_FLAG_HAS_BUFFER,
641 },
642 [ID_AD7794] = {
643 .id = AD7794_ID,
644 .channels = ad7794_channels,
645 .num_channels = ARRAY_SIZE(ad7794_channels),
646 .iio_info = &ad7793_info,
647 .sample_freq_avail = ad7793_sample_freq_avail,
648 .flags = AD7793_FLAG_HAS_CLKSEL |
649 AD7793_FLAG_HAS_REFSEL |
650 AD7793_FLAG_HAS_VBIAS |
651 AD7793_HAS_EXITATION_CURRENT |
652 AD7793_FLAG_HAS_GAIN |
653 AD7793_FLAG_HAS_BUFFER,
654 },
655 [ID_AD7795] = {
656 .id = AD7795_ID,
657 .channels = ad7795_channels,
658 .num_channels = ARRAY_SIZE(ad7795_channels),
659 .iio_info = &ad7793_info,
660 .sample_freq_avail = ad7793_sample_freq_avail,
661 .flags = AD7793_FLAG_HAS_CLKSEL |
662 AD7793_FLAG_HAS_REFSEL |
663 AD7793_FLAG_HAS_VBIAS |
664 AD7793_HAS_EXITATION_CURRENT |
665 AD7793_FLAG_HAS_GAIN |
666 AD7793_FLAG_HAS_BUFFER,
667 },
668 [ID_AD7796] = {
669 .id = AD7796_ID,
670 .channels = ad7796_channels,
671 .num_channels = ARRAY_SIZE(ad7796_channels),
672 .iio_info = &ad7797_info,
673 .sample_freq_avail = ad7797_sample_freq_avail,
674 .flags = AD7793_FLAG_HAS_CLKSEL,
675 },
676 [ID_AD7797] = {
677 .id = AD7797_ID,
678 .channels = ad7797_channels,
679 .num_channels = ARRAY_SIZE(ad7797_channels),
680 .iio_info = &ad7797_info,
681 .sample_freq_avail = ad7797_sample_freq_avail,
682 .flags = AD7793_FLAG_HAS_CLKSEL,
683 },
684 [ID_AD7798] = {
685 .id = AD7798_ID,
686 .channels = ad7798_channels,
687 .num_channels = ARRAY_SIZE(ad7798_channels),
688 .iio_info = &ad7793_info,
689 .sample_freq_avail = ad7793_sample_freq_avail,
690 .flags = AD7793_FLAG_HAS_GAIN |
691 AD7793_FLAG_HAS_BUFFER,
692 },
693 [ID_AD7799] = {
694 .id = AD7799_ID,
695 .channels = ad7799_channels,
696 .num_channels = ARRAY_SIZE(ad7799_channels),
697 .iio_info = &ad7793_info,
698 .sample_freq_avail = ad7793_sample_freq_avail,
699 .flags = AD7793_FLAG_HAS_GAIN |
700 AD7793_FLAG_HAS_BUFFER,
701 },
702 };
703
704 static int ad7793_probe(struct spi_device *spi)
705 {
706 const struct ad7793_platform_data *pdata = spi->dev.platform_data;
707 struct ad7793_state *st;
708 struct iio_dev *indio_dev;
709 int ret, vref_mv = 0;
710
711 if (!pdata) {
712 dev_err(&spi->dev, "no platform data?\n");
713 return -ENODEV;
714 }
715
716 if (!spi->irq) {
717 dev_err(&spi->dev, "no IRQ?\n");
718 return -ENODEV;
719 }
720
721 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
722 if (indio_dev == NULL)
723 return -ENOMEM;
724
725 st = iio_priv(indio_dev);
726
727 ad_sd_init(&st->sd, indio_dev, spi, &ad7793_sigma_delta_info);
728
729 if (pdata->refsel != AD7793_REFSEL_INTERNAL) {
730 st->reg = devm_regulator_get(&spi->dev, "refin");
731 if (IS_ERR(st->reg))
732 return PTR_ERR(st->reg);
733
734 ret = regulator_enable(st->reg);
735 if (ret)
736 return ret;
737
738 vref_mv = regulator_get_voltage(st->reg);
739 if (vref_mv < 0) {
740 ret = vref_mv;
741 goto error_disable_reg;
742 }
743
744 vref_mv /= 1000;
745 } else {
746 vref_mv = 1170; /* Build-in ref */
747 }
748
749 st->chip_info =
750 &ad7793_chip_info_tbl[spi_get_device_id(spi)->driver_data];
751
752 spi_set_drvdata(spi, indio_dev);
753
754 indio_dev->dev.parent = &spi->dev;
755 indio_dev->dev.of_node = spi->dev.of_node;
756 indio_dev->name = spi_get_device_id(spi)->name;
757 indio_dev->modes = INDIO_DIRECT_MODE;
758 indio_dev->channels = st->chip_info->channels;
759 indio_dev->num_channels = st->chip_info->num_channels;
760 indio_dev->info = st->chip_info->iio_info;
761
762 ret = ad_sd_setup_buffer_and_trigger(indio_dev);
763 if (ret)
764 goto error_disable_reg;
765
766 ret = ad7793_setup(indio_dev, pdata, vref_mv);
767 if (ret)
768 goto error_remove_trigger;
769
770 ret = iio_device_register(indio_dev);
771 if (ret)
772 goto error_remove_trigger;
773
774 return 0;
775
776 error_remove_trigger:
777 ad_sd_cleanup_buffer_and_trigger(indio_dev);
778 error_disable_reg:
779 if (pdata->refsel != AD7793_REFSEL_INTERNAL)
780 regulator_disable(st->reg);
781
782 return ret;
783 }
784
785 static int ad7793_remove(struct spi_device *spi)
786 {
787 const struct ad7793_platform_data *pdata = spi->dev.platform_data;
788 struct iio_dev *indio_dev = spi_get_drvdata(spi);
789 struct ad7793_state *st = iio_priv(indio_dev);
790
791 iio_device_unregister(indio_dev);
792 ad_sd_cleanup_buffer_and_trigger(indio_dev);
793
794 if (pdata->refsel != AD7793_REFSEL_INTERNAL)
795 regulator_disable(st->reg);
796
797 return 0;
798 }
799
800 static const struct spi_device_id ad7793_id[] = {
801 {"ad7785", ID_AD7785},
802 {"ad7792", ID_AD7792},
803 {"ad7793", ID_AD7793},
804 {"ad7794", ID_AD7794},
805 {"ad7795", ID_AD7795},
806 {"ad7796", ID_AD7796},
807 {"ad7797", ID_AD7797},
808 {"ad7798", ID_AD7798},
809 {"ad7799", ID_AD7799},
810 {}
811 };
812 MODULE_DEVICE_TABLE(spi, ad7793_id);
813
814 static struct spi_driver ad7793_driver = {
815 .driver = {
816 .name = "ad7793",
817 },
818 .probe = ad7793_probe,
819 .remove = ad7793_remove,
820 .id_table = ad7793_id,
821 };
822 module_spi_driver(ad7793_driver);
823
824 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
825 MODULE_DESCRIPTION("Analog Devices AD7793 and similar ADCs");
826 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support