drivers/iio/adc/ad7949.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* ad7949.c - Analog Devices ADC driver 14/16 bits 4/8 channels
   3  *
   4  * Copyright (C) 2018 CMC NV
   5  *
   6  * http://www.analog.com/media/en/technical-documentation/data-sheets/AD7949.pdf
   7  */
   8
   9 #include <linux/delay.h>
  10 #include <linux/iio/iio.h>
  11 #include <linux/module.h>
  12 #include <linux/regulator/consumer.h>
  13 #include <linux/spi/spi.h>
  14
  15 #define AD7949_MASK_CHANNEL_SEL         GENMASK(9, 7)
  16 #define AD7949_MASK_TOTAL               GENMASK(13, 0)
  17 #define AD7949_OFFSET_CHANNEL_SEL       7
  18 #define AD7949_CFG_READ_BACK            0x1
  19 #define AD7949_CFG_REG_SIZE_BITS        14
  20
  21 enum {
  22         ID_AD7949 = 0,
  23         ID_AD7682,
  24         ID_AD7689,
  25 };
  26
  27 struct ad7949_adc_spec {
  28         u8 num_channels;
  29         u8 resolution;
  30 };
  31
  32 static const struct ad7949_adc_spec ad7949_adc_spec[] = {
  33         [ID_AD7949] = { .num_channels = 8, .resolution = 14 },
  34         [ID_AD7682] = { .num_channels = 4, .resolution = 16 },
  35         [ID_AD7689] = { .num_channels = 8, .resolution = 16 },
  36 };
  37
  38 /**
  39  * struct ad7949_adc_chip - AD ADC chip
  40  * @lock: protects write sequences
  41  * @vref: regulator generating Vref
  42  * @iio_dev: reference to iio structure
  43  * @spi: reference to spi structure
  44  * @resolution: resolution of the chip
  45  * @cfg: copy of the configuration register
  46  * @current_channel: current channel in use
  47  * @buffer: buffer to send / receive data to / from device
  48  */
  49 struct ad7949_adc_chip {
  50         struct mutex lock;
  51         struct regulator *vref;
  52         struct iio_dev *indio_dev;
  53         struct spi_device *spi;
  54         u8 resolution;
  55         u16 cfg;
  56         unsigned int current_channel;
  57         u32 buffer ____cacheline_aligned;
  58 };
  59
  60 static bool ad7949_spi_cfg_is_read_back(struct ad7949_adc_chip *ad7949_adc)
  61 {
  62         if (!(ad7949_adc->cfg & AD7949_CFG_READ_BACK))
  63                 return true;
  64
  65         return false;
  66 }
  67
  68 static int ad7949_spi_bits_per_word(struct ad7949_adc_chip *ad7949_adc)
  69 {
  70         int ret = ad7949_adc->resolution;
  71
  72         if (ad7949_spi_cfg_is_read_back(ad7949_adc))
  73                 ret += AD7949_CFG_REG_SIZE_BITS;
  74
  75         return ret;
  76 }
  77
  78 static int ad7949_spi_write_cfg(struct ad7949_adc_chip *ad7949_adc, u16 val,
  79                                 u16 mask)
  80 {
  81         int ret;
  82         int bits_per_word = ad7949_spi_bits_per_word(ad7949_adc);
  83         int shift = bits_per_word - AD7949_CFG_REG_SIZE_BITS;
  84         struct spi_message msg;
  85         struct spi_transfer tx[] = {
  86                 {
  87                         .tx_buf = &ad7949_adc->buffer,
  88                         .len = 4,
  89                         .bits_per_word = bits_per_word,
  90                 },
  91         };
  92
  93         ad7949_adc->cfg = (val & mask) | (ad7949_adc->cfg & ~mask);
  94         ad7949_adc->buffer = ad7949_adc->cfg << shift;
  95         spi_message_init_with_transfers(&msg, tx, 1);
  96         ret = spi_sync(ad7949_adc->spi, &msg);
  97
  98         /*
  99          * This delay is to avoid a new request before the required time to
 100          * send a new command to the device
 101          */
 102         udelay(2);
 103         return ret;
 104 }
 105
 106 static int ad7949_spi_read_channel(struct ad7949_adc_chip *ad7949_adc, int *val,
 107                                    unsigned int channel)
 108 {
 109         int ret;
 110         int bits_per_word = ad7949_spi_bits_per_word(ad7949_adc);
 111         int mask = GENMASK(ad7949_adc->resolution, 0);
 112         struct spi_message msg;
 113         struct spi_transfer tx[] = {
 114                 {
 115                         .rx_buf = &ad7949_adc->buffer,
 116                         .len = 4,
 117                         .bits_per_word = bits_per_word,
 118                 },
 119         };
 120
 121         ret = ad7949_spi_write_cfg(ad7949_adc,
 122                                    channel << AD7949_OFFSET_CHANNEL_SEL,
 123                                    AD7949_MASK_CHANNEL_SEL);
 124         if (ret)
 125                 return ret;
 126
 127         ad7949_adc->buffer = 0;
 128         spi_message_init_with_transfers(&msg, tx, 1);
 129         ret = spi_sync(ad7949_adc->spi, &msg);
 130         if (ret)
 131                 return ret;
 132
 133         /*
 134          * This delay is to avoid a new request before the required time to
 135          * send a new command to the device
 136          */
 137         udelay(2);
 138
 139         ad7949_adc->current_channel = channel;
 140
 141         if (ad7949_spi_cfg_is_read_back(ad7949_adc))
 142                 *val = (ad7949_adc->buffer >> AD7949_CFG_REG_SIZE_BITS) & mask;
 143         else
 144                 *val = ad7949_adc->buffer & mask;
 145
 146         return 0;
 147 }
 148
 149 #define AD7949_ADC_CHANNEL(chan) {                              \
 150         .type = IIO_VOLTAGE,                                    \
 151         .indexed = 1,                                           \
 152         .channel = (chan),                                      \
 153         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),           \
 154         .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),   \
 155 }
 156
 157 static const struct iio_chan_spec ad7949_adc_channels[] = {
 158         AD7949_ADC_CHANNEL(0),
 159         AD7949_ADC_CHANNEL(1),
 160         AD7949_ADC_CHANNEL(2),
 161         AD7949_ADC_CHANNEL(3),
 162         AD7949_ADC_CHANNEL(4),
 163         AD7949_ADC_CHANNEL(5),
 164         AD7949_ADC_CHANNEL(6),
 165         AD7949_ADC_CHANNEL(7),
 166 };
 167
 168 static int ad7949_spi_read_raw(struct iio_dev *indio_dev,
 169                            struct iio_chan_spec const *chan,
 170                            int *val, int *val2, long mask)
 171 {
 172         struct ad7949_adc_chip *ad7949_adc = iio_priv(indio_dev);
 173         int ret;
 174
 175         if (!val)
 176                 return -EINVAL;
 177
 178         switch (mask) {
 179         case IIO_CHAN_INFO_RAW:
 180                 mutex_lock(&ad7949_adc->lock);
 181                 ret = ad7949_spi_read_channel(ad7949_adc, val, chan->channel);
 182                 mutex_unlock(&ad7949_adc->lock);
 183
 184                 if (ret < 0)
 185                         return ret;
 186
 187                 return IIO_VAL_INT;
 188
 189         case IIO_CHAN_INFO_SCALE:
 190                 ret = regulator_get_voltage(ad7949_adc->vref);
 191                 if (ret < 0)
 192                         return ret;
 193
 194                 *val = ret / 5000;
 195                 return IIO_VAL_INT;
 196         }
 197
 198         return -EINVAL;
 199 }
 200
 201 static int ad7949_spi_reg_access(struct iio_dev *indio_dev,
 202                         unsigned int reg, unsigned int writeval,
 203                         unsigned int *readval)
 204 {
 205         struct ad7949_adc_chip *ad7949_adc = iio_priv(indio_dev);
 206         int ret = 0;
 207
 208         if (readval)
 209                 *readval = ad7949_adc->cfg;
 210         else
 211                 ret = ad7949_spi_write_cfg(ad7949_adc,
 212                         writeval & AD7949_MASK_TOTAL, AD7949_MASK_TOTAL);
 213
 214         return ret;
 215 }
 216
 217 static const struct iio_info ad7949_spi_info = {
 218         .read_raw = ad7949_spi_read_raw,
 219         .debugfs_reg_access = ad7949_spi_reg_access,
 220 };
 221
 222 static int ad7949_spi_init(struct ad7949_adc_chip *ad7949_adc)
 223 {
 224         int ret;
 225         int val;
 226
 227         /* Sequencer disabled, CFG readback disabled, IN0 as default channel */
 228         ad7949_adc->current_channel = 0;
 229         ret = ad7949_spi_write_cfg(ad7949_adc, 0x3C79, AD7949_MASK_TOTAL);
 230
 231         /*
 232          * Do two dummy conversions to apply the first configuration setting.
 233          * Required only after the start up of the device.
 234          */
 235         ad7949_spi_read_channel(ad7949_adc, &val, ad7949_adc->current_channel);
 236         ad7949_spi_read_channel(ad7949_adc, &val, ad7949_adc->current_channel);
 237
 238         return ret;
 239 }
 240
 241 static int ad7949_spi_probe(struct spi_device *spi)
 242 {
 243         struct device *dev = &spi->dev;
 244         const struct ad7949_adc_spec *spec;
 245         struct ad7949_adc_chip *ad7949_adc;
 246         struct iio_dev *indio_dev;
 247         int ret;
 248
 249         indio_dev = devm_iio_device_alloc(dev, sizeof(*ad7949_adc));
 250         if (!indio_dev) {
 251                 dev_err(dev, "can not allocate iio device\n");
 252                 return -ENOMEM;
 253         }
 254
 255         indio_dev->dev.parent = dev;
 256         indio_dev->dev.of_node = dev->of_node;
 257         indio_dev->info = &ad7949_spi_info;
 258         indio_dev->name = spi_get_device_id(spi)->name;
 259         indio_dev->modes = INDIO_DIRECT_MODE;
 260         indio_dev->channels = ad7949_adc_channels;
 261         spi_set_drvdata(spi, indio_dev);
 262
 263         ad7949_adc = iio_priv(indio_dev);
 264         ad7949_adc->indio_dev = indio_dev;
 265         ad7949_adc->spi = spi;
 266
 267         spec = &ad7949_adc_spec[spi_get_device_id(spi)->driver_data];
 268         indio_dev->num_channels = spec->num_channels;
 269         ad7949_adc->resolution = spec->resolution;
 270
 271         ad7949_adc->vref = devm_regulator_get(dev, "vref");
 272         if (IS_ERR(ad7949_adc->vref)) {
 273                 dev_err(dev, "fail to request regulator\n");
 274                 return PTR_ERR(ad7949_adc->vref);
 275         }
 276
 277         ret = regulator_enable(ad7949_adc->vref);
 278         if (ret < 0) {
 279                 dev_err(dev, "fail to enable regulator\n");
 280                 return ret;
 281         }
 282
 283         mutex_init(&ad7949_adc->lock);
 284
 285         ret = ad7949_spi_init(ad7949_adc);
 286         if (ret) {
 287                 dev_err(dev, "enable to init this device: %d\n", ret);
 288                 goto err;
 289         }
 290
 291         ret = iio_device_register(indio_dev);
 292         if (ret) {
 293                 dev_err(dev, "fail to register iio device: %d\n", ret);
 294                 goto err;
 295         }
 296
 297         return 0;
 298
 299 err:
 300         mutex_destroy(&ad7949_adc->lock);
 301         regulator_disable(ad7949_adc->vref);
 302
 303         return ret;
 304 }
 305
 306 static int ad7949_spi_remove(struct spi_device *spi)
 307 {
 308         struct iio_dev *indio_dev = spi_get_drvdata(spi);
 309         struct ad7949_adc_chip *ad7949_adc = iio_priv(indio_dev);
 310
 311         iio_device_unregister(indio_dev);
 312         mutex_destroy(&ad7949_adc->lock);
 313         regulator_disable(ad7949_adc->vref);
 314
 315         return 0;
 316 }
 317
 318 static const struct of_device_id ad7949_spi_of_id[] = {
 319         { .compatible = "adi,ad7949" },
 320         { .compatible = "adi,ad7682" },
 321         { .compatible = "adi,ad7689" },
 322         { }
 323 };
 324 MODULE_DEVICE_TABLE(of, ad7949_spi_of_id);
 325
 326 static const struct spi_device_id ad7949_spi_id[] = {
 327         { "ad7949", ID_AD7949  },
 328         { "ad7682", ID_AD7682 },
 329         { "ad7689", ID_AD7689 },
 330         { }
 331 };
 332 MODULE_DEVICE_TABLE(spi, ad7949_spi_id);
 333
 334 static struct spi_driver ad7949_spi_driver = {
 335         .driver = {
 336                 .name           = "ad7949",
 337                 .of_match_table = ad7949_spi_of_id,
 338         },
 339         .probe    = ad7949_spi_probe,
 340         .remove   = ad7949_spi_remove,
 341         .id_table = ad7949_spi_id,
 342 };
 343 module_spi_driver(ad7949_spi_driver);
 344
 345 MODULE_AUTHOR("Charles-Antoine Couret <charles-antoine.couret@essensium.com>");
 346 MODULE_DESCRIPTION("Analog Devices 14/16-bit 8-channel ADC driver");
 347 MODULE_LICENSE("GPL v2");