drivers/iio/adc/ti_am335x_adc.c

   1 /*
   2  * TI ADC MFD driver
   3  *
   4  * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/err.h>
  18 #include <linux/module.h>
  19 #include <linux/slab.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/io.h>
  23 #include <linux/iio/iio.h>
  24 #include <linux/of.h>
  25 #include <linux/of_device.h>
  26 #include <linux/iio/machine.h>
  27 #include <linux/iio/driver.h>
  28
  29 #include <linux/mfd/ti_am335x_tscadc.h>
  30 #include <linux/iio/buffer.h>
  31 #include <linux/iio/kfifo_buf.h>
  32
  33 #include <linux/dmaengine.h>
  34 #include <linux/dma-mapping.h>
  35
  36 #define DMA_BUFFER_SIZE         SZ_2K
  37
  38 struct tiadc_dma {
  39         struct dma_slave_config conf;
  40         struct dma_chan         *chan;
  41         dma_addr_t              addr;
  42         dma_cookie_t            cookie;
  43         u8                      *buf;
  44         int                     current_period;
  45         int                     period_size;
  46         u8                      fifo_thresh;
  47 };
  48
  49 struct tiadc_device {
  50         struct ti_tscadc_dev *mfd_tscadc;
  51         struct tiadc_dma dma;
  52         struct mutex fifo1_lock; /* to protect fifo access */
  53         int channels;
  54         int total_ch_enabled;
  55         u8 channel_line[8];
  56         u8 channel_step[8];
  57         int buffer_en_ch_steps;
  58         u16 data[8];
  59         u32 open_delay[8], sample_delay[8], step_avg[8];
  60 };
  61
  62 static unsigned int tiadc_readl(struct tiadc_device *adc, unsigned int reg)
  63 {
  64         return readl(adc->mfd_tscadc->tscadc_base + reg);
  65 }
  66
  67 static void tiadc_writel(struct tiadc_device *adc, unsigned int reg,
  68                                         unsigned int val)
  69 {
  70         writel(val, adc->mfd_tscadc->tscadc_base + reg);
  71 }
  72
  73 static u32 get_adc_step_mask(struct tiadc_device *adc_dev)
  74 {
  75         u32 step_en;
  76
  77         step_en = ((1 << adc_dev->channels) - 1);
  78         step_en <<= TOTAL_STEPS - adc_dev->channels + 1;
  79         return step_en;
  80 }
  81
  82 static u32 get_adc_chan_step_mask(struct tiadc_device *adc_dev,
  83                 struct iio_chan_spec const *chan)
  84 {
  85         int i;
  86
  87         for (i = 0; i < ARRAY_SIZE(adc_dev->channel_step); i++) {
  88                 if (chan->channel == adc_dev->channel_line[i]) {
  89                         u32 step;
  90
  91                         step = adc_dev->channel_step[i];
  92                         /* +1 for the charger */
  93                         return 1 << (step + 1);
  94                 }
  95         }
  96         WARN_ON(1);
  97         return 0;
  98 }
  99
 100 static u32 get_adc_step_bit(struct tiadc_device *adc_dev, int chan)
 101 {
 102         return 1 << adc_dev->channel_step[chan];
 103 }
 104
 105 static void tiadc_step_config(struct iio_dev *indio_dev)
 106 {
 107         struct tiadc_device *adc_dev = iio_priv(indio_dev);
 108         struct device *dev = adc_dev->mfd_tscadc->dev;
 109         unsigned int stepconfig;
 110         int i, steps = 0;
 111
 112         /*
 113          * There are 16 configurable steps and 8 analog input
 114          * lines available which are shared between Touchscreen and ADC.
 115          *
 116          * Steps forwards i.e. from 0 towards 16 are used by ADC
 117          * depending on number of input lines needed.
 118          * Channel would represent which analog input
 119          * needs to be given to ADC to digitalize data.
 120          */
 121
 122
 123         for (i = 0; i < adc_dev->channels; i++) {
 124                 int chan;
 125
 126                 chan = adc_dev->channel_line[i];
 127
 128                 if (adc_dev->step_avg[i] > STEPCONFIG_AVG_16) {
 129                         dev_warn(dev, "chan %d step_avg truncating to %d\n",
 130                                  chan, STEPCONFIG_AVG_16);
 131                         adc_dev->step_avg[i] = STEPCONFIG_AVG_16;
 132                 }
 133
 134                 if (adc_dev->step_avg[i])
 135                         stepconfig =
 136                         STEPCONFIG_AVG(ffs(adc_dev->step_avg[i]) - 1) |
 137                         STEPCONFIG_FIFO1;
 138                 else
 139                         stepconfig = STEPCONFIG_FIFO1;
 140
 141                 if (iio_buffer_enabled(indio_dev))
 142                         stepconfig |= STEPCONFIG_MODE_SWCNT;
 143
 144                 tiadc_writel(adc_dev, REG_STEPCONFIG(steps),
 145                                 stepconfig | STEPCONFIG_INP(chan) |
 146                                 STEPCONFIG_INM_ADCREFM |
 147                                 STEPCONFIG_RFP_VREFP |
 148                                 STEPCONFIG_RFM_VREFN);
 149
 150                 if (adc_dev->open_delay[i] > STEPDELAY_OPEN_MASK) {
 151                         dev_warn(dev, "chan %d open delay truncating to 0x3FFFF\n",
 152                                  chan);
 153                         adc_dev->open_delay[i] = STEPDELAY_OPEN_MASK;
 154                 }
 155
 156                 if (adc_dev->sample_delay[i] > 0xFF) {
 157                         dev_warn(dev, "chan %d sample delay truncating to 0xFF\n",
 158                                  chan);
 159                         adc_dev->sample_delay[i] = 0xFF;
 160                 }
 161
 162                 tiadc_writel(adc_dev, REG_STEPDELAY(steps),
 163                                 STEPDELAY_OPEN(adc_dev->open_delay[i]) |
 164                                 STEPDELAY_SAMPLE(adc_dev->sample_delay[i]));
 165
 166                 adc_dev->channel_step[i] = steps;
 167                 steps++;
 168         }
 169 }
 170
 171 static irqreturn_t tiadc_irq_h(int irq, void *private)
 172 {
 173         struct iio_dev *indio_dev = private;
 174         struct tiadc_device *adc_dev = iio_priv(indio_dev);
 175         unsigned int status, config, adc_fsm;
 176         unsigned short count = 0;
 177
 178         status = tiadc_readl(adc_dev, REG_IRQSTATUS);
 179
 180         /*
 181          * ADC and touchscreen share the IRQ line.
 182          * FIFO0 interrupts are used by TSC. Handle FIFO1 IRQs here only
 183          */
 184         if (status & IRQENB_FIFO1OVRRUN) {
 185                 /* FIFO Overrun. Clear flag. Disable/Enable ADC to recover */
 186                 config = tiadc_readl(adc_dev, REG_CTRL);
 187                 config &= ~(CNTRLREG_TSCSSENB);
 188                 tiadc_writel(adc_dev, REG_CTRL, config);
 189                 tiadc_writel(adc_dev, REG_IRQSTATUS, IRQENB_FIFO1OVRRUN
 190                                 | IRQENB_FIFO1UNDRFLW | IRQENB_FIFO1THRES);
 191
 192                 /* wait for idle state.
 193                  * ADC needs to finish the current conversion
 194                  * before disabling the module
 195                  */
 196                 do {
 197                         adc_fsm = tiadc_readl(adc_dev, REG_ADCFSM);
 198                 } while (adc_fsm != 0x10 && count++ < 100);
 199
 200                 tiadc_writel(adc_dev, REG_CTRL, (config | CNTRLREG_TSCSSENB));
 201                 return IRQ_HANDLED;
 202         } else if (status & IRQENB_FIFO1THRES) {
 203                 /* Disable irq and wake worker thread */
 204                 tiadc_writel(adc_dev, REG_IRQCLR, IRQENB_FIFO1THRES);
 205                 return IRQ_WAKE_THREAD;
 206         }
 207
 208         return IRQ_NONE;
 209 }
 210
 211 static irqreturn_t tiadc_worker_h(int irq, void *private)
 212 {
 213         struct iio_dev *indio_dev = private;
 214         struct tiadc_device *adc_dev = iio_priv(indio_dev);
 215         int i, k, fifo1count, read;
 216         u16 *data = adc_dev->data;
 217
 218         fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT);
 219         for (k = 0; k < fifo1count; k = k + i) {
 220                 for (i = 0; i < (indio_dev->scan_bytes)/2; i++) {
 221                         read = tiadc_readl(adc_dev, REG_FIFO1);
 222                         data[i] = read & FIFOREAD_DATA_MASK;
 223                 }
 224                 iio_push_to_buffers(indio_dev, (u8 *) data);
 225         }
 226
 227         tiadc_writel(adc_dev, REG_IRQSTATUS, IRQENB_FIFO1THRES);
 228         tiadc_writel(adc_dev, REG_IRQENABLE, IRQENB_FIFO1THRES);
 229
 230         return IRQ_HANDLED;
 231 }
 232
 233 static void tiadc_dma_rx_complete(void *param)
 234 {
 235         struct iio_dev *indio_dev = param;
 236         struct tiadc_device *adc_dev = iio_priv(indio_dev);
 237         struct tiadc_dma *dma = &adc_dev->dma;
 238         u8 *data;
 239         int i;
 240
 241         data = dma->buf + dma->current_period * dma->period_size;
 242         dma->current_period = 1 - dma->current_period; /* swap the buffer ID */
 243
 244         for (i = 0; i < dma->period_size; i += indio_dev->scan_bytes) {
 245                 iio_push_to_buffers(indio_dev, data);
 246                 data += indio_dev->scan_bytes;
 247         }
 248 }
 249
 250 static int tiadc_start_dma(struct iio_dev *indio_dev)
 251 {
 252         struct tiadc_device *adc_dev = iio_priv(indio_dev);
 253         struct tiadc_dma *dma = &adc_dev->dma;
 254         struct dma_async_tx_descriptor *desc;
 255
 256         dma->current_period = 0; /* We start to fill period 0 */
 257         /*
 258          * Make the fifo thresh as the multiple of total number of
 259          * channels enabled, so make sure that cyclic DMA period
 260          * length is also a multiple of total number of channels
 261          * enabled. This ensures that no invalid data is reported
 262          * to the stack via iio_push_to_buffers().
 263          */
 264         dma->fifo_thresh = rounddown(FIFO1_THRESHOLD + 1,
 265                                      adc_dev->total_ch_enabled) - 1;
 266         /* Make sure that period length is multiple of fifo thresh level */
 267         dma->period_size = rounddown(DMA_BUFFER_SIZE / 2,
 268                                     (dma->fifo_thresh + 1) * sizeof(u16));
 269
 270         dma->conf.src_maxburst = dma->fifo_thresh + 1;
 271         dmaengine_slave_config(dma->chan, &dma->conf);
 272
 273         desc = dmaengine_prep_dma_cyclic(dma->chan, dma->addr,
 274                                          dma->period_size * 2,
 275                                          dma->period_size, DMA_DEV_TO_MEM,
 276                                          DMA_PREP_INTERRUPT);
 277         if (!desc)
 278                 return -EBUSY;
 279
 280         desc->callback = tiadc_dma_rx_complete;
 281         desc->callback_param = indio_dev;
 282
 283         dma->cookie = dmaengine_submit(desc);
 284
 285         dma_async_issue_pending(dma->chan);
 286
 287         tiadc_writel(adc_dev, REG_FIFO1THR, dma->fifo_thresh);
 288         tiadc_writel(adc_dev, REG_DMA1REQ, dma->fifo_thresh);
 289         tiadc_writel(adc_dev, REG_DMAENABLE_SET, DMA_FIFO1);
 290
 291         return 0;
 292 }
 293
 294 static int tiadc_buffer_preenable(struct iio_dev *indio_dev)
 295 {
 296         struct tiadc_device *adc_dev = iio_priv(indio_dev);
 297         int i, fifo1count, read;
 298
 299         tiadc_writel(adc_dev, REG_IRQCLR, (IRQENB_FIFO1THRES |
 300                                 IRQENB_FIFO1OVRRUN |
 301                                 IRQENB_FIFO1UNDRFLW));
 302
 303         /* Flush FIFO. Needed in corner cases in simultaneous tsc/adc use */
 304         fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT);
 305         for (i = 0; i < fifo1count; i++)
 306                 read = tiadc_readl(adc_dev, REG_FIFO1);
 307
 308         return 0;
 309 }
 310
 311 static int tiadc_buffer_postenable(struct iio_dev *indio_dev)
 312 {
 313         struct tiadc_device *adc_dev = iio_priv(indio_dev);
 314         struct tiadc_dma *dma = &adc_dev->dma;
 315         unsigned int irq_enable;
 316         unsigned int enb = 0;
 317         u8 bit;
 318
 319         tiadc_step_config(indio_dev);
 320         for_each_set_bit(bit, indio_dev->active_scan_mask, adc_dev->channels) {
 321                 enb |= (get_adc_step_bit(adc_dev, bit) << 1);
 322                 adc_dev->total_ch_enabled++;
 323         }
 324         adc_dev->buffer_en_ch_steps = enb;
 325
 326         if (dma->chan)
 327                 tiadc_start_dma(indio_dev);
 328
 329         am335x_tsc_se_set_cache(adc_dev->mfd_tscadc, enb);
 330
 331         tiadc_writel(adc_dev,  REG_IRQSTATUS, IRQENB_FIFO1THRES
 332                                 | IRQENB_FIFO1OVRRUN | IRQENB_FIFO1UNDRFLW);
 333
 334         irq_enable = IRQENB_FIFO1OVRRUN;
 335         if (!dma->chan)
 336                 irq_enable |= IRQENB_FIFO1THRES;
 337         tiadc_writel(adc_dev,  REG_IRQENABLE, irq_enable);
 338
 339         return 0;
 340 }
 341
 342 static int tiadc_buffer_predisable(struct iio_dev *indio_dev)
 343 {
 344         struct tiadc_device *adc_dev = iio_priv(indio_dev);
 345         struct tiadc_dma *dma = &adc_dev->dma;
 346         int fifo1count, i, read;
 347
 348         tiadc_writel(adc_dev, REG_IRQCLR, (IRQENB_FIFO1THRES |
 349                                 IRQENB_FIFO1OVRRUN | IRQENB_FIFO1UNDRFLW));
 350         am335x_tsc_se_clr(adc_dev->mfd_tscadc, adc_dev->buffer_en_ch_steps);
 351         adc_dev->buffer_en_ch_steps = 0;
 352         adc_dev->total_ch_enabled = 0;
 353         if (dma->chan) {
 354                 tiadc_writel(adc_dev, REG_DMAENABLE_CLEAR, 0x2);
 355                 dmaengine_terminate_async(dma->chan);
 356         }
 357
 358         /* Flush FIFO of leftover data in the time it takes to disable adc */
 359         fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT);
 360         for (i = 0; i < fifo1count; i++)
 361                 read = tiadc_readl(adc_dev, REG_FIFO1);
 362
 363         return 0;
 364 }
 365
 366 static int tiadc_buffer_postdisable(struct iio_dev *indio_dev)
 367 {
 368         tiadc_step_config(indio_dev);
 369
 370         return 0;
 371 }
 372
 373 static const struct iio_buffer_setup_ops tiadc_buffer_setup_ops = {
 374         .preenable = &tiadc_buffer_preenable,
 375         .postenable = &tiadc_buffer_postenable,
 376         .predisable = &tiadc_buffer_predisable,
 377         .postdisable = &tiadc_buffer_postdisable,
 378 };
 379
 380 static int tiadc_iio_buffered_hardware_setup(struct iio_dev *indio_dev,
 381         irqreturn_t (*pollfunc_bh)(int irq, void *p),
 382         irqreturn_t (*pollfunc_th)(int irq, void *p),
 383         int irq,
 384         unsigned long flags,
 385         const struct iio_buffer_setup_ops *setup_ops)
 386 {
 387         struct iio_buffer *buffer;
 388         int ret;
 389
 390         buffer = iio_kfifo_allocate();
 391         if (!buffer)
 392                 return -ENOMEM;
 393
 394         iio_device_attach_buffer(indio_dev, buffer);
 395
 396         ret = request_threaded_irq(irq, pollfunc_th, pollfunc_bh,
 397                                 flags, indio_dev->name, indio_dev);
 398         if (ret)
 399                 goto error_kfifo_free;
 400
 401         indio_dev->setup_ops = setup_ops;
 402         indio_dev->modes |= INDIO_BUFFER_SOFTWARE;
 403
 404         return 0;
 405
 406 error_kfifo_free:
 407         iio_kfifo_free(indio_dev->buffer);
 408         return ret;
 409 }
 410
 411 static void tiadc_iio_buffered_hardware_remove(struct iio_dev *indio_dev)
 412 {
 413         struct tiadc_device *adc_dev = iio_priv(indio_dev);
 414
 415         free_irq(adc_dev->mfd_tscadc->irq, indio_dev);
 416         iio_kfifo_free(indio_dev->buffer);
 417 }
 418
 419
 420 static const char * const chan_name_ain[] = {
 421         "AIN0",
 422         "AIN1",
 423         "AIN2",
 424         "AIN3",
 425         "AIN4",
 426         "AIN5",
 427         "AIN6",
 428         "AIN7",
 429 };
 430
 431 static int tiadc_channel_init(struct iio_dev *indio_dev, int channels)
 432 {
 433         struct tiadc_device *adc_dev = iio_priv(indio_dev);
 434         struct iio_chan_spec *chan_array;
 435         struct iio_chan_spec *chan;
 436         int i;
 437
 438         indio_dev->num_channels = channels;
 439         chan_array = kcalloc(channels, sizeof(*chan_array), GFP_KERNEL);
 440         if (chan_array == NULL)
 441                 return -ENOMEM;
 442
 443         chan = chan_array;
 444         for (i = 0; i < channels; i++, chan++) {
 445
 446                 chan->type = IIO_VOLTAGE;
 447                 chan->indexed = 1;
 448                 chan->channel = adc_dev->channel_line[i];
 449                 chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
 450                 chan->datasheet_name = chan_name_ain[chan->channel];
 451                 chan->scan_index = i;
 452                 chan->scan_type.sign = 'u';
 453                 chan->scan_type.realbits = 12;
 454                 chan->scan_type.storagebits = 16;
 455         }
 456
 457         indio_dev->channels = chan_array;
 458
 459         return 0;
 460 }
 461
 462 static void tiadc_channels_remove(struct iio_dev *indio_dev)
 463 {
 464         kfree(indio_dev->channels);
 465 }
 466
 467 static int tiadc_read_raw(struct iio_dev *indio_dev,
 468                 struct iio_chan_spec const *chan,
 469                 int *val, int *val2, long mask)
 470 {
 471         struct tiadc_device *adc_dev = iio_priv(indio_dev);
 472         int ret = IIO_VAL_INT;
 473         int i, map_val;
 474         unsigned int fifo1count, read, stepid;
 475         bool found = false;
 476         u32 step_en;
 477         unsigned long timeout;
 478
 479         if (iio_buffer_enabled(indio_dev))
 480                 return -EBUSY;
 481
 482         step_en = get_adc_chan_step_mask(adc_dev, chan);
 483         if (!step_en)
 484                 return -EINVAL;
 485
 486         mutex_lock(&adc_dev->fifo1_lock);
 487         fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT);
 488         while (fifo1count--)
 489                 tiadc_readl(adc_dev, REG_FIFO1);
 490
 491         am335x_tsc_se_set_once(adc_dev->mfd_tscadc, step_en);
 492
 493         timeout = jiffies + msecs_to_jiffies
 494                                 (IDLE_TIMEOUT * adc_dev->channels);
 495         /* Wait for Fifo threshold interrupt */
 496         while (1) {
 497                 fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT);
 498                 if (fifo1count)
 499                         break;
 500
 501                 if (time_after(jiffies, timeout)) {
 502                         am335x_tsc_se_adc_done(adc_dev->mfd_tscadc);
 503                         ret = -EAGAIN;
 504                         goto err_unlock;
 505                 }
 506         }
 507         map_val = adc_dev->channel_step[chan->scan_index];
 508
 509         /*
 510          * We check the complete FIFO. We programmed just one entry but in case
 511          * something went wrong we left empty handed (-EAGAIN previously) and
 512          * then the value apeared somehow in the FIFO we would have two entries.
 513          * Therefore we read every item and keep only the latest version of the
 514          * requested channel.
 515          */
 516         for (i = 0; i < fifo1count; i++) {
 517                 read = tiadc_readl(adc_dev, REG_FIFO1);
 518                 stepid = read & FIFOREAD_CHNLID_MASK;
 519                 stepid = stepid >> 0x10;
 520
 521                 if (stepid == map_val) {
 522                         read = read & FIFOREAD_DATA_MASK;
 523                         found = true;
 524                         *val = (u16) read;
 525                 }
 526         }
 527         am335x_tsc_se_adc_done(adc_dev->mfd_tscadc);
 528
 529         if (!found)
 530                 ret =  -EBUSY;
 531
 532 err_unlock:
 533         mutex_unlock(&adc_dev->fifo1_lock);
 534         return ret;
 535 }
 536
 537 static const struct iio_info tiadc_info = {
 538         .read_raw = &tiadc_read_raw,
 539 };
 540
 541 static int tiadc_request_dma(struct platform_device *pdev,
 542                              struct tiadc_device *adc_dev)
 543 {
 544         struct tiadc_dma        *dma = &adc_dev->dma;
 545         dma_cap_mask_t          mask;
 546
 547         /* Default slave configuration parameters */
 548         dma->conf.direction = DMA_DEV_TO_MEM;
 549         dma->conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 550         dma->conf.src_addr = adc_dev->mfd_tscadc->tscadc_phys_base + REG_FIFO1;
 551
 552         dma_cap_zero(mask);
 553         dma_cap_set(DMA_CYCLIC, mask);
 554
 555         /* Get a channel for RX */
 556         dma->chan = dma_request_chan(adc_dev->mfd_tscadc->dev, "fifo1");
 557         if (IS_ERR(dma->chan)) {
 558                 int ret = PTR_ERR(dma->chan);
 559
 560                 dma->chan = NULL;
 561                 return ret;
 562         }
 563
 564         /* RX buffer */
 565         dma->buf = dma_alloc_coherent(dma->chan->device->dev, DMA_BUFFER_SIZE,
 566                                       &dma->addr, GFP_KERNEL);
 567         if (!dma->buf)
 568                 goto err;
 569
 570         return 0;
 571 err:
 572         dma_release_channel(dma->chan);
 573         return -ENOMEM;
 574 }
 575
 576 static int tiadc_parse_dt(struct platform_device *pdev,
 577                           struct tiadc_device *adc_dev)
 578 {
 579         struct device_node *node = pdev->dev.of_node;
 580         struct property *prop;
 581         const __be32 *cur;
 582         int channels = 0;
 583         u32 val;
 584
 585         of_property_for_each_u32(node, "ti,adc-channels", prop, cur, val) {
 586                 adc_dev->channel_line[channels] = val;
 587
 588                 /* Set Default values for optional DT parameters */
 589                 adc_dev->open_delay[channels] = STEPCONFIG_OPENDLY;
 590                 adc_dev->sample_delay[channels] = STEPCONFIG_SAMPLEDLY;
 591                 adc_dev->step_avg[channels] = 16;
 592
 593                 channels++;
 594         }
 595
 596         of_property_read_u32_array(node, "ti,chan-step-avg",
 597                                    adc_dev->step_avg, channels);
 598         of_property_read_u32_array(node, "ti,chan-step-opendelay",
 599                                    adc_dev->open_delay, channels);
 600         of_property_read_u32_array(node, "ti,chan-step-sampledelay",
 601                                    adc_dev->sample_delay, channels);
 602
 603         adc_dev->channels = channels;
 604         return 0;
 605 }
 606
 607 static int tiadc_probe(struct platform_device *pdev)
 608 {
 609         struct iio_dev          *indio_dev;
 610         struct tiadc_device     *adc_dev;
 611         struct device_node      *node = pdev->dev.of_node;
 612         int                     err;
 613
 614         if (!node) {
 615                 dev_err(&pdev->dev, "Could not find valid DT data.\n");
 616                 return -EINVAL;
 617         }
 618
 619         indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc_dev));
 620         if (indio_dev == NULL) {
 621                 dev_err(&pdev->dev, "failed to allocate iio device\n");
 622                 return -ENOMEM;
 623         }
 624         adc_dev = iio_priv(indio_dev);
 625
 626         adc_dev->mfd_tscadc = ti_tscadc_dev_get(pdev);
 627         tiadc_parse_dt(pdev, adc_dev);
 628
 629         indio_dev->dev.parent = &pdev->dev;
 630         indio_dev->name = dev_name(&pdev->dev);
 631         indio_dev->modes = INDIO_DIRECT_MODE;
 632         indio_dev->info = &tiadc_info;
 633
 634         tiadc_step_config(indio_dev);
 635         tiadc_writel(adc_dev, REG_FIFO1THR, FIFO1_THRESHOLD);
 636         mutex_init(&adc_dev->fifo1_lock);
 637
 638         err = tiadc_channel_init(indio_dev, adc_dev->channels);
 639         if (err < 0)
 640                 return err;
 641
 642         err = tiadc_iio_buffered_hardware_setup(indio_dev,
 643                 &tiadc_worker_h,
 644                 &tiadc_irq_h,
 645                 adc_dev->mfd_tscadc->irq,
 646                 IRQF_SHARED,
 647                 &tiadc_buffer_setup_ops);
 648
 649         if (err)
 650                 goto err_free_channels;
 651
 652         err = iio_device_register(indio_dev);
 653         if (err)
 654                 goto err_buffer_unregister;
 655
 656         platform_set_drvdata(pdev, indio_dev);
 657
 658         err = tiadc_request_dma(pdev, adc_dev);
 659         if (err && err == -EPROBE_DEFER)
 660                 goto err_dma;
 661
 662         return 0;
 663
 664 err_dma:
 665         iio_device_unregister(indio_dev);
 666 err_buffer_unregister:
 667         tiadc_iio_buffered_hardware_remove(indio_dev);
 668 err_free_channels:
 669         tiadc_channels_remove(indio_dev);
 670         return err;
 671 }
 672
 673 static int tiadc_remove(struct platform_device *pdev)
 674 {
 675         struct iio_dev *indio_dev = platform_get_drvdata(pdev);
 676         struct tiadc_device *adc_dev = iio_priv(indio_dev);
 677         struct tiadc_dma *dma = &adc_dev->dma;
 678         u32 step_en;
 679
 680         if (dma->chan) {
 681                 dma_free_coherent(dma->chan->device->dev, DMA_BUFFER_SIZE,
 682                                   dma->buf, dma->addr);
 683                 dma_release_channel(dma->chan);
 684         }
 685         iio_device_unregister(indio_dev);
 686         tiadc_iio_buffered_hardware_remove(indio_dev);
 687         tiadc_channels_remove(indio_dev);
 688
 689         step_en = get_adc_step_mask(adc_dev);
 690         am335x_tsc_se_clr(adc_dev->mfd_tscadc, step_en);
 691
 692         return 0;
 693 }
 694
 695 static int __maybe_unused tiadc_suspend(struct device *dev)
 696 {
 697         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 698         struct tiadc_device *adc_dev = iio_priv(indio_dev);
 699         unsigned int idle;
 700
 701         idle = tiadc_readl(adc_dev, REG_CTRL);
 702         idle &= ~(CNTRLREG_TSCSSENB);
 703         tiadc_writel(adc_dev, REG_CTRL, (idle |
 704                         CNTRLREG_POWERDOWN));
 705
 706         return 0;
 707 }
 708
 709 static int __maybe_unused tiadc_resume(struct device *dev)
 710 {
 711         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 712         struct tiadc_device *adc_dev = iio_priv(indio_dev);
 713         unsigned int restore;
 714
 715         /* Make sure ADC is powered up */
 716         restore = tiadc_readl(adc_dev, REG_CTRL);
 717         restore &= ~(CNTRLREG_POWERDOWN);
 718         tiadc_writel(adc_dev, REG_CTRL, restore);
 719
 720         tiadc_step_config(indio_dev);
 721         am335x_tsc_se_set_cache(adc_dev->mfd_tscadc,
 722                         adc_dev->buffer_en_ch_steps);
 723         return 0;
 724 }
 725
 726 static SIMPLE_DEV_PM_OPS(tiadc_pm_ops, tiadc_suspend, tiadc_resume);
 727
 728 static const struct of_device_id ti_adc_dt_ids[] = {
 729         { .compatible = "ti,am3359-adc", },
 730         { }
 731 };
 732 MODULE_DEVICE_TABLE(of, ti_adc_dt_ids);
 733
 734 static struct platform_driver tiadc_driver = {
 735         .driver = {
 736                 .name   = "TI-am335x-adc",
 737                 .pm     = &tiadc_pm_ops,
 738                 .of_match_table = ti_adc_dt_ids,
 739         },
 740         .probe  = tiadc_probe,
 741         .remove = tiadc_remove,
 742 };
 743 module_platform_driver(tiadc_driver);
 744
 745 MODULE_DESCRIPTION("TI ADC controller driver");
 746 MODULE_AUTHOR("Rachna Patil <rachna@ti.com>");
 747 MODULE_LICENSE("GPL");