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Merge tag 'for-linus-20190706' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / iio / gyro / fxas21002c_core.c
blob89d2bb2282eac9c442a8904928d7e1f6a0ef3162
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for NXP FXAS21002C Gyroscope - Core
4 *
5 * Copyright (C) 2019 Linaro Ltd.
6 */
7
8 #include <linux/interrupt.h>
9 #include <linux/module.h>
10 #include <linux/of_irq.h>
11 #include <linux/pm.h>
12 #include <linux/pm_runtime.h>
13 #include <linux/regmap.h>
14 #include <linux/regulator/consumer.h>
15
16 #include <linux/iio/events.h>
17 #include <linux/iio/iio.h>
18 #include <linux/iio/buffer.h>
19 #include <linux/iio/sysfs.h>
20 #include <linux/iio/trigger.h>
21 #include <linux/iio/trigger_consumer.h>
22 #include <linux/iio/triggered_buffer.h>
23
24 #include "fxas21002c.h"
25
26 #define FXAS21002C_CHIP_ID_1 0xD6
27 #define FXAS21002C_CHIP_ID_2 0xD7
28
29 enum fxas21002c_mode_state {
30 FXAS21002C_MODE_STANDBY,
31 FXAS21002C_MODE_READY,
32 FXAS21002C_MODE_ACTIVE,
33 };
34
35 #define FXAS21002C_STANDBY_ACTIVE_TIME_MS 62
36 #define FXAS21002C_READY_ACTIVE_TIME_MS 7
37
38 #define FXAS21002C_ODR_LIST_MAX 10
39
40 #define FXAS21002C_SCALE_FRACTIONAL 32
41 #define FXAS21002C_RANGE_LIMIT_DOUBLE 2000
42
43 #define FXAS21002C_AXIS_TO_REG(axis) (FXAS21002C_REG_OUT_X_MSB + ((axis) * 2))
44
45 static const int fxas21002c_odr_values[] = {
46 800, 400, 200, 100, 50, 25, 12, 12
47 };
48
49 /*
50 * These values are taken from the low-pass filter cutoff frequency calculated
51 * ODR * 0.lpf_values. So, for ODR = 800Hz with a lpf value = 0.32
52 * => LPF cutoff frequency = 800 * 0.32 = 256 Hz
53 */
54 static const int fxas21002c_lpf_values[] = {
55 32, 16, 8
56 };
57
58 /*
59 * These values are taken from the high-pass filter cutoff frequency calculated
60 * ODR * 0.0hpf_values. So, for ODR = 800Hz with a hpf value = 0.018750
61 * => HPF cutoff frequency = 800 * 0.018750 = 15 Hz
62 */
63 static const int fxas21002c_hpf_values[] = {
64 18750, 9625, 4875, 2475
65 };
66
67 static const int fxas21002c_range_values[] = {
68 4000, 2000, 1000, 500, 250
69 };
70
71 struct fxas21002c_data {
72 u8 chip_id;
73 enum fxas21002c_mode_state mode;
74 enum fxas21002c_mode_state prev_mode;
75
76 struct mutex lock; /* serialize data access */
77 struct regmap *regmap;
78 struct regmap_field *regmap_fields[F_MAX_FIELDS];
79 struct iio_trigger *dready_trig;
80 s64 timestamp;
81 int irq;
82
83 struct regulator *vdd;
84 struct regulator *vddio;
85
86 /*
87 * DMA (thus cache coherency maintenance) requires the
88 * transfer buffers to live in their own cache lines.
89 */
90 s16 buffer[8] ____cacheline_aligned;
91 };
92
93 enum fxas21002c_channel_index {
94 CHANNEL_SCAN_INDEX_X,
95 CHANNEL_SCAN_INDEX_Y,
96 CHANNEL_SCAN_INDEX_Z,
97 CHANNEL_SCAN_MAX,
98 };
99
100 static int fxas21002c_odr_hz_from_value(struct fxas21002c_data *data, u8 value)
101 {
102 int odr_value_max = ARRAY_SIZE(fxas21002c_odr_values) - 1;
103
104 value = min_t(u8, value, odr_value_max);
105
106 return fxas21002c_odr_values[value];
107 }
108
109 static int fxas21002c_odr_value_from_hz(struct fxas21002c_data *data,
110 unsigned int hz)
111 {
112 int odr_table_size = ARRAY_SIZE(fxas21002c_odr_values);
113 int i;
114
115 for (i = 0; i < odr_table_size; i++)
116 if (fxas21002c_odr_values[i] == hz)
117 return i;
118
119 return -EINVAL;
120 }
121
122 static int fxas21002c_lpf_bw_from_value(struct fxas21002c_data *data, u8 value)
123 {
124 int lpf_value_max = ARRAY_SIZE(fxas21002c_lpf_values) - 1;
125
126 value = min_t(u8, value, lpf_value_max);
127
128 return fxas21002c_lpf_values[value];
129 }
130
131 static int fxas21002c_lpf_value_from_bw(struct fxas21002c_data *data,
132 unsigned int hz)
133 {
134 int lpf_table_size = ARRAY_SIZE(fxas21002c_lpf_values);
135 int i;
136
137 for (i = 0; i < lpf_table_size; i++)
138 if (fxas21002c_lpf_values[i] == hz)
139 return i;
140
141 return -EINVAL;
142 }
143
144 static int fxas21002c_hpf_sel_from_value(struct fxas21002c_data *data, u8 value)
145 {
146 int hpf_value_max = ARRAY_SIZE(fxas21002c_hpf_values) - 1;
147
148 value = min_t(u8, value, hpf_value_max);
149
150 return fxas21002c_hpf_values[value];
151 }
152
153 static int fxas21002c_hpf_value_from_sel(struct fxas21002c_data *data,
154 unsigned int hz)
155 {
156 int hpf_table_size = ARRAY_SIZE(fxas21002c_hpf_values);
157 int i;
158
159 for (i = 0; i < hpf_table_size; i++)
160 if (fxas21002c_hpf_values[i] == hz)
161 return i;
162
163 return -EINVAL;
164 }
165
166 static int fxas21002c_range_fs_from_value(struct fxas21002c_data *data,
167 u8 value)
168 {
169 int range_value_max = ARRAY_SIZE(fxas21002c_range_values) - 1;
170 unsigned int fs_double;
171 int ret;
172
173 /* We need to check if FS_DOUBLE is enabled to offset the value */
174 ret = regmap_field_read(data->regmap_fields[F_FS_DOUBLE], &fs_double);
175 if (ret < 0)
176 return ret;
177
178 if (!fs_double)
179 value += 1;
180
181 value = min_t(u8, value, range_value_max);
182
183 return fxas21002c_range_values[value];
184 }
185
186 static int fxas21002c_range_value_from_fs(struct fxas21002c_data *data,
187 unsigned int range)
188 {
189 int range_table_size = ARRAY_SIZE(fxas21002c_range_values);
190 bool found = false;
191 int fs_double = 0;
192 int ret;
193 int i;
194
195 for (i = 0; i < range_table_size; i++)
196 if (fxas21002c_range_values[i] == range) {
197 found = true;
198 break;
199 }
200
201 if (!found)
202 return -EINVAL;
203
204 if (range > FXAS21002C_RANGE_LIMIT_DOUBLE)
205 fs_double = 1;
206
207 ret = regmap_field_write(data->regmap_fields[F_FS_DOUBLE], fs_double);
208 if (ret < 0)
209 return ret;
210
211 return i;
212 }
213
214 static int fxas21002c_mode_get(struct fxas21002c_data *data)
215 {
216 unsigned int active;
217 unsigned int ready;
218 int ret;
219
220 ret = regmap_field_read(data->regmap_fields[F_ACTIVE], &active);
221 if (ret < 0)
222 return ret;
223 if (active)
224 return FXAS21002C_MODE_ACTIVE;
225
226 ret = regmap_field_read(data->regmap_fields[F_READY], &ready);
227 if (ret < 0)
228 return ret;
229 if (ready)
230 return FXAS21002C_MODE_READY;
231
232 return FXAS21002C_MODE_STANDBY;
233 }
234
235 static int fxas21002c_mode_set(struct fxas21002c_data *data,
236 enum fxas21002c_mode_state mode)
237 {
238 int ret;
239
240 if (mode == data->mode)
241 return 0;
242
243 if (mode == FXAS21002C_MODE_READY)
244 ret = regmap_field_write(data->regmap_fields[F_READY], 1);
245 else
246 ret = regmap_field_write(data->regmap_fields[F_READY], 0);
247 if (ret < 0)
248 return ret;
249
250 if (mode == FXAS21002C_MODE_ACTIVE)
251 ret = regmap_field_write(data->regmap_fields[F_ACTIVE], 1);
252 else
253 ret = regmap_field_write(data->regmap_fields[F_ACTIVE], 0);
254 if (ret < 0)
255 return ret;
256
257 /* if going to active wait the setup times */
258 if (mode == FXAS21002C_MODE_ACTIVE &&
259 data->mode == FXAS21002C_MODE_STANDBY)
260 msleep_interruptible(FXAS21002C_STANDBY_ACTIVE_TIME_MS);
261
262 if (data->mode == FXAS21002C_MODE_READY)
263 msleep_interruptible(FXAS21002C_READY_ACTIVE_TIME_MS);
264
265 data->prev_mode = data->mode;
266 data->mode = mode;
267
268 return ret;
269 }
270
271 static int fxas21002c_write(struct fxas21002c_data *data,
272 enum fxas21002c_fields field, int bits)
273 {
274 int actual_mode;
275 int ret;
276
277 mutex_lock(&data->lock);
278
279 actual_mode = fxas21002c_mode_get(data);
280 if (actual_mode < 0) {
281 ret = actual_mode;
282 goto out_unlock;
283 }
284
285 ret = fxas21002c_mode_set(data, FXAS21002C_MODE_READY);
286 if (ret < 0)
287 goto out_unlock;
288
289 ret = regmap_field_write(data->regmap_fields[field], bits);
290 if (ret < 0)
291 goto out_unlock;
292
293 ret = fxas21002c_mode_set(data, data->prev_mode);
294
295 out_unlock:
296 mutex_unlock(&data->lock);
297
298 return ret;
299 }
300
301 static int fxas21002c_pm_get(struct fxas21002c_data *data)
302 {
303 struct device *dev = regmap_get_device(data->regmap);
304 int ret;
305
306 ret = pm_runtime_get_sync(dev);
307 if (ret < 0)
308 pm_runtime_put_noidle(dev);
309
310 return ret;
311 }
312
313 static int fxas21002c_pm_put(struct fxas21002c_data *data)
314 {
315 struct device *dev = regmap_get_device(data->regmap);
316
317 pm_runtime_mark_last_busy(dev);
318
319 return pm_runtime_put_autosuspend(dev);
320 }
321
322 static int fxas21002c_temp_get(struct fxas21002c_data *data, int *val)
323 {
324 struct device *dev = regmap_get_device(data->regmap);
325 unsigned int temp;
326 int ret;
327
328 mutex_lock(&data->lock);
329 ret = fxas21002c_pm_get(data);
330 if (ret < 0)
331 goto data_unlock;
332
333 ret = regmap_field_read(data->regmap_fields[F_TEMP], &temp);
334 if (ret < 0) {
335 dev_err(dev, "failed to read temp: %d\n", ret);
336 goto data_unlock;
337 }
338
339 *val = sign_extend32(temp, 7);
340
341 ret = fxas21002c_pm_put(data);
342 if (ret < 0)
343 goto data_unlock;
344
345 ret = IIO_VAL_INT;
346
347 data_unlock:
348 mutex_unlock(&data->lock);
349
350 return ret;
351 }
352
353 static int fxas21002c_axis_get(struct fxas21002c_data *data,
354 int index, int *val)
355 {
356 struct device *dev = regmap_get_device(data->regmap);
357 __be16 axis_be;
358 int ret;
359
360 mutex_lock(&data->lock);
361 ret = fxas21002c_pm_get(data);
362 if (ret < 0)
363 goto data_unlock;
364
365 ret = regmap_bulk_read(data->regmap, FXAS21002C_AXIS_TO_REG(index),
366 &axis_be, sizeof(axis_be));
367 if (ret < 0) {
368 dev_err(dev, "failed to read axis: %d: %d\n", index, ret);
369 goto data_unlock;
370 }
371
372 *val = sign_extend32(be16_to_cpu(axis_be), 15);
373
374 ret = fxas21002c_pm_put(data);
375 if (ret < 0)
376 goto data_unlock;
377
378 ret = IIO_VAL_INT;
379
380 data_unlock:
381 mutex_unlock(&data->lock);
382
383 return ret;
384 }
385
386 static int fxas21002c_odr_get(struct fxas21002c_data *data, int *odr)
387 {
388 unsigned int odr_bits;
389 int ret;
390
391 mutex_lock(&data->lock);
392 ret = regmap_field_read(data->regmap_fields[F_DR], &odr_bits);
393 if (ret < 0)
394 goto data_unlock;
395
396 *odr = fxas21002c_odr_hz_from_value(data, odr_bits);
397
398 ret = IIO_VAL_INT;
399
400 data_unlock:
401 mutex_unlock(&data->lock);
402
403 return ret;
404 }
405
406 static int fxas21002c_odr_set(struct fxas21002c_data *data, int odr)
407 {
408 int odr_bits;
409
410 odr_bits = fxas21002c_odr_value_from_hz(data, odr);
411 if (odr_bits < 0)
412 return odr_bits;
413
414 return fxas21002c_write(data, F_DR, odr_bits);
415 }
416
417 static int fxas21002c_lpf_get(struct fxas21002c_data *data, int *val2)
418 {
419 unsigned int bw_bits;
420 int ret;
421
422 mutex_lock(&data->lock);
423 ret = regmap_field_read(data->regmap_fields[F_BW], &bw_bits);
424 if (ret < 0)
425 goto data_unlock;
426
427 *val2 = fxas21002c_lpf_bw_from_value(data, bw_bits) * 10000;
428
429 ret = IIO_VAL_INT_PLUS_MICRO;
430
431 data_unlock:
432 mutex_unlock(&data->lock);
433
434 return ret;
435 }
436
437 static int fxas21002c_lpf_set(struct fxas21002c_data *data, int bw)
438 {
439 int bw_bits;
440 int odr;
441 int ret;
442
443 bw_bits = fxas21002c_lpf_value_from_bw(data, bw);
444 if (bw_bits < 0)
445 return bw_bits;
446
447 /*
448 * From table 33 of the device spec, for ODR = 25Hz and 12.5 value 0.08
449 * is not allowed and for ODR = 12.5 value 0.16 is also not allowed
450 */
451 ret = fxas21002c_odr_get(data, &odr);
452 if (ret < 0)
453 return -EINVAL;
454
455 if ((odr == 25 && bw_bits > 0x01) || (odr == 12 && bw_bits > 0))
456 return -EINVAL;
457
458 return fxas21002c_write(data, F_BW, bw_bits);
459 }
460
461 static int fxas21002c_hpf_get(struct fxas21002c_data *data, int *val2)
462 {
463 unsigned int sel_bits;
464 int ret;
465
466 mutex_lock(&data->lock);
467 ret = regmap_field_read(data->regmap_fields[F_SEL], &sel_bits);
468 if (ret < 0)
469 goto data_unlock;
470
471 *val2 = fxas21002c_hpf_sel_from_value(data, sel_bits);
472
473 ret = IIO_VAL_INT_PLUS_MICRO;
474
475 data_unlock:
476 mutex_unlock(&data->lock);
477
478 return ret;
479 }
480
481 static int fxas21002c_hpf_set(struct fxas21002c_data *data, int sel)
482 {
483 int sel_bits;
484
485 sel_bits = fxas21002c_hpf_value_from_sel(data, sel);
486 if (sel_bits < 0)
487 return sel_bits;
488
489 return fxas21002c_write(data, F_SEL, sel_bits);
490 }
491
492 static int fxas21002c_scale_get(struct fxas21002c_data *data, int *val)
493 {
494 int fs_bits;
495 int scale;
496 int ret;
497
498 mutex_lock(&data->lock);
499 ret = regmap_field_read(data->regmap_fields[F_FS], &fs_bits);
500 if (ret < 0)
501 goto data_unlock;
502
503 scale = fxas21002c_range_fs_from_value(data, fs_bits);
504 if (scale < 0) {
505 ret = scale;
506 goto data_unlock;
507 }
508
509 *val = scale;
510
511 data_unlock:
512 mutex_unlock(&data->lock);
513
514 return ret;
515 }
516
517 static int fxas21002c_scale_set(struct fxas21002c_data *data, int range)
518 {
519 int fs_bits;
520
521 fs_bits = fxas21002c_range_value_from_fs(data, range);
522 if (fs_bits < 0)
523 return fs_bits;
524
525 return fxas21002c_write(data, F_FS, fs_bits);
526 }
527
528 static int fxas21002c_read_raw(struct iio_dev *indio_dev,
529 struct iio_chan_spec const *chan, int *val,
530 int *val2, long mask)
531 {
532 struct fxas21002c_data *data = iio_priv(indio_dev);
533 int ret;
534
535 switch (mask) {
536 case IIO_CHAN_INFO_RAW:
537 switch (chan->type) {
538 case IIO_TEMP:
539 return fxas21002c_temp_get(data, val);
540 case IIO_ANGL_VEL:
541 return fxas21002c_axis_get(data, chan->scan_index, val);
542 default:
543 return -EINVAL;
544 }
545 case IIO_CHAN_INFO_SCALE:
546 switch (chan->type) {
547 case IIO_ANGL_VEL:
548 *val2 = FXAS21002C_SCALE_FRACTIONAL;
549 ret = fxas21002c_scale_get(data, val);
550 if (ret < 0)
551 return ret;
552
553 return IIO_VAL_FRACTIONAL;
554 default:
555 return -EINVAL;
556 }
557 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
558 *val = 0;
559 return fxas21002c_lpf_get(data, val2);
560 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
561 *val = 0;
562 return fxas21002c_hpf_get(data, val2);
563 case IIO_CHAN_INFO_SAMP_FREQ:
564 *val2 = 0;
565 return fxas21002c_odr_get(data, val);
566 default:
567 return -EINVAL;
568 }
569 }
570
571 static int fxas21002c_write_raw(struct iio_dev *indio_dev,
572 struct iio_chan_spec const *chan, int val,
573 int val2, long mask)
574 {
575 struct fxas21002c_data *data = iio_priv(indio_dev);
576 int range;
577
578 switch (mask) {
579 case IIO_CHAN_INFO_SAMP_FREQ:
580 if (val2)
581 return -EINVAL;
582
583 return fxas21002c_odr_set(data, val);
584 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
585 if (val)
586 return -EINVAL;
587
588 val2 = val2 / 10000;
589 return fxas21002c_lpf_set(data, val2);
590 case IIO_CHAN_INFO_SCALE:
591 switch (chan->type) {
592 case IIO_ANGL_VEL:
593 range = (((val * 1000 + val2 / 1000) *
594 FXAS21002C_SCALE_FRACTIONAL) / 1000);
595 return fxas21002c_scale_set(data, range);
596 default:
597 return -EINVAL;
598 }
599 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
600 return fxas21002c_hpf_set(data, val2);
601 default:
602 return -EINVAL;
603 }
604 }
605
606 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("12.5 25 50 100 200 400 800");
607
608 static IIO_CONST_ATTR(in_anglvel_filter_low_pass_3db_frequency_available,
609 "0.32 0.16 0.08");
610
611 static IIO_CONST_ATTR(in_anglvel_filter_high_pass_3db_frequency_available,
612 "0.018750 0.009625 0.004875 0.002475");
613
614 static IIO_CONST_ATTR(in_anglvel_scale_available,
615 "125.0 62.5 31.25 15.625 7.8125");
616
617 static struct attribute *fxas21002c_attributes[] = {
618 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
619 &iio_const_attr_in_anglvel_filter_low_pass_3db_frequency_available.dev_attr.attr,
620 &iio_const_attr_in_anglvel_filter_high_pass_3db_frequency_available.dev_attr.attr,
621 &iio_const_attr_in_anglvel_scale_available.dev_attr.attr,
622 NULL,
623 };
624
625 static const struct attribute_group fxas21002c_attrs_group = {
626 .attrs = fxas21002c_attributes,
627 };
628
629 #define FXAS21002C_CHANNEL(_axis) { \
630 .type = IIO_ANGL_VEL, \
631 .modified = 1, \
632 .channel2 = IIO_MOD_##_axis, \
633 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
634 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
635 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \
636 BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY) | \
637 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
638 .scan_index = CHANNEL_SCAN_INDEX_##_axis, \
639 .scan_type = { \
640 .sign = 's', \
641 .realbits = 16, \
642 .storagebits = 16, \
643 .endianness = IIO_BE, \
644 }, \
645 }
646
647 static const struct iio_chan_spec fxas21002c_channels[] = {
648 {
649 .type = IIO_TEMP,
650 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
651 .scan_index = -1,
652 },
653 FXAS21002C_CHANNEL(X),
654 FXAS21002C_CHANNEL(Y),
655 FXAS21002C_CHANNEL(Z),
656 };
657
658 static const struct iio_info fxas21002c_info = {
659 .attrs = &fxas21002c_attrs_group,
660 .read_raw = &fxas21002c_read_raw,
661 .write_raw = &fxas21002c_write_raw,
662 };
663
664 static irqreturn_t fxas21002c_trigger_handler(int irq, void *p)
665 {
666 struct iio_poll_func *pf = p;
667 struct iio_dev *indio_dev = pf->indio_dev;
668 struct fxas21002c_data *data = iio_priv(indio_dev);
669 int ret;
670
671 mutex_lock(&data->lock);
672 ret = regmap_bulk_read(data->regmap, FXAS21002C_REG_OUT_X_MSB,
673 data->buffer, CHANNEL_SCAN_MAX * sizeof(s16));
674 if (ret < 0)
675 goto out_unlock;
676
677 iio_push_to_buffers_with_timestamp(indio_dev, data->buffer,
678 data->timestamp);
679
680 out_unlock:
681 mutex_unlock(&data->lock);
682
683 iio_trigger_notify_done(indio_dev->trig);
684
685 return IRQ_HANDLED;
686 }
687
688 static int fxas21002c_chip_init(struct fxas21002c_data *data)
689 {
690 struct device *dev = regmap_get_device(data->regmap);
691 unsigned int chip_id;
692 int ret;
693
694 ret = regmap_field_read(data->regmap_fields[F_WHO_AM_I], &chip_id);
695 if (ret < 0)
696 return ret;
697
698 if (chip_id != FXAS21002C_CHIP_ID_1 &&
699 chip_id != FXAS21002C_CHIP_ID_2) {
700 dev_err(dev, "chip id 0x%02x is not supported\n", chip_id);
701 return -EINVAL;
702 }
703
704 data->chip_id = chip_id;
705
706 ret = fxas21002c_mode_set(data, FXAS21002C_MODE_STANDBY);
707 if (ret < 0)
708 return ret;
709
710 /* Set ODR to 200HZ as default */
711 ret = fxas21002c_odr_set(data, 200);
712 if (ret < 0)
713 dev_err(dev, "failed to set ODR: %d\n", ret);
714
715 return ret;
716 }
717
718 static int fxas21002c_data_rdy_trigger_set_state(struct iio_trigger *trig,
719 bool state)
720 {
721 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
722 struct fxas21002c_data *data = iio_priv(indio_dev);
723
724 return regmap_field_write(data->regmap_fields[F_INT_EN_DRDY], state);
725 }
726
727 static const struct iio_trigger_ops fxas21002c_trigger_ops = {
728 .set_trigger_state = &fxas21002c_data_rdy_trigger_set_state,
729 };
730
731 static irqreturn_t fxas21002c_data_rdy_handler(int irq, void *private)
732 {
733 struct iio_dev *indio_dev = private;
734 struct fxas21002c_data *data = iio_priv(indio_dev);
735
736 data->timestamp = iio_get_time_ns(indio_dev);
737
738 return IRQ_WAKE_THREAD;
739 }
740
741 static irqreturn_t fxas21002c_data_rdy_thread(int irq, void *private)
742 {
743 struct iio_dev *indio_dev = private;
744 struct fxas21002c_data *data = iio_priv(indio_dev);
745 unsigned int data_ready;
746 int ret;
747
748 ret = regmap_field_read(data->regmap_fields[F_SRC_DRDY], &data_ready);
749 if (ret < 0)
750 return IRQ_NONE;
751
752 if (!data_ready)
753 return IRQ_NONE;
754
755 iio_trigger_poll_chained(data->dready_trig);
756
757 return IRQ_HANDLED;
758 }
759
760 static int fxas21002c_trigger_probe(struct fxas21002c_data *data)
761 {
762 struct device *dev = regmap_get_device(data->regmap);
763 struct iio_dev *indio_dev = dev_get_drvdata(dev);
764 struct device_node *np = indio_dev->dev.of_node;
765 unsigned long irq_trig;
766 bool irq_open_drain;
767 int irq1;
768 int ret;
769
770 if (!data->irq)
771 return 0;
772
773 irq1 = of_irq_get_byname(np, "INT1");
774
775 if (irq1 == data->irq) {
776 dev_info(dev, "using interrupt line INT1\n");
777 ret = regmap_field_write(data->regmap_fields[F_INT_CFG_DRDY],
778 1);
779 if (ret < 0)
780 return ret;
781 }
782
783 dev_info(dev, "using interrupt line INT2\n");
784
785 irq_open_drain = of_property_read_bool(np, "drive-open-drain");
786
787 data->dready_trig = devm_iio_trigger_alloc(dev, "%s-dev%d",
788 indio_dev->name,
789 indio_dev->id);
790 if (!data->dready_trig)
791 return -ENOMEM;
792
793 irq_trig = irqd_get_trigger_type(irq_get_irq_data(data->irq));
794
795 if (irq_trig == IRQF_TRIGGER_RISING) {
796 ret = regmap_field_write(data->regmap_fields[F_IPOL], 1);
797 if (ret < 0)
798 return ret;
799 }
800
801 if (irq_open_drain)
802 irq_trig |= IRQF_SHARED;
803
804 ret = devm_request_threaded_irq(dev, data->irq,
805 fxas21002c_data_rdy_handler,
806 fxas21002c_data_rdy_thread,
807 irq_trig, "fxas21002c_data_ready",
808 indio_dev);
809 if (ret < 0)
810 return ret;
811
812 data->dready_trig->dev.parent = dev;
813 data->dready_trig->ops = &fxas21002c_trigger_ops;
814 iio_trigger_set_drvdata(data->dready_trig, indio_dev);
815
816 return devm_iio_trigger_register(dev, data->dready_trig);
817 }
818
819 static int fxas21002c_power_enable(struct fxas21002c_data *data)
820 {
821 int ret;
822
823 ret = regulator_enable(data->vdd);
824 if (ret < 0)
825 return ret;
826
827 ret = regulator_enable(data->vddio);
828 if (ret < 0) {
829 regulator_disable(data->vdd);
830 return ret;
831 }
832
833 return 0;
834 }
835
836 static void fxas21002c_power_disable(struct fxas21002c_data *data)
837 {
838 regulator_disable(data->vdd);
839 regulator_disable(data->vddio);
840 }
841
842 static void fxas21002c_power_disable_action(void *_data)
843 {
844 struct fxas21002c_data *data = _data;
845
846 fxas21002c_power_disable(data);
847 }
848
849 static int fxas21002c_regulators_get(struct fxas21002c_data *data)
850 {
851 struct device *dev = regmap_get_device(data->regmap);
852
853 data->vdd = devm_regulator_get(dev->parent, "vdd");
854 if (IS_ERR(data->vdd))
855 return PTR_ERR(data->vdd);
856
857 data->vddio = devm_regulator_get(dev->parent, "vddio");
858
859 return PTR_ERR_OR_ZERO(data->vddio);
860 }
861
862 int fxas21002c_core_probe(struct device *dev, struct regmap *regmap, int irq,
863 const char *name)
864 {
865 struct fxas21002c_data *data;
866 struct iio_dev *indio_dev;
867 struct regmap_field *f;
868 int i;
869 int ret;
870
871 indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
872 if (!indio_dev)
873 return -ENOMEM;
874
875 data = iio_priv(indio_dev);
876 dev_set_drvdata(dev, indio_dev);
877 data->irq = irq;
878 data->regmap = regmap;
879
880 for (i = 0; i < F_MAX_FIELDS; i++) {
881 f = devm_regmap_field_alloc(dev, data->regmap,
882 fxas21002c_reg_fields[i]);
883 if (IS_ERR(f))
884 return PTR_ERR(f);
885
886 data->regmap_fields[i] = f;
887 }
888
889 mutex_init(&data->lock);
890
891 ret = fxas21002c_regulators_get(data);
892 if (ret < 0)
893 return ret;
894
895 ret = fxas21002c_power_enable(data);
896 if (ret < 0)
897 return ret;
898
899 ret = devm_add_action_or_reset(dev, fxas21002c_power_disable_action,
900 data);
901 if (ret < 0)
902 return ret;
903
904 ret = fxas21002c_chip_init(data);
905 if (ret < 0)
906 return ret;
907
908 indio_dev->dev.parent = dev;
909 indio_dev->channels = fxas21002c_channels;
910 indio_dev->num_channels = ARRAY_SIZE(fxas21002c_channels);
911 indio_dev->name = name;
912 indio_dev->modes = INDIO_DIRECT_MODE;
913 indio_dev->info = &fxas21002c_info;
914
915 ret = fxas21002c_trigger_probe(data);
916 if (ret < 0)
917 return ret;
918
919 ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL,
920 fxas21002c_trigger_handler, NULL);
921 if (ret < 0)
922 return ret;
923
924 ret = pm_runtime_set_active(dev);
925 if (ret)
926 return ret;
927
928 pm_runtime_enable(dev);
929 pm_runtime_set_autosuspend_delay(dev, 2000);
930 pm_runtime_use_autosuspend(dev);
931
932 ret = iio_device_register(indio_dev);
933 if (ret < 0)
934 goto pm_disable;
935
936 return 0;
937
938 pm_disable:
939 pm_runtime_disable(dev);
940 pm_runtime_set_suspended(dev);
941 pm_runtime_put_noidle(dev);
942
943 return ret;
944 }
945 EXPORT_SYMBOL_GPL(fxas21002c_core_probe);
946
947 void fxas21002c_core_remove(struct device *dev)
948 {
949 struct iio_dev *indio_dev = dev_get_drvdata(dev);
950
951 iio_device_unregister(indio_dev);
952
953 pm_runtime_disable(dev);
954 pm_runtime_set_suspended(dev);
955 pm_runtime_put_noidle(dev);
956 }
957 EXPORT_SYMBOL_GPL(fxas21002c_core_remove);
958
959 static int __maybe_unused fxas21002c_suspend(struct device *dev)
960 {
961 struct fxas21002c_data *data = iio_priv(dev_get_drvdata(dev));
962
963 fxas21002c_mode_set(data, FXAS21002C_MODE_STANDBY);
964 fxas21002c_power_disable(data);
965
966 return 0;
967 }
968
969 static int __maybe_unused fxas21002c_resume(struct device *dev)
970 {
971 struct fxas21002c_data *data = iio_priv(dev_get_drvdata(dev));
972 int ret;
973
974 ret = fxas21002c_power_enable(data);
975 if (ret < 0)
976 return ret;
977
978 return fxas21002c_mode_set(data, data->prev_mode);
979 }
980
981 static int __maybe_unused fxas21002c_runtime_suspend(struct device *dev)
982 {
983 struct fxas21002c_data *data = iio_priv(dev_get_drvdata(dev));
984
985 return fxas21002c_mode_set(data, FXAS21002C_MODE_READY);
986 }
987
988 static int __maybe_unused fxas21002c_runtime_resume(struct device *dev)
989 {
990 struct fxas21002c_data *data = iio_priv(dev_get_drvdata(dev));
991
992 return fxas21002c_mode_set(data, FXAS21002C_MODE_ACTIVE);
993 }
994
995 const struct dev_pm_ops fxas21002c_pm_ops = {
996 SET_SYSTEM_SLEEP_PM_OPS(fxas21002c_suspend, fxas21002c_resume)
997 SET_RUNTIME_PM_OPS(fxas21002c_runtime_suspend,
998 fxas21002c_runtime_resume, NULL)
999 };
1000 EXPORT_SYMBOL_GPL(fxas21002c_pm_ops);
1001
1002 MODULE_AUTHOR("Rui Miguel Silva <rui.silva@linaro.org>");
1003 MODULE_LICENSE("GPL v2");
1004 MODULE_DESCRIPTION("FXAS21002C Gyro driver");
Linux with added FPC-III support