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Merge tag 'for-linus-20190706' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / net / can / flexcan.c
blobf2fe344593d58ce66697515326efae700dab22ce
1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // flexcan.c - FLEXCAN CAN controller driver
4 //
5 // Copyright (c) 2005-2006 Varma Electronics Oy
6 // Copyright (c) 2009 Sascha Hauer, Pengutronix
7 // Copyright (c) 2010-2017 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de>
8 // Copyright (c) 2014 David Jander, Protonic Holland
9 //
10 // Based on code originally by Andrey Volkov <avolkov@varma-el.com>
11
12 #include <linux/netdevice.h>
13 #include <linux/can.h>
14 #include <linux/can/dev.h>
15 #include <linux/can/error.h>
16 #include <linux/can/led.h>
17 #include <linux/can/rx-offload.h>
18 #include <linux/clk.h>
19 #include <linux/delay.h>
20 #include <linux/interrupt.h>
21 #include <linux/io.h>
22 #include <linux/mfd/syscon.h>
23 #include <linux/module.h>
24 #include <linux/of.h>
25 #include <linux/of_device.h>
26 #include <linux/platform_device.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/regmap.h>
29
30 #define DRV_NAME "flexcan"
31
32 /* 8 for RX fifo and 2 error handling */
33 #define FLEXCAN_NAPI_WEIGHT (8 + 2)
34
35 /* FLEXCAN module configuration register (CANMCR) bits */
36 #define FLEXCAN_MCR_MDIS BIT(31)
37 #define FLEXCAN_MCR_FRZ BIT(30)
38 #define FLEXCAN_MCR_FEN BIT(29)
39 #define FLEXCAN_MCR_HALT BIT(28)
40 #define FLEXCAN_MCR_NOT_RDY BIT(27)
41 #define FLEXCAN_MCR_WAK_MSK BIT(26)
42 #define FLEXCAN_MCR_SOFTRST BIT(25)
43 #define FLEXCAN_MCR_FRZ_ACK BIT(24)
44 #define FLEXCAN_MCR_SUPV BIT(23)
45 #define FLEXCAN_MCR_SLF_WAK BIT(22)
46 #define FLEXCAN_MCR_WRN_EN BIT(21)
47 #define FLEXCAN_MCR_LPM_ACK BIT(20)
48 #define FLEXCAN_MCR_WAK_SRC BIT(19)
49 #define FLEXCAN_MCR_DOZE BIT(18)
50 #define FLEXCAN_MCR_SRX_DIS BIT(17)
51 #define FLEXCAN_MCR_IRMQ BIT(16)
52 #define FLEXCAN_MCR_LPRIO_EN BIT(13)
53 #define FLEXCAN_MCR_AEN BIT(12)
54 /* MCR_MAXMB: maximum used MBs is MAXMB + 1 */
55 #define FLEXCAN_MCR_MAXMB(x) ((x) & 0x7f)
56 #define FLEXCAN_MCR_IDAM_A (0x0 << 8)
57 #define FLEXCAN_MCR_IDAM_B (0x1 << 8)
58 #define FLEXCAN_MCR_IDAM_C (0x2 << 8)
59 #define FLEXCAN_MCR_IDAM_D (0x3 << 8)
60
61 /* FLEXCAN control register (CANCTRL) bits */
62 #define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24)
63 #define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22)
64 #define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19)
65 #define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16)
66 #define FLEXCAN_CTRL_BOFF_MSK BIT(15)
67 #define FLEXCAN_CTRL_ERR_MSK BIT(14)
68 #define FLEXCAN_CTRL_CLK_SRC BIT(13)
69 #define FLEXCAN_CTRL_LPB BIT(12)
70 #define FLEXCAN_CTRL_TWRN_MSK BIT(11)
71 #define FLEXCAN_CTRL_RWRN_MSK BIT(10)
72 #define FLEXCAN_CTRL_SMP BIT(7)
73 #define FLEXCAN_CTRL_BOFF_REC BIT(6)
74 #define FLEXCAN_CTRL_TSYN BIT(5)
75 #define FLEXCAN_CTRL_LBUF BIT(4)
76 #define FLEXCAN_CTRL_LOM BIT(3)
77 #define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07)
78 #define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK)
79 #define FLEXCAN_CTRL_ERR_STATE \
80 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
81 FLEXCAN_CTRL_BOFF_MSK)
82 #define FLEXCAN_CTRL_ERR_ALL \
83 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
84
85 /* FLEXCAN control register 2 (CTRL2) bits */
86 #define FLEXCAN_CTRL2_ECRWRE BIT(29)
87 #define FLEXCAN_CTRL2_WRMFRZ BIT(28)
88 #define FLEXCAN_CTRL2_RFFN(x) (((x) & 0x0f) << 24)
89 #define FLEXCAN_CTRL2_TASD(x) (((x) & 0x1f) << 19)
90 #define FLEXCAN_CTRL2_MRP BIT(18)
91 #define FLEXCAN_CTRL2_RRS BIT(17)
92 #define FLEXCAN_CTRL2_EACEN BIT(16)
93
94 /* FLEXCAN memory error control register (MECR) bits */
95 #define FLEXCAN_MECR_ECRWRDIS BIT(31)
96 #define FLEXCAN_MECR_HANCEI_MSK BIT(19)
97 #define FLEXCAN_MECR_FANCEI_MSK BIT(18)
98 #define FLEXCAN_MECR_CEI_MSK BIT(16)
99 #define FLEXCAN_MECR_HAERRIE BIT(15)
100 #define FLEXCAN_MECR_FAERRIE BIT(14)
101 #define FLEXCAN_MECR_EXTERRIE BIT(13)
102 #define FLEXCAN_MECR_RERRDIS BIT(9)
103 #define FLEXCAN_MECR_ECCDIS BIT(8)
104 #define FLEXCAN_MECR_NCEFAFRZ BIT(7)
105
106 /* FLEXCAN error and status register (ESR) bits */
107 #define FLEXCAN_ESR_TWRN_INT BIT(17)
108 #define FLEXCAN_ESR_RWRN_INT BIT(16)
109 #define FLEXCAN_ESR_BIT1_ERR BIT(15)
110 #define FLEXCAN_ESR_BIT0_ERR BIT(14)
111 #define FLEXCAN_ESR_ACK_ERR BIT(13)
112 #define FLEXCAN_ESR_CRC_ERR BIT(12)
113 #define FLEXCAN_ESR_FRM_ERR BIT(11)
114 #define FLEXCAN_ESR_STF_ERR BIT(10)
115 #define FLEXCAN_ESR_TX_WRN BIT(9)
116 #define FLEXCAN_ESR_RX_WRN BIT(8)
117 #define FLEXCAN_ESR_IDLE BIT(7)
118 #define FLEXCAN_ESR_TXRX BIT(6)
119 #define FLEXCAN_EST_FLT_CONF_SHIFT (4)
120 #define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
121 #define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
122 #define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
123 #define FLEXCAN_ESR_BOFF_INT BIT(2)
124 #define FLEXCAN_ESR_ERR_INT BIT(1)
125 #define FLEXCAN_ESR_WAK_INT BIT(0)
126 #define FLEXCAN_ESR_ERR_BUS \
127 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
128 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
129 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
130 #define FLEXCAN_ESR_ERR_STATE \
131 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
132 #define FLEXCAN_ESR_ERR_ALL \
133 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
134 #define FLEXCAN_ESR_ALL_INT \
135 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
136 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT | \
137 FLEXCAN_ESR_WAK_INT)
138
139 /* FLEXCAN interrupt flag register (IFLAG) bits */
140 /* Errata ERR005829 step7: Reserve first valid MB */
141 #define FLEXCAN_TX_MB_RESERVED_OFF_FIFO 8
142 #define FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP 0
143 #define FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST (FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP + 1)
144 #define FLEXCAN_IFLAG_MB(x) BIT((x) & 0x1f)
145 #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
146 #define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
147 #define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
148
149 /* FLEXCAN message buffers */
150 #define FLEXCAN_MB_CODE_MASK (0xf << 24)
151 #define FLEXCAN_MB_CODE_RX_BUSY_BIT (0x1 << 24)
152 #define FLEXCAN_MB_CODE_RX_INACTIVE (0x0 << 24)
153 #define FLEXCAN_MB_CODE_RX_EMPTY (0x4 << 24)
154 #define FLEXCAN_MB_CODE_RX_FULL (0x2 << 24)
155 #define FLEXCAN_MB_CODE_RX_OVERRUN (0x6 << 24)
156 #define FLEXCAN_MB_CODE_RX_RANSWER (0xa << 24)
157
158 #define FLEXCAN_MB_CODE_TX_INACTIVE (0x8 << 24)
159 #define FLEXCAN_MB_CODE_TX_ABORT (0x9 << 24)
160 #define FLEXCAN_MB_CODE_TX_DATA (0xc << 24)
161 #define FLEXCAN_MB_CODE_TX_TANSWER (0xe << 24)
162
163 #define FLEXCAN_MB_CNT_SRR BIT(22)
164 #define FLEXCAN_MB_CNT_IDE BIT(21)
165 #define FLEXCAN_MB_CNT_RTR BIT(20)
166 #define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16)
167 #define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff)
168
169 #define FLEXCAN_TIMEOUT_US (250)
170
171 /* FLEXCAN hardware feature flags
172 *
173 * Below is some version info we got:
174 * SOC Version IP-Version Glitch- [TR]WRN_INT IRQ Err Memory err RTR re-
175 * Filter? connected? Passive detection ception in MB
176 * MX25 FlexCAN2 03.00.00.00 no no no no no
177 * MX28 FlexCAN2 03.00.04.00 yes yes no no no
178 * MX35 FlexCAN2 03.00.00.00 no no no no no
179 * MX53 FlexCAN2 03.00.00.00 yes no no no no
180 * MX6s FlexCAN3 10.00.12.00 yes yes no no yes
181 * VF610 FlexCAN3 ? no yes no yes yes?
182 * LS1021A FlexCAN2 03.00.04.00 no yes no no yes
183 *
184 * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
185 */
186 #define FLEXCAN_QUIRK_BROKEN_WERR_STATE BIT(1) /* [TR]WRN_INT not connected */
187 #define FLEXCAN_QUIRK_DISABLE_RXFG BIT(2) /* Disable RX FIFO Global mask */
188 #define FLEXCAN_QUIRK_ENABLE_EACEN_RRS BIT(3) /* Enable EACEN and RRS bit in ctrl2 */
189 #define FLEXCAN_QUIRK_DISABLE_MECR BIT(4) /* Disable Memory error detection */
190 #define FLEXCAN_QUIRK_USE_OFF_TIMESTAMP BIT(5) /* Use timestamp based offloading */
191 #define FLEXCAN_QUIRK_BROKEN_PERR_STATE BIT(6) /* No interrupt for error passive */
192 #define FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN BIT(7) /* default to BE register access */
193 #define FLEXCAN_QUIRK_SETUP_STOP_MODE BIT(8) /* Setup stop mode to support wakeup */
194
195 /* Structure of the message buffer */
196 struct flexcan_mb {
197 u32 can_ctrl;
198 u32 can_id;
199 u32 data[];
200 };
201
202 /* Structure of the hardware registers */
203 struct flexcan_regs {
204 u32 mcr; /* 0x00 */
205 u32 ctrl; /* 0x04 */
206 u32 timer; /* 0x08 */
207 u32 _reserved1; /* 0x0c */
208 u32 rxgmask; /* 0x10 */
209 u32 rx14mask; /* 0x14 */
210 u32 rx15mask; /* 0x18 */
211 u32 ecr; /* 0x1c */
212 u32 esr; /* 0x20 */
213 u32 imask2; /* 0x24 */
214 u32 imask1; /* 0x28 */
215 u32 iflag2; /* 0x2c */
216 u32 iflag1; /* 0x30 */
217 union { /* 0x34 */
218 u32 gfwr_mx28; /* MX28, MX53 */
219 u32 ctrl2; /* MX6, VF610 */
220 };
221 u32 esr2; /* 0x38 */
222 u32 imeur; /* 0x3c */
223 u32 lrfr; /* 0x40 */
224 u32 crcr; /* 0x44 */
225 u32 rxfgmask; /* 0x48 */
226 u32 rxfir; /* 0x4c */
227 u32 _reserved3[12]; /* 0x50 */
228 u8 mb[2][512]; /* 0x80 */
229 /* FIFO-mode:
230 * MB
231 * 0x080...0x08f 0 RX message buffer
232 * 0x090...0x0df 1-5 reserverd
233 * 0x0e0...0x0ff 6-7 8 entry ID table
234 * (mx25, mx28, mx35, mx53)
235 * 0x0e0...0x2df 6-7..37 8..128 entry ID table
236 * size conf'ed via ctrl2::RFFN
237 * (mx6, vf610)
238 */
239 u32 _reserved4[256]; /* 0x480 */
240 u32 rximr[64]; /* 0x880 */
241 u32 _reserved5[24]; /* 0x980 */
242 u32 gfwr_mx6; /* 0x9e0 - MX6 */
243 u32 _reserved6[63]; /* 0x9e4 */
244 u32 mecr; /* 0xae0 */
245 u32 erriar; /* 0xae4 */
246 u32 erridpr; /* 0xae8 */
247 u32 errippr; /* 0xaec */
248 u32 rerrar; /* 0xaf0 */
249 u32 rerrdr; /* 0xaf4 */
250 u32 rerrsynr; /* 0xaf8 */
251 u32 errsr; /* 0xafc */
252 };
253
254 struct flexcan_devtype_data {
255 u32 quirks; /* quirks needed for different IP cores */
256 };
257
258 struct flexcan_stop_mode {
259 struct regmap *gpr;
260 u8 req_gpr;
261 u8 req_bit;
262 u8 ack_gpr;
263 u8 ack_bit;
264 };
265
266 struct flexcan_priv {
267 struct can_priv can;
268 struct can_rx_offload offload;
269
270 struct flexcan_regs __iomem *regs;
271 struct flexcan_mb __iomem *tx_mb;
272 struct flexcan_mb __iomem *tx_mb_reserved;
273 u8 tx_mb_idx;
274 u8 mb_count;
275 u8 mb_size;
276 u32 reg_ctrl_default;
277 u32 reg_imask1_default;
278 u32 reg_imask2_default;
279
280 struct clk *clk_ipg;
281 struct clk *clk_per;
282 const struct flexcan_devtype_data *devtype_data;
283 struct regulator *reg_xceiver;
284 struct flexcan_stop_mode stm;
285
286 /* Read and Write APIs */
287 u32 (*read)(void __iomem *addr);
288 void (*write)(u32 val, void __iomem *addr);
289 };
290
291 static const struct flexcan_devtype_data fsl_p1010_devtype_data = {
292 .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
293 FLEXCAN_QUIRK_BROKEN_PERR_STATE |
294 FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN,
295 };
296
297 static const struct flexcan_devtype_data fsl_imx25_devtype_data = {
298 .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
299 FLEXCAN_QUIRK_BROKEN_PERR_STATE,
300 };
301
302 static const struct flexcan_devtype_data fsl_imx28_devtype_data = {
303 .quirks = FLEXCAN_QUIRK_BROKEN_PERR_STATE,
304 };
305
306 static const struct flexcan_devtype_data fsl_imx6q_devtype_data = {
307 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
308 FLEXCAN_QUIRK_USE_OFF_TIMESTAMP | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
309 FLEXCAN_QUIRK_SETUP_STOP_MODE,
310 };
311
312 static const struct flexcan_devtype_data fsl_vf610_devtype_data = {
313 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
314 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP |
315 FLEXCAN_QUIRK_BROKEN_PERR_STATE,
316 };
317
318 static const struct flexcan_devtype_data fsl_ls1021a_r2_devtype_data = {
319 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
320 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
321 FLEXCAN_QUIRK_USE_OFF_TIMESTAMP,
322 };
323
324 static const struct can_bittiming_const flexcan_bittiming_const = {
325 .name = DRV_NAME,
326 .tseg1_min = 4,
327 .tseg1_max = 16,
328 .tseg2_min = 2,
329 .tseg2_max = 8,
330 .sjw_max = 4,
331 .brp_min = 1,
332 .brp_max = 256,
333 .brp_inc = 1,
334 };
335
336 /* FlexCAN module is essentially modelled as a little-endian IP in most
337 * SoCs, i.e the registers as well as the message buffer areas are
338 * implemented in a little-endian fashion.
339 *
340 * However there are some SoCs (e.g. LS1021A) which implement the FlexCAN
341 * module in a big-endian fashion (i.e the registers as well as the
342 * message buffer areas are implemented in a big-endian way).
343 *
344 * In addition, the FlexCAN module can be found on SoCs having ARM or
345 * PPC cores. So, we need to abstract off the register read/write
346 * functions, ensuring that these cater to all the combinations of module
347 * endianness and underlying CPU endianness.
348 */
349 static inline u32 flexcan_read_be(void __iomem *addr)
350 {
351 return ioread32be(addr);
352 }
353
354 static inline void flexcan_write_be(u32 val, void __iomem *addr)
355 {
356 iowrite32be(val, addr);
357 }
358
359 static inline u32 flexcan_read_le(void __iomem *addr)
360 {
361 return ioread32(addr);
362 }
363
364 static inline void flexcan_write_le(u32 val, void __iomem *addr)
365 {
366 iowrite32(val, addr);
367 }
368
369 static struct flexcan_mb __iomem *flexcan_get_mb(const struct flexcan_priv *priv,
370 u8 mb_index)
371 {
372 u8 bank_size;
373 bool bank;
374
375 if (WARN_ON(mb_index >= priv->mb_count))
376 return NULL;
377
378 bank_size = sizeof(priv->regs->mb[0]) / priv->mb_size;
379
380 bank = mb_index >= bank_size;
381 if (bank)
382 mb_index -= bank_size;
383
384 return (struct flexcan_mb __iomem *)
385 (&priv->regs->mb[bank][priv->mb_size * mb_index]);
386 }
387
388 static void flexcan_enable_wakeup_irq(struct flexcan_priv *priv, bool enable)
389 {
390 struct flexcan_regs __iomem *regs = priv->regs;
391 u32 reg_mcr;
392
393 reg_mcr = priv->read(&regs->mcr);
394
395 if (enable)
396 reg_mcr |= FLEXCAN_MCR_WAK_MSK;
397 else
398 reg_mcr &= ~FLEXCAN_MCR_WAK_MSK;
399
400 priv->write(reg_mcr, &regs->mcr);
401 }
402
403 static inline void flexcan_enter_stop_mode(struct flexcan_priv *priv)
404 {
405 struct flexcan_regs __iomem *regs = priv->regs;
406 u32 reg_mcr;
407
408 reg_mcr = priv->read(&regs->mcr);
409 reg_mcr |= FLEXCAN_MCR_SLF_WAK;
410 priv->write(reg_mcr, &regs->mcr);
411
412 /* enable stop request */
413 regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr,
414 1 << priv->stm.req_bit, 1 << priv->stm.req_bit);
415 }
416
417 static inline void flexcan_exit_stop_mode(struct flexcan_priv *priv)
418 {
419 struct flexcan_regs __iomem *regs = priv->regs;
420 u32 reg_mcr;
421
422 /* remove stop request */
423 regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr,
424 1 << priv->stm.req_bit, 0);
425
426 reg_mcr = priv->read(&regs->mcr);
427 reg_mcr &= ~FLEXCAN_MCR_SLF_WAK;
428 priv->write(reg_mcr, &regs->mcr);
429 }
430
431 static inline void flexcan_error_irq_enable(const struct flexcan_priv *priv)
432 {
433 struct flexcan_regs __iomem *regs = priv->regs;
434 u32 reg_ctrl = (priv->reg_ctrl_default | FLEXCAN_CTRL_ERR_MSK);
435
436 priv->write(reg_ctrl, &regs->ctrl);
437 }
438
439 static inline void flexcan_error_irq_disable(const struct flexcan_priv *priv)
440 {
441 struct flexcan_regs __iomem *regs = priv->regs;
442 u32 reg_ctrl = (priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_MSK);
443
444 priv->write(reg_ctrl, &regs->ctrl);
445 }
446
447 static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
448 {
449 if (!priv->reg_xceiver)
450 return 0;
451
452 return regulator_enable(priv->reg_xceiver);
453 }
454
455 static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv)
456 {
457 if (!priv->reg_xceiver)
458 return 0;
459
460 return regulator_disable(priv->reg_xceiver);
461 }
462
463 static int flexcan_chip_enable(struct flexcan_priv *priv)
464 {
465 struct flexcan_regs __iomem *regs = priv->regs;
466 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
467 u32 reg;
468
469 reg = priv->read(&regs->mcr);
470 reg &= ~FLEXCAN_MCR_MDIS;
471 priv->write(reg, &regs->mcr);
472
473 while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
474 udelay(10);
475
476 if (priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK)
477 return -ETIMEDOUT;
478
479 return 0;
480 }
481
482 static int flexcan_chip_disable(struct flexcan_priv *priv)
483 {
484 struct flexcan_regs __iomem *regs = priv->regs;
485 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
486 u32 reg;
487
488 reg = priv->read(&regs->mcr);
489 reg |= FLEXCAN_MCR_MDIS;
490 priv->write(reg, &regs->mcr);
491
492 while (timeout-- && !(priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
493 udelay(10);
494
495 if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
496 return -ETIMEDOUT;
497
498 return 0;
499 }
500
501 static int flexcan_chip_freeze(struct flexcan_priv *priv)
502 {
503 struct flexcan_regs __iomem *regs = priv->regs;
504 unsigned int timeout = 1000 * 1000 * 10 / priv->can.bittiming.bitrate;
505 u32 reg;
506
507 reg = priv->read(&regs->mcr);
508 reg |= FLEXCAN_MCR_HALT;
509 priv->write(reg, &regs->mcr);
510
511 while (timeout-- && !(priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
512 udelay(100);
513
514 if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
515 return -ETIMEDOUT;
516
517 return 0;
518 }
519
520 static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
521 {
522 struct flexcan_regs __iomem *regs = priv->regs;
523 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
524 u32 reg;
525
526 reg = priv->read(&regs->mcr);
527 reg &= ~FLEXCAN_MCR_HALT;
528 priv->write(reg, &regs->mcr);
529
530 while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
531 udelay(10);
532
533 if (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK)
534 return -ETIMEDOUT;
535
536 return 0;
537 }
538
539 static int flexcan_chip_softreset(struct flexcan_priv *priv)
540 {
541 struct flexcan_regs __iomem *regs = priv->regs;
542 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
543
544 priv->write(FLEXCAN_MCR_SOFTRST, &regs->mcr);
545 while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_SOFTRST))
546 udelay(10);
547
548 if (priv->read(&regs->mcr) & FLEXCAN_MCR_SOFTRST)
549 return -ETIMEDOUT;
550
551 return 0;
552 }
553
554 static int __flexcan_get_berr_counter(const struct net_device *dev,
555 struct can_berr_counter *bec)
556 {
557 const struct flexcan_priv *priv = netdev_priv(dev);
558 struct flexcan_regs __iomem *regs = priv->regs;
559 u32 reg = priv->read(&regs->ecr);
560
561 bec->txerr = (reg >> 0) & 0xff;
562 bec->rxerr = (reg >> 8) & 0xff;
563
564 return 0;
565 }
566
567 static int flexcan_get_berr_counter(const struct net_device *dev,
568 struct can_berr_counter *bec)
569 {
570 const struct flexcan_priv *priv = netdev_priv(dev);
571 int err;
572
573 err = clk_prepare_enable(priv->clk_ipg);
574 if (err)
575 return err;
576
577 err = clk_prepare_enable(priv->clk_per);
578 if (err)
579 goto out_disable_ipg;
580
581 err = __flexcan_get_berr_counter(dev, bec);
582
583 clk_disable_unprepare(priv->clk_per);
584 out_disable_ipg:
585 clk_disable_unprepare(priv->clk_ipg);
586
587 return err;
588 }
589
590 static netdev_tx_t flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
591 {
592 const struct flexcan_priv *priv = netdev_priv(dev);
593 struct can_frame *cf = (struct can_frame *)skb->data;
594 u32 can_id;
595 u32 data;
596 u32 ctrl = FLEXCAN_MB_CODE_TX_DATA | (cf->can_dlc << 16);
597 int i;
598
599 if (can_dropped_invalid_skb(dev, skb))
600 return NETDEV_TX_OK;
601
602 netif_stop_queue(dev);
603
604 if (cf->can_id & CAN_EFF_FLAG) {
605 can_id = cf->can_id & CAN_EFF_MASK;
606 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
607 } else {
608 can_id = (cf->can_id & CAN_SFF_MASK) << 18;
609 }
610
611 if (cf->can_id & CAN_RTR_FLAG)
612 ctrl |= FLEXCAN_MB_CNT_RTR;
613
614 for (i = 0; i < cf->can_dlc; i += sizeof(u32)) {
615 data = be32_to_cpup((__be32 *)&cf->data[i]);
616 priv->write(data, &priv->tx_mb->data[i / sizeof(u32)]);
617 }
618
619 can_put_echo_skb(skb, dev, 0);
620
621 priv->write(can_id, &priv->tx_mb->can_id);
622 priv->write(ctrl, &priv->tx_mb->can_ctrl);
623
624 /* Errata ERR005829 step8:
625 * Write twice INACTIVE(0x8) code to first MB.
626 */
627 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
628 &priv->tx_mb_reserved->can_ctrl);
629 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
630 &priv->tx_mb_reserved->can_ctrl);
631
632 return NETDEV_TX_OK;
633 }
634
635 static void flexcan_irq_bus_err(struct net_device *dev, u32 reg_esr)
636 {
637 struct flexcan_priv *priv = netdev_priv(dev);
638 struct flexcan_regs __iomem *regs = priv->regs;
639 struct sk_buff *skb;
640 struct can_frame *cf;
641 bool rx_errors = false, tx_errors = false;
642 u32 timestamp;
643
644 timestamp = priv->read(&regs->timer) << 16;
645
646 skb = alloc_can_err_skb(dev, &cf);
647 if (unlikely(!skb))
648 return;
649
650 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
651
652 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
653 netdev_dbg(dev, "BIT1_ERR irq\n");
654 cf->data[2] |= CAN_ERR_PROT_BIT1;
655 tx_errors = true;
656 }
657 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
658 netdev_dbg(dev, "BIT0_ERR irq\n");
659 cf->data[2] |= CAN_ERR_PROT_BIT0;
660 tx_errors = true;
661 }
662 if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
663 netdev_dbg(dev, "ACK_ERR irq\n");
664 cf->can_id |= CAN_ERR_ACK;
665 cf->data[3] = CAN_ERR_PROT_LOC_ACK;
666 tx_errors = true;
667 }
668 if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
669 netdev_dbg(dev, "CRC_ERR irq\n");
670 cf->data[2] |= CAN_ERR_PROT_BIT;
671 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
672 rx_errors = true;
673 }
674 if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
675 netdev_dbg(dev, "FRM_ERR irq\n");
676 cf->data[2] |= CAN_ERR_PROT_FORM;
677 rx_errors = true;
678 }
679 if (reg_esr & FLEXCAN_ESR_STF_ERR) {
680 netdev_dbg(dev, "STF_ERR irq\n");
681 cf->data[2] |= CAN_ERR_PROT_STUFF;
682 rx_errors = true;
683 }
684
685 priv->can.can_stats.bus_error++;
686 if (rx_errors)
687 dev->stats.rx_errors++;
688 if (tx_errors)
689 dev->stats.tx_errors++;
690
691 can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
692 }
693
694 static void flexcan_irq_state(struct net_device *dev, u32 reg_esr)
695 {
696 struct flexcan_priv *priv = netdev_priv(dev);
697 struct flexcan_regs __iomem *regs = priv->regs;
698 struct sk_buff *skb;
699 struct can_frame *cf;
700 enum can_state new_state, rx_state, tx_state;
701 int flt;
702 struct can_berr_counter bec;
703 u32 timestamp;
704
705 timestamp = priv->read(&regs->timer) << 16;
706
707 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
708 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
709 tx_state = unlikely(reg_esr & FLEXCAN_ESR_TX_WRN) ?
710 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
711 rx_state = unlikely(reg_esr & FLEXCAN_ESR_RX_WRN) ?
712 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
713 new_state = max(tx_state, rx_state);
714 } else {
715 __flexcan_get_berr_counter(dev, &bec);
716 new_state = flt == FLEXCAN_ESR_FLT_CONF_PASSIVE ?
717 CAN_STATE_ERROR_PASSIVE : CAN_STATE_BUS_OFF;
718 rx_state = bec.rxerr >= bec.txerr ? new_state : 0;
719 tx_state = bec.rxerr <= bec.txerr ? new_state : 0;
720 }
721
722 /* state hasn't changed */
723 if (likely(new_state == priv->can.state))
724 return;
725
726 skb = alloc_can_err_skb(dev, &cf);
727 if (unlikely(!skb))
728 return;
729
730 can_change_state(dev, cf, tx_state, rx_state);
731
732 if (unlikely(new_state == CAN_STATE_BUS_OFF))
733 can_bus_off(dev);
734
735 can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
736 }
737
738 static inline struct flexcan_priv *rx_offload_to_priv(struct can_rx_offload *offload)
739 {
740 return container_of(offload, struct flexcan_priv, offload);
741 }
742
743 static unsigned int flexcan_mailbox_read(struct can_rx_offload *offload,
744 struct can_frame *cf,
745 u32 *timestamp, unsigned int n)
746 {
747 struct flexcan_priv *priv = rx_offload_to_priv(offload);
748 struct flexcan_regs __iomem *regs = priv->regs;
749 struct flexcan_mb __iomem *mb;
750 u32 reg_ctrl, reg_id, reg_iflag1;
751 int i;
752
753 mb = flexcan_get_mb(priv, n);
754
755 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
756 u32 code;
757
758 do {
759 reg_ctrl = priv->read(&mb->can_ctrl);
760 } while (reg_ctrl & FLEXCAN_MB_CODE_RX_BUSY_BIT);
761
762 /* is this MB empty? */
763 code = reg_ctrl & FLEXCAN_MB_CODE_MASK;
764 if ((code != FLEXCAN_MB_CODE_RX_FULL) &&
765 (code != FLEXCAN_MB_CODE_RX_OVERRUN))
766 return 0;
767
768 if (code == FLEXCAN_MB_CODE_RX_OVERRUN) {
769 /* This MB was overrun, we lost data */
770 offload->dev->stats.rx_over_errors++;
771 offload->dev->stats.rx_errors++;
772 }
773 } else {
774 reg_iflag1 = priv->read(&regs->iflag1);
775 if (!(reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE))
776 return 0;
777
778 reg_ctrl = priv->read(&mb->can_ctrl);
779 }
780
781 /* increase timstamp to full 32 bit */
782 *timestamp = reg_ctrl << 16;
783
784 reg_id = priv->read(&mb->can_id);
785 if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
786 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
787 else
788 cf->can_id = (reg_id >> 18) & CAN_SFF_MASK;
789
790 if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
791 cf->can_id |= CAN_RTR_FLAG;
792 cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
793
794 for (i = 0; i < cf->can_dlc; i += sizeof(u32)) {
795 __be32 data = cpu_to_be32(priv->read(&mb->data[i / sizeof(u32)]));
796 *(__be32 *)(cf->data + i) = data;
797 }
798
799 /* mark as read */
800 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
801 /* Clear IRQ */
802 if (n < 32)
803 priv->write(BIT(n), &regs->iflag1);
804 else
805 priv->write(BIT(n - 32), &regs->iflag2);
806 } else {
807 priv->write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);
808 }
809
810 /* Read the Free Running Timer. It is optional but recommended
811 * to unlock Mailbox as soon as possible and make it available
812 * for reception.
813 */
814 priv->read(&regs->timer);
815
816 return 1;
817 }
818
819
820 static inline u64 flexcan_read_reg_iflag_rx(struct flexcan_priv *priv)
821 {
822 struct flexcan_regs __iomem *regs = priv->regs;
823 u32 iflag1, iflag2;
824
825 iflag2 = priv->read(&regs->iflag2) & priv->reg_imask2_default &
826 ~FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
827 iflag1 = priv->read(&regs->iflag1) & priv->reg_imask1_default;
828
829 return (u64)iflag2 << 32 | iflag1;
830 }
831
832 static irqreturn_t flexcan_irq(int irq, void *dev_id)
833 {
834 struct net_device *dev = dev_id;
835 struct net_device_stats *stats = &dev->stats;
836 struct flexcan_priv *priv = netdev_priv(dev);
837 struct flexcan_regs __iomem *regs = priv->regs;
838 irqreturn_t handled = IRQ_NONE;
839 u32 reg_iflag2, reg_esr;
840 enum can_state last_state = priv->can.state;
841
842 /* reception interrupt */
843 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
844 u64 reg_iflag;
845 int ret;
846
847 while ((reg_iflag = flexcan_read_reg_iflag_rx(priv))) {
848 handled = IRQ_HANDLED;
849 ret = can_rx_offload_irq_offload_timestamp(&priv->offload,
850 reg_iflag);
851 if (!ret)
852 break;
853 }
854 } else {
855 u32 reg_iflag1;
856
857 reg_iflag1 = priv->read(&regs->iflag1);
858 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) {
859 handled = IRQ_HANDLED;
860 can_rx_offload_irq_offload_fifo(&priv->offload);
861 }
862
863 /* FIFO overflow interrupt */
864 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
865 handled = IRQ_HANDLED;
866 priv->write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW,
867 &regs->iflag1);
868 dev->stats.rx_over_errors++;
869 dev->stats.rx_errors++;
870 }
871 }
872
873 reg_iflag2 = priv->read(&regs->iflag2);
874
875 /* transmission complete interrupt */
876 if (reg_iflag2 & FLEXCAN_IFLAG_MB(priv->tx_mb_idx)) {
877 u32 reg_ctrl = priv->read(&priv->tx_mb->can_ctrl);
878
879 handled = IRQ_HANDLED;
880 stats->tx_bytes += can_rx_offload_get_echo_skb(&priv->offload,
881 0, reg_ctrl << 16);
882 stats->tx_packets++;
883 can_led_event(dev, CAN_LED_EVENT_TX);
884
885 /* after sending a RTR frame MB is in RX mode */
886 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
887 &priv->tx_mb->can_ctrl);
888 priv->write(FLEXCAN_IFLAG_MB(priv->tx_mb_idx), &regs->iflag2);
889 netif_wake_queue(dev);
890 }
891
892 reg_esr = priv->read(&regs->esr);
893
894 /* ACK all bus error and state change IRQ sources */
895 if (reg_esr & FLEXCAN_ESR_ALL_INT) {
896 handled = IRQ_HANDLED;
897 priv->write(reg_esr & FLEXCAN_ESR_ALL_INT, &regs->esr);
898 }
899
900 /* state change interrupt or broken error state quirk fix is enabled */
901 if ((reg_esr & FLEXCAN_ESR_ERR_STATE) ||
902 (priv->devtype_data->quirks & (FLEXCAN_QUIRK_BROKEN_WERR_STATE |
903 FLEXCAN_QUIRK_BROKEN_PERR_STATE)))
904 flexcan_irq_state(dev, reg_esr);
905
906 /* bus error IRQ - handle if bus error reporting is activated */
907 if ((reg_esr & FLEXCAN_ESR_ERR_BUS) &&
908 (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
909 flexcan_irq_bus_err(dev, reg_esr);
910
911 /* availability of error interrupt among state transitions in case
912 * bus error reporting is de-activated and
913 * FLEXCAN_QUIRK_BROKEN_PERR_STATE is enabled:
914 * +--------------------------------------------------------------+
915 * | +----------------------------------------------+ [stopped / |
916 * | | | sleeping] -+
917 * +-+-> active <-> warning <-> passive -> bus off -+
918 * ___________^^^^^^^^^^^^_______________________________
919 * disabled(1) enabled disabled
920 *
921 * (1): enabled if FLEXCAN_QUIRK_BROKEN_WERR_STATE is enabled
922 */
923 if ((last_state != priv->can.state) &&
924 (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_PERR_STATE) &&
925 !(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) {
926 switch (priv->can.state) {
927 case CAN_STATE_ERROR_ACTIVE:
928 if (priv->devtype_data->quirks &
929 FLEXCAN_QUIRK_BROKEN_WERR_STATE)
930 flexcan_error_irq_enable(priv);
931 else
932 flexcan_error_irq_disable(priv);
933 break;
934
935 case CAN_STATE_ERROR_WARNING:
936 flexcan_error_irq_enable(priv);
937 break;
938
939 case CAN_STATE_ERROR_PASSIVE:
940 case CAN_STATE_BUS_OFF:
941 flexcan_error_irq_disable(priv);
942 break;
943
944 default:
945 break;
946 }
947 }
948
949 return handled;
950 }
951
952 static void flexcan_set_bittiming(struct net_device *dev)
953 {
954 const struct flexcan_priv *priv = netdev_priv(dev);
955 const struct can_bittiming *bt = &priv->can.bittiming;
956 struct flexcan_regs __iomem *regs = priv->regs;
957 u32 reg;
958
959 reg = priv->read(&regs->ctrl);
960 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
961 FLEXCAN_CTRL_RJW(0x3) |
962 FLEXCAN_CTRL_PSEG1(0x7) |
963 FLEXCAN_CTRL_PSEG2(0x7) |
964 FLEXCAN_CTRL_PROPSEG(0x7) |
965 FLEXCAN_CTRL_LPB |
966 FLEXCAN_CTRL_SMP |
967 FLEXCAN_CTRL_LOM);
968
969 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
970 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
971 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
972 FLEXCAN_CTRL_RJW(bt->sjw - 1) |
973 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
974
975 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
976 reg |= FLEXCAN_CTRL_LPB;
977 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
978 reg |= FLEXCAN_CTRL_LOM;
979 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
980 reg |= FLEXCAN_CTRL_SMP;
981
982 netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
983 priv->write(reg, &regs->ctrl);
984
985 /* print chip status */
986 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
987 priv->read(&regs->mcr), priv->read(&regs->ctrl));
988 }
989
990 /* flexcan_chip_start
991 *
992 * this functions is entered with clocks enabled
993 *
994 */
995 static int flexcan_chip_start(struct net_device *dev)
996 {
997 struct flexcan_priv *priv = netdev_priv(dev);
998 struct flexcan_regs __iomem *regs = priv->regs;
999 u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr;
1000 int err, i;
1001 struct flexcan_mb __iomem *mb;
1002
1003 /* enable module */
1004 err = flexcan_chip_enable(priv);
1005 if (err)
1006 return err;
1007
1008 /* soft reset */
1009 err = flexcan_chip_softreset(priv);
1010 if (err)
1011 goto out_chip_disable;
1012
1013 flexcan_set_bittiming(dev);
1014
1015 /* MCR
1016 *
1017 * enable freeze
1018 * halt now
1019 * only supervisor access
1020 * enable warning int
1021 * enable individual RX masking
1022 * choose format C
1023 * set max mailbox number
1024 */
1025 reg_mcr = priv->read(&regs->mcr);
1026 reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
1027 reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | FLEXCAN_MCR_SUPV |
1028 FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_IRMQ | FLEXCAN_MCR_IDAM_C |
1029 FLEXCAN_MCR_MAXMB(priv->tx_mb_idx);
1030
1031 /* MCR
1032 *
1033 * FIFO:
1034 * - disable for timestamp mode
1035 * - enable for FIFO mode
1036 */
1037 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)
1038 reg_mcr &= ~FLEXCAN_MCR_FEN;
1039 else
1040 reg_mcr |= FLEXCAN_MCR_FEN;
1041
1042 /* MCR
1043 *
1044 * NOTE: In loopback mode, the CAN_MCR[SRXDIS] cannot be
1045 * asserted because this will impede the self reception
1046 * of a transmitted message. This is not documented in
1047 * earlier versions of flexcan block guide.
1048 *
1049 * Self Reception:
1050 * - enable Self Reception for loopback mode
1051 * (by clearing "Self Reception Disable" bit)
1052 * - disable for normal operation
1053 */
1054 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
1055 reg_mcr &= ~FLEXCAN_MCR_SRX_DIS;
1056 else
1057 reg_mcr |= FLEXCAN_MCR_SRX_DIS;
1058
1059 netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
1060 priv->write(reg_mcr, &regs->mcr);
1061
1062 /* CTRL
1063 *
1064 * disable timer sync feature
1065 *
1066 * disable auto busoff recovery
1067 * transmit lowest buffer first
1068 *
1069 * enable tx and rx warning interrupt
1070 * enable bus off interrupt
1071 * (== FLEXCAN_CTRL_ERR_STATE)
1072 */
1073 reg_ctrl = priv->read(&regs->ctrl);
1074 reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
1075 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
1076 FLEXCAN_CTRL_ERR_STATE;
1077
1078 /* enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK),
1079 * on most Flexcan cores, too. Otherwise we don't get
1080 * any error warning or passive interrupts.
1081 */
1082 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_WERR_STATE ||
1083 priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
1084 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
1085 else
1086 reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK;
1087
1088 /* save for later use */
1089 priv->reg_ctrl_default = reg_ctrl;
1090 /* leave interrupts disabled for now */
1091 reg_ctrl &= ~FLEXCAN_CTRL_ERR_ALL;
1092 netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
1093 priv->write(reg_ctrl, &regs->ctrl);
1094
1095 if ((priv->devtype_data->quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) {
1096 reg_ctrl2 = priv->read(&regs->ctrl2);
1097 reg_ctrl2 |= FLEXCAN_CTRL2_EACEN | FLEXCAN_CTRL2_RRS;
1098 priv->write(reg_ctrl2, &regs->ctrl2);
1099 }
1100
1101 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1102 for (i = priv->offload.mb_first; i <= priv->offload.mb_last; i++) {
1103 mb = flexcan_get_mb(priv, i);
1104 priv->write(FLEXCAN_MB_CODE_RX_EMPTY,
1105 &mb->can_ctrl);
1106 }
1107 } else {
1108 /* clear and invalidate unused mailboxes first */
1109 for (i = FLEXCAN_TX_MB_RESERVED_OFF_FIFO; i < priv->mb_count; i++) {
1110 mb = flexcan_get_mb(priv, i);
1111 priv->write(FLEXCAN_MB_CODE_RX_INACTIVE,
1112 &mb->can_ctrl);
1113 }
1114 }
1115
1116 /* Errata ERR005829: mark first TX mailbox as INACTIVE */
1117 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1118 &priv->tx_mb_reserved->can_ctrl);
1119
1120 /* mark TX mailbox as INACTIVE */
1121 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1122 &priv->tx_mb->can_ctrl);
1123
1124 /* acceptance mask/acceptance code (accept everything) */
1125 priv->write(0x0, &regs->rxgmask);
1126 priv->write(0x0, &regs->rx14mask);
1127 priv->write(0x0, &regs->rx15mask);
1128
1129 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_RXFG)
1130 priv->write(0x0, &regs->rxfgmask);
1131
1132 /* clear acceptance filters */
1133 for (i = 0; i < priv->mb_count; i++)
1134 priv->write(0, &regs->rximr[i]);
1135
1136 /* On Vybrid, disable memory error detection interrupts
1137 * and freeze mode.
1138 * This also works around errata e5295 which generates
1139 * false positive memory errors and put the device in
1140 * freeze mode.
1141 */
1142 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_MECR) {
1143 /* Follow the protocol as described in "Detection
1144 * and Correction of Memory Errors" to write to
1145 * MECR register
1146 */
1147 reg_ctrl2 = priv->read(&regs->ctrl2);
1148 reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;
1149 priv->write(reg_ctrl2, &regs->ctrl2);
1150
1151 reg_mecr = priv->read(&regs->mecr);
1152 reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
1153 priv->write(reg_mecr, &regs->mecr);
1154 reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
1155 FLEXCAN_MECR_FANCEI_MSK);
1156 priv->write(reg_mecr, &regs->mecr);
1157 }
1158
1159 err = flexcan_transceiver_enable(priv);
1160 if (err)
1161 goto out_chip_disable;
1162
1163 /* synchronize with the can bus */
1164 err = flexcan_chip_unfreeze(priv);
1165 if (err)
1166 goto out_transceiver_disable;
1167
1168 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1169
1170 /* enable interrupts atomically */
1171 disable_irq(dev->irq);
1172 priv->write(priv->reg_ctrl_default, &regs->ctrl);
1173 priv->write(priv->reg_imask1_default, &regs->imask1);
1174 priv->write(priv->reg_imask2_default, &regs->imask2);
1175 enable_irq(dev->irq);
1176
1177 /* print chip status */
1178 netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
1179 priv->read(&regs->mcr), priv->read(&regs->ctrl));
1180
1181 return 0;
1182
1183 out_transceiver_disable:
1184 flexcan_transceiver_disable(priv);
1185 out_chip_disable:
1186 flexcan_chip_disable(priv);
1187 return err;
1188 }
1189
1190 /* flexcan_chip_stop
1191 *
1192 * this functions is entered with clocks enabled
1193 */
1194 static void flexcan_chip_stop(struct net_device *dev)
1195 {
1196 struct flexcan_priv *priv = netdev_priv(dev);
1197 struct flexcan_regs __iomem *regs = priv->regs;
1198
1199 /* freeze + disable module */
1200 flexcan_chip_freeze(priv);
1201 flexcan_chip_disable(priv);
1202
1203 /* Disable all interrupts */
1204 priv->write(0, &regs->imask2);
1205 priv->write(0, &regs->imask1);
1206 priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
1207 &regs->ctrl);
1208
1209 flexcan_transceiver_disable(priv);
1210 priv->can.state = CAN_STATE_STOPPED;
1211 }
1212
1213 static int flexcan_open(struct net_device *dev)
1214 {
1215 struct flexcan_priv *priv = netdev_priv(dev);
1216 int err;
1217
1218 err = clk_prepare_enable(priv->clk_ipg);
1219 if (err)
1220 return err;
1221
1222 err = clk_prepare_enable(priv->clk_per);
1223 if (err)
1224 goto out_disable_ipg;
1225
1226 err = open_candev(dev);
1227 if (err)
1228 goto out_disable_per;
1229
1230 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
1231 if (err)
1232 goto out_close;
1233
1234 priv->mb_size = sizeof(struct flexcan_mb) + CAN_MAX_DLEN;
1235 priv->mb_count = (sizeof(priv->regs->mb[0]) / priv->mb_size) +
1236 (sizeof(priv->regs->mb[1]) / priv->mb_size);
1237
1238 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)
1239 priv->tx_mb_reserved =
1240 flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP);
1241 else
1242 priv->tx_mb_reserved =
1243 flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_OFF_FIFO);
1244 priv->tx_mb_idx = priv->mb_count - 1;
1245 priv->tx_mb = flexcan_get_mb(priv, priv->tx_mb_idx);
1246
1247 priv->reg_imask1_default = 0;
1248 priv->reg_imask2_default = FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
1249
1250 priv->offload.mailbox_read = flexcan_mailbox_read;
1251
1252 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1253 u64 imask;
1254
1255 priv->offload.mb_first = FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST;
1256 priv->offload.mb_last = priv->mb_count - 2;
1257
1258 imask = GENMASK_ULL(priv->offload.mb_last,
1259 priv->offload.mb_first);
1260 priv->reg_imask1_default |= imask;
1261 priv->reg_imask2_default |= imask >> 32;
1262
1263 err = can_rx_offload_add_timestamp(dev, &priv->offload);
1264 } else {
1265 priv->reg_imask1_default |= FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
1266 FLEXCAN_IFLAG_RX_FIFO_AVAILABLE;
1267 err = can_rx_offload_add_fifo(dev, &priv->offload,
1268 FLEXCAN_NAPI_WEIGHT);
1269 }
1270 if (err)
1271 goto out_free_irq;
1272
1273 /* start chip and queuing */
1274 err = flexcan_chip_start(dev);
1275 if (err)
1276 goto out_offload_del;
1277
1278 can_led_event(dev, CAN_LED_EVENT_OPEN);
1279
1280 can_rx_offload_enable(&priv->offload);
1281 netif_start_queue(dev);
1282
1283 return 0;
1284
1285 out_offload_del:
1286 can_rx_offload_del(&priv->offload);
1287 out_free_irq:
1288 free_irq(dev->irq, dev);
1289 out_close:
1290 close_candev(dev);
1291 out_disable_per:
1292 clk_disable_unprepare(priv->clk_per);
1293 out_disable_ipg:
1294 clk_disable_unprepare(priv->clk_ipg);
1295
1296 return err;
1297 }
1298
1299 static int flexcan_close(struct net_device *dev)
1300 {
1301 struct flexcan_priv *priv = netdev_priv(dev);
1302
1303 netif_stop_queue(dev);
1304 can_rx_offload_disable(&priv->offload);
1305 flexcan_chip_stop(dev);
1306
1307 can_rx_offload_del(&priv->offload);
1308 free_irq(dev->irq, dev);
1309 clk_disable_unprepare(priv->clk_per);
1310 clk_disable_unprepare(priv->clk_ipg);
1311
1312 close_candev(dev);
1313
1314 can_led_event(dev, CAN_LED_EVENT_STOP);
1315
1316 return 0;
1317 }
1318
1319 static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
1320 {
1321 int err;
1322
1323 switch (mode) {
1324 case CAN_MODE_START:
1325 err = flexcan_chip_start(dev);
1326 if (err)
1327 return err;
1328
1329 netif_wake_queue(dev);
1330 break;
1331
1332 default:
1333 return -EOPNOTSUPP;
1334 }
1335
1336 return 0;
1337 }
1338
1339 static const struct net_device_ops flexcan_netdev_ops = {
1340 .ndo_open = flexcan_open,
1341 .ndo_stop = flexcan_close,
1342 .ndo_start_xmit = flexcan_start_xmit,
1343 .ndo_change_mtu = can_change_mtu,
1344 };
1345
1346 static int register_flexcandev(struct net_device *dev)
1347 {
1348 struct flexcan_priv *priv = netdev_priv(dev);
1349 struct flexcan_regs __iomem *regs = priv->regs;
1350 u32 reg, err;
1351
1352 err = clk_prepare_enable(priv->clk_ipg);
1353 if (err)
1354 return err;
1355
1356 err = clk_prepare_enable(priv->clk_per);
1357 if (err)
1358 goto out_disable_ipg;
1359
1360 /* select "bus clock", chip must be disabled */
1361 err = flexcan_chip_disable(priv);
1362 if (err)
1363 goto out_disable_per;
1364 reg = priv->read(&regs->ctrl);
1365 reg |= FLEXCAN_CTRL_CLK_SRC;
1366 priv->write(reg, &regs->ctrl);
1367
1368 err = flexcan_chip_enable(priv);
1369 if (err)
1370 goto out_chip_disable;
1371
1372 /* set freeze, halt and activate FIFO, restrict register access */
1373 reg = priv->read(&regs->mcr);
1374 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
1375 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
1376 priv->write(reg, &regs->mcr);
1377
1378 /* Currently we only support newer versions of this core
1379 * featuring a RX hardware FIFO (although this driver doesn't
1380 * make use of it on some cores). Older cores, found on some
1381 * Coldfire derivates are not tested.
1382 */
1383 reg = priv->read(&regs->mcr);
1384 if (!(reg & FLEXCAN_MCR_FEN)) {
1385 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
1386 err = -ENODEV;
1387 goto out_chip_disable;
1388 }
1389
1390 err = register_candev(dev);
1391
1392 /* disable core and turn off clocks */
1393 out_chip_disable:
1394 flexcan_chip_disable(priv);
1395 out_disable_per:
1396 clk_disable_unprepare(priv->clk_per);
1397 out_disable_ipg:
1398 clk_disable_unprepare(priv->clk_ipg);
1399
1400 return err;
1401 }
1402
1403 static void unregister_flexcandev(struct net_device *dev)
1404 {
1405 unregister_candev(dev);
1406 }
1407
1408 static int flexcan_setup_stop_mode(struct platform_device *pdev)
1409 {
1410 struct net_device *dev = platform_get_drvdata(pdev);
1411 struct device_node *np = pdev->dev.of_node;
1412 struct device_node *gpr_np;
1413 struct flexcan_priv *priv;
1414 phandle phandle;
1415 u32 out_val[5];
1416 int ret;
1417
1418 if (!np)
1419 return -EINVAL;
1420
1421 /* stop mode property format is:
1422 * <&gpr req_gpr req_bit ack_gpr ack_bit>.
1423 */
1424 ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val,
1425 ARRAY_SIZE(out_val));
1426 if (ret) {
1427 dev_dbg(&pdev->dev, "no stop-mode property\n");
1428 return ret;
1429 }
1430 phandle = *out_val;
1431
1432 gpr_np = of_find_node_by_phandle(phandle);
1433 if (!gpr_np) {
1434 dev_dbg(&pdev->dev, "could not find gpr node by phandle\n");
1435 return -ENODEV;
1436 }
1437
1438 priv = netdev_priv(dev);
1439 priv->stm.gpr = syscon_node_to_regmap(gpr_np);
1440 of_node_put(gpr_np);
1441 if (IS_ERR(priv->stm.gpr)) {
1442 dev_dbg(&pdev->dev, "could not find gpr regmap\n");
1443 return PTR_ERR(priv->stm.gpr);
1444 }
1445
1446 priv->stm.req_gpr = out_val[1];
1447 priv->stm.req_bit = out_val[2];
1448 priv->stm.ack_gpr = out_val[3];
1449 priv->stm.ack_bit = out_val[4];
1450
1451 dev_dbg(&pdev->dev,
1452 "gpr %s req_gpr=0x02%x req_bit=%u ack_gpr=0x02%x ack_bit=%u\n",
1453 gpr_np->full_name, priv->stm.req_gpr, priv->stm.req_bit,
1454 priv->stm.ack_gpr, priv->stm.ack_bit);
1455
1456 device_set_wakeup_capable(&pdev->dev, true);
1457
1458 return 0;
1459 }
1460
1461 static const struct of_device_id flexcan_of_match[] = {
1462 { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
1463 { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
1464 { .compatible = "fsl,imx53-flexcan", .data = &fsl_imx25_devtype_data, },
1465 { .compatible = "fsl,imx35-flexcan", .data = &fsl_imx25_devtype_data, },
1466 { .compatible = "fsl,imx25-flexcan", .data = &fsl_imx25_devtype_data, },
1467 { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
1468 { .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
1469 { .compatible = "fsl,ls1021ar2-flexcan", .data = &fsl_ls1021a_r2_devtype_data, },
1470 { /* sentinel */ },
1471 };
1472 MODULE_DEVICE_TABLE(of, flexcan_of_match);
1473
1474 static const struct platform_device_id flexcan_id_table[] = {
1475 { .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, },
1476 { /* sentinel */ },
1477 };
1478 MODULE_DEVICE_TABLE(platform, flexcan_id_table);
1479
1480 static int flexcan_probe(struct platform_device *pdev)
1481 {
1482 const struct of_device_id *of_id;
1483 const struct flexcan_devtype_data *devtype_data;
1484 struct net_device *dev;
1485 struct flexcan_priv *priv;
1486 struct regulator *reg_xceiver;
1487 struct resource *mem;
1488 struct clk *clk_ipg = NULL, *clk_per = NULL;
1489 struct flexcan_regs __iomem *regs;
1490 int err, irq;
1491 u32 clock_freq = 0;
1492
1493 reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver");
1494 if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)
1495 return -EPROBE_DEFER;
1496 else if (IS_ERR(reg_xceiver))
1497 reg_xceiver = NULL;
1498
1499 if (pdev->dev.of_node)
1500 of_property_read_u32(pdev->dev.of_node,
1501 "clock-frequency", &clock_freq);
1502
1503 if (!clock_freq) {
1504 clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1505 if (IS_ERR(clk_ipg)) {
1506 dev_err(&pdev->dev, "no ipg clock defined\n");
1507 return PTR_ERR(clk_ipg);
1508 }
1509
1510 clk_per = devm_clk_get(&pdev->dev, "per");
1511 if (IS_ERR(clk_per)) {
1512 dev_err(&pdev->dev, "no per clock defined\n");
1513 return PTR_ERR(clk_per);
1514 }
1515 clock_freq = clk_get_rate(clk_per);
1516 }
1517
1518 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1519 irq = platform_get_irq(pdev, 0);
1520 if (irq <= 0)
1521 return -ENODEV;
1522
1523 regs = devm_ioremap_resource(&pdev->dev, mem);
1524 if (IS_ERR(regs))
1525 return PTR_ERR(regs);
1526
1527 of_id = of_match_device(flexcan_of_match, &pdev->dev);
1528 if (of_id) {
1529 devtype_data = of_id->data;
1530 } else if (platform_get_device_id(pdev)->driver_data) {
1531 devtype_data = (struct flexcan_devtype_data *)
1532 platform_get_device_id(pdev)->driver_data;
1533 } else {
1534 return -ENODEV;
1535 }
1536
1537 dev = alloc_candev(sizeof(struct flexcan_priv), 1);
1538 if (!dev)
1539 return -ENOMEM;
1540
1541 platform_set_drvdata(pdev, dev);
1542 SET_NETDEV_DEV(dev, &pdev->dev);
1543
1544 dev->netdev_ops = &flexcan_netdev_ops;
1545 dev->irq = irq;
1546 dev->flags |= IFF_ECHO;
1547
1548 priv = netdev_priv(dev);
1549
1550 if (of_property_read_bool(pdev->dev.of_node, "big-endian") ||
1551 devtype_data->quirks & FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN) {
1552 priv->read = flexcan_read_be;
1553 priv->write = flexcan_write_be;
1554 } else {
1555 priv->read = flexcan_read_le;
1556 priv->write = flexcan_write_le;
1557 }
1558
1559 priv->can.clock.freq = clock_freq;
1560 priv->can.bittiming_const = &flexcan_bittiming_const;
1561 priv->can.do_set_mode = flexcan_set_mode;
1562 priv->can.do_get_berr_counter = flexcan_get_berr_counter;
1563 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1564 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
1565 CAN_CTRLMODE_BERR_REPORTING;
1566 priv->regs = regs;
1567 priv->clk_ipg = clk_ipg;
1568 priv->clk_per = clk_per;
1569 priv->devtype_data = devtype_data;
1570 priv->reg_xceiver = reg_xceiver;
1571
1572 err = register_flexcandev(dev);
1573 if (err) {
1574 dev_err(&pdev->dev, "registering netdev failed\n");
1575 goto failed_register;
1576 }
1577
1578 devm_can_led_init(dev);
1579
1580 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE) {
1581 err = flexcan_setup_stop_mode(pdev);
1582 if (err)
1583 dev_dbg(&pdev->dev, "failed to setup stop-mode\n");
1584 }
1585
1586 return 0;
1587
1588 failed_register:
1589 free_candev(dev);
1590 return err;
1591 }
1592
1593 static int flexcan_remove(struct platform_device *pdev)
1594 {
1595 struct net_device *dev = platform_get_drvdata(pdev);
1596
1597 unregister_flexcandev(dev);
1598 free_candev(dev);
1599
1600 return 0;
1601 }
1602
1603 static int __maybe_unused flexcan_suspend(struct device *device)
1604 {
1605 struct net_device *dev = dev_get_drvdata(device);
1606 struct flexcan_priv *priv = netdev_priv(dev);
1607 int err;
1608
1609 if (netif_running(dev)) {
1610 /* if wakeup is enabled, enter stop mode
1611 * else enter disabled mode.
1612 */
1613 if (device_may_wakeup(device)) {
1614 enable_irq_wake(dev->irq);
1615 flexcan_enter_stop_mode(priv);
1616 } else {
1617 err = flexcan_chip_disable(priv);
1618 if (err)
1619 return err;
1620 }
1621 netif_stop_queue(dev);
1622 netif_device_detach(dev);
1623 }
1624 priv->can.state = CAN_STATE_SLEEPING;
1625
1626 return 0;
1627 }
1628
1629 static int __maybe_unused flexcan_resume(struct device *device)
1630 {
1631 struct net_device *dev = dev_get_drvdata(device);
1632 struct flexcan_priv *priv = netdev_priv(dev);
1633 int err;
1634
1635 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1636 if (netif_running(dev)) {
1637 netif_device_attach(dev);
1638 netif_start_queue(dev);
1639 if (device_may_wakeup(device)) {
1640 disable_irq_wake(dev->irq);
1641 } else {
1642 err = flexcan_chip_enable(priv);
1643 if (err)
1644 return err;
1645 }
1646 }
1647 return 0;
1648 }
1649
1650 static int __maybe_unused flexcan_noirq_suspend(struct device *device)
1651 {
1652 struct net_device *dev = dev_get_drvdata(device);
1653 struct flexcan_priv *priv = netdev_priv(dev);
1654
1655 if (netif_running(dev) && device_may_wakeup(device))
1656 flexcan_enable_wakeup_irq(priv, true);
1657
1658 return 0;
1659 }
1660
1661 static int __maybe_unused flexcan_noirq_resume(struct device *device)
1662 {
1663 struct net_device *dev = dev_get_drvdata(device);
1664 struct flexcan_priv *priv = netdev_priv(dev);
1665
1666 if (netif_running(dev) && device_may_wakeup(device)) {
1667 flexcan_enable_wakeup_irq(priv, false);
1668 flexcan_exit_stop_mode(priv);
1669 }
1670
1671 return 0;
1672 }
1673
1674 static const struct dev_pm_ops flexcan_pm_ops = {
1675 SET_SYSTEM_SLEEP_PM_OPS(flexcan_suspend, flexcan_resume)
1676 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(flexcan_noirq_suspend, flexcan_noirq_resume)
1677 };
1678
1679 static struct platform_driver flexcan_driver = {
1680 .driver = {
1681 .name = DRV_NAME,
1682 .pm = &flexcan_pm_ops,
1683 .of_match_table = flexcan_of_match,
1684 },
1685 .probe = flexcan_probe,
1686 .remove = flexcan_remove,
1687 .id_table = flexcan_id_table,
1688 };
1689
1690 module_platform_driver(flexcan_driver);
1691
1692 MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
1693 "Marc Kleine-Budde <kernel@pengutronix.de>");
1694 MODULE_LICENSE("GPL v2");
1695 MODULE_DESCRIPTION("CAN port driver for flexcan based chip");
Linux with added FPC-III support