1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2018-2019 NXP.
6 * - The TPM counter and period counter are shared between
7 * multiple channels, so all channels should use same period
9 * - Changes to polarity cannot be latched at the time of the
11 * - Changing period and duty cycle together isn't atomic,
12 * with the wrong timing it might happen that a period is
13 * produced with old duty cycle but new period settings.
16 #include <linux/bitfield.h>
17 #include <linux/bitops.h>
18 #include <linux/clk.h>
19 #include <linux/err.h>
21 #include <linux/log2.h>
22 #include <linux/module.h>
24 #include <linux/of_address.h>
25 #include <linux/platform_device.h>
26 #include <linux/pwm.h>
27 #include <linux/slab.h>
29 #define PWM_IMX_TPM_PARAM 0x4
30 #define PWM_IMX_TPM_GLOBAL 0x8
31 #define PWM_IMX_TPM_SC 0x10
32 #define PWM_IMX_TPM_CNT 0x14
33 #define PWM_IMX_TPM_MOD 0x18
34 #define PWM_IMX_TPM_CnSC(n) (0x20 + (n) * 0x8)
35 #define PWM_IMX_TPM_CnV(n) (0x24 + (n) * 0x8)
37 #define PWM_IMX_TPM_PARAM_CHAN GENMASK(7, 0)
39 #define PWM_IMX_TPM_SC_PS GENMASK(2, 0)
40 #define PWM_IMX_TPM_SC_CMOD GENMASK(4, 3)
41 #define PWM_IMX_TPM_SC_CMOD_INC_EVERY_CLK FIELD_PREP(PWM_IMX_TPM_SC_CMOD, 1)
42 #define PWM_IMX_TPM_SC_CPWMS BIT(5)
44 #define PWM_IMX_TPM_CnSC_CHF BIT(7)
45 #define PWM_IMX_TPM_CnSC_MSB BIT(5)
46 #define PWM_IMX_TPM_CnSC_MSA BIT(4)
49 * The reference manual describes this field as two separate bits. The
50 * semantic of the two bits isn't orthogonal though, so they are treated
51 * together as a 2-bit field here.
53 #define PWM_IMX_TPM_CnSC_ELS GENMASK(3, 2)
54 #define PWM_IMX_TPM_CnSC_ELS_INVERSED FIELD_PREP(PWM_IMX_TPM_CnSC_ELS, 1)
55 #define PWM_IMX_TPM_CnSC_ELS_NORMAL FIELD_PREP(PWM_IMX_TPM_CnSC_ELS, 2)
58 #define PWM_IMX_TPM_MOD_WIDTH 16
59 #define PWM_IMX_TPM_MOD_MOD GENMASK(PWM_IMX_TPM_MOD_WIDTH - 1, 0)
61 struct imx_tpm_pwm_chip
{
71 struct imx_tpm_pwm_param
{
77 static inline struct imx_tpm_pwm_chip
*
78 to_imx_tpm_pwm_chip(struct pwm_chip
*chip
)
80 return container_of(chip
, struct imx_tpm_pwm_chip
, chip
);
84 * This function determines for a given pwm_state *state that a consumer
85 * might request the pwm_state *real_state that eventually is implemented
86 * by the hardware and the necessary register values (in *p) to achieve
89 static int pwm_imx_tpm_round_state(struct pwm_chip
*chip
,
90 struct imx_tpm_pwm_param
*p
,
91 struct pwm_state
*real_state
,
92 struct pwm_state
*state
)
94 struct imx_tpm_pwm_chip
*tpm
= to_imx_tpm_pwm_chip(chip
);
95 u32 rate
, prescale
, period_count
, clock_unit
;
98 rate
= clk_get_rate(tpm
->clk
);
99 tmp
= (u64
)state
->period
* rate
;
100 clock_unit
= DIV_ROUND_CLOSEST_ULL(tmp
, NSEC_PER_SEC
);
101 if (clock_unit
<= PWM_IMX_TPM_MOD_MOD
)
104 prescale
= ilog2(clock_unit
) + 1 - PWM_IMX_TPM_MOD_WIDTH
;
106 if ((!FIELD_FIT(PWM_IMX_TPM_SC_PS
, prescale
)))
108 p
->prescale
= prescale
;
110 period_count
= (clock_unit
+ ((1 << prescale
) >> 1)) >> prescale
;
111 p
->mod
= period_count
;
113 /* calculate real period HW can support */
114 tmp
= (u64
)period_count
<< prescale
;
116 real_state
->period
= DIV_ROUND_CLOSEST_ULL(tmp
, rate
);
119 * if eventually the PWM output is inactive, either
120 * duty cycle is 0 or status is disabled, need to
121 * make sure the output pin is inactive.
124 real_state
->duty_cycle
= 0;
126 real_state
->duty_cycle
= state
->duty_cycle
;
128 tmp
= (u64
)p
->mod
* real_state
->duty_cycle
;
129 p
->val
= DIV_ROUND_CLOSEST_ULL(tmp
, real_state
->period
);
131 real_state
->polarity
= state
->polarity
;
132 real_state
->enabled
= state
->enabled
;
137 static void pwm_imx_tpm_get_state(struct pwm_chip
*chip
,
138 struct pwm_device
*pwm
,
139 struct pwm_state
*state
)
141 struct imx_tpm_pwm_chip
*tpm
= to_imx_tpm_pwm_chip(chip
);
142 u32 rate
, val
, prescale
;
146 state
->period
= tpm
->real_period
;
149 rate
= clk_get_rate(tpm
->clk
);
150 val
= readl(tpm
->base
+ PWM_IMX_TPM_SC
);
151 prescale
= FIELD_GET(PWM_IMX_TPM_SC_PS
, val
);
152 tmp
= readl(tpm
->base
+ PWM_IMX_TPM_CnV(pwm
->hwpwm
));
153 tmp
= (tmp
<< prescale
) * NSEC_PER_SEC
;
154 state
->duty_cycle
= DIV_ROUND_CLOSEST_ULL(tmp
, rate
);
157 val
= readl(tpm
->base
+ PWM_IMX_TPM_CnSC(pwm
->hwpwm
));
158 if ((val
& PWM_IMX_TPM_CnSC_ELS
) == PWM_IMX_TPM_CnSC_ELS_INVERSED
)
159 state
->polarity
= PWM_POLARITY_INVERSED
;
162 * Assume reserved values (2b00 and 2b11) to yield
165 state
->polarity
= PWM_POLARITY_NORMAL
;
167 /* get channel status */
168 state
->enabled
= FIELD_GET(PWM_IMX_TPM_CnSC_ELS
, val
) ? true : false;
171 /* this function is supposed to be called with mutex hold */
172 static int pwm_imx_tpm_apply_hw(struct pwm_chip
*chip
,
173 struct imx_tpm_pwm_param
*p
,
174 struct pwm_state
*state
,
175 struct pwm_device
*pwm
)
177 struct imx_tpm_pwm_chip
*tpm
= to_imx_tpm_pwm_chip(chip
);
178 bool period_update
= false;
179 bool duty_update
= false;
180 u32 val
, cmod
, cur_prescale
;
181 unsigned long timeout
;
184 if (state
->period
!= tpm
->real_period
) {
186 * TPM counter is shared by multiple channels, so
187 * prescale and period can NOT be modified when
188 * there are multiple channels in use with different
191 if (tpm
->user_count
> 1)
194 val
= readl(tpm
->base
+ PWM_IMX_TPM_SC
);
195 cmod
= FIELD_GET(PWM_IMX_TPM_SC_CMOD
, val
);
196 cur_prescale
= FIELD_GET(PWM_IMX_TPM_SC_PS
, val
);
197 if (cmod
&& cur_prescale
!= p
->prescale
)
200 /* set TPM counter prescale */
201 val
&= ~PWM_IMX_TPM_SC_PS
;
202 val
|= FIELD_PREP(PWM_IMX_TPM_SC_PS
, p
->prescale
);
203 writel(val
, tpm
->base
+ PWM_IMX_TPM_SC
);
207 * if the PWM is disabled (CMOD[1:0] = 2b00), then MOD register
208 * is updated when MOD register is written.
210 * if the PWM is enabled (CMOD[1:0] ≠ 2b00), the period length
211 * is latched into hardware when the next period starts.
213 writel(p
->mod
, tpm
->base
+ PWM_IMX_TPM_MOD
);
214 tpm
->real_period
= state
->period
;
215 period_update
= true;
218 pwm_imx_tpm_get_state(chip
, pwm
, &c
);
220 /* polarity is NOT allowed to be changed if PWM is active */
221 if (c
.enabled
&& c
.polarity
!= state
->polarity
)
224 if (state
->duty_cycle
!= c
.duty_cycle
) {
227 * if the PWM is disabled (CMOD[1:0] = 2b00), then CnV register
228 * is updated when CnV register is written.
230 * if the PWM is enabled (CMOD[1:0] ≠ 2b00), the duty length
231 * is latched into hardware when the next period starts.
233 writel(p
->val
, tpm
->base
+ PWM_IMX_TPM_CnV(pwm
->hwpwm
));
237 /* make sure MOD & CnV registers are updated */
238 if (period_update
|| duty_update
) {
239 timeout
= jiffies
+ msecs_to_jiffies(tpm
->real_period
/
241 while (readl(tpm
->base
+ PWM_IMX_TPM_MOD
) != p
->mod
242 || readl(tpm
->base
+ PWM_IMX_TPM_CnV(pwm
->hwpwm
))
244 if (time_after(jiffies
, timeout
))
251 * polarity settings will enabled/disable output status
252 * immediately, so if the channel is disabled, need to
253 * make sure MSA/MSB/ELS are set to 0 which means channel
256 val
= readl(tpm
->base
+ PWM_IMX_TPM_CnSC(pwm
->hwpwm
));
257 val
&= ~(PWM_IMX_TPM_CnSC_ELS
| PWM_IMX_TPM_CnSC_MSA
|
258 PWM_IMX_TPM_CnSC_MSB
);
259 if (state
->enabled
) {
261 * set polarity (for edge-aligned PWM modes)
263 * ELS[1:0] = 2b10 yields normal polarity behaviour,
264 * ELS[1:0] = 2b01 yields inversed polarity.
265 * The other values are reserved.
267 val
|= PWM_IMX_TPM_CnSC_MSB
;
268 val
|= (state
->polarity
== PWM_POLARITY_NORMAL
) ?
269 PWM_IMX_TPM_CnSC_ELS_NORMAL
:
270 PWM_IMX_TPM_CnSC_ELS_INVERSED
;
272 writel(val
, tpm
->base
+ PWM_IMX_TPM_CnSC(pwm
->hwpwm
));
274 /* control the counter status */
275 if (state
->enabled
!= c
.enabled
) {
276 val
= readl(tpm
->base
+ PWM_IMX_TPM_SC
);
277 if (state
->enabled
) {
278 if (++tpm
->enable_count
== 1)
279 val
|= PWM_IMX_TPM_SC_CMOD_INC_EVERY_CLK
;
281 if (--tpm
->enable_count
== 0)
282 val
&= ~PWM_IMX_TPM_SC_CMOD
;
284 writel(val
, tpm
->base
+ PWM_IMX_TPM_SC
);
290 static int pwm_imx_tpm_apply(struct pwm_chip
*chip
,
291 struct pwm_device
*pwm
,
292 struct pwm_state
*state
)
294 struct imx_tpm_pwm_chip
*tpm
= to_imx_tpm_pwm_chip(chip
);
295 struct imx_tpm_pwm_param param
;
296 struct pwm_state real_state
;
299 ret
= pwm_imx_tpm_round_state(chip
, ¶m
, &real_state
, state
);
303 mutex_lock(&tpm
->lock
);
304 ret
= pwm_imx_tpm_apply_hw(chip
, ¶m
, &real_state
, pwm
);
305 mutex_unlock(&tpm
->lock
);
310 static int pwm_imx_tpm_request(struct pwm_chip
*chip
, struct pwm_device
*pwm
)
312 struct imx_tpm_pwm_chip
*tpm
= to_imx_tpm_pwm_chip(chip
);
314 mutex_lock(&tpm
->lock
);
316 mutex_unlock(&tpm
->lock
);
321 static void pwm_imx_tpm_free(struct pwm_chip
*chip
, struct pwm_device
*pwm
)
323 struct imx_tpm_pwm_chip
*tpm
= to_imx_tpm_pwm_chip(chip
);
325 mutex_lock(&tpm
->lock
);
327 mutex_unlock(&tpm
->lock
);
330 static const struct pwm_ops imx_tpm_pwm_ops
= {
331 .request
= pwm_imx_tpm_request
,
332 .free
= pwm_imx_tpm_free
,
333 .get_state
= pwm_imx_tpm_get_state
,
334 .apply
= pwm_imx_tpm_apply
,
335 .owner
= THIS_MODULE
,
338 static int pwm_imx_tpm_probe(struct platform_device
*pdev
)
340 struct imx_tpm_pwm_chip
*tpm
;
344 tpm
= devm_kzalloc(&pdev
->dev
, sizeof(*tpm
), GFP_KERNEL
);
348 platform_set_drvdata(pdev
, tpm
);
350 tpm
->base
= devm_platform_ioremap_resource(pdev
, 0);
351 if (IS_ERR(tpm
->base
))
352 return PTR_ERR(tpm
->base
);
354 tpm
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
355 if (IS_ERR(tpm
->clk
)) {
356 ret
= PTR_ERR(tpm
->clk
);
357 if (ret
!= -EPROBE_DEFER
)
359 "failed to get PWM clock: %d\n", ret
);
363 ret
= clk_prepare_enable(tpm
->clk
);
366 "failed to prepare or enable clock: %d\n", ret
);
370 tpm
->chip
.dev
= &pdev
->dev
;
371 tpm
->chip
.ops
= &imx_tpm_pwm_ops
;
373 tpm
->chip
.of_xlate
= of_pwm_xlate_with_flags
;
374 tpm
->chip
.of_pwm_n_cells
= 3;
376 /* get number of channels */
377 val
= readl(tpm
->base
+ PWM_IMX_TPM_PARAM
);
378 tpm
->chip
.npwm
= FIELD_GET(PWM_IMX_TPM_PARAM_CHAN
, val
);
380 mutex_init(&tpm
->lock
);
382 ret
= pwmchip_add(&tpm
->chip
);
384 dev_err(&pdev
->dev
, "failed to add PWM chip: %d\n", ret
);
385 clk_disable_unprepare(tpm
->clk
);
391 static int pwm_imx_tpm_remove(struct platform_device
*pdev
)
393 struct imx_tpm_pwm_chip
*tpm
= platform_get_drvdata(pdev
);
394 int ret
= pwmchip_remove(&tpm
->chip
);
396 clk_disable_unprepare(tpm
->clk
);
401 static int __maybe_unused
pwm_imx_tpm_suspend(struct device
*dev
)
403 struct imx_tpm_pwm_chip
*tpm
= dev_get_drvdata(dev
);
405 if (tpm
->enable_count
> 0)
408 clk_disable_unprepare(tpm
->clk
);
413 static int __maybe_unused
pwm_imx_tpm_resume(struct device
*dev
)
415 struct imx_tpm_pwm_chip
*tpm
= dev_get_drvdata(dev
);
418 ret
= clk_prepare_enable(tpm
->clk
);
421 "failed to prepare or enable clock: %d\n",
427 static SIMPLE_DEV_PM_OPS(imx_tpm_pwm_pm
,
428 pwm_imx_tpm_suspend
, pwm_imx_tpm_resume
);
430 static const struct of_device_id imx_tpm_pwm_dt_ids
[] = {
431 { .compatible
= "fsl,imx7ulp-pwm", },
434 MODULE_DEVICE_TABLE(of
, imx_tpm_pwm_dt_ids
);
436 static struct platform_driver imx_tpm_pwm_driver
= {
438 .name
= "imx7ulp-tpm-pwm",
439 .of_match_table
= imx_tpm_pwm_dt_ids
,
440 .pm
= &imx_tpm_pwm_pm
,
442 .probe
= pwm_imx_tpm_probe
,
443 .remove
= pwm_imx_tpm_remove
,
445 module_platform_driver(imx_tpm_pwm_driver
);
447 MODULE_AUTHOR("Anson Huang <Anson.Huang@nxp.com>");
448 MODULE_DESCRIPTION("i.MX TPM PWM Driver");
449 MODULE_LICENSE("GPL v2");