drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Mediatek MT7621 PCI PHY Driver
   4  * Author: Sergio Paracuellos <sergio.paracuellos@gmail.com>
   5  */
   6
   7 #include <dt-bindings/phy/phy.h>
   8 #include <linux/bitops.h>
   9 #include <linux/module.h>
  10 #include <linux/of_address.h>
  11 #include <linux/of_device.h>
  12 #include <linux/phy/phy.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/regmap.h>
  15 #include <linux/sys_soc.h>
  16 #include <mt7621.h>
  17 #include <ralink_regs.h>
  18
  19 #define RALINK_CLKCFG1                          0x30
  20
  21 #define PCIE_PORT_CLK_EN(x)                     BIT(24 + (x))
  22
  23 #define RG_PE1_PIPE_REG                         0x02c
  24 #define RG_PE1_PIPE_RST                         BIT(12)
  25 #define RG_PE1_PIPE_CMD_FRC                     BIT(4)
  26
  27 #define RG_P0_TO_P1_WIDTH                       0x100
  28 #define RG_PE1_H_LCDDS_REG                      0x49c
  29 #define RG_PE1_H_LCDDS_PCW                      GENMASK(30, 0)
  30 #define RG_PE1_H_LCDDS_PCW_VAL(x)               ((0x7fffffff & (x)) << 0)
  31
  32 #define RG_PE1_FRC_H_XTAL_REG                   0x400
  33 #define RG_PE1_FRC_H_XTAL_TYPE                  BIT(8)
  34 #define RG_PE1_H_XTAL_TYPE                      GENMASK(10, 9)
  35 #define RG_PE1_H_XTAL_TYPE_VAL(x)               ((0x3 & (x)) << 9)
  36
  37 #define RG_PE1_FRC_PHY_REG                      0x000
  38 #define RG_PE1_FRC_PHY_EN                       BIT(4)
  39 #define RG_PE1_PHY_EN                           BIT(5)
  40
  41 #define RG_PE1_H_PLL_REG                        0x490
  42 #define RG_PE1_H_PLL_BC                         GENMASK(23, 22)
  43 #define RG_PE1_H_PLL_BC_VAL(x)                  ((0x3 & (x)) << 22)
  44 #define RG_PE1_H_PLL_BP                         GENMASK(21, 18)
  45 #define RG_PE1_H_PLL_BP_VAL(x)                  ((0xf & (x)) << 18)
  46 #define RG_PE1_H_PLL_IR                         GENMASK(15, 12)
  47 #define RG_PE1_H_PLL_IR_VAL(x)                  ((0xf & (x)) << 12)
  48 #define RG_PE1_H_PLL_IC                         GENMASK(11, 8)
  49 #define RG_PE1_H_PLL_IC_VAL(x)                  ((0xf & (x)) << 8)
  50 #define RG_PE1_H_PLL_PREDIV                     GENMASK(7, 6)
  51 #define RG_PE1_H_PLL_PREDIV_VAL(x)              ((0x3 & (x)) << 6)
  52 #define RG_PE1_PLL_DIVEN                        GENMASK(3, 1)
  53 #define RG_PE1_PLL_DIVEN_VAL(x)                 ((0x7 & (x)) << 1)
  54
  55 #define RG_PE1_H_PLL_FBKSEL_REG                 0x4bc
  56 #define RG_PE1_H_PLL_FBKSEL                     GENMASK(5, 4)
  57 #define RG_PE1_H_PLL_FBKSEL_VAL(x)              ((0x3 & (x)) << 4)
  58
  59 #define RG_PE1_H_LCDDS_SSC_PRD_REG              0x4a4
  60 #define RG_PE1_H_LCDDS_SSC_PRD                  GENMASK(15, 0)
  61 #define RG_PE1_H_LCDDS_SSC_PRD_VAL(x)           ((0xffff & (x)) << 0)
  62
  63 #define RG_PE1_H_LCDDS_SSC_DELTA_REG            0x4a8
  64 #define RG_PE1_H_LCDDS_SSC_DELTA                GENMASK(11, 0)
  65 #define RG_PE1_H_LCDDS_SSC_DELTA_VAL(x)         ((0xfff & (x)) << 0)
  66 #define RG_PE1_H_LCDDS_SSC_DELTA1               GENMASK(27, 16)
  67 #define RG_PE1_H_LCDDS_SSC_DELTA1_VAL(x)        ((0xff & (x)) << 16)
  68
  69 #define RG_PE1_LCDDS_CLK_PH_INV_REG             0x4a0
  70 #define RG_PE1_LCDDS_CLK_PH_INV                 BIT(5)
  71
  72 #define RG_PE1_H_PLL_BR_REG                     0x4ac
  73 #define RG_PE1_H_PLL_BR                         GENMASK(18, 16)
  74 #define RG_PE1_H_PLL_BR_VAL(x)                  ((0x7 & (x)) << 16)
  75
  76 #define RG_PE1_MSTCKDIV_REG                     0x414
  77 #define RG_PE1_MSTCKDIV                         GENMASK(7, 6)
  78 #define RG_PE1_MSTCKDIV_VAL(x)                  ((0x3 & (x)) << 6)
  79
  80 #define RG_PE1_FRC_MSTCKDIV                     BIT(5)
  81
  82 #define MAX_PHYS        2
  83
  84 /**
  85  * struct mt7621_pci_phy_instance - Mt7621 Pcie PHY device
  86  * @phy: pointer to the kernel PHY device
  87  * @port_base: base register
  88  * @index: internal ID to identify the Mt7621 PCIe PHY
  89  */
  90 struct mt7621_pci_phy_instance {
  91         struct phy *phy;
  92         void __iomem *port_base;
  93         u32 index;
  94 };
  95
  96 /**
  97  * struct mt7621_pci_phy - Mt7621 Pcie PHY core
  98  * @dev: pointer to device
  99  * @regmap: kernel regmap pointer
 100  * @phys: pointer to Mt7621 PHY device
 101  * @nphys: number of PHY devices for this core
 102  * @bypass_pipe_rst: mark if 'mt7621_bypass_pipe_rst'
 103  * needs to be executed. Depends on chip revision.
 104  */
 105 struct mt7621_pci_phy {
 106         struct device *dev;
 107         struct regmap *regmap;
 108         struct mt7621_pci_phy_instance **phys;
 109         int nphys;
 110         bool bypass_pipe_rst;
 111 };
 112
 113 static inline u32 phy_read(struct mt7621_pci_phy *phy, u32 reg)
 114 {
 115         u32 val;
 116
 117         regmap_read(phy->regmap, reg, &val);
 118
 119         return val;
 120 }
 121
 122 static inline void phy_write(struct mt7621_pci_phy *phy, u32 val, u32 reg)
 123 {
 124         regmap_write(phy->regmap, reg, val);
 125 }
 126
 127 static void mt7621_bypass_pipe_rst(struct mt7621_pci_phy *phy,
 128                                    struct mt7621_pci_phy_instance *instance)
 129 {
 130         u32 offset = (instance->index != 1) ?
 131                 RG_PE1_PIPE_REG : RG_PE1_PIPE_REG + RG_P0_TO_P1_WIDTH;
 132         u32 reg;
 133
 134         reg = phy_read(phy, offset);
 135         reg &= ~(RG_PE1_PIPE_RST | RG_PE1_PIPE_CMD_FRC);
 136         reg |= (RG_PE1_PIPE_RST | RG_PE1_PIPE_CMD_FRC);
 137         phy_write(phy, reg, offset);
 138 }
 139
 140 static void mt7621_set_phy_for_ssc(struct mt7621_pci_phy *phy,
 141                                    struct mt7621_pci_phy_instance *instance)
 142 {
 143         struct device *dev = phy->dev;
 144         u32 reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0);
 145         u32 offset;
 146         u32 val;
 147
 148         reg = (reg >> 6) & 0x7;
 149         /* Set PCIe Port PHY to disable SSC */
 150         /* Debug Xtal Type */
 151         val = phy_read(phy, RG_PE1_FRC_H_XTAL_REG);
 152         val &= ~(RG_PE1_FRC_H_XTAL_TYPE | RG_PE1_H_XTAL_TYPE);
 153         val |= RG_PE1_FRC_H_XTAL_TYPE;
 154         val |= RG_PE1_H_XTAL_TYPE_VAL(0x00);
 155         phy_write(phy, val, RG_PE1_FRC_H_XTAL_REG);
 156
 157         /* disable port */
 158         offset = (instance->index != 1) ?
 159                 RG_PE1_FRC_PHY_REG : RG_PE1_FRC_PHY_REG + RG_P0_TO_P1_WIDTH;
 160         val = phy_read(phy, offset);
 161         val &= ~(RG_PE1_FRC_PHY_EN | RG_PE1_PHY_EN);
 162         val |= RG_PE1_FRC_PHY_EN;
 163         phy_write(phy, val, offset);
 164
 165         /* Set Pre-divider ratio (for host mode) */
 166         val = phy_read(phy, RG_PE1_H_PLL_REG);
 167         val &= ~(RG_PE1_H_PLL_PREDIV);
 168
 169         if (reg <= 5 && reg >= 3) { /* 40MHz Xtal */
 170                 val |= RG_PE1_H_PLL_PREDIV_VAL(0x01);
 171                 phy_write(phy, val, RG_PE1_H_PLL_REG);
 172                 dev_info(dev, "Xtal is 40MHz\n");
 173         } else { /* 25MHz | 20MHz Xtal */
 174                 val |= RG_PE1_H_PLL_PREDIV_VAL(0x00);
 175                 phy_write(phy, val, RG_PE1_H_PLL_REG);
 176                 if (reg >= 6) {
 177                         dev_info(dev, "Xtal is 25MHz\n");
 178
 179                         /* Select feedback clock */
 180                         val = phy_read(phy, RG_PE1_H_PLL_FBKSEL_REG);
 181                         val &= ~(RG_PE1_H_PLL_FBKSEL);
 182                         val |= RG_PE1_H_PLL_FBKSEL_VAL(0x01);
 183                         phy_write(phy, val, RG_PE1_H_PLL_FBKSEL_REG);
 184
 185                         /* DDS NCPO PCW (for host mode) */
 186                         val = phy_read(phy, RG_PE1_H_LCDDS_SSC_PRD_REG);
 187                         val &= ~(RG_PE1_H_LCDDS_SSC_PRD);
 188                         val |= RG_PE1_H_LCDDS_SSC_PRD_VAL(0x18000000);
 189                         phy_write(phy, val, RG_PE1_H_LCDDS_SSC_PRD_REG);
 190
 191                         /* DDS SSC dither period control */
 192                         val = phy_read(phy, RG_PE1_H_LCDDS_SSC_PRD_REG);
 193                         val &= ~(RG_PE1_H_LCDDS_SSC_PRD);
 194                         val |= RG_PE1_H_LCDDS_SSC_PRD_VAL(0x18d);
 195                         phy_write(phy, val, RG_PE1_H_LCDDS_SSC_PRD_REG);
 196
 197                         /* DDS SSC dither amplitude control */
 198                         val = phy_read(phy, RG_PE1_H_LCDDS_SSC_DELTA_REG);
 199                         val &= ~(RG_PE1_H_LCDDS_SSC_DELTA |
 200                                  RG_PE1_H_LCDDS_SSC_DELTA1);
 201                         val |= RG_PE1_H_LCDDS_SSC_DELTA_VAL(0x4a);
 202                         val |= RG_PE1_H_LCDDS_SSC_DELTA1_VAL(0x4a);
 203                         phy_write(phy, val, RG_PE1_H_LCDDS_SSC_DELTA_REG);
 204                 } else {
 205                         dev_info(dev, "Xtal is 20MHz\n");
 206                 }
 207         }
 208
 209         /* DDS clock inversion */
 210         val = phy_read(phy, RG_PE1_LCDDS_CLK_PH_INV_REG);
 211         val &= ~(RG_PE1_LCDDS_CLK_PH_INV);
 212         val |= RG_PE1_LCDDS_CLK_PH_INV;
 213         phy_write(phy, val, RG_PE1_LCDDS_CLK_PH_INV_REG);
 214
 215         /* Set PLL bits */
 216         val = phy_read(phy, RG_PE1_H_PLL_REG);
 217         val &= ~(RG_PE1_H_PLL_BC | RG_PE1_H_PLL_BP | RG_PE1_H_PLL_IR |
 218                  RG_PE1_H_PLL_IC | RG_PE1_PLL_DIVEN);
 219         val |= RG_PE1_H_PLL_BC_VAL(0x02);
 220         val |= RG_PE1_H_PLL_BP_VAL(0x06);
 221         val |= RG_PE1_H_PLL_IR_VAL(0x02);
 222         val |= RG_PE1_H_PLL_IC_VAL(0x01);
 223         val |= RG_PE1_PLL_DIVEN_VAL(0x02);
 224         phy_write(phy, val, RG_PE1_H_PLL_REG);
 225
 226         val = phy_read(phy, RG_PE1_H_PLL_BR_REG);
 227         val &= ~(RG_PE1_H_PLL_BR);
 228         val |= RG_PE1_H_PLL_BR_VAL(0x00);
 229         phy_write(phy, val, RG_PE1_H_PLL_BR_REG);
 230
 231         if (reg <= 5 && reg >= 3) { /* 40MHz Xtal */
 232                 /* set force mode enable of da_pe1_mstckdiv */
 233                 val = phy_read(phy, RG_PE1_MSTCKDIV_REG);
 234                 val &= ~(RG_PE1_MSTCKDIV | RG_PE1_FRC_MSTCKDIV);
 235                 val |= (RG_PE1_MSTCKDIV_VAL(0x01) | RG_PE1_FRC_MSTCKDIV);
 236                 phy_write(phy, val, RG_PE1_MSTCKDIV_REG);
 237         }
 238 }
 239
 240 static int mt7621_pci_phy_init(struct phy *phy)
 241 {
 242         struct mt7621_pci_phy_instance *instance = phy_get_drvdata(phy);
 243         struct mt7621_pci_phy *mphy = dev_get_drvdata(phy->dev.parent);
 244
 245         if (mphy->bypass_pipe_rst)
 246                 mt7621_bypass_pipe_rst(mphy, instance);
 247
 248         mt7621_set_phy_for_ssc(mphy, instance);
 249
 250         return 0;
 251 }
 252
 253 static int mt7621_pci_phy_power_on(struct phy *phy)
 254 {
 255         struct mt7621_pci_phy_instance *instance = phy_get_drvdata(phy);
 256         struct mt7621_pci_phy *mphy = dev_get_drvdata(phy->dev.parent);
 257         u32 offset = (instance->index != 1) ?
 258                 RG_PE1_FRC_PHY_REG : RG_PE1_FRC_PHY_REG + RG_P0_TO_P1_WIDTH;
 259         u32 val;
 260
 261         /* Enable PHY and disable force mode */
 262         val = phy_read(mphy, offset);
 263         val &= ~(RG_PE1_FRC_PHY_EN | RG_PE1_PHY_EN);
 264         val |= (RG_PE1_FRC_PHY_EN | RG_PE1_PHY_EN);
 265         phy_write(mphy, val, offset);
 266
 267         return 0;
 268 }
 269
 270 static int mt7621_pci_phy_power_off(struct phy *phy)
 271 {
 272         struct mt7621_pci_phy_instance *instance = phy_get_drvdata(phy);
 273         struct mt7621_pci_phy *mphy = dev_get_drvdata(phy->dev.parent);
 274         u32 offset = (instance->index != 1) ?
 275                 RG_PE1_FRC_PHY_REG : RG_PE1_FRC_PHY_REG + RG_P0_TO_P1_WIDTH;
 276         u32 val;
 277
 278         /* Disable PHY */
 279         val = phy_read(mphy, offset);
 280         val &= ~(RG_PE1_FRC_PHY_EN | RG_PE1_PHY_EN);
 281         val |= RG_PE1_FRC_PHY_EN;
 282         phy_write(mphy, val, offset);
 283
 284         return 0;
 285 }
 286
 287 static int mt7621_pci_phy_exit(struct phy *phy)
 288 {
 289         struct mt7621_pci_phy_instance *instance = phy_get_drvdata(phy);
 290
 291         rt_sysc_m32(PCIE_PORT_CLK_EN(instance->index), 0, RALINK_CLKCFG1);
 292
 293         return 0;
 294 }
 295
 296 static const struct phy_ops mt7621_pci_phy_ops = {
 297         .init           = mt7621_pci_phy_init,
 298         .exit           = mt7621_pci_phy_exit,
 299         .power_on       = mt7621_pci_phy_power_on,
 300         .power_off      = mt7621_pci_phy_power_off,
 301         .owner          = THIS_MODULE,
 302 };
 303
 304 static struct phy *mt7621_pcie_phy_of_xlate(struct device *dev,
 305                                             struct of_phandle_args *args)
 306 {
 307         struct mt7621_pci_phy *mt7621_phy = dev_get_drvdata(dev);
 308
 309         if (args->args_count == 0)
 310                 return mt7621_phy->phys[0]->phy;
 311
 312         if (WARN_ON(args->args[0] >= MAX_PHYS))
 313                 return ERR_PTR(-ENODEV);
 314
 315         return mt7621_phy->phys[args->args[0]]->phy;
 316 }
 317
 318 static const struct soc_device_attribute mt7621_pci_quirks_match[] = {
 319         { .soc_id = "mt7621", .revision = "E2" }
 320 };
 321
 322 static const struct regmap_config mt7621_pci_phy_regmap_config = {
 323         .reg_bits = 32,
 324         .val_bits = 32,
 325         .reg_stride = 4,
 326         .max_register = 0x700,
 327 };
 328
 329 static int mt7621_pci_phy_probe(struct platform_device *pdev)
 330 {
 331         struct device *dev = &pdev->dev;
 332         const struct soc_device_attribute *attr;
 333         struct phy_provider *provider;
 334         struct mt7621_pci_phy *phy;
 335         struct resource *res;
 336         int port;
 337         void __iomem *port_base;
 338
 339         phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
 340         if (!phy)
 341                 return -ENOMEM;
 342
 343         phy->nphys = MAX_PHYS;
 344         phy->phys = devm_kcalloc(dev, phy->nphys,
 345                                  sizeof(*phy->phys), GFP_KERNEL);
 346         if (!phy->phys)
 347                 return -ENOMEM;
 348
 349         attr = soc_device_match(mt7621_pci_quirks_match);
 350         if (attr)
 351                 phy->bypass_pipe_rst = true;
 352
 353         phy->dev = dev;
 354         platform_set_drvdata(pdev, phy);
 355
 356         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 357         if (!res) {
 358                 dev_err(dev, "failed to get address resource\n");
 359                 return -ENXIO;
 360         }
 361
 362         port_base = devm_ioremap_resource(dev, res);
 363         if (IS_ERR(port_base)) {
 364                 dev_err(dev, "failed to remap phy regs\n");
 365                 return PTR_ERR(port_base);
 366         }
 367
 368         phy->regmap = devm_regmap_init_mmio(phy->dev, port_base,
 369                                             &mt7621_pci_phy_regmap_config);
 370         if (IS_ERR(phy->regmap))
 371                 return PTR_ERR(phy->regmap);
 372
 373         for (port = 0; port < MAX_PHYS; port++) {
 374                 struct mt7621_pci_phy_instance *instance;
 375                 struct phy *pphy;
 376
 377                 instance = devm_kzalloc(dev, sizeof(*instance), GFP_KERNEL);
 378                 if (!instance)
 379                         return -ENOMEM;
 380
 381                 phy->phys[port] = instance;
 382
 383                 pphy = devm_phy_create(dev, dev->of_node, &mt7621_pci_phy_ops);
 384                 if (IS_ERR(phy)) {
 385                         dev_err(dev, "failed to create phy\n");
 386                         return PTR_ERR(phy);
 387                 }
 388
 389                 instance->port_base = port_base;
 390                 instance->phy = pphy;
 391                 instance->index = port;
 392                 phy_set_drvdata(pphy, instance);
 393         }
 394
 395         provider = devm_of_phy_provider_register(dev, mt7621_pcie_phy_of_xlate);
 396
 397         return PTR_ERR_OR_ZERO(provider);
 398 }
 399
 400 static const struct of_device_id mt7621_pci_phy_ids[] = {
 401         { .compatible = "mediatek,mt7621-pci-phy" },
 402         {},
 403 };
 404 MODULE_DEVICE_TABLE(of, mt7621_pci_ids);
 405
 406 static struct platform_driver mt7621_pci_phy_driver = {
 407         .probe = mt7621_pci_phy_probe,
 408         .driver = {
 409                 .name = "mt7621-pci-phy",
 410                 .of_match_table = of_match_ptr(mt7621_pci_phy_ids),
 411         },
 412 };
 413
 414 static int __init mt7621_pci_phy_drv_init(void)
 415 {
 416         return platform_driver_register(&mt7621_pci_phy_driver);
 417 }
 418
 419 module_init(mt7621_pci_phy_drv_init);
 420
 421 MODULE_AUTHOR("Sergio Paracuellos <sergio.paracuellos@gmail.com>");
 422 MODULE_DESCRIPTION("MediaTek MT7621 PCIe PHY driver");
 423 MODULE_LICENSE("GPL v2");