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Merge tag 'for-linus-20190706' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / staging / mt7621-pci / pci-mt7621.c
blob03d919a945521345bd0270bc4ce3dbd702913864
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * BRIEF MODULE DESCRIPTION
4 * PCI init for Ralink RT2880 solution
5 *
6 * Copyright 2007 Ralink Inc. (bruce_chang@ralinktech.com.tw)
7 *
8 * May 2007 Bruce Chang
9 * Initial Release
10 *
11 * May 2009 Bruce Chang
12 * support RT2880/RT3883 PCIe
13 *
14 * May 2011 Bruce Chang
15 * support RT6855/MT7620 PCIe
16 */
17
18 #include <linux/bitops.h>
19 #include <linux/delay.h>
20 #include <linux/iopoll.h>
21 #include <linux/module.h>
22 #include <linux/of.h>
23 #include <linux/of_address.h>
24 #include <linux/of_irq.h>
25 #include <linux/of_pci.h>
26 #include <linux/of_platform.h>
27 #include <linux/pci.h>
28 #include <linux/phy/phy.h>
29 #include <linux/platform_device.h>
30 #include <linux/reset.h>
31 #include <mt7621.h>
32 #include <ralink_regs.h>
33
34 #include "../../pci/pci.h"
35
36 /* sysctl */
37 #define MT7621_CHIP_REV_ID 0x0c
38 #define CHIP_REV_MT7621_E2 0x0101
39
40 /* MediaTek specific configuration registers */
41 #define PCIE_FTS_NUM 0x70c
42 #define PCIE_FTS_NUM_MASK GENMASK(15, 8)
43 #define PCIE_FTS_NUM_L0(x) ((x) & 0xff << 8)
44
45 /* rt_sysc_membase relative registers */
46 #define RALINK_PCIE_CLK_GEN 0x7c
47 #define RALINK_PCIE_CLK_GEN1 0x80
48
49 /* Host-PCI bridge registers */
50 #define RALINK_PCI_PCICFG_ADDR 0x0000
51 #define RALINK_PCI_PCIMSK_ADDR 0x000C
52 #define RALINK_PCI_CONFIG_ADDR 0x0020
53 #define RALINK_PCI_CONFIG_DATA 0x0024
54 #define RALINK_PCI_MEMBASE 0x0028
55 #define RALINK_PCI_IOBASE 0x002C
56
57 /* PCICFG virtual bridges */
58 #define MT7621_BR0_MASK GENMASK(19, 16)
59 #define MT7621_BR1_MASK GENMASK(23, 20)
60 #define MT7621_BR2_MASK GENMASK(27, 24)
61 #define MT7621_BR_ALL_MASK GENMASK(27, 16)
62 #define MT7621_BR0_SHIFT 16
63 #define MT7621_BR1_SHIFT 20
64 #define MT7621_BR2_SHIFT 24
65
66 /* PCIe RC control registers */
67 #define MT7621_PCIE_OFFSET 0x2000
68 #define MT7621_NEXT_PORT 0x1000
69
70 #define RALINK_PCI_BAR0SETUP_ADDR 0x0010
71 #define RALINK_PCI_IMBASEBAR0_ADDR 0x0018
72 #define RALINK_PCI_ID 0x0030
73 #define RALINK_PCI_CLASS 0x0034
74 #define RALINK_PCI_SUBID 0x0038
75 #define RALINK_PCI_STATUS 0x0050
76
77 /* Some definition values */
78 #define PCIE_REVISION_ID BIT(0)
79 #define PCIE_CLASS_CODE (0x60400 << 8)
80 #define PCIE_BAR_MAP_MAX GENMASK(30, 16)
81 #define PCIE_BAR_ENABLE BIT(0)
82 #define PCIE_PORT_INT_EN(x) BIT(20 + (x))
83 #define PCIE_PORT_CLK_EN(x) BIT(24 + (x))
84 #define PCIE_PORT_PERST(x) BIT(1 + (x))
85 #define PCIE_PORT_LINKUP BIT(0)
86
87 #define PCIE_CLK_GEN_EN BIT(31)
88 #define PCIE_CLK_GEN_DIS 0
89 #define PCIE_CLK_GEN1_DIS GENMASK(30, 24)
90 #define PCIE_CLK_GEN1_EN (BIT(27) | BIT(25))
91 #define MEMORY_BASE 0x0
92
93 /**
94 * struct mt7621_pcie_port - PCIe port information
95 * @base: I/O mapped register base
96 * @list: port list
97 * @pcie: pointer to PCIe host info
98 * @phy: pointer to PHY control block
99 * @pcie_rst: pointer to port reset control
100 * @slot: port slot
101 * @enabled: indicates if port is enabled
102 */
103 struct mt7621_pcie_port {
104 void __iomem *base;
105 struct list_head list;
106 struct mt7621_pcie *pcie;
107 struct phy *phy;
108 struct reset_control *pcie_rst;
109 u32 slot;
110 bool enabled;
111 };
112
113 /**
114 * struct mt7621_pcie - PCIe host information
115 * @base: IO Mapped Register Base
116 * @io: IO resource
117 * @mem: non-prefetchable memory resource
118 * @busn: bus range
119 * @offset: IO / Memory offset
120 * @dev: Pointer to PCIe device
121 * @ports: pointer to PCIe port information
122 * @rst: pointer to pcie reset
123 */
124 struct mt7621_pcie {
125 void __iomem *base;
126 struct device *dev;
127 struct resource io;
128 struct resource mem;
129 struct resource busn;
130 struct {
131 resource_size_t mem;
132 resource_size_t io;
133 } offset;
134 struct list_head ports;
135 struct reset_control *rst;
136 };
137
138 static inline u32 pcie_read(struct mt7621_pcie *pcie, u32 reg)
139 {
140 return readl(pcie->base + reg);
141 }
142
143 static inline void pcie_write(struct mt7621_pcie *pcie, u32 val, u32 reg)
144 {
145 writel(val, pcie->base + reg);
146 }
147
148 static inline u32 pcie_port_read(struct mt7621_pcie_port *port, u32 reg)
149 {
150 return readl(port->base + reg);
151 }
152
153 static inline void pcie_port_write(struct mt7621_pcie_port *port,
154 u32 val, u32 reg)
155 {
156 writel(val, port->base + reg);
157 }
158
159 static inline u32 mt7621_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
160 unsigned int func, unsigned int where)
161 {
162 return (((where & 0xF00) >> 8) << 24) | (bus << 16) | (slot << 11) |
163 (func << 8) | (where & 0xfc) | 0x80000000;
164 }
165
166 static void __iomem *mt7621_pcie_map_bus(struct pci_bus *bus,
167 unsigned int devfn, int where)
168 {
169 struct mt7621_pcie *pcie = bus->sysdata;
170 u32 address = mt7621_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
171 PCI_FUNC(devfn), where);
172
173 writel(address, pcie->base + RALINK_PCI_CONFIG_ADDR);
174
175 return pcie->base + RALINK_PCI_CONFIG_DATA + (where & 3);
176 }
177
178 struct pci_ops mt7621_pci_ops = {
179 .map_bus = mt7621_pcie_map_bus,
180 .read = pci_generic_config_read,
181 .write = pci_generic_config_write,
182 };
183
184 static u32 read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg)
185 {
186 u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
187
188 pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
189 return pcie_read(pcie, RALINK_PCI_CONFIG_DATA);
190 }
191
192 static void write_config(struct mt7621_pcie *pcie, unsigned int dev,
193 u32 reg, u32 val)
194 {
195 u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
196
197 pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
198 pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA);
199 }
200
201 static inline void mt7621_control_assert(struct mt7621_pcie_port *port)
202 {
203 u32 chip_rev_id = rt_sysc_r32(MT7621_CHIP_REV_ID);
204
205 if ((chip_rev_id & 0xFFFF) == CHIP_REV_MT7621_E2)
206 reset_control_assert(port->pcie_rst);
207 else
208 reset_control_deassert(port->pcie_rst);
209 }
210
211 static inline void mt7621_control_deassert(struct mt7621_pcie_port *port)
212 {
213 u32 chip_rev_id = rt_sysc_r32(MT7621_CHIP_REV_ID);
214
215 if ((chip_rev_id & 0xFFFF) == CHIP_REV_MT7621_E2)
216 reset_control_deassert(port->pcie_rst);
217 else
218 reset_control_assert(port->pcie_rst);
219 }
220
221 static void mt7621_reset_port(struct mt7621_pcie_port *port)
222 {
223 mt7621_control_assert(port);
224 msleep(100);
225 mt7621_control_deassert(port);
226 }
227
228 static void setup_cm_memory_region(struct mt7621_pcie *pcie)
229 {
230 struct resource *mem_resource = &pcie->mem;
231 struct device *dev = pcie->dev;
232 resource_size_t mask;
233
234 if (mips_cps_numiocu(0)) {
235 /*
236 * FIXME: hardware doesn't accept mask values with 1s after
237 * 0s (e.g. 0xffef), so it would be great to warn if that's
238 * about to happen
239 */
240 mask = ~(mem_resource->end - mem_resource->start);
241
242 write_gcr_reg1_base(mem_resource->start);
243 write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);
244 dev_info(dev, "PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\n",
245 (unsigned long long)read_gcr_reg1_base(),
246 (unsigned long long)read_gcr_reg1_mask());
247 }
248 }
249
250 static int mt7621_pci_parse_request_of_pci_ranges(struct mt7621_pcie *pcie)
251 {
252 struct device *dev = pcie->dev;
253 struct device_node *node = dev->of_node;
254 struct of_pci_range_parser parser;
255 struct of_pci_range range;
256 int err;
257
258 if (of_pci_range_parser_init(&parser, node)) {
259 dev_err(dev, "missing \"ranges\" property\n");
260 return -EINVAL;
261 }
262
263 for_each_of_pci_range(&parser, &range) {
264 struct resource *res = NULL;
265
266 switch (range.flags & IORESOURCE_TYPE_BITS) {
267 case IORESOURCE_IO:
268 ioremap(range.cpu_addr, range.size);
269 res = &pcie->io;
270 pcie->offset.io = 0x00000000UL;
271 break;
272 case IORESOURCE_MEM:
273 res = &pcie->mem;
274 pcie->offset.mem = 0x00000000UL;
275 break;
276 }
277
278 if (res)
279 of_pci_range_to_resource(&range, node, res);
280 }
281
282 err = of_pci_parse_bus_range(node, &pcie->busn);
283 if (err < 0) {
284 dev_err(dev, "failed to parse bus ranges property: %d\n", err);
285 pcie->busn.name = node->name;
286 pcie->busn.start = 0;
287 pcie->busn.end = 0xff;
288 pcie->busn.flags = IORESOURCE_BUS;
289 }
290
291 return 0;
292 }
293
294 static int mt7621_pcie_parse_port(struct mt7621_pcie *pcie,
295 struct device_node *node,
296 int slot)
297 {
298 struct mt7621_pcie_port *port;
299 struct device *dev = pcie->dev;
300 struct device_node *pnode = dev->of_node;
301 struct resource regs;
302 char name[10];
303 int err;
304
305 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
306 if (!port)
307 return -ENOMEM;
308
309 err = of_address_to_resource(pnode, slot + 1, &regs);
310 if (err) {
311 dev_err(dev, "missing \"reg\" property\n");
312 return err;
313 }
314
315 port->base = devm_ioremap_resource(dev, &regs);
316 if (IS_ERR(port->base))
317 return PTR_ERR(port->base);
318
319 snprintf(name, sizeof(name), "pcie%d", slot);
320 port->pcie_rst = devm_reset_control_get_exclusive(dev, name);
321 if (PTR_ERR(port->pcie_rst) == -EPROBE_DEFER) {
322 dev_err(dev, "failed to get pcie%d reset control\n", slot);
323 return PTR_ERR(port->pcie_rst);
324 }
325
326 snprintf(name, sizeof(name), "pcie-phy%d", slot);
327 port->phy = devm_phy_get(dev, name);
328 if (IS_ERR(port->phy))
329 return PTR_ERR(port->phy);
330
331 port->slot = slot;
332 port->pcie = pcie;
333
334 INIT_LIST_HEAD(&port->list);
335 list_add_tail(&port->list, &pcie->ports);
336
337 return 0;
338 }
339
340 static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie)
341 {
342 struct device *dev = pcie->dev;
343 struct device_node *node = dev->of_node, *child;
344 struct resource regs;
345 int err;
346
347 err = of_address_to_resource(node, 0, &regs);
348 if (err) {
349 dev_err(dev, "missing \"reg\" property\n");
350 return err;
351 }
352
353 pcie->base = devm_ioremap_resource(dev, &regs);
354 if (IS_ERR(pcie->base))
355 return PTR_ERR(pcie->base);
356
357 pcie->rst = devm_reset_control_get_exclusive(dev, "pcie");
358 if (PTR_ERR(pcie->rst) == -EPROBE_DEFER) {
359 dev_err(dev, "failed to get pcie reset control\n");
360 return PTR_ERR(pcie->rst);
361 }
362
363 for_each_available_child_of_node(node, child) {
364 int slot;
365
366 err = of_pci_get_devfn(child);
367 if (err < 0) {
368 dev_err(dev, "failed to parse devfn: %d\n", err);
369 return err;
370 }
371
372 slot = PCI_SLOT(err);
373
374 err = mt7621_pcie_parse_port(pcie, child, slot);
375 if (err)
376 return err;
377 }
378
379 return 0;
380 }
381
382 static int mt7621_pcie_init_port(struct mt7621_pcie_port *port)
383 {
384 struct mt7621_pcie *pcie = port->pcie;
385 struct device *dev = pcie->dev;
386 u32 slot = port->slot;
387 u32 val = 0;
388 int err;
389
390 /*
391 * Any MT7621 Ralink pcie controller that doesn't have 0x0101 at
392 * the end of the chip_id has inverted PCI resets.
393 */
394 mt7621_reset_port(port);
395
396 val = read_config(pcie, slot, PCIE_FTS_NUM);
397 dev_info(dev, "Port %d N_FTS = %x\n", (unsigned int)val, slot);
398
399 err = phy_init(port->phy);
400 if (err) {
401 dev_err(dev, "failed to initialize port%d phy\n", slot);
402 goto err_phy_init;
403 }
404
405 err = phy_power_on(port->phy);
406 if (err) {
407 dev_err(dev, "failed to power on port%d phy\n", slot);
408 goto err_phy_on;
409 }
410
411 if ((pcie_port_read(port, RALINK_PCI_STATUS) & PCIE_PORT_LINKUP) == 0) {
412 dev_err(dev, "pcie%d no card, disable it (RST & CLK)\n", slot);
413 mt7621_control_assert(port);
414 port->enabled = false;
415 err = -ENODEV;
416 goto err_no_link_up;
417 }
418
419 port->enabled = true;
420
421 return 0;
422
423 err_no_link_up:
424 phy_power_off(port->phy);
425 err_phy_on:
426 phy_exit(port->phy);
427 err_phy_init:
428 return err;
429 }
430
431 static void mt7621_pcie_init_ports(struct mt7621_pcie *pcie)
432 {
433 struct device *dev = pcie->dev;
434 struct mt7621_pcie_port *port, *tmp;
435 int err;
436
437 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
438 u32 slot = port->slot;
439
440 err = mt7621_pcie_init_port(port);
441 if (err) {
442 dev_err(dev, "Initiating port %d failed\n", slot);
443 list_del(&port->list);
444 }
445 }
446
447 reset_control_assert(pcie->rst);
448 rt_sysc_m32(0x30, 2 << 4, SYSC_REG_SYSTEM_CONFIG1);
449 rt_sysc_m32(PCIE_CLK_GEN_EN, PCIE_CLK_GEN_DIS, RALINK_PCIE_CLK_GEN);
450 rt_sysc_m32(PCIE_CLK_GEN1_DIS, PCIE_CLK_GEN1_EN, RALINK_PCIE_CLK_GEN1);
451 rt_sysc_m32(PCIE_CLK_GEN_DIS, PCIE_CLK_GEN_EN, RALINK_PCIE_CLK_GEN);
452 msleep(50);
453 reset_control_deassert(pcie->rst);
454 }
455
456 static int mt7621_pcie_enable_port(struct mt7621_pcie_port *port)
457 {
458 struct mt7621_pcie *pcie = port->pcie;
459 u32 slot = port->slot;
460 u32 offset = MT7621_PCIE_OFFSET + (slot * MT7621_NEXT_PORT);
461 u32 val;
462 int err;
463
464 /* assert port PERST_N */
465 val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
466 val |= PCIE_PORT_PERST(slot);
467 pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
468
469 /* de-assert port PERST_N */
470 val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
471 val &= ~PCIE_PORT_PERST(slot);
472 pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
473
474 /* 100ms timeout value should be enough for Gen1 training */
475 err = readl_poll_timeout(port->base + RALINK_PCI_STATUS,
476 val, !!(val & PCIE_PORT_LINKUP),
477 20, 100 * USEC_PER_MSEC);
478 if (err)
479 return -ETIMEDOUT;
480
481 /* enable pcie interrupt */
482 val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
483 val |= PCIE_PORT_INT_EN(slot);
484 pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
485
486 /* map 2G DDR region */
487 pcie_write(pcie, PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,
488 offset + RALINK_PCI_BAR0SETUP_ADDR);
489 pcie_write(pcie, MEMORY_BASE,
490 offset + RALINK_PCI_IMBASEBAR0_ADDR);
491
492 /* configure class code and revision ID */
493 pcie_write(pcie, PCIE_CLASS_CODE | PCIE_REVISION_ID,
494 offset + RALINK_PCI_CLASS);
495
496 return 0;
497 }
498
499 static void mt7621_pcie_enable_ports(struct mt7621_pcie *pcie)
500 {
501 struct device *dev = pcie->dev;
502 struct mt7621_pcie_port *port;
503 u8 num_slots_enabled = 0;
504 u32 slot;
505 u32 val;
506
507 list_for_each_entry(port, &pcie->ports, list) {
508 if (port->enabled) {
509 if (mt7621_pcie_enable_port(port)) {
510 dev_err(dev, "de-assert port %d PERST_N\n",
511 port->slot);
512 continue;
513 }
514 dev_info(dev, "PCIE%d enabled\n", slot);
515 num_slots_enabled++;
516 }
517 }
518
519 for (slot = 0; slot < num_slots_enabled; slot++) {
520 val = read_config(pcie, slot, PCI_COMMAND);
521 val |= PCI_COMMAND_MASTER;
522 write_config(pcie, slot, PCI_COMMAND, val);
523 /* configure RC FTS number to 250 when it leaves L0s */
524 val = read_config(pcie, slot, PCIE_FTS_NUM);
525 val &= ~PCIE_FTS_NUM_MASK;
526 val |= PCIE_FTS_NUM_L0(0x50);
527 write_config(pcie, slot, PCIE_FTS_NUM, val);
528 }
529 }
530
531 static int mt7621_pcie_init_virtual_bridges(struct mt7621_pcie *pcie)
532 {
533 u32 pcie_link_status = 0;
534 u32 val = 0;
535 struct mt7621_pcie_port *port;
536
537 list_for_each_entry(port, &pcie->ports, list) {
538 u32 slot = port->slot;
539
540 if (port->enabled)
541 pcie_link_status |= BIT(slot);
542 }
543
544 if (pcie_link_status == 0)
545 return -1;
546
547 /*
548 * pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
549 * 3'b000 x x x
550 * 3'b001 x x 0
551 * 3'b010 x 0 x
552 * 3'b011 x 1 0
553 * 3'b100 0 x x
554 * 3'b101 1 x 0
555 * 3'b110 1 0 x
556 * 3'b111 2 1 0
557 */
558 switch (pcie_link_status) {
559 case 2:
560 val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
561 val &= ~(MT7621_BR0_MASK | MT7621_BR1_MASK);
562 val |= 0x1 << MT7621_BR0_SHIFT;
563 val |= 0x0 << MT7621_BR1_SHIFT;
564 pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
565 break;
566 case 4:
567 val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
568 val &= ~MT7621_BR_ALL_MASK;
569 val |= 0x1 << MT7621_BR0_SHIFT;
570 val |= 0x2 << MT7621_BR1_SHIFT;
571 val |= 0x0 << MT7621_BR2_SHIFT;
572 pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
573 break;
574 case 5:
575 val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
576 val &= ~MT7621_BR_ALL_MASK;
577 val |= 0x0 << MT7621_BR0_SHIFT;
578 val |= 0x2 << MT7621_BR1_SHIFT;
579 val |= 0x1 << MT7621_BR2_SHIFT;
580 pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
581 break;
582 case 6:
583 val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
584 val &= ~MT7621_BR_ALL_MASK;
585 val |= 0x2 << MT7621_BR0_SHIFT;
586 val |= 0x0 << MT7621_BR1_SHIFT;
587 val |= 0x1 << MT7621_BR2_SHIFT;
588 pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
589 break;
590 }
591
592 return 0;
593 }
594
595 static int mt7621_pcie_request_resources(struct mt7621_pcie *pcie,
596 struct list_head *res)
597 {
598 struct device *dev = pcie->dev;
599 int err;
600
601 pci_add_resource_offset(res, &pcie->io, pcie->offset.io);
602 pci_add_resource_offset(res, &pcie->mem, pcie->offset.mem);
603 pci_add_resource(res, &pcie->busn);
604
605 err = devm_request_pci_bus_resources(dev, res);
606 if (err < 0)
607 return err;
608
609 return 0;
610 }
611
612 static int mt7621_pcie_register_host(struct pci_host_bridge *host,
613 struct list_head *res)
614 {
615 struct mt7621_pcie *pcie = pci_host_bridge_priv(host);
616
617 list_splice_init(res, &host->windows);
618 host->busnr = pcie->busn.start;
619 host->dev.parent = pcie->dev;
620 host->ops = &mt7621_pci_ops;
621 host->map_irq = of_irq_parse_and_map_pci;
622 host->swizzle_irq = pci_common_swizzle;
623 host->sysdata = pcie;
624
625 return pci_host_probe(host);
626 }
627
628 static int mt7621_pci_probe(struct platform_device *pdev)
629 {
630 struct device *dev = &pdev->dev;
631 struct mt7621_pcie *pcie;
632 struct pci_host_bridge *bridge;
633 int err;
634 LIST_HEAD(res);
635
636 if (!dev->of_node)
637 return -ENODEV;
638
639 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
640 if (!bridge)
641 return -ENOMEM;
642
643 pcie = pci_host_bridge_priv(bridge);
644 pcie->dev = dev;
645 platform_set_drvdata(pdev, pcie);
646 INIT_LIST_HEAD(&pcie->ports);
647
648 err = mt7621_pcie_parse_dt(pcie);
649 if (err) {
650 dev_err(dev, "Parsing DT failed\n");
651 return err;
652 }
653
654 /* set resources limits */
655 iomem_resource.start = 0;
656 iomem_resource.end = ~0UL; /* no limit */
657 ioport_resource.start = 0;
658 ioport_resource.end = ~0UL; /* no limit */
659
660 mt7621_pcie_init_ports(pcie);
661
662 err = mt7621_pcie_init_virtual_bridges(pcie);
663 if (err) {
664 dev_err(dev, "Nothing is connected in virtual bridges. Exiting...");
665 return 0;
666 }
667
668 mt7621_pcie_enable_ports(pcie);
669
670 err = mt7621_pci_parse_request_of_pci_ranges(pcie);
671 if (err) {
672 dev_err(dev, "Error requesting pci resources from ranges");
673 return err;
674 }
675
676 setup_cm_memory_region(pcie);
677
678 err = mt7621_pcie_request_resources(pcie, &res);
679 if (err) {
680 dev_err(dev, "Error requesting resources\n");
681 return err;
682 }
683
684 err = mt7621_pcie_register_host(bridge, &res);
685 if (err) {
686 dev_err(dev, "Error registering host\n");
687 return err;
688 }
689
690 return 0;
691 }
692
693 static const struct of_device_id mt7621_pci_ids[] = {
694 { .compatible = "mediatek,mt7621-pci" },
695 {},
696 };
697 MODULE_DEVICE_TABLE(of, mt7621_pci_ids);
698
699 static struct platform_driver mt7621_pci_driver = {
700 .probe = mt7621_pci_probe,
701 .driver = {
702 .name = "mt7621-pci",
703 .of_match_table = of_match_ptr(mt7621_pci_ids),
704 },
705 };
706
707 static int __init mt7621_pci_init(void)
708 {
709 return platform_driver_register(&mt7621_pci_driver);
710 }
711
712 arch_initcall(mt7621_pci_init);
Linux with added FPC-III support