drivers/usb/dwc2/params.c

   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /*
   3  * Copyright (C) 2004-2016 Synopsys, Inc.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions, and the following disclaimer,
  10  *    without modification.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. The names of the above-listed copyright holders may not be used
  15  *    to endorse or promote products derived from this software without
  16  *    specific prior written permission.
  17  *
  18  * ALTERNATIVELY, this software may be distributed under the terms of the
  19  * GNU General Public License ("GPL") as published by the Free Software
  20  * Foundation; either version 2 of the License, or (at your option) any
  21  * later version.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  24  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  25  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  26  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  27  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  28  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  29  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  30  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  31  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  32  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  33  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34  */
  35
  36 #include <linux/kernel.h>
  37 #include <linux/module.h>
  38 #include <linux/of_device.h>
  39
  40 #include "core.h"
  41
  42 static void dwc2_set_bcm_params(struct dwc2_hsotg *hsotg)
  43 {
  44         struct dwc2_core_params *p = &hsotg->params;
  45
  46         p->host_rx_fifo_size = 774;
  47         p->max_transfer_size = 65535;
  48         p->max_packet_count = 511;
  49         p->ahbcfg = 0x10;
  50 }
  51
  52 static void dwc2_set_his_params(struct dwc2_hsotg *hsotg)
  53 {
  54         struct dwc2_core_params *p = &hsotg->params;
  55
  56         p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
  57         p->speed = DWC2_SPEED_PARAM_HIGH;
  58         p->host_rx_fifo_size = 512;
  59         p->host_nperio_tx_fifo_size = 512;
  60         p->host_perio_tx_fifo_size = 512;
  61         p->max_transfer_size = 65535;
  62         p->max_packet_count = 511;
  63         p->host_channels = 16;
  64         p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
  65         p->phy_utmi_width = 8;
  66         p->i2c_enable = false;
  67         p->reload_ctl = false;
  68         p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
  69                 GAHBCFG_HBSTLEN_SHIFT;
  70         p->change_speed_quirk = true;
  71         p->power_down = false;
  72 }
  73
  74 static void dwc2_set_s3c6400_params(struct dwc2_hsotg *hsotg)
  75 {
  76         struct dwc2_core_params *p = &hsotg->params;
  77
  78         p->power_down = 0;
  79 }
  80
  81 static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg)
  82 {
  83         struct dwc2_core_params *p = &hsotg->params;
  84
  85         p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
  86         p->host_rx_fifo_size = 525;
  87         p->host_nperio_tx_fifo_size = 128;
  88         p->host_perio_tx_fifo_size = 256;
  89         p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
  90                 GAHBCFG_HBSTLEN_SHIFT;
  91         p->power_down = 0;
  92 }
  93
  94 static void dwc2_set_ltq_params(struct dwc2_hsotg *hsotg)
  95 {
  96         struct dwc2_core_params *p = &hsotg->params;
  97
  98         p->otg_cap = 2;
  99         p->host_rx_fifo_size = 288;
 100         p->host_nperio_tx_fifo_size = 128;
 101         p->host_perio_tx_fifo_size = 96;
 102         p->max_transfer_size = 65535;
 103         p->max_packet_count = 511;
 104         p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
 105                 GAHBCFG_HBSTLEN_SHIFT;
 106 }
 107
 108 static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg)
 109 {
 110         struct dwc2_core_params *p = &hsotg->params;
 111
 112         p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
 113         p->speed = DWC2_SPEED_PARAM_HIGH;
 114         p->host_rx_fifo_size = 512;
 115         p->host_nperio_tx_fifo_size = 500;
 116         p->host_perio_tx_fifo_size = 500;
 117         p->host_channels = 16;
 118         p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
 119         p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 <<
 120                 GAHBCFG_HBSTLEN_SHIFT;
 121         p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
 122 }
 123
 124 static void dwc2_set_amlogic_g12a_params(struct dwc2_hsotg *hsotg)
 125 {
 126         struct dwc2_core_params *p = &hsotg->params;
 127
 128         p->lpm = false;
 129         p->lpm_clock_gating = false;
 130         p->besl = false;
 131         p->hird_threshold_en = false;
 132 }
 133
 134 static void dwc2_set_amcc_params(struct dwc2_hsotg *hsotg)
 135 {
 136         struct dwc2_core_params *p = &hsotg->params;
 137
 138         p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
 139 }
 140
 141 static void dwc2_set_stm32f4x9_fsotg_params(struct dwc2_hsotg *hsotg)
 142 {
 143         struct dwc2_core_params *p = &hsotg->params;
 144
 145         p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
 146         p->speed = DWC2_SPEED_PARAM_FULL;
 147         p->host_rx_fifo_size = 128;
 148         p->host_nperio_tx_fifo_size = 96;
 149         p->host_perio_tx_fifo_size = 96;
 150         p->max_packet_count = 256;
 151         p->phy_type = DWC2_PHY_TYPE_PARAM_FS;
 152         p->i2c_enable = false;
 153         p->activate_stm_fs_transceiver = true;
 154 }
 155
 156 static void dwc2_set_stm32f7_hsotg_params(struct dwc2_hsotg *hsotg)
 157 {
 158         struct dwc2_core_params *p = &hsotg->params;
 159
 160         p->host_rx_fifo_size = 622;
 161         p->host_nperio_tx_fifo_size = 128;
 162         p->host_perio_tx_fifo_size = 256;
 163 }
 164
 165 const struct of_device_id dwc2_of_match_table[] = {
 166         { .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params },
 167         { .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params  },
 168         { .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params },
 169         { .compatible = "lantiq,arx100-usb", .data = dwc2_set_ltq_params },
 170         { .compatible = "lantiq,xrx200-usb", .data = dwc2_set_ltq_params },
 171         { .compatible = "snps,dwc2" },
 172         { .compatible = "samsung,s3c6400-hsotg",
 173           .data = dwc2_set_s3c6400_params },
 174         { .compatible = "amlogic,meson8-usb",
 175           .data = dwc2_set_amlogic_params },
 176         { .compatible = "amlogic,meson8b-usb",
 177           .data = dwc2_set_amlogic_params },
 178         { .compatible = "amlogic,meson-gxbb-usb",
 179           .data = dwc2_set_amlogic_params },
 180         { .compatible = "amlogic,meson-g12a-usb",
 181           .data = dwc2_set_amlogic_g12a_params },
 182         { .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params },
 183         { .compatible = "st,stm32f4x9-fsotg",
 184           .data = dwc2_set_stm32f4x9_fsotg_params },
 185         { .compatible = "st,stm32f4x9-hsotg" },
 186         { .compatible = "st,stm32f7-hsotg",
 187           .data = dwc2_set_stm32f7_hsotg_params },
 188         {},
 189 };
 190 MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
 191
 192 static void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg)
 193 {
 194         u8 val;
 195
 196         switch (hsotg->hw_params.op_mode) {
 197         case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
 198                 val = DWC2_CAP_PARAM_HNP_SRP_CAPABLE;
 199                 break;
 200         case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
 201         case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
 202         case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
 203                 val = DWC2_CAP_PARAM_SRP_ONLY_CAPABLE;
 204                 break;
 205         default:
 206                 val = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
 207                 break;
 208         }
 209
 210         hsotg->params.otg_cap = val;
 211 }
 212
 213 static void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg)
 214 {
 215         int val;
 216         u32 hs_phy_type = hsotg->hw_params.hs_phy_type;
 217
 218         val = DWC2_PHY_TYPE_PARAM_FS;
 219         if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) {
 220                 if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI ||
 221                     hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)
 222                         val = DWC2_PHY_TYPE_PARAM_UTMI;
 223                 else
 224                         val = DWC2_PHY_TYPE_PARAM_ULPI;
 225         }
 226
 227         if (dwc2_is_fs_iot(hsotg))
 228                 hsotg->params.phy_type = DWC2_PHY_TYPE_PARAM_FS;
 229
 230         hsotg->params.phy_type = val;
 231 }
 232
 233 static void dwc2_set_param_speed(struct dwc2_hsotg *hsotg)
 234 {
 235         int val;
 236
 237         val = hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS ?
 238                 DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH;
 239
 240         if (dwc2_is_fs_iot(hsotg))
 241                 val = DWC2_SPEED_PARAM_FULL;
 242
 243         if (dwc2_is_hs_iot(hsotg))
 244                 val = DWC2_SPEED_PARAM_HIGH;
 245
 246         hsotg->params.speed = val;
 247 }
 248
 249 static void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg)
 250 {
 251         int val;
 252
 253         val = (hsotg->hw_params.utmi_phy_data_width ==
 254                GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16;
 255
 256         if (hsotg->phy) {
 257                 /*
 258                  * If using the generic PHY framework, check if the PHY bus
 259                  * width is 8-bit and set the phyif appropriately.
 260                  */
 261                 if (phy_get_bus_width(hsotg->phy) == 8)
 262                         val = 8;
 263         }
 264
 265         hsotg->params.phy_utmi_width = val;
 266 }
 267
 268 static void dwc2_set_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg)
 269 {
 270         struct dwc2_core_params *p = &hsotg->params;
 271         int depth_average;
 272         int fifo_count;
 273         int i;
 274
 275         fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
 276
 277         memset(p->g_tx_fifo_size, 0, sizeof(p->g_tx_fifo_size));
 278         depth_average = dwc2_hsotg_tx_fifo_average_depth(hsotg);
 279         for (i = 1; i <= fifo_count; i++)
 280                 p->g_tx_fifo_size[i] = depth_average;
 281 }
 282
 283 static void dwc2_set_param_power_down(struct dwc2_hsotg *hsotg)
 284 {
 285         int val;
 286
 287         if (hsotg->hw_params.hibernation)
 288                 val = 2;
 289         else if (hsotg->hw_params.power_optimized)
 290                 val = 1;
 291         else
 292                 val = 0;
 293
 294         hsotg->params.power_down = val;
 295 }
 296
 297 static void dwc2_set_param_lpm(struct dwc2_hsotg *hsotg)
 298 {
 299         struct dwc2_core_params *p = &hsotg->params;
 300
 301         p->lpm = hsotg->hw_params.lpm_mode;
 302         if (p->lpm) {
 303                 p->lpm_clock_gating = true;
 304                 p->besl = true;
 305                 p->hird_threshold_en = true;
 306                 p->hird_threshold = 4;
 307         } else {
 308                 p->lpm_clock_gating = false;
 309                 p->besl = false;
 310                 p->hird_threshold_en = false;
 311         }
 312 }
 313
 314 /**
 315  * dwc2_set_default_params() - Set all core parameters to their
 316  * auto-detected default values.
 317  *
 318  * @hsotg: Programming view of the DWC_otg controller
 319  *
 320  */
 321 static void dwc2_set_default_params(struct dwc2_hsotg *hsotg)
 322 {
 323         struct dwc2_hw_params *hw = &hsotg->hw_params;
 324         struct dwc2_core_params *p = &hsotg->params;
 325         bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH);
 326
 327         dwc2_set_param_otg_cap(hsotg);
 328         dwc2_set_param_phy_type(hsotg);
 329         dwc2_set_param_speed(hsotg);
 330         dwc2_set_param_phy_utmi_width(hsotg);
 331         dwc2_set_param_power_down(hsotg);
 332         dwc2_set_param_lpm(hsotg);
 333         p->phy_ulpi_ddr = false;
 334         p->phy_ulpi_ext_vbus = false;
 335
 336         p->enable_dynamic_fifo = hw->enable_dynamic_fifo;
 337         p->en_multiple_tx_fifo = hw->en_multiple_tx_fifo;
 338         p->i2c_enable = hw->i2c_enable;
 339         p->acg_enable = hw->acg_enable;
 340         p->ulpi_fs_ls = false;
 341         p->ts_dline = false;
 342         p->reload_ctl = (hw->snpsid >= DWC2_CORE_REV_2_92a);
 343         p->uframe_sched = true;
 344         p->external_id_pin_ctl = false;
 345         p->ipg_isoc_en = false;
 346         p->service_interval = false;
 347         p->max_packet_count = hw->max_packet_count;
 348         p->max_transfer_size = hw->max_transfer_size;
 349         p->ahbcfg = GAHBCFG_HBSTLEN_INCR << GAHBCFG_HBSTLEN_SHIFT;
 350         p->ref_clk_per = 33333;
 351         p->sof_cnt_wkup_alert = 100;
 352
 353         if ((hsotg->dr_mode == USB_DR_MODE_HOST) ||
 354             (hsotg->dr_mode == USB_DR_MODE_OTG)) {
 355                 p->host_dma = dma_capable;
 356                 p->dma_desc_enable = false;
 357                 p->dma_desc_fs_enable = false;
 358                 p->host_support_fs_ls_low_power = false;
 359                 p->host_ls_low_power_phy_clk = false;
 360                 p->host_channels = hw->host_channels;
 361                 p->host_rx_fifo_size = hw->rx_fifo_size;
 362                 p->host_nperio_tx_fifo_size = hw->host_nperio_tx_fifo_size;
 363                 p->host_perio_tx_fifo_size = hw->host_perio_tx_fifo_size;
 364         }
 365
 366         if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
 367             (hsotg->dr_mode == USB_DR_MODE_OTG)) {
 368                 p->g_dma = dma_capable;
 369                 p->g_dma_desc = hw->dma_desc_enable;
 370
 371                 /*
 372                  * The values for g_rx_fifo_size (2048) and
 373                  * g_np_tx_fifo_size (1024) come from the legacy s3c
 374                  * gadget driver. These defaults have been hard-coded
 375                  * for some time so many platforms depend on these
 376                  * values. Leave them as defaults for now and only
 377                  * auto-detect if the hardware does not support the
 378                  * default.
 379                  */
 380                 p->g_rx_fifo_size = 2048;
 381                 p->g_np_tx_fifo_size = 1024;
 382                 dwc2_set_param_tx_fifo_sizes(hsotg);
 383         }
 384 }
 385
 386 /**
 387  * dwc2_get_device_properties() - Read in device properties.
 388  *
 389  * @hsotg: Programming view of the DWC_otg controller
 390  *
 391  * Read in the device properties and adjust core parameters if needed.
 392  */
 393 static void dwc2_get_device_properties(struct dwc2_hsotg *hsotg)
 394 {
 395         struct dwc2_core_params *p = &hsotg->params;
 396         int num;
 397
 398         if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
 399             (hsotg->dr_mode == USB_DR_MODE_OTG)) {
 400                 device_property_read_u32(hsotg->dev, "g-rx-fifo-size",
 401                                          &p->g_rx_fifo_size);
 402
 403                 device_property_read_u32(hsotg->dev, "g-np-tx-fifo-size",
 404                                          &p->g_np_tx_fifo_size);
 405
 406                 num = device_property_read_u32_array(hsotg->dev,
 407                                                      "g-tx-fifo-size",
 408                                                      NULL, 0);
 409
 410                 if (num > 0) {
 411                         num = min(num, 15);
 412                         memset(p->g_tx_fifo_size, 0,
 413                                sizeof(p->g_tx_fifo_size));
 414                         device_property_read_u32_array(hsotg->dev,
 415                                                        "g-tx-fifo-size",
 416                                                        &p->g_tx_fifo_size[1],
 417                                                        num);
 418                 }
 419         }
 420
 421         if (of_find_property(hsotg->dev->of_node, "disable-over-current", NULL))
 422                 p->oc_disable = true;
 423 }
 424
 425 static void dwc2_check_param_otg_cap(struct dwc2_hsotg *hsotg)
 426 {
 427         int valid = 1;
 428
 429         switch (hsotg->params.otg_cap) {
 430         case DWC2_CAP_PARAM_HNP_SRP_CAPABLE:
 431                 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE)
 432                         valid = 0;
 433                 break;
 434         case DWC2_CAP_PARAM_SRP_ONLY_CAPABLE:
 435                 switch (hsotg->hw_params.op_mode) {
 436                 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
 437                 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
 438                 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
 439                 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
 440                         break;
 441                 default:
 442                         valid = 0;
 443                         break;
 444                 }
 445                 break;
 446         case DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE:
 447                 /* always valid */
 448                 break;
 449         default:
 450                 valid = 0;
 451                 break;
 452         }
 453
 454         if (!valid)
 455                 dwc2_set_param_otg_cap(hsotg);
 456 }
 457
 458 static void dwc2_check_param_phy_type(struct dwc2_hsotg *hsotg)
 459 {
 460         int valid = 0;
 461         u32 hs_phy_type;
 462         u32 fs_phy_type;
 463
 464         hs_phy_type = hsotg->hw_params.hs_phy_type;
 465         fs_phy_type = hsotg->hw_params.fs_phy_type;
 466
 467         switch (hsotg->params.phy_type) {
 468         case DWC2_PHY_TYPE_PARAM_FS:
 469                 if (fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
 470                         valid = 1;
 471                 break;
 472         case DWC2_PHY_TYPE_PARAM_UTMI:
 473                 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) ||
 474                     (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
 475                         valid = 1;
 476                 break;
 477         case DWC2_PHY_TYPE_PARAM_ULPI:
 478                 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) ||
 479                     (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
 480                         valid = 1;
 481                 break;
 482         default:
 483                 break;
 484         }
 485
 486         if (!valid)
 487                 dwc2_set_param_phy_type(hsotg);
 488 }
 489
 490 static void dwc2_check_param_speed(struct dwc2_hsotg *hsotg)
 491 {
 492         int valid = 1;
 493         int phy_type = hsotg->params.phy_type;
 494         int speed = hsotg->params.speed;
 495
 496         switch (speed) {
 497         case DWC2_SPEED_PARAM_HIGH:
 498                 if ((hsotg->params.speed == DWC2_SPEED_PARAM_HIGH) &&
 499                     (phy_type == DWC2_PHY_TYPE_PARAM_FS))
 500                         valid = 0;
 501                 break;
 502         case DWC2_SPEED_PARAM_FULL:
 503         case DWC2_SPEED_PARAM_LOW:
 504                 break;
 505         default:
 506                 valid = 0;
 507                 break;
 508         }
 509
 510         if (!valid)
 511                 dwc2_set_param_speed(hsotg);
 512 }
 513
 514 static void dwc2_check_param_phy_utmi_width(struct dwc2_hsotg *hsotg)
 515 {
 516         int valid = 0;
 517         int param = hsotg->params.phy_utmi_width;
 518         int width = hsotg->hw_params.utmi_phy_data_width;
 519
 520         switch (width) {
 521         case GHWCFG4_UTMI_PHY_DATA_WIDTH_8:
 522                 valid = (param == 8);
 523                 break;
 524         case GHWCFG4_UTMI_PHY_DATA_WIDTH_16:
 525                 valid = (param == 16);
 526                 break;
 527         case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16:
 528                 valid = (param == 8 || param == 16);
 529                 break;
 530         }
 531
 532         if (!valid)
 533                 dwc2_set_param_phy_utmi_width(hsotg);
 534 }
 535
 536 static void dwc2_check_param_power_down(struct dwc2_hsotg *hsotg)
 537 {
 538         int param = hsotg->params.power_down;
 539
 540         switch (param) {
 541         case DWC2_POWER_DOWN_PARAM_NONE:
 542                 break;
 543         case DWC2_POWER_DOWN_PARAM_PARTIAL:
 544                 if (hsotg->hw_params.power_optimized)
 545                         break;
 546                 dev_dbg(hsotg->dev,
 547                         "Partial power down isn't supported by HW\n");
 548                 param = DWC2_POWER_DOWN_PARAM_NONE;
 549                 break;
 550         case DWC2_POWER_DOWN_PARAM_HIBERNATION:
 551                 if (hsotg->hw_params.hibernation)
 552                         break;
 553                 dev_dbg(hsotg->dev,
 554                         "Hibernation isn't supported by HW\n");
 555                 param = DWC2_POWER_DOWN_PARAM_NONE;
 556                 break;
 557         default:
 558                 dev_err(hsotg->dev,
 559                         "%s: Invalid parameter power_down=%d\n",
 560                         __func__, param);
 561                 param = DWC2_POWER_DOWN_PARAM_NONE;
 562                 break;
 563         }
 564
 565         hsotg->params.power_down = param;
 566 }
 567
 568 static void dwc2_check_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg)
 569 {
 570         int fifo_count;
 571         int fifo;
 572         int min;
 573         u32 total = 0;
 574         u32 dptxfszn;
 575
 576         fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
 577         min = hsotg->hw_params.en_multiple_tx_fifo ? 16 : 4;
 578
 579         for (fifo = 1; fifo <= fifo_count; fifo++)
 580                 total += hsotg->params.g_tx_fifo_size[fifo];
 581
 582         if (total > dwc2_hsotg_tx_fifo_total_depth(hsotg) || !total) {
 583                 dev_warn(hsotg->dev, "%s: Invalid parameter g-tx-fifo-size, setting to default average\n",
 584                          __func__);
 585                 dwc2_set_param_tx_fifo_sizes(hsotg);
 586         }
 587
 588         for (fifo = 1; fifo <= fifo_count; fifo++) {
 589                 dptxfszn = hsotg->hw_params.g_tx_fifo_size[fifo];
 590
 591                 if (hsotg->params.g_tx_fifo_size[fifo] < min ||
 592                     hsotg->params.g_tx_fifo_size[fifo] >  dptxfszn) {
 593                         dev_warn(hsotg->dev, "%s: Invalid parameter g_tx_fifo_size[%d]=%d\n",
 594                                  __func__, fifo,
 595                                  hsotg->params.g_tx_fifo_size[fifo]);
 596                         hsotg->params.g_tx_fifo_size[fifo] = dptxfszn;
 597                 }
 598         }
 599 }
 600
 601 #define CHECK_RANGE(_param, _min, _max, _def) do {                      \
 602                 if ((int)(hsotg->params._param) < (_min) ||             \
 603                     (hsotg->params._param) > (_max)) {                  \
 604                         dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \
 605                                  __func__, #_param, hsotg->params._param); \
 606                         hsotg->params._param = (_def);                  \
 607                 }                                                       \
 608         } while (0)
 609
 610 #define CHECK_BOOL(_param, _check) do {                                 \
 611                 if (hsotg->params._param && !(_check)) {                \
 612                         dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \
 613                                  __func__, #_param, hsotg->params._param); \
 614                         hsotg->params._param = false;                   \
 615                 }                                                       \
 616         } while (0)
 617
 618 static void dwc2_check_params(struct dwc2_hsotg *hsotg)
 619 {
 620         struct dwc2_hw_params *hw = &hsotg->hw_params;
 621         struct dwc2_core_params *p = &hsotg->params;
 622         bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH);
 623
 624         dwc2_check_param_otg_cap(hsotg);
 625         dwc2_check_param_phy_type(hsotg);
 626         dwc2_check_param_speed(hsotg);
 627         dwc2_check_param_phy_utmi_width(hsotg);
 628         dwc2_check_param_power_down(hsotg);
 629         CHECK_BOOL(enable_dynamic_fifo, hw->enable_dynamic_fifo);
 630         CHECK_BOOL(en_multiple_tx_fifo, hw->en_multiple_tx_fifo);
 631         CHECK_BOOL(i2c_enable, hw->i2c_enable);
 632         CHECK_BOOL(ipg_isoc_en, hw->ipg_isoc_en);
 633         CHECK_BOOL(acg_enable, hw->acg_enable);
 634         CHECK_BOOL(reload_ctl, (hsotg->hw_params.snpsid > DWC2_CORE_REV_2_92a));
 635         CHECK_BOOL(lpm, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_80a));
 636         CHECK_BOOL(lpm, hw->lpm_mode);
 637         CHECK_BOOL(lpm_clock_gating, hsotg->params.lpm);
 638         CHECK_BOOL(besl, hsotg->params.lpm);
 639         CHECK_BOOL(besl, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a));
 640         CHECK_BOOL(hird_threshold_en, hsotg->params.lpm);
 641         CHECK_RANGE(hird_threshold, 0, hsotg->params.besl ? 12 : 7, 0);
 642         CHECK_BOOL(service_interval, hw->service_interval_mode);
 643         CHECK_RANGE(max_packet_count,
 644                     15, hw->max_packet_count,
 645                     hw->max_packet_count);
 646         CHECK_RANGE(max_transfer_size,
 647                     2047, hw->max_transfer_size,
 648                     hw->max_transfer_size);
 649
 650         if ((hsotg->dr_mode == USB_DR_MODE_HOST) ||
 651             (hsotg->dr_mode == USB_DR_MODE_OTG)) {
 652                 CHECK_BOOL(host_dma, dma_capable);
 653                 CHECK_BOOL(dma_desc_enable, p->host_dma);
 654                 CHECK_BOOL(dma_desc_fs_enable, p->dma_desc_enable);
 655                 CHECK_BOOL(host_ls_low_power_phy_clk,
 656                            p->phy_type == DWC2_PHY_TYPE_PARAM_FS);
 657                 CHECK_RANGE(host_channels,
 658                             1, hw->host_channels,
 659                             hw->host_channels);
 660                 CHECK_RANGE(host_rx_fifo_size,
 661                             16, hw->rx_fifo_size,
 662                             hw->rx_fifo_size);
 663                 CHECK_RANGE(host_nperio_tx_fifo_size,
 664                             16, hw->host_nperio_tx_fifo_size,
 665                             hw->host_nperio_tx_fifo_size);
 666                 CHECK_RANGE(host_perio_tx_fifo_size,
 667                             16, hw->host_perio_tx_fifo_size,
 668                             hw->host_perio_tx_fifo_size);
 669         }
 670
 671         if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
 672             (hsotg->dr_mode == USB_DR_MODE_OTG)) {
 673                 CHECK_BOOL(g_dma, dma_capable);
 674                 CHECK_BOOL(g_dma_desc, (p->g_dma && hw->dma_desc_enable));
 675                 CHECK_RANGE(g_rx_fifo_size,
 676                             16, hw->rx_fifo_size,
 677                             hw->rx_fifo_size);
 678                 CHECK_RANGE(g_np_tx_fifo_size,
 679                             16, hw->dev_nperio_tx_fifo_size,
 680                             hw->dev_nperio_tx_fifo_size);
 681                 dwc2_check_param_tx_fifo_sizes(hsotg);
 682         }
 683 }
 684
 685 /*
 686  * Gets host hardware parameters. Forces host mode if not currently in
 687  * host mode. Should be called immediately after a core soft reset in
 688  * order to get the reset values.
 689  */
 690 static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg)
 691 {
 692         struct dwc2_hw_params *hw = &hsotg->hw_params;
 693         u32 gnptxfsiz;
 694         u32 hptxfsiz;
 695
 696         if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
 697                 return;
 698
 699         dwc2_force_mode(hsotg, true);
 700
 701         gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ);
 702         hptxfsiz = dwc2_readl(hsotg, HPTXFSIZ);
 703
 704         hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
 705                                        FIFOSIZE_DEPTH_SHIFT;
 706         hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >>
 707                                       FIFOSIZE_DEPTH_SHIFT;
 708 }
 709
 710 /*
 711  * Gets device hardware parameters. Forces device mode if not
 712  * currently in device mode. Should be called immediately after a core
 713  * soft reset in order to get the reset values.
 714  */
 715 static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg)
 716 {
 717         struct dwc2_hw_params *hw = &hsotg->hw_params;
 718         u32 gnptxfsiz;
 719         int fifo, fifo_count;
 720
 721         if (hsotg->dr_mode == USB_DR_MODE_HOST)
 722                 return;
 723
 724         dwc2_force_mode(hsotg, false);
 725
 726         gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ);
 727
 728         fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
 729
 730         for (fifo = 1; fifo <= fifo_count; fifo++) {
 731                 hw->g_tx_fifo_size[fifo] =
 732                         (dwc2_readl(hsotg, DPTXFSIZN(fifo)) &
 733                          FIFOSIZE_DEPTH_MASK) >> FIFOSIZE_DEPTH_SHIFT;
 734         }
 735
 736         hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
 737                                        FIFOSIZE_DEPTH_SHIFT;
 738 }
 739
 740 /**
 741  * During device initialization, read various hardware configuration
 742  * registers and interpret the contents.
 743  *
 744  * @hsotg: Programming view of the DWC_otg controller
 745  *
 746  */
 747 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
 748 {
 749         struct dwc2_hw_params *hw = &hsotg->hw_params;
 750         unsigned int width;
 751         u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4;
 752         u32 grxfsiz;
 753
 754         /*
 755          * Attempt to ensure this device is really a DWC_otg Controller.
 756          * Read and verify the GSNPSID register contents. The value should be
 757          * 0x45f4xxxx, 0x5531xxxx or 0x5532xxxx
 758          */
 759
 760         hw->snpsid = dwc2_readl(hsotg, GSNPSID);
 761         if ((hw->snpsid & GSNPSID_ID_MASK) != DWC2_OTG_ID &&
 762             (hw->snpsid & GSNPSID_ID_MASK) != DWC2_FS_IOT_ID &&
 763             (hw->snpsid & GSNPSID_ID_MASK) != DWC2_HS_IOT_ID) {
 764                 dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n",
 765                         hw->snpsid);
 766                 return -ENODEV;
 767         }
 768
 769         dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x (snpsid=%x)\n",
 770                 hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf,
 771                 hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid);
 772
 773         hwcfg1 = dwc2_readl(hsotg, GHWCFG1);
 774         hwcfg2 = dwc2_readl(hsotg, GHWCFG2);
 775         hwcfg3 = dwc2_readl(hsotg, GHWCFG3);
 776         hwcfg4 = dwc2_readl(hsotg, GHWCFG4);
 777         grxfsiz = dwc2_readl(hsotg, GRXFSIZ);
 778
 779         /* hwcfg1 */
 780         hw->dev_ep_dirs = hwcfg1;
 781
 782         /* hwcfg2 */
 783         hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >>
 784                       GHWCFG2_OP_MODE_SHIFT;
 785         hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >>
 786                    GHWCFG2_ARCHITECTURE_SHIFT;
 787         hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO);
 788         hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >>
 789                                 GHWCFG2_NUM_HOST_CHAN_SHIFT);
 790         hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >>
 791                           GHWCFG2_HS_PHY_TYPE_SHIFT;
 792         hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >>
 793                           GHWCFG2_FS_PHY_TYPE_SHIFT;
 794         hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >>
 795                          GHWCFG2_NUM_DEV_EP_SHIFT;
 796         hw->nperio_tx_q_depth =
 797                 (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >>
 798                 GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1;
 799         hw->host_perio_tx_q_depth =
 800                 (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >>
 801                 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1;
 802         hw->dev_token_q_depth =
 803                 (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >>
 804                 GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT;
 805
 806         /* hwcfg3 */
 807         width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >>
 808                 GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT;
 809         hw->max_transfer_size = (1 << (width + 11)) - 1;
 810         width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >>
 811                 GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT;
 812         hw->max_packet_count = (1 << (width + 4)) - 1;
 813         hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C);
 814         hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >>
 815                               GHWCFG3_DFIFO_DEPTH_SHIFT;
 816         hw->lpm_mode = !!(hwcfg3 & GHWCFG3_OTG_LPM_EN);
 817
 818         /* hwcfg4 */
 819         hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN);
 820         hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >>
 821                                   GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT;
 822         hw->num_dev_in_eps = (hwcfg4 & GHWCFG4_NUM_IN_EPS_MASK) >>
 823                              GHWCFG4_NUM_IN_EPS_SHIFT;
 824         hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA);
 825         hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ);
 826         hw->hibernation = !!(hwcfg4 & GHWCFG4_HIBER);
 827         hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >>
 828                                   GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT;
 829         hw->acg_enable = !!(hwcfg4 & GHWCFG4_ACG_SUPPORTED);
 830         hw->ipg_isoc_en = !!(hwcfg4 & GHWCFG4_IPG_ISOC_SUPPORTED);
 831         hw->service_interval_mode = !!(hwcfg4 &
 832                                        GHWCFG4_SERVICE_INTERVAL_SUPPORTED);
 833
 834         /* fifo sizes */
 835         hw->rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >>
 836                                 GRXFSIZ_DEPTH_SHIFT;
 837         /*
 838          * Host specific hardware parameters. Reading these parameters
 839          * requires the controller to be in host mode. The mode will
 840          * be forced, if necessary, to read these values.
 841          */
 842         dwc2_get_host_hwparams(hsotg);
 843         dwc2_get_dev_hwparams(hsotg);
 844
 845         return 0;
 846 }
 847
 848 int dwc2_init_params(struct dwc2_hsotg *hsotg)
 849 {
 850         const struct of_device_id *match;
 851         void (*set_params)(void *data);
 852
 853         dwc2_set_default_params(hsotg);
 854         dwc2_get_device_properties(hsotg);
 855
 856         match = of_match_device(dwc2_of_match_table, hsotg->dev);
 857         if (match && match->data) {
 858                 set_params = match->data;
 859                 set_params(hsotg);
 860         }
 861
 862         dwc2_check_params(hsotg);
 863
 864         return 0;
 865 }