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Merge tag 'for-linus-20190706' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / sound / soc / codecs / cs42l73.c
bloba81739367109eeed98276d59e80de18b6510c5c9
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * cs42l73.c -- CS42L73 ALSA Soc Audio driver
4 *
5 * Copyright 2011 Cirrus Logic, Inc.
6 *
7 * Authors: Georgi Vlaev, Nucleus Systems Ltd, <joe@nucleusys.com>
8 * Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>
9 */
10
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/delay.h>
16 #include <linux/of_gpio.h>
17 #include <linux/pm.h>
18 #include <linux/i2c.h>
19 #include <linux/regmap.h>
20 #include <linux/slab.h>
21 #include <sound/core.h>
22 #include <sound/pcm.h>
23 #include <sound/pcm_params.h>
24 #include <sound/soc.h>
25 #include <sound/soc-dapm.h>
26 #include <sound/initval.h>
27 #include <sound/tlv.h>
28 #include <sound/cs42l73.h>
29 #include "cs42l73.h"
30
31 struct sp_config {
32 u8 spc, mmcc, spfs;
33 u32 srate;
34 };
35 struct cs42l73_private {
36 struct cs42l73_platform_data pdata;
37 struct sp_config config[3];
38 struct regmap *regmap;
39 u32 sysclk;
40 u8 mclksel;
41 u32 mclk;
42 int shutdwn_delay;
43 };
44
45 static const struct reg_default cs42l73_reg_defaults[] = {
46 { 6, 0xF1 }, /* r06 - Power Ctl 1 */
47 { 7, 0xDF }, /* r07 - Power Ctl 2 */
48 { 8, 0x3F }, /* r08 - Power Ctl 3 */
49 { 9, 0x50 }, /* r09 - Charge Pump Freq */
50 { 10, 0x53 }, /* r0A - Output Load MicBias Short Detect */
51 { 11, 0x00 }, /* r0B - DMIC Master Clock Ctl */
52 { 12, 0x00 }, /* r0C - Aux PCM Ctl */
53 { 13, 0x15 }, /* r0D - Aux PCM Master Clock Ctl */
54 { 14, 0x00 }, /* r0E - Audio PCM Ctl */
55 { 15, 0x15 }, /* r0F - Audio PCM Master Clock Ctl */
56 { 16, 0x00 }, /* r10 - Voice PCM Ctl */
57 { 17, 0x15 }, /* r11 - Voice PCM Master Clock Ctl */
58 { 18, 0x00 }, /* r12 - Voice/Aux Sample Rate */
59 { 19, 0x06 }, /* r13 - Misc I/O Path Ctl */
60 { 20, 0x00 }, /* r14 - ADC Input Path Ctl */
61 { 21, 0x00 }, /* r15 - MICA Preamp, PGA Volume */
62 { 22, 0x00 }, /* r16 - MICB Preamp, PGA Volume */
63 { 23, 0x00 }, /* r17 - Input Path A Digital Volume */
64 { 24, 0x00 }, /* r18 - Input Path B Digital Volume */
65 { 25, 0x00 }, /* r19 - Playback Digital Ctl */
66 { 26, 0x00 }, /* r1A - HP/LO Left Digital Volume */
67 { 27, 0x00 }, /* r1B - HP/LO Right Digital Volume */
68 { 28, 0x00 }, /* r1C - Speakerphone Digital Volume */
69 { 29, 0x00 }, /* r1D - Ear/SPKLO Digital Volume */
70 { 30, 0x00 }, /* r1E - HP Left Analog Volume */
71 { 31, 0x00 }, /* r1F - HP Right Analog Volume */
72 { 32, 0x00 }, /* r20 - LO Left Analog Volume */
73 { 33, 0x00 }, /* r21 - LO Right Analog Volume */
74 { 34, 0x00 }, /* r22 - Stereo Input Path Advisory Volume */
75 { 35, 0x00 }, /* r23 - Aux PCM Input Advisory Volume */
76 { 36, 0x00 }, /* r24 - Audio PCM Input Advisory Volume */
77 { 37, 0x00 }, /* r25 - Voice PCM Input Advisory Volume */
78 { 38, 0x00 }, /* r26 - Limiter Attack Rate HP/LO */
79 { 39, 0x7F }, /* r27 - Limter Ctl, Release Rate HP/LO */
80 { 40, 0x00 }, /* r28 - Limter Threshold HP/LO */
81 { 41, 0x00 }, /* r29 - Limiter Attack Rate Speakerphone */
82 { 42, 0x3F }, /* r2A - Limter Ctl, Release Rate Speakerphone */
83 { 43, 0x00 }, /* r2B - Limter Threshold Speakerphone */
84 { 44, 0x00 }, /* r2C - Limiter Attack Rate Ear/SPKLO */
85 { 45, 0x3F }, /* r2D - Limter Ctl, Release Rate Ear/SPKLO */
86 { 46, 0x00 }, /* r2E - Limter Threshold Ear/SPKLO */
87 { 47, 0x00 }, /* r2F - ALC Enable, Attack Rate Left/Right */
88 { 48, 0x3F }, /* r30 - ALC Release Rate Left/Right */
89 { 49, 0x00 }, /* r31 - ALC Threshold Left/Right */
90 { 50, 0x00 }, /* r32 - Noise Gate Ctl Left/Right */
91 { 51, 0x00 }, /* r33 - ALC/NG Misc Ctl */
92 { 52, 0x18 }, /* r34 - Mixer Ctl */
93 { 53, 0x3F }, /* r35 - HP/LO Left Mixer Input Path Volume */
94 { 54, 0x3F }, /* r36 - HP/LO Right Mixer Input Path Volume */
95 { 55, 0x3F }, /* r37 - HP/LO Left Mixer Aux PCM Volume */
96 { 56, 0x3F }, /* r38 - HP/LO Right Mixer Aux PCM Volume */
97 { 57, 0x3F }, /* r39 - HP/LO Left Mixer Audio PCM Volume */
98 { 58, 0x3F }, /* r3A - HP/LO Right Mixer Audio PCM Volume */
99 { 59, 0x3F }, /* r3B - HP/LO Left Mixer Voice PCM Mono Volume */
100 { 60, 0x3F }, /* r3C - HP/LO Right Mixer Voice PCM Mono Volume */
101 { 61, 0x3F }, /* r3D - Aux PCM Left Mixer Input Path Volume */
102 { 62, 0x3F }, /* r3E - Aux PCM Right Mixer Input Path Volume */
103 { 63, 0x3F }, /* r3F - Aux PCM Left Mixer Volume */
104 { 64, 0x3F }, /* r40 - Aux PCM Left Mixer Volume */
105 { 65, 0x3F }, /* r41 - Aux PCM Left Mixer Audio PCM L Volume */
106 { 66, 0x3F }, /* r42 - Aux PCM Right Mixer Audio PCM R Volume */
107 { 67, 0x3F }, /* r43 - Aux PCM Left Mixer Voice PCM Volume */
108 { 68, 0x3F }, /* r44 - Aux PCM Right Mixer Voice PCM Volume */
109 { 69, 0x3F }, /* r45 - Audio PCM Left Input Path Volume */
110 { 70, 0x3F }, /* r46 - Audio PCM Right Input Path Volume */
111 { 71, 0x3F }, /* r47 - Audio PCM Left Mixer Aux PCM L Volume */
112 { 72, 0x3F }, /* r48 - Audio PCM Right Mixer Aux PCM R Volume */
113 { 73, 0x3F }, /* r49 - Audio PCM Left Mixer Volume */
114 { 74, 0x3F }, /* r4A - Audio PCM Right Mixer Volume */
115 { 75, 0x3F }, /* r4B - Audio PCM Left Mixer Voice PCM Volume */
116 { 76, 0x3F }, /* r4C - Audio PCM Right Mixer Voice PCM Volume */
117 { 77, 0x3F }, /* r4D - Voice PCM Left Input Path Volume */
118 { 78, 0x3F }, /* r4E - Voice PCM Right Input Path Volume */
119 { 79, 0x3F }, /* r4F - Voice PCM Left Mixer Aux PCM L Volume */
120 { 80, 0x3F }, /* r50 - Voice PCM Right Mixer Aux PCM R Volume */
121 { 81, 0x3F }, /* r51 - Voice PCM Left Mixer Audio PCM L Volume */
122 { 82, 0x3F }, /* r52 - Voice PCM Right Mixer Audio PCM R Volume */
123 { 83, 0x3F }, /* r53 - Voice PCM Left Mixer Voice PCM Volume */
124 { 84, 0x3F }, /* r54 - Voice PCM Right Mixer Voice PCM Volume */
125 { 85, 0xAA }, /* r55 - Mono Mixer Ctl */
126 { 86, 0x3F }, /* r56 - SPK Mono Mixer Input Path Volume */
127 { 87, 0x3F }, /* r57 - SPK Mono Mixer Aux PCM Mono/L/R Volume */
128 { 88, 0x3F }, /* r58 - SPK Mono Mixer Audio PCM Mono/L/R Volume */
129 { 89, 0x3F }, /* r59 - SPK Mono Mixer Voice PCM Mono Volume */
130 { 90, 0x3F }, /* r5A - SPKLO Mono Mixer Input Path Mono Volume */
131 { 91, 0x3F }, /* r5B - SPKLO Mono Mixer Aux Mono/L/R Volume */
132 { 92, 0x3F }, /* r5C - SPKLO Mono Mixer Audio Mono/L/R Volume */
133 { 93, 0x3F }, /* r5D - SPKLO Mono Mixer Voice Mono Volume */
134 { 94, 0x00 }, /* r5E - Interrupt Mask 1 */
135 { 95, 0x00 }, /* r5F - Interrupt Mask 2 */
136 };
137
138 static bool cs42l73_volatile_register(struct device *dev, unsigned int reg)
139 {
140 switch (reg) {
141 case CS42L73_IS1:
142 case CS42L73_IS2:
143 return true;
144 default:
145 return false;
146 }
147 }
148
149 static bool cs42l73_readable_register(struct device *dev, unsigned int reg)
150 {
151 switch (reg) {
152 case CS42L73_DEVID_AB ... CS42L73_DEVID_E:
153 case CS42L73_REVID ... CS42L73_IM2:
154 return true;
155 default:
156 return false;
157 }
158 }
159
160 static const DECLARE_TLV_DB_RANGE(hpaloa_tlv,
161 0, 13, TLV_DB_SCALE_ITEM(-7600, 200, 0),
162 14, 75, TLV_DB_SCALE_ITEM(-4900, 100, 0)
163 );
164
165 static DECLARE_TLV_DB_SCALE(adc_boost_tlv, 0, 2500, 0);
166
167 static DECLARE_TLV_DB_SCALE(hl_tlv, -10200, 50, 0);
168
169 static DECLARE_TLV_DB_SCALE(ipd_tlv, -9600, 100, 0);
170
171 static DECLARE_TLV_DB_SCALE(micpga_tlv, -600, 50, 0);
172
173 static const DECLARE_TLV_DB_RANGE(limiter_tlv,
174 0, 2, TLV_DB_SCALE_ITEM(-3000, 600, 0),
175 3, 7, TLV_DB_SCALE_ITEM(-1200, 300, 0)
176 );
177
178 static const DECLARE_TLV_DB_SCALE(attn_tlv, -6300, 100, 1);
179
180 static const char * const cs42l73_pgaa_text[] = { "Line A", "Mic 1" };
181 static const char * const cs42l73_pgab_text[] = { "Line B", "Mic 2" };
182
183 static SOC_ENUM_SINGLE_DECL(pgaa_enum,
184 CS42L73_ADCIPC, 3,
185 cs42l73_pgaa_text);
186
187 static SOC_ENUM_SINGLE_DECL(pgab_enum,
188 CS42L73_ADCIPC, 7,
189 cs42l73_pgab_text);
190
191 static const struct snd_kcontrol_new pgaa_mux =
192 SOC_DAPM_ENUM("Left Analog Input Capture Mux", pgaa_enum);
193
194 static const struct snd_kcontrol_new pgab_mux =
195 SOC_DAPM_ENUM("Right Analog Input Capture Mux", pgab_enum);
196
197 static const struct snd_kcontrol_new input_left_mixer[] = {
198 SOC_DAPM_SINGLE("ADC Left Input", CS42L73_PWRCTL1,
199 5, 1, 1),
200 SOC_DAPM_SINGLE("DMIC Left Input", CS42L73_PWRCTL1,
201 4, 1, 1),
202 };
203
204 static const struct snd_kcontrol_new input_right_mixer[] = {
205 SOC_DAPM_SINGLE("ADC Right Input", CS42L73_PWRCTL1,
206 7, 1, 1),
207 SOC_DAPM_SINGLE("DMIC Right Input", CS42L73_PWRCTL1,
208 6, 1, 1),
209 };
210
211 static const char * const cs42l73_ng_delay_text[] = {
212 "50ms", "100ms", "150ms", "200ms" };
213
214 static SOC_ENUM_SINGLE_DECL(ng_delay_enum,
215 CS42L73_NGCAB, 0,
216 cs42l73_ng_delay_text);
217
218 static const char * const cs42l73_mono_mix_texts[] = {
219 "Left", "Right", "Mono Mix"};
220
221 static const unsigned int cs42l73_mono_mix_values[] = { 0, 1, 2 };
222
223 static const struct soc_enum spk_asp_enum =
224 SOC_VALUE_ENUM_SINGLE(CS42L73_MMIXCTL, 6, 3,
225 ARRAY_SIZE(cs42l73_mono_mix_texts),
226 cs42l73_mono_mix_texts,
227 cs42l73_mono_mix_values);
228
229 static const struct snd_kcontrol_new spk_asp_mixer =
230 SOC_DAPM_ENUM("Route", spk_asp_enum);
231
232 static const struct soc_enum spk_xsp_enum =
233 SOC_VALUE_ENUM_SINGLE(CS42L73_MMIXCTL, 4, 3,
234 ARRAY_SIZE(cs42l73_mono_mix_texts),
235 cs42l73_mono_mix_texts,
236 cs42l73_mono_mix_values);
237
238 static const struct snd_kcontrol_new spk_xsp_mixer =
239 SOC_DAPM_ENUM("Route", spk_xsp_enum);
240
241 static const struct soc_enum esl_asp_enum =
242 SOC_VALUE_ENUM_SINGLE(CS42L73_MMIXCTL, 2, 3,
243 ARRAY_SIZE(cs42l73_mono_mix_texts),
244 cs42l73_mono_mix_texts,
245 cs42l73_mono_mix_values);
246
247 static const struct snd_kcontrol_new esl_asp_mixer =
248 SOC_DAPM_ENUM("Route", esl_asp_enum);
249
250 static const struct soc_enum esl_xsp_enum =
251 SOC_VALUE_ENUM_SINGLE(CS42L73_MMIXCTL, 0, 3,
252 ARRAY_SIZE(cs42l73_mono_mix_texts),
253 cs42l73_mono_mix_texts,
254 cs42l73_mono_mix_values);
255
256 static const struct snd_kcontrol_new esl_xsp_mixer =
257 SOC_DAPM_ENUM("Route", esl_xsp_enum);
258
259 static const char * const cs42l73_ip_swap_text[] = {
260 "Stereo", "Mono A", "Mono B", "Swap A-B"};
261
262 static SOC_ENUM_SINGLE_DECL(ip_swap_enum,
263 CS42L73_MIOPC, 6,
264 cs42l73_ip_swap_text);
265
266 static const char * const cs42l73_spo_mixer_text[] = {"Mono", "Stereo"};
267
268 static SOC_ENUM_SINGLE_DECL(vsp_output_mux_enum,
269 CS42L73_MIXERCTL, 5,
270 cs42l73_spo_mixer_text);
271
272 static SOC_ENUM_SINGLE_DECL(xsp_output_mux_enum,
273 CS42L73_MIXERCTL, 4,
274 cs42l73_spo_mixer_text);
275
276 static const struct snd_kcontrol_new vsp_output_mux =
277 SOC_DAPM_ENUM("Route", vsp_output_mux_enum);
278
279 static const struct snd_kcontrol_new xsp_output_mux =
280 SOC_DAPM_ENUM("Route", xsp_output_mux_enum);
281
282 static const struct snd_kcontrol_new hp_amp_ctl =
283 SOC_DAPM_SINGLE("Switch", CS42L73_PWRCTL3, 0, 1, 1);
284
285 static const struct snd_kcontrol_new lo_amp_ctl =
286 SOC_DAPM_SINGLE("Switch", CS42L73_PWRCTL3, 1, 1, 1);
287
288 static const struct snd_kcontrol_new spk_amp_ctl =
289 SOC_DAPM_SINGLE("Switch", CS42L73_PWRCTL3, 2, 1, 1);
290
291 static const struct snd_kcontrol_new spklo_amp_ctl =
292 SOC_DAPM_SINGLE("Switch", CS42L73_PWRCTL3, 4, 1, 1);
293
294 static const struct snd_kcontrol_new ear_amp_ctl =
295 SOC_DAPM_SINGLE("Switch", CS42L73_PWRCTL3, 3, 1, 1);
296
297 static const struct snd_kcontrol_new cs42l73_snd_controls[] = {
298 SOC_DOUBLE_R_SX_TLV("Headphone Analog Playback Volume",
299 CS42L73_HPAAVOL, CS42L73_HPBAVOL, 0,
300 0x41, 0x4B, hpaloa_tlv),
301
302 SOC_DOUBLE_R_SX_TLV("LineOut Analog Playback Volume", CS42L73_LOAAVOL,
303 CS42L73_LOBAVOL, 0, 0x41, 0x4B, hpaloa_tlv),
304
305 SOC_DOUBLE_R_SX_TLV("Input PGA Analog Volume", CS42L73_MICAPREPGAAVOL,
306 CS42L73_MICBPREPGABVOL, 0, 0x34,
307 0x24, micpga_tlv),
308
309 SOC_DOUBLE_R("MIC Preamp Switch", CS42L73_MICAPREPGAAVOL,
310 CS42L73_MICBPREPGABVOL, 6, 1, 1),
311
312 SOC_DOUBLE_R_SX_TLV("Input Path Digital Volume", CS42L73_IPADVOL,
313 CS42L73_IPBDVOL, 0, 0xA0, 0x6C, ipd_tlv),
314
315 SOC_DOUBLE_R_SX_TLV("HL Digital Playback Volume",
316 CS42L73_HLADVOL, CS42L73_HLBDVOL,
317 0, 0x34, 0xE4, hl_tlv),
318
319 SOC_SINGLE_TLV("ADC A Boost Volume",
320 CS42L73_ADCIPC, 2, 0x01, 1, adc_boost_tlv),
321
322 SOC_SINGLE_TLV("ADC B Boost Volume",
323 CS42L73_ADCIPC, 6, 0x01, 1, adc_boost_tlv),
324
325 SOC_SINGLE_SX_TLV("Speakerphone Digital Volume",
326 CS42L73_SPKDVOL, 0, 0x34, 0xE4, hl_tlv),
327
328 SOC_SINGLE_SX_TLV("Ear Speaker Digital Volume",
329 CS42L73_ESLDVOL, 0, 0x34, 0xE4, hl_tlv),
330
331 SOC_DOUBLE_R("Headphone Analog Playback Switch", CS42L73_HPAAVOL,
332 CS42L73_HPBAVOL, 7, 1, 1),
333
334 SOC_DOUBLE_R("LineOut Analog Playback Switch", CS42L73_LOAAVOL,
335 CS42L73_LOBAVOL, 7, 1, 1),
336 SOC_DOUBLE("Input Path Digital Switch", CS42L73_ADCIPC, 0, 4, 1, 1),
337 SOC_DOUBLE("HL Digital Playback Switch", CS42L73_PBDC, 0,
338 1, 1, 1),
339 SOC_SINGLE("Speakerphone Digital Playback Switch", CS42L73_PBDC, 2, 1,
340 1),
341 SOC_SINGLE("Ear Speaker Digital Playback Switch", CS42L73_PBDC, 3, 1,
342 1),
343
344 SOC_SINGLE("PGA Soft-Ramp Switch", CS42L73_MIOPC, 3, 1, 0),
345 SOC_SINGLE("Analog Zero Cross Switch", CS42L73_MIOPC, 2, 1, 0),
346 SOC_SINGLE("Digital Soft-Ramp Switch", CS42L73_MIOPC, 1, 1, 0),
347 SOC_SINGLE("Analog Output Soft-Ramp Switch", CS42L73_MIOPC, 0, 1, 0),
348
349 SOC_DOUBLE("ADC Signal Polarity Switch", CS42L73_ADCIPC, 1, 5, 1,
350 0),
351
352 SOC_SINGLE("HL Limiter Attack Rate", CS42L73_LIMARATEHL, 0, 0x3F,
353 0),
354 SOC_SINGLE("HL Limiter Release Rate", CS42L73_LIMRRATEHL, 0,
355 0x3F, 0),
356
357
358 SOC_SINGLE("HL Limiter Switch", CS42L73_LIMRRATEHL, 7, 1, 0),
359 SOC_SINGLE("HL Limiter All Channels Switch", CS42L73_LIMRRATEHL, 6, 1,
360 0),
361
362 SOC_SINGLE_TLV("HL Limiter Max Threshold Volume", CS42L73_LMAXHL, 5, 7,
363 1, limiter_tlv),
364
365 SOC_SINGLE_TLV("HL Limiter Cushion Volume", CS42L73_LMAXHL, 2, 7, 1,
366 limiter_tlv),
367
368 SOC_SINGLE("SPK Limiter Attack Rate Volume", CS42L73_LIMARATESPK, 0,
369 0x3F, 0),
370 SOC_SINGLE("SPK Limiter Release Rate Volume", CS42L73_LIMRRATESPK, 0,
371 0x3F, 0),
372 SOC_SINGLE("SPK Limiter Switch", CS42L73_LIMRRATESPK, 7, 1, 0),
373 SOC_SINGLE("SPK Limiter All Channels Switch", CS42L73_LIMRRATESPK,
374 6, 1, 0),
375 SOC_SINGLE_TLV("SPK Limiter Max Threshold Volume", CS42L73_LMAXSPK, 5,
376 7, 1, limiter_tlv),
377
378 SOC_SINGLE_TLV("SPK Limiter Cushion Volume", CS42L73_LMAXSPK, 2, 7, 1,
379 limiter_tlv),
380
381 SOC_SINGLE("ESL Limiter Attack Rate Volume", CS42L73_LIMARATEESL, 0,
382 0x3F, 0),
383 SOC_SINGLE("ESL Limiter Release Rate Volume", CS42L73_LIMRRATEESL, 0,
384 0x3F, 0),
385 SOC_SINGLE("ESL Limiter Switch", CS42L73_LIMRRATEESL, 7, 1, 0),
386 SOC_SINGLE_TLV("ESL Limiter Max Threshold Volume", CS42L73_LMAXESL, 5,
387 7, 1, limiter_tlv),
388
389 SOC_SINGLE_TLV("ESL Limiter Cushion Volume", CS42L73_LMAXESL, 2, 7, 1,
390 limiter_tlv),
391
392 SOC_SINGLE("ALC Attack Rate Volume", CS42L73_ALCARATE, 0, 0x3F, 0),
393 SOC_SINGLE("ALC Release Rate Volume", CS42L73_ALCRRATE, 0, 0x3F, 0),
394 SOC_DOUBLE("ALC Switch", CS42L73_ALCARATE, 6, 7, 1, 0),
395 SOC_SINGLE_TLV("ALC Max Threshold Volume", CS42L73_ALCMINMAX, 5, 7, 0,
396 limiter_tlv),
397 SOC_SINGLE_TLV("ALC Min Threshold Volume", CS42L73_ALCMINMAX, 2, 7, 0,
398 limiter_tlv),
399
400 SOC_DOUBLE("NG Enable Switch", CS42L73_NGCAB, 6, 7, 1, 0),
401 SOC_SINGLE("NG Boost Switch", CS42L73_NGCAB, 5, 1, 0),
402 /*
403 NG Threshold depends on NG_BOOTSAB, which selects
404 between two threshold scales in decibels.
405 Set linear values for now ..
406 */
407 SOC_SINGLE("NG Threshold", CS42L73_NGCAB, 2, 7, 0),
408 SOC_ENUM("NG Delay", ng_delay_enum),
409
410 SOC_DOUBLE_R_TLV("XSP-IP Volume",
411 CS42L73_XSPAIPAA, CS42L73_XSPBIPBA, 0, 0x3F, 1,
412 attn_tlv),
413 SOC_DOUBLE_R_TLV("XSP-XSP Volume",
414 CS42L73_XSPAXSPAA, CS42L73_XSPBXSPBA, 0, 0x3F, 1,
415 attn_tlv),
416 SOC_DOUBLE_R_TLV("XSP-ASP Volume",
417 CS42L73_XSPAASPAA, CS42L73_XSPAASPBA, 0, 0x3F, 1,
418 attn_tlv),
419 SOC_DOUBLE_R_TLV("XSP-VSP Volume",
420 CS42L73_XSPAVSPMA, CS42L73_XSPBVSPMA, 0, 0x3F, 1,
421 attn_tlv),
422
423 SOC_DOUBLE_R_TLV("ASP-IP Volume",
424 CS42L73_ASPAIPAA, CS42L73_ASPBIPBA, 0, 0x3F, 1,
425 attn_tlv),
426 SOC_DOUBLE_R_TLV("ASP-XSP Volume",
427 CS42L73_ASPAXSPAA, CS42L73_ASPBXSPBA, 0, 0x3F, 1,
428 attn_tlv),
429 SOC_DOUBLE_R_TLV("ASP-ASP Volume",
430 CS42L73_ASPAASPAA, CS42L73_ASPBASPBA, 0, 0x3F, 1,
431 attn_tlv),
432 SOC_DOUBLE_R_TLV("ASP-VSP Volume",
433 CS42L73_ASPAVSPMA, CS42L73_ASPBVSPMA, 0, 0x3F, 1,
434 attn_tlv),
435
436 SOC_DOUBLE_R_TLV("VSP-IP Volume",
437 CS42L73_VSPAIPAA, CS42L73_VSPBIPBA, 0, 0x3F, 1,
438 attn_tlv),
439 SOC_DOUBLE_R_TLV("VSP-XSP Volume",
440 CS42L73_VSPAXSPAA, CS42L73_VSPBXSPBA, 0, 0x3F, 1,
441 attn_tlv),
442 SOC_DOUBLE_R_TLV("VSP-ASP Volume",
443 CS42L73_VSPAASPAA, CS42L73_VSPBASPBA, 0, 0x3F, 1,
444 attn_tlv),
445 SOC_DOUBLE_R_TLV("VSP-VSP Volume",
446 CS42L73_VSPAVSPMA, CS42L73_VSPBVSPMA, 0, 0x3F, 1,
447 attn_tlv),
448
449 SOC_DOUBLE_R_TLV("HL-IP Volume",
450 CS42L73_HLAIPAA, CS42L73_HLBIPBA, 0, 0x3F, 1,
451 attn_tlv),
452 SOC_DOUBLE_R_TLV("HL-XSP Volume",
453 CS42L73_HLAXSPAA, CS42L73_HLBXSPBA, 0, 0x3F, 1,
454 attn_tlv),
455 SOC_DOUBLE_R_TLV("HL-ASP Volume",
456 CS42L73_HLAASPAA, CS42L73_HLBASPBA, 0, 0x3F, 1,
457 attn_tlv),
458 SOC_DOUBLE_R_TLV("HL-VSP Volume",
459 CS42L73_HLAVSPMA, CS42L73_HLBVSPMA, 0, 0x3F, 1,
460 attn_tlv),
461
462 SOC_SINGLE_TLV("SPK-IP Mono Volume",
463 CS42L73_SPKMIPMA, 0, 0x3F, 1, attn_tlv),
464 SOC_SINGLE_TLV("SPK-XSP Mono Volume",
465 CS42L73_SPKMXSPA, 0, 0x3F, 1, attn_tlv),
466 SOC_SINGLE_TLV("SPK-ASP Mono Volume",
467 CS42L73_SPKMASPA, 0, 0x3F, 1, attn_tlv),
468 SOC_SINGLE_TLV("SPK-VSP Mono Volume",
469 CS42L73_SPKMVSPMA, 0, 0x3F, 1, attn_tlv),
470
471 SOC_SINGLE_TLV("ESL-IP Mono Volume",
472 CS42L73_ESLMIPMA, 0, 0x3F, 1, attn_tlv),
473 SOC_SINGLE_TLV("ESL-XSP Mono Volume",
474 CS42L73_ESLMXSPA, 0, 0x3F, 1, attn_tlv),
475 SOC_SINGLE_TLV("ESL-ASP Mono Volume",
476 CS42L73_ESLMASPA, 0, 0x3F, 1, attn_tlv),
477 SOC_SINGLE_TLV("ESL-VSP Mono Volume",
478 CS42L73_ESLMVSPMA, 0, 0x3F, 1, attn_tlv),
479
480 SOC_ENUM("IP Digital Swap/Mono Select", ip_swap_enum),
481
482 SOC_ENUM("VSPOUT Mono/Stereo Select", vsp_output_mux_enum),
483 SOC_ENUM("XSPOUT Mono/Stereo Select", xsp_output_mux_enum),
484 };
485
486 static int cs42l73_spklo_spk_amp_event(struct snd_soc_dapm_widget *w,
487 struct snd_kcontrol *kcontrol, int event)
488 {
489 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
490 struct cs42l73_private *priv = snd_soc_component_get_drvdata(component);
491 switch (event) {
492 case SND_SOC_DAPM_POST_PMD:
493 /* 150 ms delay between setting PDN and MCLKDIS */
494 priv->shutdwn_delay = 150;
495 break;
496 default:
497 pr_err("Invalid event = 0x%x\n", event);
498 }
499 return 0;
500 }
501
502 static int cs42l73_ear_amp_event(struct snd_soc_dapm_widget *w,
503 struct snd_kcontrol *kcontrol, int event)
504 {
505 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
506 struct cs42l73_private *priv = snd_soc_component_get_drvdata(component);
507 switch (event) {
508 case SND_SOC_DAPM_POST_PMD:
509 /* 50 ms delay between setting PDN and MCLKDIS */
510 if (priv->shutdwn_delay < 50)
511 priv->shutdwn_delay = 50;
512 break;
513 default:
514 pr_err("Invalid event = 0x%x\n", event);
515 }
516 return 0;
517 }
518
519
520 static int cs42l73_hp_amp_event(struct snd_soc_dapm_widget *w,
521 struct snd_kcontrol *kcontrol, int event)
522 {
523 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
524 struct cs42l73_private *priv = snd_soc_component_get_drvdata(component);
525 switch (event) {
526 case SND_SOC_DAPM_POST_PMD:
527 /* 30 ms delay between setting PDN and MCLKDIS */
528 if (priv->shutdwn_delay < 30)
529 priv->shutdwn_delay = 30;
530 break;
531 default:
532 pr_err("Invalid event = 0x%x\n", event);
533 }
534 return 0;
535 }
536
537 static const struct snd_soc_dapm_widget cs42l73_dapm_widgets[] = {
538 SND_SOC_DAPM_INPUT("DMICA"),
539 SND_SOC_DAPM_INPUT("DMICB"),
540 SND_SOC_DAPM_INPUT("LINEINA"),
541 SND_SOC_DAPM_INPUT("LINEINB"),
542 SND_SOC_DAPM_INPUT("MIC1"),
543 SND_SOC_DAPM_SUPPLY("MIC1 Bias", CS42L73_PWRCTL2, 6, 1, NULL, 0),
544 SND_SOC_DAPM_INPUT("MIC2"),
545 SND_SOC_DAPM_SUPPLY("MIC2 Bias", CS42L73_PWRCTL2, 7, 1, NULL, 0),
546
547 SND_SOC_DAPM_AIF_OUT("XSPOUTL", NULL, 0,
548 CS42L73_PWRCTL2, 1, 1),
549 SND_SOC_DAPM_AIF_OUT("XSPOUTR", NULL, 0,
550 CS42L73_PWRCTL2, 1, 1),
551 SND_SOC_DAPM_AIF_OUT("ASPOUTL", NULL, 0,
552 CS42L73_PWRCTL2, 3, 1),
553 SND_SOC_DAPM_AIF_OUT("ASPOUTR", NULL, 0,
554 CS42L73_PWRCTL2, 3, 1),
555 SND_SOC_DAPM_AIF_OUT("VSPINOUT", NULL, 0,
556 CS42L73_PWRCTL2, 4, 1),
557
558 SND_SOC_DAPM_PGA("PGA Left", SND_SOC_NOPM, 0, 0, NULL, 0),
559 SND_SOC_DAPM_PGA("PGA Right", SND_SOC_NOPM, 0, 0, NULL, 0),
560
561 SND_SOC_DAPM_MUX("PGA Left Mux", SND_SOC_NOPM, 0, 0, &pgaa_mux),
562 SND_SOC_DAPM_MUX("PGA Right Mux", SND_SOC_NOPM, 0, 0, &pgab_mux),
563
564 SND_SOC_DAPM_ADC("ADC Left", NULL, CS42L73_PWRCTL1, 7, 1),
565 SND_SOC_DAPM_ADC("ADC Right", NULL, CS42L73_PWRCTL1, 5, 1),
566 SND_SOC_DAPM_ADC("DMIC Left", NULL, CS42L73_PWRCTL1, 6, 1),
567 SND_SOC_DAPM_ADC("DMIC Right", NULL, CS42L73_PWRCTL1, 4, 1),
568
569 SND_SOC_DAPM_MIXER_NAMED_CTL("Input Left Capture", SND_SOC_NOPM,
570 0, 0, input_left_mixer,
571 ARRAY_SIZE(input_left_mixer)),
572
573 SND_SOC_DAPM_MIXER_NAMED_CTL("Input Right Capture", SND_SOC_NOPM,
574 0, 0, input_right_mixer,
575 ARRAY_SIZE(input_right_mixer)),
576
577 SND_SOC_DAPM_MIXER("ASPL Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
578 SND_SOC_DAPM_MIXER("ASPR Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
579 SND_SOC_DAPM_MIXER("XSPL Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
580 SND_SOC_DAPM_MIXER("XSPR Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
581 SND_SOC_DAPM_MIXER("VSP Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
582
583 SND_SOC_DAPM_AIF_IN("XSPINL", NULL, 0,
584 CS42L73_PWRCTL2, 0, 1),
585 SND_SOC_DAPM_AIF_IN("XSPINR", NULL, 0,
586 CS42L73_PWRCTL2, 0, 1),
587 SND_SOC_DAPM_AIF_IN("XSPINM", NULL, 0,
588 CS42L73_PWRCTL2, 0, 1),
589
590 SND_SOC_DAPM_AIF_IN("ASPINL", NULL, 0,
591 CS42L73_PWRCTL2, 2, 1),
592 SND_SOC_DAPM_AIF_IN("ASPINR", NULL, 0,
593 CS42L73_PWRCTL2, 2, 1),
594 SND_SOC_DAPM_AIF_IN("ASPINM", NULL, 0,
595 CS42L73_PWRCTL2, 2, 1),
596
597 SND_SOC_DAPM_AIF_IN("VSPINOUT", NULL, 0,
598 CS42L73_PWRCTL2, 4, 1),
599
600 SND_SOC_DAPM_MIXER("HL Left Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
601 SND_SOC_DAPM_MIXER("HL Right Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
602 SND_SOC_DAPM_MIXER("SPK Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
603 SND_SOC_DAPM_MIXER("ESL Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
604
605 SND_SOC_DAPM_MUX("ESL-XSP Mux", SND_SOC_NOPM,
606 0, 0, &esl_xsp_mixer),
607
608 SND_SOC_DAPM_MUX("ESL-ASP Mux", SND_SOC_NOPM,
609 0, 0, &esl_asp_mixer),
610
611 SND_SOC_DAPM_MUX("SPK-ASP Mux", SND_SOC_NOPM,
612 0, 0, &spk_asp_mixer),
613
614 SND_SOC_DAPM_MUX("SPK-XSP Mux", SND_SOC_NOPM,
615 0, 0, &spk_xsp_mixer),
616
617 SND_SOC_DAPM_PGA("HL Left DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
618 SND_SOC_DAPM_PGA("HL Right DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
619 SND_SOC_DAPM_PGA("SPK DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
620 SND_SOC_DAPM_PGA("ESL DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
621
622 SND_SOC_DAPM_SWITCH_E("HP Amp", CS42L73_PWRCTL3, 0, 1,
623 &hp_amp_ctl, cs42l73_hp_amp_event,
624 SND_SOC_DAPM_POST_PMD),
625 SND_SOC_DAPM_SWITCH("LO Amp", CS42L73_PWRCTL3, 1, 1,
626 &lo_amp_ctl),
627 SND_SOC_DAPM_SWITCH_E("SPK Amp", CS42L73_PWRCTL3, 2, 1,
628 &spk_amp_ctl, cs42l73_spklo_spk_amp_event,
629 SND_SOC_DAPM_POST_PMD),
630 SND_SOC_DAPM_SWITCH_E("EAR Amp", CS42L73_PWRCTL3, 3, 1,
631 &ear_amp_ctl, cs42l73_ear_amp_event,
632 SND_SOC_DAPM_POST_PMD),
633 SND_SOC_DAPM_SWITCH_E("SPKLO Amp", CS42L73_PWRCTL3, 4, 1,
634 &spklo_amp_ctl, cs42l73_spklo_spk_amp_event,
635 SND_SOC_DAPM_POST_PMD),
636
637 SND_SOC_DAPM_OUTPUT("HPOUTA"),
638 SND_SOC_DAPM_OUTPUT("HPOUTB"),
639 SND_SOC_DAPM_OUTPUT("LINEOUTA"),
640 SND_SOC_DAPM_OUTPUT("LINEOUTB"),
641 SND_SOC_DAPM_OUTPUT("EAROUT"),
642 SND_SOC_DAPM_OUTPUT("SPKOUT"),
643 SND_SOC_DAPM_OUTPUT("SPKLINEOUT"),
644 };
645
646 static const struct snd_soc_dapm_route cs42l73_audio_map[] = {
647
648 /* SPKLO EARSPK Paths */
649 {"EAROUT", NULL, "EAR Amp"},
650 {"SPKLINEOUT", NULL, "SPKLO Amp"},
651
652 {"EAR Amp", "Switch", "ESL DAC"},
653 {"SPKLO Amp", "Switch", "ESL DAC"},
654
655 {"ESL DAC", "ESL-ASP Mono Volume", "ESL Mixer"},
656 {"ESL DAC", "ESL-XSP Mono Volume", "ESL Mixer"},
657 {"ESL DAC", "ESL-VSP Mono Volume", "VSPINOUT"},
658 /* Loopback */
659 {"ESL DAC", "ESL-IP Mono Volume", "Input Left Capture"},
660 {"ESL DAC", "ESL-IP Mono Volume", "Input Right Capture"},
661
662 {"ESL Mixer", NULL, "ESL-ASP Mux"},
663 {"ESL Mixer", NULL, "ESL-XSP Mux"},
664
665 {"ESL-ASP Mux", "Left", "ASPINL"},
666 {"ESL-ASP Mux", "Right", "ASPINR"},
667 {"ESL-ASP Mux", "Mono Mix", "ASPINM"},
668
669 {"ESL-XSP Mux", "Left", "XSPINL"},
670 {"ESL-XSP Mux", "Right", "XSPINR"},
671 {"ESL-XSP Mux", "Mono Mix", "XSPINM"},
672
673 /* Speakerphone Paths */
674 {"SPKOUT", NULL, "SPK Amp"},
675 {"SPK Amp", "Switch", "SPK DAC"},
676
677 {"SPK DAC", "SPK-ASP Mono Volume", "SPK Mixer"},
678 {"SPK DAC", "SPK-XSP Mono Volume", "SPK Mixer"},
679 {"SPK DAC", "SPK-VSP Mono Volume", "VSPINOUT"},
680 /* Loopback */
681 {"SPK DAC", "SPK-IP Mono Volume", "Input Left Capture"},
682 {"SPK DAC", "SPK-IP Mono Volume", "Input Right Capture"},
683
684 {"SPK Mixer", NULL, "SPK-ASP Mux"},
685 {"SPK Mixer", NULL, "SPK-XSP Mux"},
686
687 {"SPK-ASP Mux", "Left", "ASPINL"},
688 {"SPK-ASP Mux", "Mono Mix", "ASPINM"},
689 {"SPK-ASP Mux", "Right", "ASPINR"},
690
691 {"SPK-XSP Mux", "Left", "XSPINL"},
692 {"SPK-XSP Mux", "Mono Mix", "XSPINM"},
693 {"SPK-XSP Mux", "Right", "XSPINR"},
694
695 /* HP LineOUT Paths */
696 {"HPOUTA", NULL, "HP Amp"},
697 {"HPOUTB", NULL, "HP Amp"},
698 {"LINEOUTA", NULL, "LO Amp"},
699 {"LINEOUTB", NULL, "LO Amp"},
700
701 {"HP Amp", "Switch", "HL Left DAC"},
702 {"HP Amp", "Switch", "HL Right DAC"},
703 {"LO Amp", "Switch", "HL Left DAC"},
704 {"LO Amp", "Switch", "HL Right DAC"},
705
706 {"HL Left DAC", "HL-XSP Volume", "HL Left Mixer"},
707 {"HL Right DAC", "HL-XSP Volume", "HL Right Mixer"},
708 {"HL Left DAC", "HL-ASP Volume", "HL Left Mixer"},
709 {"HL Right DAC", "HL-ASP Volume", "HL Right Mixer"},
710 {"HL Left DAC", "HL-VSP Volume", "HL Left Mixer"},
711 {"HL Right DAC", "HL-VSP Volume", "HL Right Mixer"},
712 /* Loopback */
713 {"HL Left DAC", "HL-IP Volume", "HL Left Mixer"},
714 {"HL Right DAC", "HL-IP Volume", "HL Right Mixer"},
715 {"HL Left Mixer", NULL, "Input Left Capture"},
716 {"HL Right Mixer", NULL, "Input Right Capture"},
717
718 {"HL Left Mixer", NULL, "ASPINL"},
719 {"HL Right Mixer", NULL, "ASPINR"},
720 {"HL Left Mixer", NULL, "XSPINL"},
721 {"HL Right Mixer", NULL, "XSPINR"},
722 {"HL Left Mixer", NULL, "VSPINOUT"},
723 {"HL Right Mixer", NULL, "VSPINOUT"},
724
725 {"ASPINL", NULL, "ASP Playback"},
726 {"ASPINM", NULL, "ASP Playback"},
727 {"ASPINR", NULL, "ASP Playback"},
728 {"XSPINL", NULL, "XSP Playback"},
729 {"XSPINM", NULL, "XSP Playback"},
730 {"XSPINR", NULL, "XSP Playback"},
731 {"VSPINOUT", NULL, "VSP Playback"},
732
733 /* Capture Paths */
734 {"MIC1", NULL, "MIC1 Bias"},
735 {"PGA Left Mux", "Mic 1", "MIC1"},
736 {"MIC2", NULL, "MIC2 Bias"},
737 {"PGA Right Mux", "Mic 2", "MIC2"},
738
739 {"PGA Left Mux", "Line A", "LINEINA"},
740 {"PGA Right Mux", "Line B", "LINEINB"},
741
742 {"PGA Left", NULL, "PGA Left Mux"},
743 {"PGA Right", NULL, "PGA Right Mux"},
744
745 {"ADC Left", NULL, "PGA Left"},
746 {"ADC Right", NULL, "PGA Right"},
747 {"DMIC Left", NULL, "DMICA"},
748 {"DMIC Right", NULL, "DMICB"},
749
750 {"Input Left Capture", "ADC Left Input", "ADC Left"},
751 {"Input Right Capture", "ADC Right Input", "ADC Right"},
752 {"Input Left Capture", "DMIC Left Input", "DMIC Left"},
753 {"Input Right Capture", "DMIC Right Input", "DMIC Right"},
754
755 /* Audio Capture */
756 {"ASPL Output Mixer", NULL, "Input Left Capture"},
757 {"ASPR Output Mixer", NULL, "Input Right Capture"},
758
759 {"ASPOUTL", "ASP-IP Volume", "ASPL Output Mixer"},
760 {"ASPOUTR", "ASP-IP Volume", "ASPR Output Mixer"},
761
762 /* Auxillary Capture */
763 {"XSPL Output Mixer", NULL, "Input Left Capture"},
764 {"XSPR Output Mixer", NULL, "Input Right Capture"},
765
766 {"XSPOUTL", "XSP-IP Volume", "XSPL Output Mixer"},
767 {"XSPOUTR", "XSP-IP Volume", "XSPR Output Mixer"},
768
769 {"XSPOUTL", NULL, "XSPL Output Mixer"},
770 {"XSPOUTR", NULL, "XSPR Output Mixer"},
771
772 /* Voice Capture */
773 {"VSP Output Mixer", NULL, "Input Left Capture"},
774 {"VSP Output Mixer", NULL, "Input Right Capture"},
775
776 {"VSPINOUT", "VSP-IP Volume", "VSP Output Mixer"},
777
778 {"VSPINOUT", NULL, "VSP Output Mixer"},
779
780 {"ASP Capture", NULL, "ASPOUTL"},
781 {"ASP Capture", NULL, "ASPOUTR"},
782 {"XSP Capture", NULL, "XSPOUTL"},
783 {"XSP Capture", NULL, "XSPOUTR"},
784 {"VSP Capture", NULL, "VSPINOUT"},
785 };
786
787 struct cs42l73_mclk_div {
788 u32 mclk;
789 u32 srate;
790 u8 mmcc;
791 };
792
793 static const struct cs42l73_mclk_div cs42l73_mclk_coeffs[] = {
794 /* MCLK, Sample Rate, xMMCC[5:0] */
795 {5644800, 11025, 0x30},
796 {5644800, 22050, 0x20},
797 {5644800, 44100, 0x10},
798
799 {6000000, 8000, 0x39},
800 {6000000, 11025, 0x33},
801 {6000000, 12000, 0x31},
802 {6000000, 16000, 0x29},
803 {6000000, 22050, 0x23},
804 {6000000, 24000, 0x21},
805 {6000000, 32000, 0x19},
806 {6000000, 44100, 0x13},
807 {6000000, 48000, 0x11},
808
809 {6144000, 8000, 0x38},
810 {6144000, 12000, 0x30},
811 {6144000, 16000, 0x28},
812 {6144000, 24000, 0x20},
813 {6144000, 32000, 0x18},
814 {6144000, 48000, 0x10},
815
816 {6500000, 8000, 0x3C},
817 {6500000, 11025, 0x35},
818 {6500000, 12000, 0x34},
819 {6500000, 16000, 0x2C},
820 {6500000, 22050, 0x25},
821 {6500000, 24000, 0x24},
822 {6500000, 32000, 0x1C},
823 {6500000, 44100, 0x15},
824 {6500000, 48000, 0x14},
825
826 {6400000, 8000, 0x3E},
827 {6400000, 11025, 0x37},
828 {6400000, 12000, 0x36},
829 {6400000, 16000, 0x2E},
830 {6400000, 22050, 0x27},
831 {6400000, 24000, 0x26},
832 {6400000, 32000, 0x1E},
833 {6400000, 44100, 0x17},
834 {6400000, 48000, 0x16},
835 };
836
837 struct cs42l73_mclkx_div {
838 u32 mclkx;
839 u8 ratio;
840 u8 mclkdiv;
841 };
842
843 static const struct cs42l73_mclkx_div cs42l73_mclkx_coeffs[] = {
844 {5644800, 1, 0}, /* 5644800 */
845 {6000000, 1, 0}, /* 6000000 */
846 {6144000, 1, 0}, /* 6144000 */
847 {11289600, 2, 2}, /* 5644800 */
848 {12288000, 2, 2}, /* 6144000 */
849 {12000000, 2, 2}, /* 6000000 */
850 {13000000, 2, 2}, /* 6500000 */
851 {19200000, 3, 3}, /* 6400000 */
852 {24000000, 4, 4}, /* 6000000 */
853 {26000000, 4, 4}, /* 6500000 */
854 {38400000, 6, 5} /* 6400000 */
855 };
856
857 static int cs42l73_get_mclkx_coeff(int mclkx)
858 {
859 int i;
860
861 for (i = 0; i < ARRAY_SIZE(cs42l73_mclkx_coeffs); i++) {
862 if (cs42l73_mclkx_coeffs[i].mclkx == mclkx)
863 return i;
864 }
865 return -EINVAL;
866 }
867
868 static int cs42l73_get_mclk_coeff(int mclk, int srate)
869 {
870 int i;
871
872 for (i = 0; i < ARRAY_SIZE(cs42l73_mclk_coeffs); i++) {
873 if (cs42l73_mclk_coeffs[i].mclk == mclk &&
874 cs42l73_mclk_coeffs[i].srate == srate)
875 return i;
876 }
877 return -EINVAL;
878
879 }
880
881 static int cs42l73_set_mclk(struct snd_soc_dai *dai, unsigned int freq)
882 {
883 struct snd_soc_component *component = dai->component;
884 struct cs42l73_private *priv = snd_soc_component_get_drvdata(component);
885
886 int mclkx_coeff;
887 u32 mclk = 0;
888 u8 dmmcc = 0;
889
890 /* MCLKX -> MCLK */
891 mclkx_coeff = cs42l73_get_mclkx_coeff(freq);
892 if (mclkx_coeff < 0)
893 return mclkx_coeff;
894
895 mclk = cs42l73_mclkx_coeffs[mclkx_coeff].mclkx /
896 cs42l73_mclkx_coeffs[mclkx_coeff].ratio;
897
898 dev_dbg(component->dev, "MCLK%u %u <-> internal MCLK %u\n",
899 priv->mclksel + 1, cs42l73_mclkx_coeffs[mclkx_coeff].mclkx,
900 mclk);
901
902 dmmcc = (priv->mclksel << 4) |
903 (cs42l73_mclkx_coeffs[mclkx_coeff].mclkdiv << 1);
904
905 snd_soc_component_write(component, CS42L73_DMMCC, dmmcc);
906
907 priv->sysclk = mclkx_coeff;
908 priv->mclk = mclk;
909
910 return 0;
911 }
912
913 static int cs42l73_set_sysclk(struct snd_soc_dai *dai,
914 int clk_id, unsigned int freq, int dir)
915 {
916 struct snd_soc_component *component = dai->component;
917 struct cs42l73_private *priv = snd_soc_component_get_drvdata(component);
918
919 switch (clk_id) {
920 case CS42L73_CLKID_MCLK1:
921 break;
922 case CS42L73_CLKID_MCLK2:
923 break;
924 default:
925 return -EINVAL;
926 }
927
928 if ((cs42l73_set_mclk(dai, freq)) < 0) {
929 dev_err(component->dev, "Unable to set MCLK for dai %s\n",
930 dai->name);
931 return -EINVAL;
932 }
933
934 priv->mclksel = clk_id;
935
936 return 0;
937 }
938
939 static int cs42l73_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
940 {
941 struct snd_soc_component *component = codec_dai->component;
942 struct cs42l73_private *priv = snd_soc_component_get_drvdata(component);
943 u8 id = codec_dai->id;
944 unsigned int inv, format;
945 u8 spc, mmcc;
946
947 spc = snd_soc_component_read32(component, CS42L73_SPC(id));
948 mmcc = snd_soc_component_read32(component, CS42L73_MMCC(id));
949
950 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
951 case SND_SOC_DAIFMT_CBM_CFM:
952 mmcc |= CS42L73_MS_MASTER;
953 break;
954
955 case SND_SOC_DAIFMT_CBS_CFS:
956 mmcc &= ~CS42L73_MS_MASTER;
957 break;
958
959 default:
960 return -EINVAL;
961 }
962
963 format = (fmt & SND_SOC_DAIFMT_FORMAT_MASK);
964 inv = (fmt & SND_SOC_DAIFMT_INV_MASK);
965
966 switch (format) {
967 case SND_SOC_DAIFMT_I2S:
968 spc &= ~CS42L73_SPDIF_PCM;
969 break;
970 case SND_SOC_DAIFMT_DSP_A:
971 case SND_SOC_DAIFMT_DSP_B:
972 if (mmcc & CS42L73_MS_MASTER) {
973 dev_err(component->dev,
974 "PCM format in slave mode only\n");
975 return -EINVAL;
976 }
977 if (id == CS42L73_ASP) {
978 dev_err(component->dev,
979 "PCM format is not supported on ASP port\n");
980 return -EINVAL;
981 }
982 spc |= CS42L73_SPDIF_PCM;
983 break;
984 default:
985 return -EINVAL;
986 }
987
988 if (spc & CS42L73_SPDIF_PCM) {
989 /* Clear PCM mode, clear PCM_BIT_ORDER bit for MSB->LSB */
990 spc &= ~(CS42L73_PCM_MODE_MASK | CS42L73_PCM_BIT_ORDER);
991 switch (format) {
992 case SND_SOC_DAIFMT_DSP_B:
993 if (inv == SND_SOC_DAIFMT_IB_IF)
994 spc |= CS42L73_PCM_MODE0;
995 if (inv == SND_SOC_DAIFMT_IB_NF)
996 spc |= CS42L73_PCM_MODE1;
997 break;
998 case SND_SOC_DAIFMT_DSP_A:
999 if (inv == SND_SOC_DAIFMT_IB_IF)
1000 spc |= CS42L73_PCM_MODE1;
1001 break;
1002 default:
1003 return -EINVAL;
1004 }
1005 }
1006
1007 priv->config[id].spc = spc;
1008 priv->config[id].mmcc = mmcc;
1009
1010 return 0;
1011 }
1012
1013 static const unsigned int cs42l73_asrc_rates[] = {
1014 8000, 11025, 12000, 16000, 22050,
1015 24000, 32000, 44100, 48000
1016 };
1017
1018 static unsigned int cs42l73_get_xspfs_coeff(u32 rate)
1019 {
1020 int i;
1021 for (i = 0; i < ARRAY_SIZE(cs42l73_asrc_rates); i++) {
1022 if (cs42l73_asrc_rates[i] == rate)
1023 return i + 1;
1024 }
1025 return 0; /* 0 = Don't know */
1026 }
1027
1028 static void cs42l73_update_asrc(struct snd_soc_component *component, int id, int srate)
1029 {
1030 u8 spfs = 0;
1031
1032 if (srate > 0)
1033 spfs = cs42l73_get_xspfs_coeff(srate);
1034
1035 switch (id) {
1036 case CS42L73_XSP:
1037 snd_soc_component_update_bits(component, CS42L73_VXSPFS, 0x0f, spfs);
1038 break;
1039 case CS42L73_ASP:
1040 snd_soc_component_update_bits(component, CS42L73_ASPC, 0x3c, spfs << 2);
1041 break;
1042 case CS42L73_VSP:
1043 snd_soc_component_update_bits(component, CS42L73_VXSPFS, 0xf0, spfs << 4);
1044 break;
1045 default:
1046 break;
1047 }
1048 }
1049
1050 static int cs42l73_pcm_hw_params(struct snd_pcm_substream *substream,
1051 struct snd_pcm_hw_params *params,
1052 struct snd_soc_dai *dai)
1053 {
1054 struct snd_soc_component *component = dai->component;
1055 struct cs42l73_private *priv = snd_soc_component_get_drvdata(component);
1056 int id = dai->id;
1057 int mclk_coeff;
1058 int srate = params_rate(params);
1059
1060 if (priv->config[id].mmcc & CS42L73_MS_MASTER) {
1061 /* CS42L73 Master */
1062 /* MCLK -> srate */
1063 mclk_coeff =
1064 cs42l73_get_mclk_coeff(priv->mclk, srate);
1065
1066 if (mclk_coeff < 0)
1067 return -EINVAL;
1068
1069 dev_dbg(component->dev,
1070 "DAI[%d]: MCLK %u, srate %u, MMCC[5:0] = %x\n",
1071 id, priv->mclk, srate,
1072 cs42l73_mclk_coeffs[mclk_coeff].mmcc);
1073
1074 priv->config[id].mmcc &= 0xC0;
1075 priv->config[id].mmcc |= cs42l73_mclk_coeffs[mclk_coeff].mmcc;
1076 priv->config[id].spc &= 0xFC;
1077 /* Use SCLK=64*Fs if internal MCLK >= 6.4MHz */
1078 if (priv->mclk >= 6400000)
1079 priv->config[id].spc |= CS42L73_MCK_SCLK_64FS;
1080 else
1081 priv->config[id].spc |= CS42L73_MCK_SCLK_MCLK;
1082 } else {
1083 /* CS42L73 Slave */
1084 priv->config[id].spc &= 0xFC;
1085 priv->config[id].spc |= CS42L73_MCK_SCLK_64FS;
1086 }
1087 /* Update ASRCs */
1088 priv->config[id].srate = srate;
1089
1090 snd_soc_component_write(component, CS42L73_SPC(id), priv->config[id].spc);
1091 snd_soc_component_write(component, CS42L73_MMCC(id), priv->config[id].mmcc);
1092
1093 cs42l73_update_asrc(component, id, srate);
1094
1095 return 0;
1096 }
1097
1098 static int cs42l73_set_bias_level(struct snd_soc_component *component,
1099 enum snd_soc_bias_level level)
1100 {
1101 struct cs42l73_private *cs42l73 = snd_soc_component_get_drvdata(component);
1102
1103 switch (level) {
1104 case SND_SOC_BIAS_ON:
1105 snd_soc_component_update_bits(component, CS42L73_DMMCC, CS42L73_MCLKDIS, 0);
1106 snd_soc_component_update_bits(component, CS42L73_PWRCTL1, CS42L73_PDN, 0);
1107 break;
1108
1109 case SND_SOC_BIAS_PREPARE:
1110 break;
1111
1112 case SND_SOC_BIAS_STANDBY:
1113 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
1114 regcache_cache_only(cs42l73->regmap, false);
1115 regcache_sync(cs42l73->regmap);
1116 }
1117 snd_soc_component_update_bits(component, CS42L73_PWRCTL1, CS42L73_PDN, 1);
1118 break;
1119
1120 case SND_SOC_BIAS_OFF:
1121 snd_soc_component_update_bits(component, CS42L73_PWRCTL1, CS42L73_PDN, 1);
1122 if (cs42l73->shutdwn_delay > 0) {
1123 mdelay(cs42l73->shutdwn_delay);
1124 cs42l73->shutdwn_delay = 0;
1125 } else {
1126 mdelay(15); /* Min amount of time requred to power
1127 * down.
1128 */
1129 }
1130 snd_soc_component_update_bits(component, CS42L73_DMMCC, CS42L73_MCLKDIS, 1);
1131 break;
1132 }
1133 return 0;
1134 }
1135
1136 static int cs42l73_set_tristate(struct snd_soc_dai *dai, int tristate)
1137 {
1138 struct snd_soc_component *component = dai->component;
1139 int id = dai->id;
1140
1141 return snd_soc_component_update_bits(component, CS42L73_SPC(id), CS42L73_SP_3ST,
1142 tristate << 7);
1143 }
1144
1145 static const struct snd_pcm_hw_constraint_list constraints_12_24 = {
1146 .count = ARRAY_SIZE(cs42l73_asrc_rates),
1147 .list = cs42l73_asrc_rates,
1148 };
1149
1150 static int cs42l73_pcm_startup(struct snd_pcm_substream *substream,
1151 struct snd_soc_dai *dai)
1152 {
1153 snd_pcm_hw_constraint_list(substream->runtime, 0,
1154 SNDRV_PCM_HW_PARAM_RATE,
1155 &constraints_12_24);
1156 return 0;
1157 }
1158
1159
1160 #define CS42L73_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1161 SNDRV_PCM_FMTBIT_S24_LE)
1162
1163 static const struct snd_soc_dai_ops cs42l73_ops = {
1164 .startup = cs42l73_pcm_startup,
1165 .hw_params = cs42l73_pcm_hw_params,
1166 .set_fmt = cs42l73_set_dai_fmt,
1167 .set_sysclk = cs42l73_set_sysclk,
1168 .set_tristate = cs42l73_set_tristate,
1169 };
1170
1171 static struct snd_soc_dai_driver cs42l73_dai[] = {
1172 {
1173 .name = "cs42l73-xsp",
1174 .id = CS42L73_XSP,
1175 .playback = {
1176 .stream_name = "XSP Playback",
1177 .channels_min = 1,
1178 .channels_max = 2,
1179 .rates = SNDRV_PCM_RATE_KNOT,
1180 .formats = CS42L73_FORMATS,
1181 },
1182 .capture = {
1183 .stream_name = "XSP Capture",
1184 .channels_min = 1,
1185 .channels_max = 2,
1186 .rates = SNDRV_PCM_RATE_KNOT,
1187 .formats = CS42L73_FORMATS,
1188 },
1189 .ops = &cs42l73_ops,
1190 .symmetric_rates = 1,
1191 },
1192 {
1193 .name = "cs42l73-asp",
1194 .id = CS42L73_ASP,
1195 .playback = {
1196 .stream_name = "ASP Playback",
1197 .channels_min = 2,
1198 .channels_max = 2,
1199 .rates = SNDRV_PCM_RATE_KNOT,
1200 .formats = CS42L73_FORMATS,
1201 },
1202 .capture = {
1203 .stream_name = "ASP Capture",
1204 .channels_min = 2,
1205 .channels_max = 2,
1206 .rates = SNDRV_PCM_RATE_KNOT,
1207 .formats = CS42L73_FORMATS,
1208 },
1209 .ops = &cs42l73_ops,
1210 .symmetric_rates = 1,
1211 },
1212 {
1213 .name = "cs42l73-vsp",
1214 .id = CS42L73_VSP,
1215 .playback = {
1216 .stream_name = "VSP Playback",
1217 .channels_min = 1,
1218 .channels_max = 2,
1219 .rates = SNDRV_PCM_RATE_KNOT,
1220 .formats = CS42L73_FORMATS,
1221 },
1222 .capture = {
1223 .stream_name = "VSP Capture",
1224 .channels_min = 1,
1225 .channels_max = 2,
1226 .rates = SNDRV_PCM_RATE_KNOT,
1227 .formats = CS42L73_FORMATS,
1228 },
1229 .ops = &cs42l73_ops,
1230 .symmetric_rates = 1,
1231 }
1232 };
1233
1234 static int cs42l73_probe(struct snd_soc_component *component)
1235 {
1236 struct cs42l73_private *cs42l73 = snd_soc_component_get_drvdata(component);
1237
1238 /* Set Charge Pump Frequency */
1239 if (cs42l73->pdata.chgfreq)
1240 snd_soc_component_update_bits(component, CS42L73_CPFCHC,
1241 CS42L73_CHARGEPUMP_MASK,
1242 cs42l73->pdata.chgfreq << 4);
1243
1244 /* MCLK1 as master clk */
1245 cs42l73->mclksel = CS42L73_CLKID_MCLK1;
1246 cs42l73->mclk = 0;
1247
1248 return 0;
1249 }
1250
1251 static const struct snd_soc_component_driver soc_component_dev_cs42l73 = {
1252 .probe = cs42l73_probe,
1253 .set_bias_level = cs42l73_set_bias_level,
1254 .controls = cs42l73_snd_controls,
1255 .num_controls = ARRAY_SIZE(cs42l73_snd_controls),
1256 .dapm_widgets = cs42l73_dapm_widgets,
1257 .num_dapm_widgets = ARRAY_SIZE(cs42l73_dapm_widgets),
1258 .dapm_routes = cs42l73_audio_map,
1259 .num_dapm_routes = ARRAY_SIZE(cs42l73_audio_map),
1260 .suspend_bias_off = 1,
1261 .idle_bias_on = 1,
1262 .use_pmdown_time = 1,
1263 .endianness = 1,
1264 .non_legacy_dai_naming = 1,
1265 };
1266
1267 static const struct regmap_config cs42l73_regmap = {
1268 .reg_bits = 8,
1269 .val_bits = 8,
1270
1271 .max_register = CS42L73_MAX_REGISTER,
1272 .reg_defaults = cs42l73_reg_defaults,
1273 .num_reg_defaults = ARRAY_SIZE(cs42l73_reg_defaults),
1274 .volatile_reg = cs42l73_volatile_register,
1275 .readable_reg = cs42l73_readable_register,
1276 .cache_type = REGCACHE_RBTREE,
1277 };
1278
1279 static int cs42l73_i2c_probe(struct i2c_client *i2c_client,
1280 const struct i2c_device_id *id)
1281 {
1282 struct cs42l73_private *cs42l73;
1283 struct cs42l73_platform_data *pdata = dev_get_platdata(&i2c_client->dev);
1284 int ret;
1285 unsigned int devid = 0;
1286 unsigned int reg;
1287 u32 val32;
1288
1289 cs42l73 = devm_kzalloc(&i2c_client->dev, sizeof(*cs42l73), GFP_KERNEL);
1290 if (!cs42l73)
1291 return -ENOMEM;
1292
1293 cs42l73->regmap = devm_regmap_init_i2c(i2c_client, &cs42l73_regmap);
1294 if (IS_ERR(cs42l73->regmap)) {
1295 ret = PTR_ERR(cs42l73->regmap);
1296 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
1297 return ret;
1298 }
1299
1300 if (pdata) {
1301 cs42l73->pdata = *pdata;
1302 } else {
1303 pdata = devm_kzalloc(&i2c_client->dev, sizeof(*pdata),
1304 GFP_KERNEL);
1305 if (!pdata)
1306 return -ENOMEM;
1307
1308 if (i2c_client->dev.of_node) {
1309 if (of_property_read_u32(i2c_client->dev.of_node,
1310 "chgfreq", &val32) >= 0)
1311 pdata->chgfreq = val32;
1312 }
1313 pdata->reset_gpio = of_get_named_gpio(i2c_client->dev.of_node,
1314 "reset-gpio", 0);
1315 cs42l73->pdata = *pdata;
1316 }
1317
1318 i2c_set_clientdata(i2c_client, cs42l73);
1319
1320 if (cs42l73->pdata.reset_gpio) {
1321 ret = devm_gpio_request_one(&i2c_client->dev,
1322 cs42l73->pdata.reset_gpio,
1323 GPIOF_OUT_INIT_HIGH,
1324 "CS42L73 /RST");
1325 if (ret < 0) {
1326 dev_err(&i2c_client->dev, "Failed to request /RST %d: %d\n",
1327 cs42l73->pdata.reset_gpio, ret);
1328 return ret;
1329 }
1330 gpio_set_value_cansleep(cs42l73->pdata.reset_gpio, 0);
1331 gpio_set_value_cansleep(cs42l73->pdata.reset_gpio, 1);
1332 }
1333
1334 /* initialize codec */
1335 ret = regmap_read(cs42l73->regmap, CS42L73_DEVID_AB, &reg);
1336 devid = (reg & 0xFF) << 12;
1337
1338 ret = regmap_read(cs42l73->regmap, CS42L73_DEVID_CD, &reg);
1339 devid |= (reg & 0xFF) << 4;
1340
1341 ret = regmap_read(cs42l73->regmap, CS42L73_DEVID_E, &reg);
1342 devid |= (reg & 0xF0) >> 4;
1343
1344 if (devid != CS42L73_DEVID) {
1345 ret = -ENODEV;
1346 dev_err(&i2c_client->dev,
1347 "CS42L73 Device ID (%X). Expected %X\n",
1348 devid, CS42L73_DEVID);
1349 return ret;
1350 }
1351
1352 ret = regmap_read(cs42l73->regmap, CS42L73_REVID, &reg);
1353 if (ret < 0) {
1354 dev_err(&i2c_client->dev, "Get Revision ID failed\n");
1355 return ret;
1356 }
1357
1358 dev_info(&i2c_client->dev,
1359 "Cirrus Logic CS42L73, Revision: %02X\n", reg & 0xFF);
1360
1361 ret = devm_snd_soc_register_component(&i2c_client->dev,
1362 &soc_component_dev_cs42l73, cs42l73_dai,
1363 ARRAY_SIZE(cs42l73_dai));
1364 if (ret < 0)
1365 return ret;
1366 return 0;
1367 }
1368
1369 static const struct of_device_id cs42l73_of_match[] = {
1370 { .compatible = "cirrus,cs42l73", },
1371 {},
1372 };
1373 MODULE_DEVICE_TABLE(of, cs42l73_of_match);
1374
1375 static const struct i2c_device_id cs42l73_id[] = {
1376 {"cs42l73", 0},
1377 {}
1378 };
1379
1380 MODULE_DEVICE_TABLE(i2c, cs42l73_id);
1381
1382 static struct i2c_driver cs42l73_i2c_driver = {
1383 .driver = {
1384 .name = "cs42l73",
1385 .of_match_table = cs42l73_of_match,
1386 },
1387 .id_table = cs42l73_id,
1388 .probe = cs42l73_i2c_probe,
1389
1390 };
1391
1392 module_i2c_driver(cs42l73_i2c_driver);
1393
1394 MODULE_DESCRIPTION("ASoC CS42L73 driver");
1395 MODULE_AUTHOR("Georgi Vlaev, Nucleus Systems Ltd, <joe@nucleusys.com>");
1396 MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>");
1397 MODULE_LICENSE("GPL");
Linux with added FPC-III support