sound/soc/codecs/es8328.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * es8328.c  --  ES8328 ALSA SoC Audio driver
   4  *
   5  * Copyright 2014 Sutajio Ko-Usagi PTE LTD
   6  *
   7  * Author: Sean Cross <xobs@kosagi.com>
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/delay.h>
  12 #include <linux/of_device.h>
  13 #include <linux/module.h>
  14 #include <linux/pm.h>
  15 #include <linux/regmap.h>
  16 #include <linux/slab.h>
  17 #include <linux/regulator/consumer.h>
  18 #include <sound/core.h>
  19 #include <sound/initval.h>
  20 #include <sound/pcm.h>
  21 #include <sound/pcm_params.h>
  22 #include <sound/soc.h>
  23 #include <sound/tlv.h>
  24 #include "es8328.h"
  25
  26 static const unsigned int rates_12288[] = {
  27         8000, 12000, 16000, 24000, 32000, 48000, 96000,
  28 };
  29
  30 static const int ratios_12288[] = {
  31         10, 7, 6, 4, 3, 2, 0,
  32 };
  33
  34 static const struct snd_pcm_hw_constraint_list constraints_12288 = {
  35         .count  = ARRAY_SIZE(rates_12288),
  36         .list   = rates_12288,
  37 };
  38
  39 static const unsigned int rates_11289[] = {
  40         8018, 11025, 22050, 44100, 88200,
  41 };
  42
  43 static const int ratios_11289[] = {
  44         9, 7, 4, 2, 0,
  45 };
  46
  47 static const struct snd_pcm_hw_constraint_list constraints_11289 = {
  48         .count  = ARRAY_SIZE(rates_11289),
  49         .list   = rates_11289,
  50 };
  51
  52 /* regulator supplies for sgtl5000, VDDD is an optional external supply */
  53 enum sgtl5000_regulator_supplies {
  54         DVDD,
  55         AVDD,
  56         PVDD,
  57         HPVDD,
  58         ES8328_SUPPLY_NUM
  59 };
  60
  61 /* vddd is optional supply */
  62 static const char * const supply_names[ES8328_SUPPLY_NUM] = {
  63         "DVDD",
  64         "AVDD",
  65         "PVDD",
  66         "HPVDD",
  67 };
  68
  69 #define ES8328_RATES (SNDRV_PCM_RATE_192000 | \
  70                 SNDRV_PCM_RATE_96000 | \
  71                 SNDRV_PCM_RATE_88200 | \
  72                 SNDRV_PCM_RATE_8000_48000)
  73 #define ES8328_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
  74                 SNDRV_PCM_FMTBIT_S18_3LE | \
  75                 SNDRV_PCM_FMTBIT_S20_3LE | \
  76                 SNDRV_PCM_FMTBIT_S24_LE | \
  77                 SNDRV_PCM_FMTBIT_S32_LE)
  78
  79 struct es8328_priv {
  80         struct regmap *regmap;
  81         struct clk *clk;
  82         int playback_fs;
  83         bool deemph;
  84         int mclkdiv2;
  85         const struct snd_pcm_hw_constraint_list *sysclk_constraints;
  86         const int *mclk_ratios;
  87         bool master;
  88         struct regulator_bulk_data supplies[ES8328_SUPPLY_NUM];
  89 };
  90
  91 /*
  92  * ES8328 Controls
  93  */
  94
  95 static const char * const adcpol_txt[] = {"Normal", "L Invert", "R Invert",
  96                                           "L + R Invert"};
  97 static SOC_ENUM_SINGLE_DECL(adcpol,
  98                             ES8328_ADCCONTROL6, 6, adcpol_txt);
  99
 100 static const DECLARE_TLV_DB_SCALE(play_tlv, -3000, 100, 0);
 101 static const DECLARE_TLV_DB_SCALE(dac_adc_tlv, -9600, 50, 0);
 102 static const DECLARE_TLV_DB_SCALE(pga_tlv, 0, 300, 0);
 103 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
 104 static const DECLARE_TLV_DB_SCALE(mic_tlv, 0, 300, 0);
 105
 106 static const struct {
 107         int rate;
 108         unsigned int val;
 109 } deemph_settings[] = {
 110         { 0,     ES8328_DACCONTROL6_DEEMPH_OFF },
 111         { 32000, ES8328_DACCONTROL6_DEEMPH_32k },
 112         { 44100, ES8328_DACCONTROL6_DEEMPH_44_1k },
 113         { 48000, ES8328_DACCONTROL6_DEEMPH_48k },
 114 };
 115
 116 static int es8328_set_deemph(struct snd_soc_component *component)
 117 {
 118         struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component);
 119         int val, i, best;
 120
 121         /*
 122          * If we're using deemphasis select the nearest available sample
 123          * rate.
 124          */
 125         if (es8328->deemph) {
 126                 best = 0;
 127                 for (i = 1; i < ARRAY_SIZE(deemph_settings); i++) {
 128                         if (abs(deemph_settings[i].rate - es8328->playback_fs) <
 129                             abs(deemph_settings[best].rate - es8328->playback_fs))
 130                                 best = i;
 131                 }
 132
 133                 val = deemph_settings[best].val;
 134         } else {
 135                 val = ES8328_DACCONTROL6_DEEMPH_OFF;
 136         }
 137
 138         dev_dbg(component->dev, "Set deemphasis %d\n", val);
 139
 140         return snd_soc_component_update_bits(component, ES8328_DACCONTROL6,
 141                         ES8328_DACCONTROL6_DEEMPH_MASK, val);
 142 }
 143
 144 static int es8328_get_deemph(struct snd_kcontrol *kcontrol,
 145                              struct snd_ctl_elem_value *ucontrol)
 146 {
 147         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
 148         struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component);
 149
 150         ucontrol->value.integer.value[0] = es8328->deemph;
 151         return 0;
 152 }
 153
 154 static int es8328_put_deemph(struct snd_kcontrol *kcontrol,
 155                              struct snd_ctl_elem_value *ucontrol)
 156 {
 157         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
 158         struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component);
 159         unsigned int deemph = ucontrol->value.integer.value[0];
 160         int ret;
 161
 162         if (deemph > 1)
 163                 return -EINVAL;
 164
 165         ret = es8328_set_deemph(component);
 166         if (ret < 0)
 167                 return ret;
 168
 169         es8328->deemph = deemph;
 170
 171         return 0;
 172 }
 173
 174
 175
 176 static const struct snd_kcontrol_new es8328_snd_controls[] = {
 177         SOC_DOUBLE_R_TLV("Capture Digital Volume",
 178                 ES8328_ADCCONTROL8, ES8328_ADCCONTROL9,
 179                  0, 0xc0, 1, dac_adc_tlv),
 180         SOC_SINGLE("Capture ZC Switch", ES8328_ADCCONTROL7, 6, 1, 0),
 181
 182         SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0,
 183                     es8328_get_deemph, es8328_put_deemph),
 184
 185         SOC_ENUM("Capture Polarity", adcpol),
 186
 187         SOC_SINGLE_TLV("Left Mixer Left Bypass Volume",
 188                         ES8328_DACCONTROL17, 3, 7, 1, bypass_tlv),
 189         SOC_SINGLE_TLV("Left Mixer Right Bypass Volume",
 190                         ES8328_DACCONTROL19, 3, 7, 1, bypass_tlv),
 191         SOC_SINGLE_TLV("Right Mixer Left Bypass Volume",
 192                         ES8328_DACCONTROL18, 3, 7, 1, bypass_tlv),
 193         SOC_SINGLE_TLV("Right Mixer Right Bypass Volume",
 194                         ES8328_DACCONTROL20, 3, 7, 1, bypass_tlv),
 195
 196         SOC_DOUBLE_R_TLV("PCM Volume",
 197                         ES8328_LDACVOL, ES8328_RDACVOL,
 198                         0, ES8328_DACVOL_MAX, 1, dac_adc_tlv),
 199
 200         SOC_DOUBLE_R_TLV("Output 1 Playback Volume",
 201                         ES8328_LOUT1VOL, ES8328_ROUT1VOL,
 202                         0, ES8328_OUT1VOL_MAX, 0, play_tlv),
 203
 204         SOC_DOUBLE_R_TLV("Output 2 Playback Volume",
 205                         ES8328_LOUT2VOL, ES8328_ROUT2VOL,
 206                         0, ES8328_OUT2VOL_MAX, 0, play_tlv),
 207
 208         SOC_DOUBLE_TLV("Mic PGA Volume", ES8328_ADCCONTROL1,
 209                         4, 0, 8, 0, mic_tlv),
 210 };
 211
 212 /*
 213  * DAPM Controls
 214  */
 215
 216 static const char * const es8328_line_texts[] = {
 217         "Line 1", "Line 2", "PGA", "Differential"};
 218
 219 static const struct soc_enum es8328_lline_enum =
 220         SOC_ENUM_SINGLE(ES8328_DACCONTROL16, 3,
 221                               ARRAY_SIZE(es8328_line_texts),
 222                               es8328_line_texts);
 223 static const struct snd_kcontrol_new es8328_left_line_controls =
 224         SOC_DAPM_ENUM("Route", es8328_lline_enum);
 225
 226 static const struct soc_enum es8328_rline_enum =
 227         SOC_ENUM_SINGLE(ES8328_DACCONTROL16, 0,
 228                               ARRAY_SIZE(es8328_line_texts),
 229                               es8328_line_texts);
 230 static const struct snd_kcontrol_new es8328_right_line_controls =
 231         SOC_DAPM_ENUM("Route", es8328_lline_enum);
 232
 233 /* Left Mixer */
 234 static const struct snd_kcontrol_new es8328_left_mixer_controls[] = {
 235         SOC_DAPM_SINGLE("Playback Switch", ES8328_DACCONTROL17, 7, 1, 0),
 236         SOC_DAPM_SINGLE("Left Bypass Switch", ES8328_DACCONTROL17, 6, 1, 0),
 237         SOC_DAPM_SINGLE("Right Playback Switch", ES8328_DACCONTROL18, 7, 1, 0),
 238         SOC_DAPM_SINGLE("Right Bypass Switch", ES8328_DACCONTROL18, 6, 1, 0),
 239 };
 240
 241 /* Right Mixer */
 242 static const struct snd_kcontrol_new es8328_right_mixer_controls[] = {
 243         SOC_DAPM_SINGLE("Left Playback Switch", ES8328_DACCONTROL19, 7, 1, 0),
 244         SOC_DAPM_SINGLE("Left Bypass Switch", ES8328_DACCONTROL19, 6, 1, 0),
 245         SOC_DAPM_SINGLE("Playback Switch", ES8328_DACCONTROL20, 7, 1, 0),
 246         SOC_DAPM_SINGLE("Right Bypass Switch", ES8328_DACCONTROL20, 6, 1, 0),
 247 };
 248
 249 static const char * const es8328_pga_sel[] = {
 250         "Line 1", "Line 2", "Line 3", "Differential"};
 251
 252 /* Left PGA Mux */
 253 static const struct soc_enum es8328_lpga_enum =
 254         SOC_ENUM_SINGLE(ES8328_ADCCONTROL2, 6,
 255                               ARRAY_SIZE(es8328_pga_sel),
 256                               es8328_pga_sel);
 257 static const struct snd_kcontrol_new es8328_left_pga_controls =
 258         SOC_DAPM_ENUM("Route", es8328_lpga_enum);
 259
 260 /* Right PGA Mux */
 261 static const struct soc_enum es8328_rpga_enum =
 262         SOC_ENUM_SINGLE(ES8328_ADCCONTROL2, 4,
 263                               ARRAY_SIZE(es8328_pga_sel),
 264                               es8328_pga_sel);
 265 static const struct snd_kcontrol_new es8328_right_pga_controls =
 266         SOC_DAPM_ENUM("Route", es8328_rpga_enum);
 267
 268 /* Differential Mux */
 269 static const char * const es8328_diff_sel[] = {"Line 1", "Line 2"};
 270 static SOC_ENUM_SINGLE_DECL(diffmux,
 271                             ES8328_ADCCONTROL3, 7, es8328_diff_sel);
 272 static const struct snd_kcontrol_new es8328_diffmux_controls =
 273         SOC_DAPM_ENUM("Route", diffmux);
 274
 275 /* Mono ADC Mux */
 276 static const char * const es8328_mono_mux[] = {"Stereo", "Mono (Left)",
 277         "Mono (Right)", "Digital Mono"};
 278 static SOC_ENUM_SINGLE_DECL(monomux,
 279                             ES8328_ADCCONTROL3, 3, es8328_mono_mux);
 280 static const struct snd_kcontrol_new es8328_monomux_controls =
 281         SOC_DAPM_ENUM("Route", monomux);
 282
 283 static const struct snd_soc_dapm_widget es8328_dapm_widgets[] = {
 284         SND_SOC_DAPM_MUX("Differential Mux", SND_SOC_NOPM, 0, 0,
 285                 &es8328_diffmux_controls),
 286         SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0,
 287                 &es8328_monomux_controls),
 288         SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0,
 289                 &es8328_monomux_controls),
 290
 291         SND_SOC_DAPM_MUX("Left PGA Mux", ES8328_ADCPOWER,
 292                         ES8328_ADCPOWER_AINL_OFF, 1,
 293                         &es8328_left_pga_controls),
 294         SND_SOC_DAPM_MUX("Right PGA Mux", ES8328_ADCPOWER,
 295                         ES8328_ADCPOWER_AINR_OFF, 1,
 296                         &es8328_right_pga_controls),
 297
 298         SND_SOC_DAPM_MUX("Left Line Mux", SND_SOC_NOPM, 0, 0,
 299                 &es8328_left_line_controls),
 300         SND_SOC_DAPM_MUX("Right Line Mux", SND_SOC_NOPM, 0, 0,
 301                 &es8328_right_line_controls),
 302
 303         SND_SOC_DAPM_ADC("Right ADC", "Right Capture", ES8328_ADCPOWER,
 304                         ES8328_ADCPOWER_ADCR_OFF, 1),
 305         SND_SOC_DAPM_ADC("Left ADC", "Left Capture", ES8328_ADCPOWER,
 306                         ES8328_ADCPOWER_ADCL_OFF, 1),
 307
 308         SND_SOC_DAPM_SUPPLY("Mic Bias", ES8328_ADCPOWER,
 309                         ES8328_ADCPOWER_MIC_BIAS_OFF, 1, NULL, 0),
 310         SND_SOC_DAPM_SUPPLY("Mic Bias Gen", ES8328_ADCPOWER,
 311                         ES8328_ADCPOWER_ADC_BIAS_GEN_OFF, 1, NULL, 0),
 312
 313         SND_SOC_DAPM_SUPPLY("DAC STM", ES8328_CHIPPOWER,
 314                         ES8328_CHIPPOWER_DACSTM_RESET, 1, NULL, 0),
 315         SND_SOC_DAPM_SUPPLY("ADC STM", ES8328_CHIPPOWER,
 316                         ES8328_CHIPPOWER_ADCSTM_RESET, 1, NULL, 0),
 317
 318         SND_SOC_DAPM_SUPPLY("DAC DIG", ES8328_CHIPPOWER,
 319                         ES8328_CHIPPOWER_DACDIG_OFF, 1, NULL, 0),
 320         SND_SOC_DAPM_SUPPLY("ADC DIG", ES8328_CHIPPOWER,
 321                         ES8328_CHIPPOWER_ADCDIG_OFF, 1, NULL, 0),
 322
 323         SND_SOC_DAPM_SUPPLY("DAC DLL", ES8328_CHIPPOWER,
 324                         ES8328_CHIPPOWER_DACDLL_OFF, 1, NULL, 0),
 325         SND_SOC_DAPM_SUPPLY("ADC DLL", ES8328_CHIPPOWER,
 326                         ES8328_CHIPPOWER_ADCDLL_OFF, 1, NULL, 0),
 327
 328         SND_SOC_DAPM_SUPPLY("ADC Vref", ES8328_CHIPPOWER,
 329                         ES8328_CHIPPOWER_ADCVREF_OFF, 1, NULL, 0),
 330         SND_SOC_DAPM_SUPPLY("DAC Vref", ES8328_CHIPPOWER,
 331                         ES8328_CHIPPOWER_DACVREF_OFF, 1, NULL, 0),
 332
 333         SND_SOC_DAPM_DAC("Right DAC", "Right Playback", ES8328_DACPOWER,
 334                         ES8328_DACPOWER_RDAC_OFF, 1),
 335         SND_SOC_DAPM_DAC("Left DAC", "Left Playback", ES8328_DACPOWER,
 336                         ES8328_DACPOWER_LDAC_OFF, 1),
 337
 338         SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0,
 339                 &es8328_left_mixer_controls[0],
 340                 ARRAY_SIZE(es8328_left_mixer_controls)),
 341         SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0,
 342                 &es8328_right_mixer_controls[0],
 343                 ARRAY_SIZE(es8328_right_mixer_controls)),
 344
 345         SND_SOC_DAPM_PGA("Right Out 2", ES8328_DACPOWER,
 346                         ES8328_DACPOWER_ROUT2_ON, 0, NULL, 0),
 347         SND_SOC_DAPM_PGA("Left Out 2", ES8328_DACPOWER,
 348                         ES8328_DACPOWER_LOUT2_ON, 0, NULL, 0),
 349         SND_SOC_DAPM_PGA("Right Out 1", ES8328_DACPOWER,
 350                         ES8328_DACPOWER_ROUT1_ON, 0, NULL, 0),
 351         SND_SOC_DAPM_PGA("Left Out 1", ES8328_DACPOWER,
 352                         ES8328_DACPOWER_LOUT1_ON, 0, NULL, 0),
 353
 354         SND_SOC_DAPM_OUTPUT("LOUT1"),
 355         SND_SOC_DAPM_OUTPUT("ROUT1"),
 356         SND_SOC_DAPM_OUTPUT("LOUT2"),
 357         SND_SOC_DAPM_OUTPUT("ROUT2"),
 358
 359         SND_SOC_DAPM_INPUT("LINPUT1"),
 360         SND_SOC_DAPM_INPUT("LINPUT2"),
 361         SND_SOC_DAPM_INPUT("RINPUT1"),
 362         SND_SOC_DAPM_INPUT("RINPUT2"),
 363 };
 364
 365 static const struct snd_soc_dapm_route es8328_dapm_routes[] = {
 366
 367         { "Left Line Mux", "Line 1", "LINPUT1" },
 368         { "Left Line Mux", "Line 2", "LINPUT2" },
 369         { "Left Line Mux", "PGA", "Left PGA Mux" },
 370         { "Left Line Mux", "Differential", "Differential Mux" },
 371
 372         { "Right Line Mux", "Line 1", "RINPUT1" },
 373         { "Right Line Mux", "Line 2", "RINPUT2" },
 374         { "Right Line Mux", "PGA", "Right PGA Mux" },
 375         { "Right Line Mux", "Differential", "Differential Mux" },
 376
 377         { "Left PGA Mux", "Line 1", "LINPUT1" },
 378         { "Left PGA Mux", "Line 2", "LINPUT2" },
 379         { "Left PGA Mux", "Differential", "Differential Mux" },
 380
 381         { "Right PGA Mux", "Line 1", "RINPUT1" },
 382         { "Right PGA Mux", "Line 2", "RINPUT2" },
 383         { "Right PGA Mux", "Differential", "Differential Mux" },
 384
 385         { "Differential Mux", "Line 1", "LINPUT1" },
 386         { "Differential Mux", "Line 1", "RINPUT1" },
 387         { "Differential Mux", "Line 2", "LINPUT2" },
 388         { "Differential Mux", "Line 2", "RINPUT2" },
 389
 390         { "Left ADC Mux", "Stereo", "Left PGA Mux" },
 391         { "Left ADC Mux", "Mono (Left)", "Left PGA Mux" },
 392         { "Left ADC Mux", "Digital Mono", "Left PGA Mux" },
 393
 394         { "Right ADC Mux", "Stereo", "Right PGA Mux" },
 395         { "Right ADC Mux", "Mono (Right)", "Right PGA Mux" },
 396         { "Right ADC Mux", "Digital Mono", "Right PGA Mux" },
 397
 398         { "Left ADC", NULL, "Left ADC Mux" },
 399         { "Right ADC", NULL, "Right ADC Mux" },
 400
 401         { "ADC DIG", NULL, "ADC STM" },
 402         { "ADC DIG", NULL, "ADC Vref" },
 403         { "ADC DIG", NULL, "ADC DLL" },
 404
 405         { "Left ADC", NULL, "ADC DIG" },
 406         { "Right ADC", NULL, "ADC DIG" },
 407
 408         { "Mic Bias", NULL, "Mic Bias Gen" },
 409
 410         { "Left Line Mux", "Line 1", "LINPUT1" },
 411         { "Left Line Mux", "Line 2", "LINPUT2" },
 412         { "Left Line Mux", "PGA", "Left PGA Mux" },
 413         { "Left Line Mux", "Differential", "Differential Mux" },
 414
 415         { "Right Line Mux", "Line 1", "RINPUT1" },
 416         { "Right Line Mux", "Line 2", "RINPUT2" },
 417         { "Right Line Mux", "PGA", "Right PGA Mux" },
 418         { "Right Line Mux", "Differential", "Differential Mux" },
 419
 420         { "Left Out 1", NULL, "Left DAC" },
 421         { "Right Out 1", NULL, "Right DAC" },
 422         { "Left Out 2", NULL, "Left DAC" },
 423         { "Right Out 2", NULL, "Right DAC" },
 424
 425         { "Left Mixer", "Playback Switch", "Left DAC" },
 426         { "Left Mixer", "Left Bypass Switch", "Left Line Mux" },
 427         { "Left Mixer", "Right Playback Switch", "Right DAC" },
 428         { "Left Mixer", "Right Bypass Switch", "Right Line Mux" },
 429
 430         { "Right Mixer", "Left Playback Switch", "Left DAC" },
 431         { "Right Mixer", "Left Bypass Switch", "Left Line Mux" },
 432         { "Right Mixer", "Playback Switch", "Right DAC" },
 433         { "Right Mixer", "Right Bypass Switch", "Right Line Mux" },
 434
 435         { "DAC DIG", NULL, "DAC STM" },
 436         { "DAC DIG", NULL, "DAC Vref" },
 437         { "DAC DIG", NULL, "DAC DLL" },
 438
 439         { "Left DAC", NULL, "DAC DIG" },
 440         { "Right DAC", NULL, "DAC DIG" },
 441
 442         { "Left Out 1", NULL, "Left Mixer" },
 443         { "LOUT1", NULL, "Left Out 1" },
 444         { "Right Out 1", NULL, "Right Mixer" },
 445         { "ROUT1", NULL, "Right Out 1" },
 446
 447         { "Left Out 2", NULL, "Left Mixer" },
 448         { "LOUT2", NULL, "Left Out 2" },
 449         { "Right Out 2", NULL, "Right Mixer" },
 450         { "ROUT2", NULL, "Right Out 2" },
 451 };
 452
 453 static int es8328_mute(struct snd_soc_dai *dai, int mute)
 454 {
 455         return snd_soc_component_update_bits(dai->component, ES8328_DACCONTROL3,
 456                         ES8328_DACCONTROL3_DACMUTE,
 457                         mute ? ES8328_DACCONTROL3_DACMUTE : 0);
 458 }
 459
 460 static int es8328_startup(struct snd_pcm_substream *substream,
 461                           struct snd_soc_dai *dai)
 462 {
 463         struct snd_soc_component *component = dai->component;
 464         struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component);
 465
 466         if (es8328->master && es8328->sysclk_constraints)
 467                 snd_pcm_hw_constraint_list(substream->runtime, 0,
 468                                 SNDRV_PCM_HW_PARAM_RATE,
 469                                 es8328->sysclk_constraints);
 470
 471         return 0;
 472 }
 473
 474 static int es8328_hw_params(struct snd_pcm_substream *substream,
 475         struct snd_pcm_hw_params *params,
 476         struct snd_soc_dai *dai)
 477 {
 478         struct snd_soc_component *component = dai->component;
 479         struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component);
 480         int i;
 481         int reg;
 482         int wl;
 483         int ratio;
 484
 485         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 486                 reg = ES8328_DACCONTROL2;
 487         else
 488                 reg = ES8328_ADCCONTROL5;
 489
 490         if (es8328->master) {
 491                 if (!es8328->sysclk_constraints) {
 492                         dev_err(component->dev, "No MCLK configured\n");
 493                         return -EINVAL;
 494                 }
 495
 496                 for (i = 0; i < es8328->sysclk_constraints->count; i++)
 497                         if (es8328->sysclk_constraints->list[i] ==
 498                             params_rate(params))
 499                                 break;
 500
 501                 if (i == es8328->sysclk_constraints->count) {
 502                         dev_err(component->dev,
 503                                 "LRCLK %d unsupported with current clock\n",
 504                                 params_rate(params));
 505                         return -EINVAL;
 506                 }
 507                 ratio = es8328->mclk_ratios[i];
 508         } else {
 509                 ratio = 0;
 510                 es8328->mclkdiv2 = 0;
 511         }
 512
 513         snd_soc_component_update_bits(component, ES8328_MASTERMODE,
 514                         ES8328_MASTERMODE_MCLKDIV2,
 515                         es8328->mclkdiv2 ? ES8328_MASTERMODE_MCLKDIV2 : 0);
 516
 517         switch (params_width(params)) {
 518         case 16:
 519                 wl = 3;
 520                 break;
 521         case 18:
 522                 wl = 2;
 523                 break;
 524         case 20:
 525                 wl = 1;
 526                 break;
 527         case 24:
 528                 wl = 0;
 529                 break;
 530         case 32:
 531                 wl = 4;
 532                 break;
 533         default:
 534                 return -EINVAL;
 535         }
 536
 537         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 538                 snd_soc_component_update_bits(component, ES8328_DACCONTROL1,
 539                                 ES8328_DACCONTROL1_DACWL_MASK,
 540                                 wl << ES8328_DACCONTROL1_DACWL_SHIFT);
 541
 542                 es8328->playback_fs = params_rate(params);
 543                 es8328_set_deemph(component);
 544         } else
 545                 snd_soc_component_update_bits(component, ES8328_ADCCONTROL4,
 546                                 ES8328_ADCCONTROL4_ADCWL_MASK,
 547                                 wl << ES8328_ADCCONTROL4_ADCWL_SHIFT);
 548
 549         return snd_soc_component_update_bits(component, reg, ES8328_RATEMASK, ratio);
 550 }
 551
 552 static int es8328_set_sysclk(struct snd_soc_dai *codec_dai,
 553                 int clk_id, unsigned int freq, int dir)
 554 {
 555         struct snd_soc_component *component = codec_dai->component;
 556         struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component);
 557         int mclkdiv2 = 0;
 558
 559         switch (freq) {
 560         case 0:
 561                 es8328->sysclk_constraints = NULL;
 562                 es8328->mclk_ratios = NULL;
 563                 break;
 564         case 22579200:
 565                 mclkdiv2 = 1;
 566                 /* fall through */
 567         case 11289600:
 568                 es8328->sysclk_constraints = &constraints_11289;
 569                 es8328->mclk_ratios = ratios_11289;
 570                 break;
 571         case 24576000:
 572                 mclkdiv2 = 1;
 573                 /* fall through */
 574         case 12288000:
 575                 es8328->sysclk_constraints = &constraints_12288;
 576                 es8328->mclk_ratios = ratios_12288;
 577                 break;
 578         default:
 579                 return -EINVAL;
 580         }
 581
 582         es8328->mclkdiv2 = mclkdiv2;
 583         return 0;
 584 }
 585
 586 static int es8328_set_dai_fmt(struct snd_soc_dai *codec_dai,
 587                 unsigned int fmt)
 588 {
 589         struct snd_soc_component *component = codec_dai->component;
 590         struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component);
 591         u8 dac_mode = 0;
 592         u8 adc_mode = 0;
 593
 594         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 595         case SND_SOC_DAIFMT_CBM_CFM:
 596                 /* Master serial port mode, with BCLK generated automatically */
 597                 snd_soc_component_update_bits(component, ES8328_MASTERMODE,
 598                                     ES8328_MASTERMODE_MSC,
 599                                     ES8328_MASTERMODE_MSC);
 600                 es8328->master = true;
 601                 break;
 602         case SND_SOC_DAIFMT_CBS_CFS:
 603                 /* Slave serial port mode */
 604                 snd_soc_component_update_bits(component, ES8328_MASTERMODE,
 605                                     ES8328_MASTERMODE_MSC, 0);
 606                 es8328->master = false;
 607                 break;
 608         default:
 609                 return -EINVAL;
 610         }
 611
 612         /* interface format */
 613         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 614         case SND_SOC_DAIFMT_I2S:
 615                 dac_mode |= ES8328_DACCONTROL1_DACFORMAT_I2S;
 616                 adc_mode |= ES8328_ADCCONTROL4_ADCFORMAT_I2S;
 617                 break;
 618         case SND_SOC_DAIFMT_RIGHT_J:
 619                 dac_mode |= ES8328_DACCONTROL1_DACFORMAT_RJUST;
 620                 adc_mode |= ES8328_ADCCONTROL4_ADCFORMAT_RJUST;
 621                 break;
 622         case SND_SOC_DAIFMT_LEFT_J:
 623                 dac_mode |= ES8328_DACCONTROL1_DACFORMAT_LJUST;
 624                 adc_mode |= ES8328_ADCCONTROL4_ADCFORMAT_LJUST;
 625                 break;
 626         default:
 627                 return -EINVAL;
 628         }
 629
 630         /* clock inversion */
 631         if ((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_NB_NF)
 632                 return -EINVAL;
 633
 634         snd_soc_component_update_bits(component, ES8328_DACCONTROL1,
 635                         ES8328_DACCONTROL1_DACFORMAT_MASK, dac_mode);
 636         snd_soc_component_update_bits(component, ES8328_ADCCONTROL4,
 637                         ES8328_ADCCONTROL4_ADCFORMAT_MASK, adc_mode);
 638
 639         return 0;
 640 }
 641
 642 static int es8328_set_bias_level(struct snd_soc_component *component,
 643                                  enum snd_soc_bias_level level)
 644 {
 645         switch (level) {
 646         case SND_SOC_BIAS_ON:
 647                 break;
 648
 649         case SND_SOC_BIAS_PREPARE:
 650                 /* VREF, VMID=2x50k, digital enabled */
 651                 snd_soc_component_write(component, ES8328_CHIPPOWER, 0);
 652                 snd_soc_component_update_bits(component, ES8328_CONTROL1,
 653                                 ES8328_CONTROL1_VMIDSEL_MASK |
 654                                 ES8328_CONTROL1_ENREF,
 655                                 ES8328_CONTROL1_VMIDSEL_50k |
 656                                 ES8328_CONTROL1_ENREF);
 657                 break;
 658
 659         case SND_SOC_BIAS_STANDBY:
 660                 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
 661                         snd_soc_component_update_bits(component, ES8328_CONTROL1,
 662                                         ES8328_CONTROL1_VMIDSEL_MASK |
 663                                         ES8328_CONTROL1_ENREF,
 664                                         ES8328_CONTROL1_VMIDSEL_5k |
 665                                         ES8328_CONTROL1_ENREF);
 666
 667                         /* Charge caps */
 668                         msleep(100);
 669                 }
 670
 671                 snd_soc_component_write(component, ES8328_CONTROL2,
 672                                 ES8328_CONTROL2_OVERCURRENT_ON |
 673                                 ES8328_CONTROL2_THERMAL_SHUTDOWN_ON);
 674
 675                 /* VREF, VMID=2*500k, digital stopped */
 676                 snd_soc_component_update_bits(component, ES8328_CONTROL1,
 677                                 ES8328_CONTROL1_VMIDSEL_MASK |
 678                                 ES8328_CONTROL1_ENREF,
 679                                 ES8328_CONTROL1_VMIDSEL_500k |
 680                                 ES8328_CONTROL1_ENREF);
 681                 break;
 682
 683         case SND_SOC_BIAS_OFF:
 684                 snd_soc_component_update_bits(component, ES8328_CONTROL1,
 685                                 ES8328_CONTROL1_VMIDSEL_MASK |
 686                                 ES8328_CONTROL1_ENREF,
 687                                 0);
 688                 break;
 689         }
 690         return 0;
 691 }
 692
 693 static const struct snd_soc_dai_ops es8328_dai_ops = {
 694         .startup        = es8328_startup,
 695         .hw_params      = es8328_hw_params,
 696         .digital_mute   = es8328_mute,
 697         .set_sysclk     = es8328_set_sysclk,
 698         .set_fmt        = es8328_set_dai_fmt,
 699 };
 700
 701 static struct snd_soc_dai_driver es8328_dai = {
 702         .name = "es8328-hifi-analog",
 703         .playback = {
 704                 .stream_name = "Playback",
 705                 .channels_min = 2,
 706                 .channels_max = 2,
 707                 .rates = ES8328_RATES,
 708                 .formats = ES8328_FORMATS,
 709         },
 710         .capture = {
 711                 .stream_name = "Capture",
 712                 .channels_min = 2,
 713                 .channels_max = 2,
 714                 .rates = ES8328_RATES,
 715                 .formats = ES8328_FORMATS,
 716         },
 717         .ops = &es8328_dai_ops,
 718         .symmetric_rates = 1,
 719 };
 720
 721 static int es8328_suspend(struct snd_soc_component *component)
 722 {
 723         struct es8328_priv *es8328;
 724         int ret;
 725
 726         es8328 = snd_soc_component_get_drvdata(component);
 727
 728         clk_disable_unprepare(es8328->clk);
 729
 730         ret = regulator_bulk_disable(ARRAY_SIZE(es8328->supplies),
 731                         es8328->supplies);
 732         if (ret) {
 733                 dev_err(component->dev, "unable to disable regulators\n");
 734                 return ret;
 735         }
 736         return 0;
 737 }
 738
 739 static int es8328_resume(struct snd_soc_component *component)
 740 {
 741         struct regmap *regmap = dev_get_regmap(component->dev, NULL);
 742         struct es8328_priv *es8328;
 743         int ret;
 744
 745         es8328 = snd_soc_component_get_drvdata(component);
 746
 747         ret = clk_prepare_enable(es8328->clk);
 748         if (ret) {
 749                 dev_err(component->dev, "unable to enable clock\n");
 750                 return ret;
 751         }
 752
 753         ret = regulator_bulk_enable(ARRAY_SIZE(es8328->supplies),
 754                                         es8328->supplies);
 755         if (ret) {
 756                 dev_err(component->dev, "unable to enable regulators\n");
 757                 return ret;
 758         }
 759
 760         regcache_mark_dirty(regmap);
 761         ret = regcache_sync(regmap);
 762         if (ret) {
 763                 dev_err(component->dev, "unable to sync regcache\n");
 764                 return ret;
 765         }
 766
 767         return 0;
 768 }
 769
 770 static int es8328_component_probe(struct snd_soc_component *component)
 771 {
 772         struct es8328_priv *es8328;
 773         int ret;
 774
 775         es8328 = snd_soc_component_get_drvdata(component);
 776
 777         ret = regulator_bulk_enable(ARRAY_SIZE(es8328->supplies),
 778                                         es8328->supplies);
 779         if (ret) {
 780                 dev_err(component->dev, "unable to enable regulators\n");
 781                 return ret;
 782         }
 783
 784         /* Setup clocks */
 785         es8328->clk = devm_clk_get(component->dev, NULL);
 786         if (IS_ERR(es8328->clk)) {
 787                 dev_err(component->dev, "codec clock missing or invalid\n");
 788                 ret = PTR_ERR(es8328->clk);
 789                 goto clk_fail;
 790         }
 791
 792         ret = clk_prepare_enable(es8328->clk);
 793         if (ret) {
 794                 dev_err(component->dev, "unable to prepare codec clk\n");
 795                 goto clk_fail;
 796         }
 797
 798         return 0;
 799
 800 clk_fail:
 801         regulator_bulk_disable(ARRAY_SIZE(es8328->supplies),
 802                                es8328->supplies);
 803         return ret;
 804 }
 805
 806 static void es8328_remove(struct snd_soc_component *component)
 807 {
 808         struct es8328_priv *es8328;
 809
 810         es8328 = snd_soc_component_get_drvdata(component);
 811
 812         if (es8328->clk)
 813                 clk_disable_unprepare(es8328->clk);
 814
 815         regulator_bulk_disable(ARRAY_SIZE(es8328->supplies),
 816                                es8328->supplies);
 817 }
 818
 819 const struct regmap_config es8328_regmap_config = {
 820         .reg_bits       = 8,
 821         .val_bits       = 8,
 822         .max_register   = ES8328_REG_MAX,
 823         .cache_type     = REGCACHE_RBTREE,
 824         .use_single_read = true,
 825         .use_single_write = true,
 826 };
 827 EXPORT_SYMBOL_GPL(es8328_regmap_config);
 828
 829 static const struct snd_soc_component_driver es8328_component_driver = {
 830         .probe                  = es8328_component_probe,
 831         .remove                 = es8328_remove,
 832         .suspend                = es8328_suspend,
 833         .resume                 = es8328_resume,
 834         .set_bias_level         = es8328_set_bias_level,
 835         .controls               = es8328_snd_controls,
 836         .num_controls           = ARRAY_SIZE(es8328_snd_controls),
 837         .dapm_widgets           = es8328_dapm_widgets,
 838         .num_dapm_widgets       = ARRAY_SIZE(es8328_dapm_widgets),
 839         .dapm_routes            = es8328_dapm_routes,
 840         .num_dapm_routes        = ARRAY_SIZE(es8328_dapm_routes),
 841         .suspend_bias_off       = 1,
 842         .idle_bias_on           = 1,
 843         .use_pmdown_time        = 1,
 844         .endianness             = 1,
 845         .non_legacy_dai_naming  = 1,
 846 };
 847
 848 int es8328_probe(struct device *dev, struct regmap *regmap)
 849 {
 850         struct es8328_priv *es8328;
 851         int ret;
 852         int i;
 853
 854         if (IS_ERR(regmap))
 855                 return PTR_ERR(regmap);
 856
 857         es8328 = devm_kzalloc(dev, sizeof(*es8328), GFP_KERNEL);
 858         if (es8328 == NULL)
 859                 return -ENOMEM;
 860
 861         es8328->regmap = regmap;
 862
 863         for (i = 0; i < ARRAY_SIZE(es8328->supplies); i++)
 864                 es8328->supplies[i].supply = supply_names[i];
 865
 866         ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(es8328->supplies),
 867                                 es8328->supplies);
 868         if (ret) {
 869                 dev_err(dev, "unable to get regulators\n");
 870                 return ret;
 871         }
 872
 873         dev_set_drvdata(dev, es8328);
 874
 875         return devm_snd_soc_register_component(dev,
 876                         &es8328_component_driver, &es8328_dai, 1);
 877 }
 878 EXPORT_SYMBOL_GPL(es8328_probe);
 879
 880 MODULE_DESCRIPTION("ASoC ES8328 driver");
 881 MODULE_AUTHOR("Sean Cross <xobs@kosagi.com>");
 882 MODULE_LICENSE("GPL");