2 * R-Car Gen2 Clock Pulse Generator
4 * Copyright (C) 2016 Cogent Embedded Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
11 #include <linux/bug.h>
12 #include <linux/clk.h>
13 #include <linux/clk-provider.h>
14 #include <linux/device.h>
15 #include <linux/err.h>
16 #include <linux/init.h>
18 #include <linux/slab.h>
20 #include "renesas-cpg-mssr.h"
21 #include "rcar-gen2-cpg.h"
23 #define CPG_FRQCRB 0x0004
24 #define CPG_FRQCRB_KICK BIT(31)
25 #define CPG_SDCKCR 0x0074
26 #define CPG_PLL0CR 0x00d8
27 #define CPG_PLL0CR_STC_SHIFT 24
28 #define CPG_PLL0CR_STC_MASK (0x7f << CPG_PLL0CR_STC_SHIFT)
29 #define CPG_FRQCRC 0x00e0
30 #define CPG_FRQCRC_ZFC_SHIFT 8
31 #define CPG_FRQCRC_ZFC_MASK (0x1f << CPG_FRQCRC_ZFC_SHIFT)
32 #define CPG_ADSPCKCR 0x025c
33 #define CPG_RCANCKCR 0x0270
35 static spinlock_t cpg_lock
;
40 * Traits of this clock:
41 * prepare - clk_prepare only ensures that parents are prepared
42 * enable - clk_enable only ensures that parents are enabled
43 * rate - rate is adjustable. clk->rate = parent->rate * mult / 32
44 * parent - fixed parent. No clk_set_parent support
50 void __iomem
*kick_reg
;
53 #define to_z_clk(_hw) container_of(_hw, struct cpg_z_clk, hw)
55 static unsigned long cpg_z_clk_recalc_rate(struct clk_hw
*hw
,
56 unsigned long parent_rate
)
58 struct cpg_z_clk
*zclk
= to_z_clk(hw
);
62 val
= (readl(zclk
->reg
) & CPG_FRQCRC_ZFC_MASK
) >> CPG_FRQCRC_ZFC_SHIFT
;
65 return div_u64((u64
)parent_rate
* mult
, 32);
68 static long cpg_z_clk_round_rate(struct clk_hw
*hw
, unsigned long rate
,
69 unsigned long *parent_rate
)
71 unsigned long prate
= *parent_rate
;
77 mult
= div_u64((u64
)rate
* 32, prate
);
78 mult
= clamp(mult
, 1U, 32U);
80 return *parent_rate
/ 32 * mult
;
83 static int cpg_z_clk_set_rate(struct clk_hw
*hw
, unsigned long rate
,
84 unsigned long parent_rate
)
86 struct cpg_z_clk
*zclk
= to_z_clk(hw
);
91 mult
= div_u64((u64
)rate
* 32, parent_rate
);
92 mult
= clamp(mult
, 1U, 32U);
94 if (readl(zclk
->kick_reg
) & CPG_FRQCRB_KICK
)
97 val
= readl(zclk
->reg
);
98 val
&= ~CPG_FRQCRC_ZFC_MASK
;
99 val
|= (32 - mult
) << CPG_FRQCRC_ZFC_SHIFT
;
100 writel(val
, zclk
->reg
);
103 * Set KICK bit in FRQCRB to update hardware setting and wait for
104 * clock change completion.
106 kick
= readl(zclk
->kick_reg
);
107 kick
|= CPG_FRQCRB_KICK
;
108 writel(kick
, zclk
->kick_reg
);
111 * Note: There is no HW information about the worst case latency.
113 * Using experimental measurements, it seems that no more than
114 * ~10 iterations are needed, independently of the CPU rate.
115 * Since this value might be dependent on external xtal rate, pll1
116 * rate or even the other emulation clocks rate, use 1000 as a
117 * "super" safe value.
119 for (i
= 1000; i
; i
--) {
120 if (!(readl(zclk
->kick_reg
) & CPG_FRQCRB_KICK
))
129 static const struct clk_ops cpg_z_clk_ops
= {
130 .recalc_rate
= cpg_z_clk_recalc_rate
,
131 .round_rate
= cpg_z_clk_round_rate
,
132 .set_rate
= cpg_z_clk_set_rate
,
135 static struct clk
* __init
cpg_z_clk_register(const char *name
,
136 const char *parent_name
,
139 struct clk_init_data init
;
140 struct cpg_z_clk
*zclk
;
143 zclk
= kzalloc(sizeof(*zclk
), GFP_KERNEL
);
145 return ERR_PTR(-ENOMEM
);
148 init
.ops
= &cpg_z_clk_ops
;
150 init
.parent_names
= &parent_name
;
151 init
.num_parents
= 1;
153 zclk
->reg
= base
+ CPG_FRQCRC
;
154 zclk
->kick_reg
= base
+ CPG_FRQCRB
;
155 zclk
->hw
.init
= &init
;
157 clk
= clk_register(NULL
, &zclk
->hw
);
164 static struct clk
* __init
cpg_rcan_clk_register(const char *name
,
165 const char *parent_name
,
168 struct clk_fixed_factor
*fixed
;
169 struct clk_gate
*gate
;
172 fixed
= kzalloc(sizeof(*fixed
), GFP_KERNEL
);
174 return ERR_PTR(-ENOMEM
);
179 gate
= kzalloc(sizeof(*gate
), GFP_KERNEL
);
182 return ERR_PTR(-ENOMEM
);
185 gate
->reg
= base
+ CPG_RCANCKCR
;
187 gate
->flags
= CLK_GATE_SET_TO_DISABLE
;
188 gate
->lock
= &cpg_lock
;
190 clk
= clk_register_composite(NULL
, name
, &parent_name
, 1, NULL
, NULL
,
191 &fixed
->hw
, &clk_fixed_factor_ops
,
192 &gate
->hw
, &clk_gate_ops
, 0);
202 static const struct clk_div_table cpg_adsp_div_table
[] = {
203 { 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 },
204 { 5, 12 }, { 6, 16 }, { 7, 18 }, { 8, 24 },
205 { 10, 36 }, { 11, 48 }, { 0, 0 },
208 static struct clk
* __init
cpg_adsp_clk_register(const char *name
,
209 const char *parent_name
,
212 struct clk_divider
*div
;
213 struct clk_gate
*gate
;
216 div
= kzalloc(sizeof(*div
), GFP_KERNEL
);
218 return ERR_PTR(-ENOMEM
);
220 div
->reg
= base
+ CPG_ADSPCKCR
;
222 div
->table
= cpg_adsp_div_table
;
223 div
->lock
= &cpg_lock
;
225 gate
= kzalloc(sizeof(*gate
), GFP_KERNEL
);
228 return ERR_PTR(-ENOMEM
);
231 gate
->reg
= base
+ CPG_ADSPCKCR
;
233 gate
->flags
= CLK_GATE_SET_TO_DISABLE
;
234 gate
->lock
= &cpg_lock
;
236 clk
= clk_register_composite(NULL
, name
, &parent_name
, 1, NULL
, NULL
,
237 &div
->hw
, &clk_divider_ops
,
238 &gate
->hw
, &clk_gate_ops
, 0);
248 static const struct clk_div_table cpg_sdh_div_table
[] = {
249 { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 },
250 { 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
251 { 8, 24 }, { 10, 36 }, { 11, 48 }, { 0, 0 },
254 static const struct clk_div_table cpg_sd01_div_table
[] = {
255 { 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
256 { 8, 24 }, { 10, 36 }, { 11, 48 }, { 12, 10 },
260 static const struct rcar_gen2_cpg_pll_config
*cpg_pll_config __initdata
;
261 static unsigned int cpg_pll0_div __initdata
;
262 static u32 cpg_mode __initdata
;
264 struct clk
* __init
rcar_gen2_cpg_clk_register(struct device
*dev
,
265 const struct cpg_core_clk
*core
,
266 const struct cpg_mssr_info
*info
,
270 const struct clk_div_table
*table
= NULL
;
271 const struct clk
*parent
;
272 const char *parent_name
;
273 unsigned int mult
= 1;
274 unsigned int div
= 1;
277 parent
= clks
[core
->parent
];
279 return ERR_CAST(parent
);
281 parent_name
= __clk_get_name(parent
);
283 switch (core
->type
) {
285 case CLK_TYPE_GEN2_MAIN
:
286 div
= cpg_pll_config
->extal_div
;
289 case CLK_TYPE_GEN2_PLL0
:
291 * PLL0 is a configurable multiplier clock except on R-Car
292 * V2H/E2. Register the PLL0 clock as a fixed factor clock for
293 * now as there's no generic multiplier clock implementation and
294 * we currently have no need to change the multiplier value.
296 mult
= cpg_pll_config
->pll0_mult
;
299 u32 pll0cr
= readl(base
+ CPG_PLL0CR
);
301 mult
= (((pll0cr
& CPG_PLL0CR_STC_MASK
) >>
302 CPG_PLL0CR_STC_SHIFT
) + 1) * 2;
306 case CLK_TYPE_GEN2_PLL1
:
307 mult
= cpg_pll_config
->pll1_mult
/ 2;
310 case CLK_TYPE_GEN2_PLL3
:
311 mult
= cpg_pll_config
->pll3_mult
;
314 case CLK_TYPE_GEN2_Z
:
315 return cpg_z_clk_register(core
->name
, parent_name
, base
);
317 case CLK_TYPE_GEN2_LB
:
318 div
= cpg_mode
& BIT(18) ? 36 : 24;
321 case CLK_TYPE_GEN2_ADSP
:
322 return cpg_adsp_clk_register(core
->name
, parent_name
, base
);
324 case CLK_TYPE_GEN2_SDH
:
325 table
= cpg_sdh_div_table
;
329 case CLK_TYPE_GEN2_SD0
:
330 table
= cpg_sd01_div_table
;
334 case CLK_TYPE_GEN2_SD1
:
335 table
= cpg_sd01_div_table
;
339 case CLK_TYPE_GEN2_QSPI
:
340 div
= (cpg_mode
& (BIT(3) | BIT(2) | BIT(1))) == BIT(2) ?
344 case CLK_TYPE_GEN2_RCAN
:
345 return cpg_rcan_clk_register(core
->name
, parent_name
, base
);
348 return ERR_PTR(-EINVAL
);
352 return clk_register_fixed_factor(NULL
, core
->name
, parent_name
,
355 return clk_register_divider_table(NULL
, core
->name
,
357 base
+ CPG_SDCKCR
, shift
, 4,
358 0, table
, &cpg_lock
);
361 int __init
rcar_gen2_cpg_init(const struct rcar_gen2_cpg_pll_config
*config
,
362 unsigned int pll0_div
, u32 mode
)
364 cpg_pll_config
= config
;
365 cpg_pll0_div
= pll0_div
;
368 spin_lock_init(&cpg_lock
);