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tcp: fix lockdep splat in tcp_snd_una_update()
[linux/fpc-iii.git] / drivers / media / i2c / adv7604.c
blob41a1bfc5eaa7bde77612a35ae7e629ad05764021
1 /*
2 * adv7604 - Analog Devices ADV7604 video decoder driver
3 *
4 * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
5 *
6 * This program is free software; you may redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
17 * SOFTWARE.
18 *
19 */
20
21 /*
22 * References (c = chapter, p = page):
23 * REF_01 - Analog devices, ADV7604, Register Settings Recommendations,
24 * Revision 2.5, June 2010
25 * REF_02 - Analog devices, Register map documentation, Documentation of
26 * the register maps, Software manual, Rev. F, June 2010
27 * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010
28 */
29
30 #include <linux/delay.h>
31 #include <linux/gpio/consumer.h>
32 #include <linux/hdmi.h>
33 #include <linux/i2c.h>
34 #include <linux/kernel.h>
35 #include <linux/module.h>
36 #include <linux/slab.h>
37 #include <linux/v4l2-dv-timings.h>
38 #include <linux/videodev2.h>
39 #include <linux/workqueue.h>
40 #include <linux/regmap.h>
41
42 #include <media/i2c/adv7604.h>
43 #include <media/v4l2-ctrls.h>
44 #include <media/v4l2-device.h>
45 #include <media/v4l2-event.h>
46 #include <media/v4l2-dv-timings.h>
47 #include <media/v4l2-of.h>
48
49 static int debug;
50 module_param(debug, int, 0644);
51 MODULE_PARM_DESC(debug, "debug level (0-2)");
52
53 MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver");
54 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
55 MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>");
56 MODULE_LICENSE("GPL");
57
58 /* ADV7604 system clock frequency */
59 #define ADV76XX_FSC (28636360)
60
61 #define ADV76XX_RGB_OUT (1 << 1)
62
63 #define ADV76XX_OP_FORMAT_SEL_8BIT (0 << 0)
64 #define ADV7604_OP_FORMAT_SEL_10BIT (1 << 0)
65 #define ADV76XX_OP_FORMAT_SEL_12BIT (2 << 0)
66
67 #define ADV76XX_OP_MODE_SEL_SDR_422 (0 << 5)
68 #define ADV7604_OP_MODE_SEL_DDR_422 (1 << 5)
69 #define ADV76XX_OP_MODE_SEL_SDR_444 (2 << 5)
70 #define ADV7604_OP_MODE_SEL_DDR_444 (3 << 5)
71 #define ADV76XX_OP_MODE_SEL_SDR_422_2X (4 << 5)
72 #define ADV7604_OP_MODE_SEL_ADI_CM (5 << 5)
73
74 #define ADV76XX_OP_CH_SEL_GBR (0 << 5)
75 #define ADV76XX_OP_CH_SEL_GRB (1 << 5)
76 #define ADV76XX_OP_CH_SEL_BGR (2 << 5)
77 #define ADV76XX_OP_CH_SEL_RGB (3 << 5)
78 #define ADV76XX_OP_CH_SEL_BRG (4 << 5)
79 #define ADV76XX_OP_CH_SEL_RBG (5 << 5)
80
81 #define ADV76XX_OP_SWAP_CB_CR (1 << 0)
82
83 enum adv76xx_type {
84 ADV7604,
85 ADV7611,
86 ADV7612,
87 };
88
89 struct adv76xx_reg_seq {
90 unsigned int reg;
91 u8 val;
92 };
93
94 struct adv76xx_format_info {
95 u32 code;
96 u8 op_ch_sel;
97 bool rgb_out;
98 bool swap_cb_cr;
99 u8 op_format_sel;
100 };
101
102 struct adv76xx_cfg_read_infoframe {
103 const char *desc;
104 u8 present_mask;
105 u8 head_addr;
106 u8 payload_addr;
107 };
108
109 struct adv76xx_chip_info {
110 enum adv76xx_type type;
111
112 bool has_afe;
113 unsigned int max_port;
114 unsigned int num_dv_ports;
115
116 unsigned int edid_enable_reg;
117 unsigned int edid_status_reg;
118 unsigned int lcf_reg;
119
120 unsigned int cable_det_mask;
121 unsigned int tdms_lock_mask;
122 unsigned int fmt_change_digital_mask;
123 unsigned int cp_csc;
124
125 const struct adv76xx_format_info *formats;
126 unsigned int nformats;
127
128 void (*set_termination)(struct v4l2_subdev *sd, bool enable);
129 void (*setup_irqs)(struct v4l2_subdev *sd);
130 unsigned int (*read_hdmi_pixelclock)(struct v4l2_subdev *sd);
131 unsigned int (*read_cable_det)(struct v4l2_subdev *sd);
132
133 /* 0 = AFE, 1 = HDMI */
134 const struct adv76xx_reg_seq *recommended_settings[2];
135 unsigned int num_recommended_settings[2];
136
137 unsigned long page_mask;
138
139 /* Masks for timings */
140 unsigned int linewidth_mask;
141 unsigned int field0_height_mask;
142 unsigned int field1_height_mask;
143 unsigned int hfrontporch_mask;
144 unsigned int hsync_mask;
145 unsigned int hbackporch_mask;
146 unsigned int field0_vfrontporch_mask;
147 unsigned int field1_vfrontporch_mask;
148 unsigned int field0_vsync_mask;
149 unsigned int field1_vsync_mask;
150 unsigned int field0_vbackporch_mask;
151 unsigned int field1_vbackporch_mask;
152 };
153
154 /*
155 **********************************************************************
156 *
157 * Arrays with configuration parameters for the ADV7604
158 *
159 **********************************************************************
160 */
161
162 struct adv76xx_state {
163 const struct adv76xx_chip_info *info;
164 struct adv76xx_platform_data pdata;
165
166 struct gpio_desc *hpd_gpio[4];
167
168 struct v4l2_subdev sd;
169 struct media_pad pads[ADV76XX_PAD_MAX];
170 unsigned int source_pad;
171
172 struct v4l2_ctrl_handler hdl;
173
174 enum adv76xx_pad selected_input;
175
176 struct v4l2_dv_timings timings;
177 const struct adv76xx_format_info *format;
178
179 struct {
180 u8 edid[256];
181 u32 present;
182 unsigned blocks;
183 } edid;
184 u16 spa_port_a[2];
185 struct v4l2_fract aspect_ratio;
186 u32 rgb_quantization_range;
187 struct workqueue_struct *work_queues;
188 struct delayed_work delayed_work_enable_hotplug;
189 bool restart_stdi_once;
190
191 /* i2c clients */
192 struct i2c_client *i2c_clients[ADV76XX_PAGE_MAX];
193
194 /* Regmaps */
195 struct regmap *regmap[ADV76XX_PAGE_MAX];
196
197 /* controls */
198 struct v4l2_ctrl *detect_tx_5v_ctrl;
199 struct v4l2_ctrl *analog_sampling_phase_ctrl;
200 struct v4l2_ctrl *free_run_color_manual_ctrl;
201 struct v4l2_ctrl *free_run_color_ctrl;
202 struct v4l2_ctrl *rgb_quantization_range_ctrl;
203 };
204
205 static bool adv76xx_has_afe(struct adv76xx_state *state)
206 {
207 return state->info->has_afe;
208 }
209
210 /* Unsupported timings. This device cannot support 720p30. */
211 static const struct v4l2_dv_timings adv76xx_timings_exceptions[] = {
212 V4L2_DV_BT_CEA_1280X720P30,
213 { }
214 };
215
216 static bool adv76xx_check_dv_timings(const struct v4l2_dv_timings *t, void *hdl)
217 {
218 int i;
219
220 for (i = 0; adv76xx_timings_exceptions[i].bt.width; i++)
221 if (v4l2_match_dv_timings(t, adv76xx_timings_exceptions + i, 0, false))
222 return false;
223 return true;
224 }
225
226 struct adv76xx_video_standards {
227 struct v4l2_dv_timings timings;
228 u8 vid_std;
229 u8 v_freq;
230 };
231
232 /* sorted by number of lines */
233 static const struct adv76xx_video_standards adv7604_prim_mode_comp[] = {
234 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
235 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
236 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
237 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
238 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
239 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
240 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
241 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
242 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
243 /* TODO add 1920x1080P60_RB (CVT timing) */
244 { },
245 };
246
247 /* sorted by number of lines */
248 static const struct adv76xx_video_standards adv7604_prim_mode_gr[] = {
249 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
250 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
251 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
252 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
253 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
254 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
255 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
256 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
257 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
258 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
259 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
260 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
261 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
262 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
263 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
264 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
265 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
266 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
267 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
268 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
269 /* TODO add 1600X1200P60_RB (not a DMT timing) */
270 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
271 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
272 { },
273 };
274
275 /* sorted by number of lines */
276 static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_comp[] = {
277 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
278 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
279 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
280 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
281 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
282 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
283 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
284 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
285 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
286 { },
287 };
288
289 /* sorted by number of lines */
290 static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_gr[] = {
291 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
292 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
293 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
294 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
295 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
296 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
297 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
298 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
299 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
300 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
301 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
302 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
303 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
304 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
305 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
306 { },
307 };
308
309 static const struct v4l2_event adv76xx_ev_fmt = {
310 .type = V4L2_EVENT_SOURCE_CHANGE,
311 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
312 };
313
314 /* ----------------------------------------------------------------------- */
315
316 static inline struct adv76xx_state *to_state(struct v4l2_subdev *sd)
317 {
318 return container_of(sd, struct adv76xx_state, sd);
319 }
320
321 static inline unsigned htotal(const struct v4l2_bt_timings *t)
322 {
323 return V4L2_DV_BT_FRAME_WIDTH(t);
324 }
325
326 static inline unsigned vtotal(const struct v4l2_bt_timings *t)
327 {
328 return V4L2_DV_BT_FRAME_HEIGHT(t);
329 }
330
331 /* ----------------------------------------------------------------------- */
332
333 static int adv76xx_read_check(struct adv76xx_state *state,
334 int client_page, u8 reg)
335 {
336 struct i2c_client *client = state->i2c_clients[client_page];
337 int err;
338 unsigned int val;
339
340 err = regmap_read(state->regmap[client_page], reg, &val);
341
342 if (err) {
343 v4l_err(client, "error reading %02x, %02x\n",
344 client->addr, reg);
345 return err;
346 }
347 return val;
348 }
349
350 /* adv76xx_write_block(): Write raw data with a maximum of I2C_SMBUS_BLOCK_MAX
351 * size to one or more registers.
352 *
353 * A value of zero will be returned on success, a negative errno will
354 * be returned in error cases.
355 */
356 static int adv76xx_write_block(struct adv76xx_state *state, int client_page,
357 unsigned int init_reg, const void *val,
358 size_t val_len)
359 {
360 struct regmap *regmap = state->regmap[client_page];
361
362 if (val_len > I2C_SMBUS_BLOCK_MAX)
363 val_len = I2C_SMBUS_BLOCK_MAX;
364
365 return regmap_raw_write(regmap, init_reg, val, val_len);
366 }
367
368 /* ----------------------------------------------------------------------- */
369
370 static inline int io_read(struct v4l2_subdev *sd, u8 reg)
371 {
372 struct adv76xx_state *state = to_state(sd);
373
374 return adv76xx_read_check(state, ADV76XX_PAGE_IO, reg);
375 }
376
377 static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
378 {
379 struct adv76xx_state *state = to_state(sd);
380
381 return regmap_write(state->regmap[ADV76XX_PAGE_IO], reg, val);
382 }
383
384 static inline int io_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
385 {
386 return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val);
387 }
388
389 static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
390 {
391 struct adv76xx_state *state = to_state(sd);
392
393 return adv76xx_read_check(state, ADV7604_PAGE_AVLINK, reg);
394 }
395
396 static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
397 {
398 struct adv76xx_state *state = to_state(sd);
399
400 return regmap_write(state->regmap[ADV7604_PAGE_AVLINK], reg, val);
401 }
402
403 static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
404 {
405 struct adv76xx_state *state = to_state(sd);
406
407 return adv76xx_read_check(state, ADV76XX_PAGE_CEC, reg);
408 }
409
410 static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
411 {
412 struct adv76xx_state *state = to_state(sd);
413
414 return regmap_write(state->regmap[ADV76XX_PAGE_CEC], reg, val);
415 }
416
417 static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
418 {
419 struct adv76xx_state *state = to_state(sd);
420
421 return adv76xx_read_check(state, ADV76XX_PAGE_INFOFRAME, reg);
422 }
423
424 static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
425 {
426 struct adv76xx_state *state = to_state(sd);
427
428 return regmap_write(state->regmap[ADV76XX_PAGE_INFOFRAME], reg, val);
429 }
430
431 static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
432 {
433 struct adv76xx_state *state = to_state(sd);
434
435 return adv76xx_read_check(state, ADV76XX_PAGE_AFE, reg);
436 }
437
438 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
439 {
440 struct adv76xx_state *state = to_state(sd);
441
442 return regmap_write(state->regmap[ADV76XX_PAGE_AFE], reg, val);
443 }
444
445 static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
446 {
447 struct adv76xx_state *state = to_state(sd);
448
449 return adv76xx_read_check(state, ADV76XX_PAGE_REP, reg);
450 }
451
452 static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
453 {
454 struct adv76xx_state *state = to_state(sd);
455
456 return regmap_write(state->regmap[ADV76XX_PAGE_REP], reg, val);
457 }
458
459 static inline int rep_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
460 {
461 return rep_write(sd, reg, (rep_read(sd, reg) & ~mask) | val);
462 }
463
464 static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
465 {
466 struct adv76xx_state *state = to_state(sd);
467
468 return adv76xx_read_check(state, ADV76XX_PAGE_EDID, reg);
469 }
470
471 static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
472 {
473 struct adv76xx_state *state = to_state(sd);
474
475 return regmap_write(state->regmap[ADV76XX_PAGE_EDID], reg, val);
476 }
477
478 static inline int edid_write_block(struct v4l2_subdev *sd,
479 unsigned int total_len, const u8 *val)
480 {
481 struct adv76xx_state *state = to_state(sd);
482 int err = 0;
483 int i = 0;
484 int len = 0;
485
486 v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n",
487 __func__, total_len);
488
489 while (!err && i < total_len) {
490 len = (total_len - i) > I2C_SMBUS_BLOCK_MAX ?
491 I2C_SMBUS_BLOCK_MAX :
492 (total_len - i);
493
494 err = adv76xx_write_block(state, ADV76XX_PAGE_EDID,
495 i, val + i, len);
496 i += len;
497 }
498
499 return err;
500 }
501
502 static void adv76xx_set_hpd(struct adv76xx_state *state, unsigned int hpd)
503 {
504 unsigned int i;
505
506 for (i = 0; i < state->info->num_dv_ports; ++i)
507 gpiod_set_value_cansleep(state->hpd_gpio[i], hpd & BIT(i));
508
509 v4l2_subdev_notify(&state->sd, ADV76XX_HOTPLUG, &hpd);
510 }
511
512 static void adv76xx_delayed_work_enable_hotplug(struct work_struct *work)
513 {
514 struct delayed_work *dwork = to_delayed_work(work);
515 struct adv76xx_state *state = container_of(dwork, struct adv76xx_state,
516 delayed_work_enable_hotplug);
517 struct v4l2_subdev *sd = &state->sd;
518
519 v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__);
520
521 adv76xx_set_hpd(state, state->edid.present);
522 }
523
524 static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
525 {
526 struct adv76xx_state *state = to_state(sd);
527
528 return adv76xx_read_check(state, ADV76XX_PAGE_HDMI, reg);
529 }
530
531 static u16 hdmi_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
532 {
533 return ((hdmi_read(sd, reg) << 8) | hdmi_read(sd, reg + 1)) & mask;
534 }
535
536 static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
537 {
538 struct adv76xx_state *state = to_state(sd);
539
540 return regmap_write(state->regmap[ADV76XX_PAGE_HDMI], reg, val);
541 }
542
543 static inline int hdmi_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
544 {
545 return hdmi_write(sd, reg, (hdmi_read(sd, reg) & ~mask) | val);
546 }
547
548 static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val)
549 {
550 struct adv76xx_state *state = to_state(sd);
551
552 return regmap_write(state->regmap[ADV76XX_PAGE_TEST], reg, val);
553 }
554
555 static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
556 {
557 struct adv76xx_state *state = to_state(sd);
558
559 return adv76xx_read_check(state, ADV76XX_PAGE_CP, reg);
560 }
561
562 static u16 cp_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
563 {
564 return ((cp_read(sd, reg) << 8) | cp_read(sd, reg + 1)) & mask;
565 }
566
567 static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
568 {
569 struct adv76xx_state *state = to_state(sd);
570
571 return regmap_write(state->regmap[ADV76XX_PAGE_CP], reg, val);
572 }
573
574 static inline int cp_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
575 {
576 return cp_write(sd, reg, (cp_read(sd, reg) & ~mask) | val);
577 }
578
579 static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
580 {
581 struct adv76xx_state *state = to_state(sd);
582
583 return adv76xx_read_check(state, ADV7604_PAGE_VDP, reg);
584 }
585
586 static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
587 {
588 struct adv76xx_state *state = to_state(sd);
589
590 return regmap_write(state->regmap[ADV7604_PAGE_VDP], reg, val);
591 }
592
593 #define ADV76XX_REG(page, offset) (((page) << 8) | (offset))
594 #define ADV76XX_REG_SEQ_TERM 0xffff
595
596 #ifdef CONFIG_VIDEO_ADV_DEBUG
597 static int adv76xx_read_reg(struct v4l2_subdev *sd, unsigned int reg)
598 {
599 struct adv76xx_state *state = to_state(sd);
600 unsigned int page = reg >> 8;
601 unsigned int val;
602 int err;
603
604 if (!(BIT(page) & state->info->page_mask))
605 return -EINVAL;
606
607 reg &= 0xff;
608 err = regmap_read(state->regmap[page], reg, &val);
609
610 return err ? err : val;
611 }
612 #endif
613
614 static int adv76xx_write_reg(struct v4l2_subdev *sd, unsigned int reg, u8 val)
615 {
616 struct adv76xx_state *state = to_state(sd);
617 unsigned int page = reg >> 8;
618
619 if (!(BIT(page) & state->info->page_mask))
620 return -EINVAL;
621
622 reg &= 0xff;
623
624 return regmap_write(state->regmap[page], reg, val);
625 }
626
627 static void adv76xx_write_reg_seq(struct v4l2_subdev *sd,
628 const struct adv76xx_reg_seq *reg_seq)
629 {
630 unsigned int i;
631
632 for (i = 0; reg_seq[i].reg != ADV76XX_REG_SEQ_TERM; i++)
633 adv76xx_write_reg(sd, reg_seq[i].reg, reg_seq[i].val);
634 }
635
636 /* -----------------------------------------------------------------------------
637 * Format helpers
638 */
639
640 static const struct adv76xx_format_info adv7604_formats[] = {
641 { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
642 ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
643 { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
644 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
645 { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
646 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
647 { MEDIA_BUS_FMT_YUYV10_2X10, ADV76XX_OP_CH_SEL_RGB, false, false,
648 ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
649 { MEDIA_BUS_FMT_YVYU10_2X10, ADV76XX_OP_CH_SEL_RGB, false, true,
650 ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
651 { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false,
652 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
653 { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true,
654 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
655 { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
656 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
657 { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
658 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
659 { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
660 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
661 { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
662 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
663 { MEDIA_BUS_FMT_UYVY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, false,
664 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
665 { MEDIA_BUS_FMT_VYUY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, true,
666 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
667 { MEDIA_BUS_FMT_YUYV10_1X20, ADV76XX_OP_CH_SEL_RGB, false, false,
668 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
669 { MEDIA_BUS_FMT_YVYU10_1X20, ADV76XX_OP_CH_SEL_RGB, false, true,
670 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
671 { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false,
672 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
673 { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true,
674 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
675 { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false,
676 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
677 { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true,
678 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
679 };
680
681 static const struct adv76xx_format_info adv7611_formats[] = {
682 { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
683 ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
684 { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
685 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
686 { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
687 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
688 { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false,
689 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
690 { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true,
691 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
692 { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
693 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
694 { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
695 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
696 { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
697 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
698 { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
699 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
700 { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false,
701 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
702 { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true,
703 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
704 { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false,
705 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
706 { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true,
707 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
708 };
709
710 static const struct adv76xx_format_info adv7612_formats[] = {
711 { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
712 ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
713 { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
714 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
715 { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
716 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
717 { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
718 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
719 { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
720 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
721 { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
722 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
723 { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
724 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
725 };
726
727 static const struct adv76xx_format_info *
728 adv76xx_format_info(struct adv76xx_state *state, u32 code)
729 {
730 unsigned int i;
731
732 for (i = 0; i < state->info->nformats; ++i) {
733 if (state->info->formats[i].code == code)
734 return &state->info->formats[i];
735 }
736
737 return NULL;
738 }
739
740 /* ----------------------------------------------------------------------- */
741
742 static inline bool is_analog_input(struct v4l2_subdev *sd)
743 {
744 struct adv76xx_state *state = to_state(sd);
745
746 return state->selected_input == ADV7604_PAD_VGA_RGB ||
747 state->selected_input == ADV7604_PAD_VGA_COMP;
748 }
749
750 static inline bool is_digital_input(struct v4l2_subdev *sd)
751 {
752 struct adv76xx_state *state = to_state(sd);
753
754 return state->selected_input == ADV76XX_PAD_HDMI_PORT_A ||
755 state->selected_input == ADV7604_PAD_HDMI_PORT_B ||
756 state->selected_input == ADV7604_PAD_HDMI_PORT_C ||
757 state->selected_input == ADV7604_PAD_HDMI_PORT_D;
758 }
759
760 static const struct v4l2_dv_timings_cap adv7604_timings_cap_analog = {
761 .type = V4L2_DV_BT_656_1120,
762 /* keep this initialization for compatibility with GCC < 4.4.6 */
763 .reserved = { 0 },
764 V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 170000000,
765 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
766 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
767 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
768 V4L2_DV_BT_CAP_CUSTOM)
769 };
770
771 static const struct v4l2_dv_timings_cap adv76xx_timings_cap_digital = {
772 .type = V4L2_DV_BT_656_1120,
773 /* keep this initialization for compatibility with GCC < 4.4.6 */
774 .reserved = { 0 },
775 V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 225000000,
776 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
777 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
778 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
779 V4L2_DV_BT_CAP_CUSTOM)
780 };
781
782 static inline const struct v4l2_dv_timings_cap *
783 adv76xx_get_dv_timings_cap(struct v4l2_subdev *sd)
784 {
785 return is_digital_input(sd) ? &adv76xx_timings_cap_digital :
786 &adv7604_timings_cap_analog;
787 }
788
789
790 /* ----------------------------------------------------------------------- */
791
792 #ifdef CONFIG_VIDEO_ADV_DEBUG
793 static void adv76xx_inv_register(struct v4l2_subdev *sd)
794 {
795 v4l2_info(sd, "0x000-0x0ff: IO Map\n");
796 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
797 v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
798 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
799 v4l2_info(sd, "0x400-0x4ff: ESDP Map\n");
800 v4l2_info(sd, "0x500-0x5ff: DPP Map\n");
801 v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
802 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
803 v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
804 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
805 v4l2_info(sd, "0xa00-0xaff: Test Map\n");
806 v4l2_info(sd, "0xb00-0xbff: CP Map\n");
807 v4l2_info(sd, "0xc00-0xcff: VDP Map\n");
808 }
809
810 static int adv76xx_g_register(struct v4l2_subdev *sd,
811 struct v4l2_dbg_register *reg)
812 {
813 int ret;
814
815 ret = adv76xx_read_reg(sd, reg->reg);
816 if (ret < 0) {
817 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
818 adv76xx_inv_register(sd);
819 return ret;
820 }
821
822 reg->size = 1;
823 reg->val = ret;
824
825 return 0;
826 }
827
828 static int adv76xx_s_register(struct v4l2_subdev *sd,
829 const struct v4l2_dbg_register *reg)
830 {
831 int ret;
832
833 ret = adv76xx_write_reg(sd, reg->reg, reg->val);
834 if (ret < 0) {
835 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
836 adv76xx_inv_register(sd);
837 return ret;
838 }
839
840 return 0;
841 }
842 #endif
843
844 static unsigned int adv7604_read_cable_det(struct v4l2_subdev *sd)
845 {
846 u8 value = io_read(sd, 0x6f);
847
848 return ((value & 0x10) >> 4)
849 | ((value & 0x08) >> 2)
850 | ((value & 0x04) << 0)
851 | ((value & 0x02) << 2);
852 }
853
854 static unsigned int adv7611_read_cable_det(struct v4l2_subdev *sd)
855 {
856 u8 value = io_read(sd, 0x6f);
857
858 return value & 1;
859 }
860
861 static unsigned int adv7612_read_cable_det(struct v4l2_subdev *sd)
862 {
863 /* Reads CABLE_DET_A_RAW. For input B support, need to
864 * account for bit 7 [MSB] of 0x6a (ie. CABLE_DET_B_RAW)
865 */
866 u8 value = io_read(sd, 0x6f);
867
868 return value & 1;
869 }
870
871 static int adv76xx_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
872 {
873 struct adv76xx_state *state = to_state(sd);
874 const struct adv76xx_chip_info *info = state->info;
875
876 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
877 info->read_cable_det(sd));
878 }
879
880 static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
881 u8 prim_mode,
882 const struct adv76xx_video_standards *predef_vid_timings,
883 const struct v4l2_dv_timings *timings)
884 {
885 int i;
886
887 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
888 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
889 is_digital_input(sd) ? 250000 : 1000000, false))
890 continue;
891 io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */
892 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) +
893 prim_mode); /* v_freq and prim mode */
894 return 0;
895 }
896
897 return -1;
898 }
899
900 static int configure_predefined_video_timings(struct v4l2_subdev *sd,
901 struct v4l2_dv_timings *timings)
902 {
903 struct adv76xx_state *state = to_state(sd);
904 int err;
905
906 v4l2_dbg(1, debug, sd, "%s", __func__);
907
908 if (adv76xx_has_afe(state)) {
909 /* reset to default values */
910 io_write(sd, 0x16, 0x43);
911 io_write(sd, 0x17, 0x5a);
912 }
913 /* disable embedded syncs for auto graphics mode */
914 cp_write_clr_set(sd, 0x81, 0x10, 0x00);
915 cp_write(sd, 0x8f, 0x00);
916 cp_write(sd, 0x90, 0x00);
917 cp_write(sd, 0xa2, 0x00);
918 cp_write(sd, 0xa3, 0x00);
919 cp_write(sd, 0xa4, 0x00);
920 cp_write(sd, 0xa5, 0x00);
921 cp_write(sd, 0xa6, 0x00);
922 cp_write(sd, 0xa7, 0x00);
923 cp_write(sd, 0xab, 0x00);
924 cp_write(sd, 0xac, 0x00);
925
926 if (is_analog_input(sd)) {
927 err = find_and_set_predefined_video_timings(sd,
928 0x01, adv7604_prim_mode_comp, timings);
929 if (err)
930 err = find_and_set_predefined_video_timings(sd,
931 0x02, adv7604_prim_mode_gr, timings);
932 } else if (is_digital_input(sd)) {
933 err = find_and_set_predefined_video_timings(sd,
934 0x05, adv76xx_prim_mode_hdmi_comp, timings);
935 if (err)
936 err = find_and_set_predefined_video_timings(sd,
937 0x06, adv76xx_prim_mode_hdmi_gr, timings);
938 } else {
939 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
940 __func__, state->selected_input);
941 err = -1;
942 }
943
944
945 return err;
946 }
947
948 static void configure_custom_video_timings(struct v4l2_subdev *sd,
949 const struct v4l2_bt_timings *bt)
950 {
951 struct adv76xx_state *state = to_state(sd);
952 u32 width = htotal(bt);
953 u32 height = vtotal(bt);
954 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
955 u16 cp_start_eav = width - bt->hfrontporch;
956 u16 cp_start_vbi = height - bt->vfrontporch;
957 u16 cp_end_vbi = bt->vsync + bt->vbackporch;
958 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
959 ((width * (ADV76XX_FSC / 100)) / ((u32)bt->pixelclock / 100)) : 0;
960 const u8 pll[2] = {
961 0xc0 | ((width >> 8) & 0x1f),
962 width & 0xff
963 };
964
965 v4l2_dbg(2, debug, sd, "%s\n", __func__);
966
967 if (is_analog_input(sd)) {
968 /* auto graphics */
969 io_write(sd, 0x00, 0x07); /* video std */
970 io_write(sd, 0x01, 0x02); /* prim mode */
971 /* enable embedded syncs for auto graphics mode */
972 cp_write_clr_set(sd, 0x81, 0x10, 0x10);
973
974 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
975 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
976 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
977 if (regmap_raw_write(state->regmap[ADV76XX_PAGE_IO],
978 0x16, pll, 2))
979 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
980
981 /* active video - horizontal timing */
982 cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff);
983 cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) |
984 ((cp_start_eav >> 8) & 0x0f));
985 cp_write(sd, 0xa4, cp_start_eav & 0xff);
986
987 /* active video - vertical timing */
988 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
989 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
990 ((cp_end_vbi >> 8) & 0xf));
991 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
992 } else if (is_digital_input(sd)) {
993 /* set default prim_mode/vid_std for HDMI
994 according to [REF_03, c. 4.2] */
995 io_write(sd, 0x00, 0x02); /* video std */
996 io_write(sd, 0x01, 0x06); /* prim mode */
997 } else {
998 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
999 __func__, state->selected_input);
1000 }
1001
1002 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
1003 cp_write(sd, 0x90, ch1_fr_ll & 0xff);
1004 cp_write(sd, 0xab, (height >> 4) & 0xff);
1005 cp_write(sd, 0xac, (height & 0x0f) << 4);
1006 }
1007
1008 static void adv76xx_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c)
1009 {
1010 struct adv76xx_state *state = to_state(sd);
1011 u8 offset_buf[4];
1012
1013 if (auto_offset) {
1014 offset_a = 0x3ff;
1015 offset_b = 0x3ff;
1016 offset_c = 0x3ff;
1017 }
1018
1019 v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n",
1020 __func__, auto_offset ? "Auto" : "Manual",
1021 offset_a, offset_b, offset_c);
1022
1023 offset_buf[0] = (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4);
1024 offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6);
1025 offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8);
1026 offset_buf[3] = offset_c & 0x0ff;
1027
1028 /* Registers must be written in this order with no i2c access in between */
1029 if (regmap_raw_write(state->regmap[ADV76XX_PAGE_CP],
1030 0x77, offset_buf, 4))
1031 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__);
1032 }
1033
1034 static void adv76xx_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c)
1035 {
1036 struct adv76xx_state *state = to_state(sd);
1037 u8 gain_buf[4];
1038 u8 gain_man = 1;
1039 u8 agc_mode_man = 1;
1040
1041 if (auto_gain) {
1042 gain_man = 0;
1043 agc_mode_man = 0;
1044 gain_a = 0x100;
1045 gain_b = 0x100;
1046 gain_c = 0x100;
1047 }
1048
1049 v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n",
1050 __func__, auto_gain ? "Auto" : "Manual",
1051 gain_a, gain_b, gain_c);
1052
1053 gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4));
1054 gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6));
1055 gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8));
1056 gain_buf[3] = ((gain_c & 0x0ff));
1057
1058 /* Registers must be written in this order with no i2c access in between */
1059 if (regmap_raw_write(state->regmap[ADV76XX_PAGE_CP],
1060 0x73, gain_buf, 4))
1061 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__);
1062 }
1063
1064 static void set_rgb_quantization_range(struct v4l2_subdev *sd)
1065 {
1066 struct adv76xx_state *state = to_state(sd);
1067 bool rgb_output = io_read(sd, 0x02) & 0x02;
1068 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;
1069
1070 v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n",
1071 __func__, state->rgb_quantization_range,
1072 rgb_output, hdmi_signal);
1073
1074 adv76xx_set_gain(sd, true, 0x0, 0x0, 0x0);
1075 adv76xx_set_offset(sd, true, 0x0, 0x0, 0x0);
1076
1077 switch (state->rgb_quantization_range) {
1078 case V4L2_DV_RGB_RANGE_AUTO:
1079 if (state->selected_input == ADV7604_PAD_VGA_RGB) {
1080 /* Receiving analog RGB signal
1081 * Set RGB full range (0-255) */
1082 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
1083 break;
1084 }
1085
1086 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
1087 /* Receiving analog YPbPr signal
1088 * Set automode */
1089 io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
1090 break;
1091 }
1092
1093 if (hdmi_signal) {
1094 /* Receiving HDMI signal
1095 * Set automode */
1096 io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
1097 break;
1098 }
1099
1100 /* Receiving DVI-D signal
1101 * ADV7604 selects RGB limited range regardless of
1102 * input format (CE/IT) in automatic mode */
1103 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) {
1104 /* RGB limited range (16-235) */
1105 io_write_clr_set(sd, 0x02, 0xf0, 0x00);
1106 } else {
1107 /* RGB full range (0-255) */
1108 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
1109
1110 if (is_digital_input(sd) && rgb_output) {
1111 adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40);
1112 } else {
1113 adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1114 adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70);
1115 }
1116 }
1117 break;
1118 case V4L2_DV_RGB_RANGE_LIMITED:
1119 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
1120 /* YCrCb limited range (16-235) */
1121 io_write_clr_set(sd, 0x02, 0xf0, 0x20);
1122 break;
1123 }
1124
1125 /* RGB limited range (16-235) */
1126 io_write_clr_set(sd, 0x02, 0xf0, 0x00);
1127
1128 break;
1129 case V4L2_DV_RGB_RANGE_FULL:
1130 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
1131 /* YCrCb full range (0-255) */
1132 io_write_clr_set(sd, 0x02, 0xf0, 0x60);
1133 break;
1134 }
1135
1136 /* RGB full range (0-255) */
1137 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
1138
1139 if (is_analog_input(sd) || hdmi_signal)
1140 break;
1141
1142 /* Adjust gain/offset for DVI-D signals only */
1143 if (rgb_output) {
1144 adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40);
1145 } else {
1146 adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1147 adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70);
1148 }
1149 break;
1150 }
1151 }
1152
1153 static int adv76xx_s_ctrl(struct v4l2_ctrl *ctrl)
1154 {
1155 struct v4l2_subdev *sd =
1156 &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd;
1157
1158 struct adv76xx_state *state = to_state(sd);
1159
1160 switch (ctrl->id) {
1161 case V4L2_CID_BRIGHTNESS:
1162 cp_write(sd, 0x3c, ctrl->val);
1163 return 0;
1164 case V4L2_CID_CONTRAST:
1165 cp_write(sd, 0x3a, ctrl->val);
1166 return 0;
1167 case V4L2_CID_SATURATION:
1168 cp_write(sd, 0x3b, ctrl->val);
1169 return 0;
1170 case V4L2_CID_HUE:
1171 cp_write(sd, 0x3d, ctrl->val);
1172 return 0;
1173 case V4L2_CID_DV_RX_RGB_RANGE:
1174 state->rgb_quantization_range = ctrl->val;
1175 set_rgb_quantization_range(sd);
1176 return 0;
1177 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
1178 if (!adv76xx_has_afe(state))
1179 return -EINVAL;
1180 /* Set the analog sampling phase. This is needed to find the
1181 best sampling phase for analog video: an application or
1182 driver has to try a number of phases and analyze the picture
1183 quality before settling on the best performing phase. */
1184 afe_write(sd, 0xc8, ctrl->val);
1185 return 0;
1186 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
1187 /* Use the default blue color for free running mode,
1188 or supply your own. */
1189 cp_write_clr_set(sd, 0xbf, 0x04, ctrl->val << 2);
1190 return 0;
1191 case V4L2_CID_ADV_RX_FREE_RUN_COLOR:
1192 cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16);
1193 cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8);
1194 cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff));
1195 return 0;
1196 }
1197 return -EINVAL;
1198 }
1199
1200 static int adv76xx_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
1201 {
1202 struct v4l2_subdev *sd =
1203 &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd;
1204
1205 if (ctrl->id == V4L2_CID_DV_RX_IT_CONTENT_TYPE) {
1206 ctrl->val = V4L2_DV_IT_CONTENT_TYPE_NO_ITC;
1207 if ((io_read(sd, 0x60) & 1) && (infoframe_read(sd, 0x03) & 0x80))
1208 ctrl->val = (infoframe_read(sd, 0x05) >> 4) & 3;
1209 return 0;
1210 }
1211 return -EINVAL;
1212 }
1213
1214 /* ----------------------------------------------------------------------- */
1215
1216 static inline bool no_power(struct v4l2_subdev *sd)
1217 {
1218 /* Entire chip or CP powered off */
1219 return io_read(sd, 0x0c) & 0x24;
1220 }
1221
1222 static inline bool no_signal_tmds(struct v4l2_subdev *sd)
1223 {
1224 struct adv76xx_state *state = to_state(sd);
1225
1226 return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input));
1227 }
1228
1229 static inline bool no_lock_tmds(struct v4l2_subdev *sd)
1230 {
1231 struct adv76xx_state *state = to_state(sd);
1232 const struct adv76xx_chip_info *info = state->info;
1233
1234 return (io_read(sd, 0x6a) & info->tdms_lock_mask) != info->tdms_lock_mask;
1235 }
1236
1237 static inline bool is_hdmi(struct v4l2_subdev *sd)
1238 {
1239 return hdmi_read(sd, 0x05) & 0x80;
1240 }
1241
1242 static inline bool no_lock_sspd(struct v4l2_subdev *sd)
1243 {
1244 struct adv76xx_state *state = to_state(sd);
1245
1246 /*
1247 * Chips without a AFE don't expose registers for the SSPD, so just assume
1248 * that we have a lock.
1249 */
1250 if (adv76xx_has_afe(state))
1251 return false;
1252
1253 /* TODO channel 2 */
1254 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0);
1255 }
1256
1257 static inline bool no_lock_stdi(struct v4l2_subdev *sd)
1258 {
1259 /* TODO channel 2 */
1260 return !(cp_read(sd, 0xb1) & 0x80);
1261 }
1262
1263 static inline bool no_signal(struct v4l2_subdev *sd)
1264 {
1265 bool ret;
1266
1267 ret = no_power(sd);
1268
1269 ret |= no_lock_stdi(sd);
1270 ret |= no_lock_sspd(sd);
1271
1272 if (is_digital_input(sd)) {
1273 ret |= no_lock_tmds(sd);
1274 ret |= no_signal_tmds(sd);
1275 }
1276
1277 return ret;
1278 }
1279
1280 static inline bool no_lock_cp(struct v4l2_subdev *sd)
1281 {
1282 struct adv76xx_state *state = to_state(sd);
1283
1284 if (!adv76xx_has_afe(state))
1285 return false;
1286
1287 /* CP has detected a non standard number of lines on the incoming
1288 video compared to what it is configured to receive by s_dv_timings */
1289 return io_read(sd, 0x12) & 0x01;
1290 }
1291
1292 static inline bool in_free_run(struct v4l2_subdev *sd)
1293 {
1294 return cp_read(sd, 0xff) & 0x10;
1295 }
1296
1297 static int adv76xx_g_input_status(struct v4l2_subdev *sd, u32 *status)
1298 {
1299 *status = 0;
1300 *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0;
1301 *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
1302 if (!in_free_run(sd) && no_lock_cp(sd))
1303 *status |= is_digital_input(sd) ?
1304 V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK;
1305
1306 v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1307
1308 return 0;
1309 }
1310
1311 /* ----------------------------------------------------------------------- */
1312
1313 struct stdi_readback {
1314 u16 bl, lcf, lcvs;
1315 u8 hs_pol, vs_pol;
1316 bool interlaced;
1317 };
1318
1319 static int stdi2dv_timings(struct v4l2_subdev *sd,
1320 struct stdi_readback *stdi,
1321 struct v4l2_dv_timings *timings)
1322 {
1323 struct adv76xx_state *state = to_state(sd);
1324 u32 hfreq = (ADV76XX_FSC * 8) / stdi->bl;
1325 u32 pix_clk;
1326 int i;
1327
1328 for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) {
1329 const struct v4l2_bt_timings *bt = &v4l2_dv_timings_presets[i].bt;
1330
1331 if (!v4l2_valid_dv_timings(&v4l2_dv_timings_presets[i],
1332 adv76xx_get_dv_timings_cap(sd),
1333 adv76xx_check_dv_timings, NULL))
1334 continue;
1335 if (vtotal(bt) != stdi->lcf + 1)
1336 continue;
1337 if (bt->vsync != stdi->lcvs)
1338 continue;
1339
1340 pix_clk = hfreq * htotal(bt);
1341
1342 if ((pix_clk < bt->pixelclock + 1000000) &&
1343 (pix_clk > bt->pixelclock - 1000000)) {
1344 *timings = v4l2_dv_timings_presets[i];
1345 return 0;
1346 }
1347 }
1348
1349 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, 0,
1350 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1351 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1352 false, timings))
1353 return 0;
1354 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1355 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1356 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1357 false, state->aspect_ratio, timings))
1358 return 0;
1359
1360 v4l2_dbg(2, debug, sd,
1361 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1362 __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1363 stdi->hs_pol, stdi->vs_pol);
1364 return -1;
1365 }
1366
1367
1368 static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1369 {
1370 struct adv76xx_state *state = to_state(sd);
1371 const struct adv76xx_chip_info *info = state->info;
1372 u8 polarity;
1373
1374 if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1375 v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__);
1376 return -1;
1377 }
1378
1379 /* read STDI */
1380 stdi->bl = cp_read16(sd, 0xb1, 0x3fff);
1381 stdi->lcf = cp_read16(sd, info->lcf_reg, 0x7ff);
1382 stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1383 stdi->interlaced = io_read(sd, 0x12) & 0x10;
1384
1385 if (adv76xx_has_afe(state)) {
1386 /* read SSPD */
1387 polarity = cp_read(sd, 0xb5);
1388 if ((polarity & 0x03) == 0x01) {
1389 stdi->hs_pol = polarity & 0x10
1390 ? (polarity & 0x08 ? '+' : '-') : 'x';
1391 stdi->vs_pol = polarity & 0x40
1392 ? (polarity & 0x20 ? '+' : '-') : 'x';
1393 } else {
1394 stdi->hs_pol = 'x';
1395 stdi->vs_pol = 'x';
1396 }
1397 } else {
1398 polarity = hdmi_read(sd, 0x05);
1399 stdi->hs_pol = polarity & 0x20 ? '+' : '-';
1400 stdi->vs_pol = polarity & 0x10 ? '+' : '-';
1401 }
1402
1403 if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1404 v4l2_dbg(2, debug, sd,
1405 "%s: signal lost during readout of STDI/SSPD\n", __func__);
1406 return -1;
1407 }
1408
1409 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1410 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1411 memset(stdi, 0, sizeof(struct stdi_readback));
1412 return -1;
1413 }
1414
1415 v4l2_dbg(2, debug, sd,
1416 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1417 __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1418 stdi->hs_pol, stdi->vs_pol,
1419 stdi->interlaced ? "interlaced" : "progressive");
1420
1421 return 0;
1422 }
1423
1424 static int adv76xx_enum_dv_timings(struct v4l2_subdev *sd,
1425 struct v4l2_enum_dv_timings *timings)
1426 {
1427 struct adv76xx_state *state = to_state(sd);
1428
1429 if (timings->pad >= state->source_pad)
1430 return -EINVAL;
1431
1432 return v4l2_enum_dv_timings_cap(timings,
1433 adv76xx_get_dv_timings_cap(sd), adv76xx_check_dv_timings, NULL);
1434 }
1435
1436 static int adv76xx_dv_timings_cap(struct v4l2_subdev *sd,
1437 struct v4l2_dv_timings_cap *cap)
1438 {
1439 struct adv76xx_state *state = to_state(sd);
1440
1441 if (cap->pad >= state->source_pad)
1442 return -EINVAL;
1443
1444 *cap = *adv76xx_get_dv_timings_cap(sd);
1445 return 0;
1446 }
1447
1448 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
1449 if the format is listed in adv76xx_timings[] */
1450 static void adv76xx_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
1451 struct v4l2_dv_timings *timings)
1452 {
1453 v4l2_find_dv_timings_cap(timings, adv76xx_get_dv_timings_cap(sd),
1454 is_digital_input(sd) ? 250000 : 1000000,
1455 adv76xx_check_dv_timings, NULL);
1456 }
1457
1458 static unsigned int adv7604_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1459 {
1460 unsigned int freq;
1461 int a, b;
1462
1463 a = hdmi_read(sd, 0x06);
1464 b = hdmi_read(sd, 0x3b);
1465 if (a < 0 || b < 0)
1466 return 0;
1467 freq = a * 1000000 + ((b & 0x30) >> 4) * 250000;
1468
1469 if (is_hdmi(sd)) {
1470 /* adjust for deep color mode */
1471 unsigned bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8;
1472
1473 freq = freq * 8 / bits_per_channel;
1474 }
1475
1476 return freq;
1477 }
1478
1479 static unsigned int adv7611_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1480 {
1481 int a, b;
1482
1483 a = hdmi_read(sd, 0x51);
1484 b = hdmi_read(sd, 0x52);
1485 if (a < 0 || b < 0)
1486 return 0;
1487 return ((a << 1) | (b >> 7)) * 1000000 + (b & 0x7f) * 1000000 / 128;
1488 }
1489
1490 static int adv76xx_query_dv_timings(struct v4l2_subdev *sd,
1491 struct v4l2_dv_timings *timings)
1492 {
1493 struct adv76xx_state *state = to_state(sd);
1494 const struct adv76xx_chip_info *info = state->info;
1495 struct v4l2_bt_timings *bt = &timings->bt;
1496 struct stdi_readback stdi;
1497
1498 if (!timings)
1499 return -EINVAL;
1500
1501 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1502
1503 if (no_signal(sd)) {
1504 state->restart_stdi_once = true;
1505 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1506 return -ENOLINK;
1507 }
1508
1509 /* read STDI */
1510 if (read_stdi(sd, &stdi)) {
1511 v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__);
1512 return -ENOLINK;
1513 }
1514 bt->interlaced = stdi.interlaced ?
1515 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
1516
1517 if (is_digital_input(sd)) {
1518 timings->type = V4L2_DV_BT_656_1120;
1519
1520 bt->width = hdmi_read16(sd, 0x07, info->linewidth_mask);
1521 bt->height = hdmi_read16(sd, 0x09, info->field0_height_mask);
1522 bt->pixelclock = info->read_hdmi_pixelclock(sd);
1523 bt->hfrontporch = hdmi_read16(sd, 0x20, info->hfrontporch_mask);
1524 bt->hsync = hdmi_read16(sd, 0x22, info->hsync_mask);
1525 bt->hbackporch = hdmi_read16(sd, 0x24, info->hbackporch_mask);
1526 bt->vfrontporch = hdmi_read16(sd, 0x2a,
1527 info->field0_vfrontporch_mask) / 2;
1528 bt->vsync = hdmi_read16(sd, 0x2e, info->field0_vsync_mask) / 2;
1529 bt->vbackporch = hdmi_read16(sd, 0x32,
1530 info->field0_vbackporch_mask) / 2;
1531 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1532 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1533 if (bt->interlaced == V4L2_DV_INTERLACED) {
1534 bt->height += hdmi_read16(sd, 0x0b,
1535 info->field1_height_mask);
1536 bt->il_vfrontporch = hdmi_read16(sd, 0x2c,
1537 info->field1_vfrontporch_mask) / 2;
1538 bt->il_vsync = hdmi_read16(sd, 0x30,
1539 info->field1_vsync_mask) / 2;
1540 bt->il_vbackporch = hdmi_read16(sd, 0x34,
1541 info->field1_vbackporch_mask) / 2;
1542 }
1543 adv76xx_fill_optional_dv_timings_fields(sd, timings);
1544 } else {
1545 /* find format
1546 * Since LCVS values are inaccurate [REF_03, p. 275-276],
1547 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
1548 */
1549 if (!stdi2dv_timings(sd, &stdi, timings))
1550 goto found;
1551 stdi.lcvs += 1;
1552 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
1553 if (!stdi2dv_timings(sd, &stdi, timings))
1554 goto found;
1555 stdi.lcvs -= 2;
1556 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
1557 if (stdi2dv_timings(sd, &stdi, timings)) {
1558 /*
1559 * The STDI block may measure wrong values, especially
1560 * for lcvs and lcf. If the driver can not find any
1561 * valid timing, the STDI block is restarted to measure
1562 * the video timings again. The function will return an
1563 * error, but the restart of STDI will generate a new
1564 * STDI interrupt and the format detection process will
1565 * restart.
1566 */
1567 if (state->restart_stdi_once) {
1568 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
1569 /* TODO restart STDI for Sync Channel 2 */
1570 /* enter one-shot mode */
1571 cp_write_clr_set(sd, 0x86, 0x06, 0x00);
1572 /* trigger STDI restart */
1573 cp_write_clr_set(sd, 0x86, 0x06, 0x04);
1574 /* reset to continuous mode */
1575 cp_write_clr_set(sd, 0x86, 0x06, 0x02);
1576 state->restart_stdi_once = false;
1577 return -ENOLINK;
1578 }
1579 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1580 return -ERANGE;
1581 }
1582 state->restart_stdi_once = true;
1583 }
1584 found:
1585
1586 if (no_signal(sd)) {
1587 v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__);
1588 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1589 return -ENOLINK;
1590 }
1591
1592 if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
1593 (is_digital_input(sd) && bt->pixelclock > 225000000)) {
1594 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1595 __func__, (u32)bt->pixelclock);
1596 return -ERANGE;
1597 }
1598
1599 if (debug > 1)
1600 v4l2_print_dv_timings(sd->name, "adv76xx_query_dv_timings: ",
1601 timings, true);
1602
1603 return 0;
1604 }
1605
1606 static int adv76xx_s_dv_timings(struct v4l2_subdev *sd,
1607 struct v4l2_dv_timings *timings)
1608 {
1609 struct adv76xx_state *state = to_state(sd);
1610 struct v4l2_bt_timings *bt;
1611 int err;
1612
1613 if (!timings)
1614 return -EINVAL;
1615
1616 if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) {
1617 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1618 return 0;
1619 }
1620
1621 bt = &timings->bt;
1622
1623 if (!v4l2_valid_dv_timings(timings, adv76xx_get_dv_timings_cap(sd),
1624 adv76xx_check_dv_timings, NULL))
1625 return -ERANGE;
1626
1627 adv76xx_fill_optional_dv_timings_fields(sd, timings);
1628
1629 state->timings = *timings;
1630
1631 cp_write_clr_set(sd, 0x91, 0x40, bt->interlaced ? 0x40 : 0x00);
1632
1633 /* Use prim_mode and vid_std when available */
1634 err = configure_predefined_video_timings(sd, timings);
1635 if (err) {
1636 /* custom settings when the video format
1637 does not have prim_mode/vid_std */
1638 configure_custom_video_timings(sd, bt);
1639 }
1640
1641 set_rgb_quantization_range(sd);
1642
1643 if (debug > 1)
1644 v4l2_print_dv_timings(sd->name, "adv76xx_s_dv_timings: ",
1645 timings, true);
1646 return 0;
1647 }
1648
1649 static int adv76xx_g_dv_timings(struct v4l2_subdev *sd,
1650 struct v4l2_dv_timings *timings)
1651 {
1652 struct adv76xx_state *state = to_state(sd);
1653
1654 *timings = state->timings;
1655 return 0;
1656 }
1657
1658 static void adv7604_set_termination(struct v4l2_subdev *sd, bool enable)
1659 {
1660 hdmi_write(sd, 0x01, enable ? 0x00 : 0x78);
1661 }
1662
1663 static void adv7611_set_termination(struct v4l2_subdev *sd, bool enable)
1664 {
1665 hdmi_write(sd, 0x83, enable ? 0xfe : 0xff);
1666 }
1667
1668 static void enable_input(struct v4l2_subdev *sd)
1669 {
1670 struct adv76xx_state *state = to_state(sd);
1671
1672 if (is_analog_input(sd)) {
1673 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */
1674 } else if (is_digital_input(sd)) {
1675 hdmi_write_clr_set(sd, 0x00, 0x03, state->selected_input);
1676 state->info->set_termination(sd, true);
1677 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */
1678 hdmi_write_clr_set(sd, 0x1a, 0x10, 0x00); /* Unmute audio */
1679 } else {
1680 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1681 __func__, state->selected_input);
1682 }
1683 }
1684
1685 static void disable_input(struct v4l2_subdev *sd)
1686 {
1687 struct adv76xx_state *state = to_state(sd);
1688
1689 hdmi_write_clr_set(sd, 0x1a, 0x10, 0x10); /* Mute audio */
1690 msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 7.16.10] */
1691 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */
1692 state->info->set_termination(sd, false);
1693 }
1694
1695 static void select_input(struct v4l2_subdev *sd)
1696 {
1697 struct adv76xx_state *state = to_state(sd);
1698 const struct adv76xx_chip_info *info = state->info;
1699
1700 if (is_analog_input(sd)) {
1701 adv76xx_write_reg_seq(sd, info->recommended_settings[0]);
1702
1703 afe_write(sd, 0x00, 0x08); /* power up ADC */
1704 afe_write(sd, 0x01, 0x06); /* power up Analog Front End */
1705 afe_write(sd, 0xc8, 0x00); /* phase control */
1706 } else if (is_digital_input(sd)) {
1707 hdmi_write(sd, 0x00, state->selected_input & 0x03);
1708
1709 adv76xx_write_reg_seq(sd, info->recommended_settings[1]);
1710
1711 if (adv76xx_has_afe(state)) {
1712 afe_write(sd, 0x00, 0xff); /* power down ADC */
1713 afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */
1714 afe_write(sd, 0xc8, 0x40); /* phase control */
1715 }
1716
1717 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
1718 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1719 cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */
1720 } else {
1721 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1722 __func__, state->selected_input);
1723 }
1724 }
1725
1726 static int adv76xx_s_routing(struct v4l2_subdev *sd,
1727 u32 input, u32 output, u32 config)
1728 {
1729 struct adv76xx_state *state = to_state(sd);
1730
1731 v4l2_dbg(2, debug, sd, "%s: input %d, selected input %d",
1732 __func__, input, state->selected_input);
1733
1734 if (input == state->selected_input)
1735 return 0;
1736
1737 if (input > state->info->max_port)
1738 return -EINVAL;
1739
1740 state->selected_input = input;
1741
1742 disable_input(sd);
1743 select_input(sd);
1744 enable_input(sd);
1745
1746 v4l2_subdev_notify_event(sd, &adv76xx_ev_fmt);
1747
1748 return 0;
1749 }
1750
1751 static int adv76xx_enum_mbus_code(struct v4l2_subdev *sd,
1752 struct v4l2_subdev_pad_config *cfg,
1753 struct v4l2_subdev_mbus_code_enum *code)
1754 {
1755 struct adv76xx_state *state = to_state(sd);
1756
1757 if (code->index >= state->info->nformats)
1758 return -EINVAL;
1759
1760 code->code = state->info->formats[code->index].code;
1761
1762 return 0;
1763 }
1764
1765 static void adv76xx_fill_format(struct adv76xx_state *state,
1766 struct v4l2_mbus_framefmt *format)
1767 {
1768 memset(format, 0, sizeof(*format));
1769
1770 format->width = state->timings.bt.width;
1771 format->height = state->timings.bt.height;
1772 format->field = V4L2_FIELD_NONE;
1773 format->colorspace = V4L2_COLORSPACE_SRGB;
1774
1775 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO)
1776 format->colorspace = (state->timings.bt.height <= 576) ?
1777 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
1778 }
1779
1780 /*
1781 * Compute the op_ch_sel value required to obtain on the bus the component order
1782 * corresponding to the selected format taking into account bus reordering
1783 * applied by the board at the output of the device.
1784 *
1785 * The following table gives the op_ch_value from the format component order
1786 * (expressed as op_ch_sel value in column) and the bus reordering (expressed as
1787 * adv76xx_bus_order value in row).
1788 *
1789 * | GBR(0) GRB(1) BGR(2) RGB(3) BRG(4) RBG(5)
1790 * ----------+-------------------------------------------------
1791 * RGB (NOP) | GBR GRB BGR RGB BRG RBG
1792 * GRB (1-2) | BGR RGB GBR GRB RBG BRG
1793 * RBG (2-3) | GRB GBR BRG RBG BGR RGB
1794 * BGR (1-3) | RBG BRG RGB BGR GRB GBR
1795 * BRG (ROR) | BRG RBG GRB GBR RGB BGR
1796 * GBR (ROL) | RGB BGR RBG BRG GBR GRB
1797 */
1798 static unsigned int adv76xx_op_ch_sel(struct adv76xx_state *state)
1799 {
1800 #define _SEL(a,b,c,d,e,f) { \
1801 ADV76XX_OP_CH_SEL_##a, ADV76XX_OP_CH_SEL_##b, ADV76XX_OP_CH_SEL_##c, \
1802 ADV76XX_OP_CH_SEL_##d, ADV76XX_OP_CH_SEL_##e, ADV76XX_OP_CH_SEL_##f }
1803 #define _BUS(x) [ADV7604_BUS_ORDER_##x]
1804
1805 static const unsigned int op_ch_sel[6][6] = {
1806 _BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG),
1807 _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG),
1808 _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB),
1809 _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR),
1810 _BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR),
1811 _BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB),
1812 };
1813
1814 return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5];
1815 }
1816
1817 static void adv76xx_setup_format(struct adv76xx_state *state)
1818 {
1819 struct v4l2_subdev *sd = &state->sd;
1820
1821 io_write_clr_set(sd, 0x02, 0x02,
1822 state->format->rgb_out ? ADV76XX_RGB_OUT : 0);
1823 io_write(sd, 0x03, state->format->op_format_sel |
1824 state->pdata.op_format_mode_sel);
1825 io_write_clr_set(sd, 0x04, 0xe0, adv76xx_op_ch_sel(state));
1826 io_write_clr_set(sd, 0x05, 0x01,
1827 state->format->swap_cb_cr ? ADV76XX_OP_SWAP_CB_CR : 0);
1828 }
1829
1830 static int adv76xx_get_format(struct v4l2_subdev *sd,
1831 struct v4l2_subdev_pad_config *cfg,
1832 struct v4l2_subdev_format *format)
1833 {
1834 struct adv76xx_state *state = to_state(sd);
1835
1836 if (format->pad != state->source_pad)
1837 return -EINVAL;
1838
1839 adv76xx_fill_format(state, &format->format);
1840
1841 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1842 struct v4l2_mbus_framefmt *fmt;
1843
1844 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
1845 format->format.code = fmt->code;
1846 } else {
1847 format->format.code = state->format->code;
1848 }
1849
1850 return 0;
1851 }
1852
1853 static int adv76xx_get_selection(struct v4l2_subdev *sd,
1854 struct v4l2_subdev_pad_config *cfg,
1855 struct v4l2_subdev_selection *sel)
1856 {
1857 struct adv76xx_state *state = to_state(sd);
1858
1859 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
1860 return -EINVAL;
1861 /* Only CROP, CROP_DEFAULT and CROP_BOUNDS are supported */
1862 if (sel->target > V4L2_SEL_TGT_CROP_BOUNDS)
1863 return -EINVAL;
1864
1865 sel->r.left = 0;
1866 sel->r.top = 0;
1867 sel->r.width = state->timings.bt.width;
1868 sel->r.height = state->timings.bt.height;
1869
1870 return 0;
1871 }
1872
1873 static int adv76xx_set_format(struct v4l2_subdev *sd,
1874 struct v4l2_subdev_pad_config *cfg,
1875 struct v4l2_subdev_format *format)
1876 {
1877 struct adv76xx_state *state = to_state(sd);
1878 const struct adv76xx_format_info *info;
1879
1880 if (format->pad != state->source_pad)
1881 return -EINVAL;
1882
1883 info = adv76xx_format_info(state, format->format.code);
1884 if (info == NULL)
1885 info = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
1886
1887 adv76xx_fill_format(state, &format->format);
1888 format->format.code = info->code;
1889
1890 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1891 struct v4l2_mbus_framefmt *fmt;
1892
1893 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
1894 fmt->code = format->format.code;
1895 } else {
1896 state->format = info;
1897 adv76xx_setup_format(state);
1898 }
1899
1900 return 0;
1901 }
1902
1903 static int adv76xx_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
1904 {
1905 struct adv76xx_state *state = to_state(sd);
1906 const struct adv76xx_chip_info *info = state->info;
1907 const u8 irq_reg_0x43 = io_read(sd, 0x43);
1908 const u8 irq_reg_0x6b = io_read(sd, 0x6b);
1909 const u8 irq_reg_0x70 = io_read(sd, 0x70);
1910 u8 fmt_change_digital;
1911 u8 fmt_change;
1912 u8 tx_5v;
1913
1914 if (irq_reg_0x43)
1915 io_write(sd, 0x44, irq_reg_0x43);
1916 if (irq_reg_0x70)
1917 io_write(sd, 0x71, irq_reg_0x70);
1918 if (irq_reg_0x6b)
1919 io_write(sd, 0x6c, irq_reg_0x6b);
1920
1921 v4l2_dbg(2, debug, sd, "%s: ", __func__);
1922
1923 /* format change */
1924 fmt_change = irq_reg_0x43 & 0x98;
1925 fmt_change_digital = is_digital_input(sd)
1926 ? irq_reg_0x6b & info->fmt_change_digital_mask
1927 : 0;
1928
1929 if (fmt_change || fmt_change_digital) {
1930 v4l2_dbg(1, debug, sd,
1931 "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n",
1932 __func__, fmt_change, fmt_change_digital);
1933
1934 v4l2_subdev_notify_event(sd, &adv76xx_ev_fmt);
1935
1936 if (handled)
1937 *handled = true;
1938 }
1939 /* HDMI/DVI mode */
1940 if (irq_reg_0x6b & 0x01) {
1941 v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__,
1942 (io_read(sd, 0x6a) & 0x01) ? "HDMI" : "DVI");
1943 set_rgb_quantization_range(sd);
1944 if (handled)
1945 *handled = true;
1946 }
1947
1948 /* tx 5v detect */
1949 tx_5v = irq_reg_0x70 & info->cable_det_mask;
1950 if (tx_5v) {
1951 v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v);
1952 adv76xx_s_detect_tx_5v_ctrl(sd);
1953 if (handled)
1954 *handled = true;
1955 }
1956 return 0;
1957 }
1958
1959 static int adv76xx_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
1960 {
1961 struct adv76xx_state *state = to_state(sd);
1962 u8 *data = NULL;
1963
1964 memset(edid->reserved, 0, sizeof(edid->reserved));
1965
1966 switch (edid->pad) {
1967 case ADV76XX_PAD_HDMI_PORT_A:
1968 case ADV7604_PAD_HDMI_PORT_B:
1969 case ADV7604_PAD_HDMI_PORT_C:
1970 case ADV7604_PAD_HDMI_PORT_D:
1971 if (state->edid.present & (1 << edid->pad))
1972 data = state->edid.edid;
1973 break;
1974 default:
1975 return -EINVAL;
1976 }
1977
1978 if (edid->start_block == 0 && edid->blocks == 0) {
1979 edid->blocks = data ? state->edid.blocks : 0;
1980 return 0;
1981 }
1982
1983 if (data == NULL)
1984 return -ENODATA;
1985
1986 if (edid->start_block >= state->edid.blocks)
1987 return -EINVAL;
1988
1989 if (edid->start_block + edid->blocks > state->edid.blocks)
1990 edid->blocks = state->edid.blocks - edid->start_block;
1991
1992 memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128);
1993
1994 return 0;
1995 }
1996
1997 static int get_edid_spa_location(const u8 *edid)
1998 {
1999 u8 d;
2000
2001 if ((edid[0x7e] != 1) ||
2002 (edid[0x80] != 0x02) ||
2003 (edid[0x81] != 0x03)) {
2004 return -1;
2005 }
2006
2007 /* search Vendor Specific Data Block (tag 3) */
2008 d = edid[0x82] & 0x7f;
2009 if (d > 4) {
2010 int i = 0x84;
2011 int end = 0x80 + d;
2012
2013 do {
2014 u8 tag = edid[i] >> 5;
2015 u8 len = edid[i] & 0x1f;
2016
2017 if ((tag == 3) && (len >= 5))
2018 return i + 4;
2019 i += len + 1;
2020 } while (i < end);
2021 }
2022 return -1;
2023 }
2024
2025 static int adv76xx_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
2026 {
2027 struct adv76xx_state *state = to_state(sd);
2028 const struct adv76xx_chip_info *info = state->info;
2029 int spa_loc;
2030 int err;
2031 int i;
2032
2033 memset(edid->reserved, 0, sizeof(edid->reserved));
2034
2035 if (edid->pad > ADV7604_PAD_HDMI_PORT_D)
2036 return -EINVAL;
2037 if (edid->start_block != 0)
2038 return -EINVAL;
2039 if (edid->blocks == 0) {
2040 /* Disable hotplug and I2C access to EDID RAM from DDC port */
2041 state->edid.present &= ~(1 << edid->pad);
2042 adv76xx_set_hpd(state, state->edid.present);
2043 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
2044
2045 /* Fall back to a 16:9 aspect ratio */
2046 state->aspect_ratio.numerator = 16;
2047 state->aspect_ratio.denominator = 9;
2048
2049 if (!state->edid.present)
2050 state->edid.blocks = 0;
2051
2052 v4l2_dbg(2, debug, sd, "%s: clear EDID pad %d, edid.present = 0x%x\n",
2053 __func__, edid->pad, state->edid.present);
2054 return 0;
2055 }
2056 if (edid->blocks > 2) {
2057 edid->blocks = 2;
2058 return -E2BIG;
2059 }
2060
2061 v4l2_dbg(2, debug, sd, "%s: write EDID pad %d, edid.present = 0x%x\n",
2062 __func__, edid->pad, state->edid.present);
2063
2064 /* Disable hotplug and I2C access to EDID RAM from DDC port */
2065 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
2066 adv76xx_set_hpd(state, 0);
2067 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, 0x00);
2068
2069 spa_loc = get_edid_spa_location(edid->edid);
2070 if (spa_loc < 0)
2071 spa_loc = 0xc0; /* Default value [REF_02, p. 116] */
2072
2073 switch (edid->pad) {
2074 case ADV76XX_PAD_HDMI_PORT_A:
2075 state->spa_port_a[0] = edid->edid[spa_loc];
2076 state->spa_port_a[1] = edid->edid[spa_loc + 1];
2077 break;
2078 case ADV7604_PAD_HDMI_PORT_B:
2079 rep_write(sd, 0x70, edid->edid[spa_loc]);
2080 rep_write(sd, 0x71, edid->edid[spa_loc + 1]);
2081 break;
2082 case ADV7604_PAD_HDMI_PORT_C:
2083 rep_write(sd, 0x72, edid->edid[spa_loc]);
2084 rep_write(sd, 0x73, edid->edid[spa_loc + 1]);
2085 break;
2086 case ADV7604_PAD_HDMI_PORT_D:
2087 rep_write(sd, 0x74, edid->edid[spa_loc]);
2088 rep_write(sd, 0x75, edid->edid[spa_loc + 1]);
2089 break;
2090 default:
2091 return -EINVAL;
2092 }
2093
2094 if (info->type == ADV7604) {
2095 rep_write(sd, 0x76, spa_loc & 0xff);
2096 rep_write_clr_set(sd, 0x77, 0x40, (spa_loc & 0x100) >> 2);
2097 } else {
2098 /* ADV7612 Software Manual Rev. A, p. 15 */
2099 rep_write(sd, 0x70, spa_loc & 0xff);
2100 rep_write_clr_set(sd, 0x71, 0x01, (spa_loc & 0x100) >> 8);
2101 }
2102
2103 edid->edid[spa_loc] = state->spa_port_a[0];
2104 edid->edid[spa_loc + 1] = state->spa_port_a[1];
2105
2106 memcpy(state->edid.edid, edid->edid, 128 * edid->blocks);
2107 state->edid.blocks = edid->blocks;
2108 state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15],
2109 edid->edid[0x16]);
2110 state->edid.present |= 1 << edid->pad;
2111
2112 err = edid_write_block(sd, 128 * edid->blocks, state->edid.edid);
2113 if (err < 0) {
2114 v4l2_err(sd, "error %d writing edid pad %d\n", err, edid->pad);
2115 return err;
2116 }
2117
2118 /* adv76xx calculates the checksums and enables I2C access to internal
2119 EDID RAM from DDC port. */
2120 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
2121
2122 for (i = 0; i < 1000; i++) {
2123 if (rep_read(sd, info->edid_status_reg) & state->edid.present)
2124 break;
2125 mdelay(1);
2126 }
2127 if (i == 1000) {
2128 v4l2_err(sd, "error enabling edid (0x%x)\n", state->edid.present);
2129 return -EIO;
2130 }
2131
2132 /* enable hotplug after 100 ms */
2133 queue_delayed_work(state->work_queues,
2134 &state->delayed_work_enable_hotplug, HZ / 10);
2135 return 0;
2136 }
2137
2138 /*********** avi info frame CEA-861-E **************/
2139
2140 static const struct adv76xx_cfg_read_infoframe adv76xx_cri[] = {
2141 { "AVI", 0x01, 0xe0, 0x00 },
2142 { "Audio", 0x02, 0xe3, 0x1c },
2143 { "SDP", 0x04, 0xe6, 0x2a },
2144 { "Vendor", 0x10, 0xec, 0x54 }
2145 };
2146
2147 static int adv76xx_read_infoframe(struct v4l2_subdev *sd, int index,
2148 union hdmi_infoframe *frame)
2149 {
2150 uint8_t buffer[32];
2151 u8 len;
2152 int i;
2153
2154 if (!(io_read(sd, 0x60) & adv76xx_cri[index].present_mask)) {
2155 v4l2_info(sd, "%s infoframe not received\n",
2156 adv76xx_cri[index].desc);
2157 return -ENOENT;
2158 }
2159
2160 for (i = 0; i < 3; i++)
2161 buffer[i] = infoframe_read(sd,
2162 adv76xx_cri[index].head_addr + i);
2163
2164 len = buffer[2] + 1;
2165
2166 if (len + 3 > sizeof(buffer)) {
2167 v4l2_err(sd, "%s: invalid %s infoframe length %d\n", __func__,
2168 adv76xx_cri[index].desc, len);
2169 return -ENOENT;
2170 }
2171
2172 for (i = 0; i < len; i++)
2173 buffer[i + 3] = infoframe_read(sd,
2174 adv76xx_cri[index].payload_addr + i);
2175
2176 if (hdmi_infoframe_unpack(frame, buffer) < 0) {
2177 v4l2_err(sd, "%s: unpack of %s infoframe failed\n", __func__,
2178 adv76xx_cri[index].desc);
2179 return -ENOENT;
2180 }
2181 return 0;
2182 }
2183
2184 static void adv76xx_log_infoframes(struct v4l2_subdev *sd)
2185 {
2186 int i;
2187
2188 if (!is_hdmi(sd)) {
2189 v4l2_info(sd, "receive DVI-D signal, no infoframes\n");
2190 return;
2191 }
2192
2193 for (i = 0; i < ARRAY_SIZE(adv76xx_cri); i++) {
2194 union hdmi_infoframe frame;
2195 struct i2c_client *client = v4l2_get_subdevdata(sd);
2196
2197 if (adv76xx_read_infoframe(sd, i, &frame))
2198 return;
2199 hdmi_infoframe_log(KERN_INFO, &client->dev, &frame);
2200 }
2201 }
2202
2203 static int adv76xx_log_status(struct v4l2_subdev *sd)
2204 {
2205 struct adv76xx_state *state = to_state(sd);
2206 const struct adv76xx_chip_info *info = state->info;
2207 struct v4l2_dv_timings timings;
2208 struct stdi_readback stdi;
2209 u8 reg_io_0x02 = io_read(sd, 0x02);
2210 u8 edid_enabled;
2211 u8 cable_det;
2212
2213 static const char * const csc_coeff_sel_rb[16] = {
2214 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
2215 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
2216 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
2217 "reserved", "reserved", "reserved", "reserved", "manual"
2218 };
2219 static const char * const input_color_space_txt[16] = {
2220 "RGB limited range (16-235)", "RGB full range (0-255)",
2221 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
2222 "xvYCC Bt.601", "xvYCC Bt.709",
2223 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2224 "invalid", "invalid", "invalid", "invalid", "invalid",
2225 "invalid", "invalid", "automatic"
2226 };
2227 static const char * const hdmi_color_space_txt[16] = {
2228 "RGB limited range (16-235)", "RGB full range (0-255)",
2229 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
2230 "xvYCC Bt.601", "xvYCC Bt.709",
2231 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2232 "sYCC", "Adobe YCC 601", "AdobeRGB", "invalid", "invalid",
2233 "invalid", "invalid", "invalid"
2234 };
2235 static const char * const rgb_quantization_range_txt[] = {
2236 "Automatic",
2237 "RGB limited range (16-235)",
2238 "RGB full range (0-255)",
2239 };
2240 static const char * const deep_color_mode_txt[4] = {
2241 "8-bits per channel",
2242 "10-bits per channel",
2243 "12-bits per channel",
2244 "16-bits per channel (not supported)"
2245 };
2246
2247 v4l2_info(sd, "-----Chip status-----\n");
2248 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
2249 edid_enabled = rep_read(sd, info->edid_status_reg);
2250 v4l2_info(sd, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n",
2251 ((edid_enabled & 0x01) ? "Yes" : "No"),
2252 ((edid_enabled & 0x02) ? "Yes" : "No"),
2253 ((edid_enabled & 0x04) ? "Yes" : "No"),
2254 ((edid_enabled & 0x08) ? "Yes" : "No"));
2255 v4l2_info(sd, "CEC: %s\n", !!(cec_read(sd, 0x2a) & 0x01) ?
2256 "enabled" : "disabled");
2257
2258 v4l2_info(sd, "-----Signal status-----\n");
2259 cable_det = info->read_cable_det(sd);
2260 v4l2_info(sd, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n",
2261 ((cable_det & 0x01) ? "Yes" : "No"),
2262 ((cable_det & 0x02) ? "Yes" : "No"),
2263 ((cable_det & 0x04) ? "Yes" : "No"),
2264 ((cable_det & 0x08) ? "Yes" : "No"));
2265 v4l2_info(sd, "TMDS signal detected: %s\n",
2266 no_signal_tmds(sd) ? "false" : "true");
2267 v4l2_info(sd, "TMDS signal locked: %s\n",
2268 no_lock_tmds(sd) ? "false" : "true");
2269 v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true");
2270 v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true");
2271 v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true");
2272 v4l2_info(sd, "CP free run: %s\n",
2273 (in_free_run(sd)) ? "on" : "off");
2274 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
2275 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
2276 (io_read(sd, 0x01) & 0x70) >> 4);
2277
2278 v4l2_info(sd, "-----Video Timings-----\n");
2279 if (read_stdi(sd, &stdi))
2280 v4l2_info(sd, "STDI: not locked\n");
2281 else
2282 v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n",
2283 stdi.lcf, stdi.bl, stdi.lcvs,
2284 stdi.interlaced ? "interlaced" : "progressive",
2285 stdi.hs_pol, stdi.vs_pol);
2286 if (adv76xx_query_dv_timings(sd, &timings))
2287 v4l2_info(sd, "No video detected\n");
2288 else
2289 v4l2_print_dv_timings(sd->name, "Detected format: ",
2290 &timings, true);
2291 v4l2_print_dv_timings(sd->name, "Configured format: ",
2292 &state->timings, true);
2293
2294 if (no_signal(sd))
2295 return 0;
2296
2297 v4l2_info(sd, "-----Color space-----\n");
2298 v4l2_info(sd, "RGB quantization range ctrl: %s\n",
2299 rgb_quantization_range_txt[state->rgb_quantization_range]);
2300 v4l2_info(sd, "Input color space: %s\n",
2301 input_color_space_txt[reg_io_0x02 >> 4]);
2302 v4l2_info(sd, "Output color space: %s %s, saturator %s, alt-gamma %s\n",
2303 (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
2304 (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)",
2305 (((reg_io_0x02 >> 2) & 0x01) ^ (reg_io_0x02 & 0x01)) ?
2306 "enabled" : "disabled",
2307 (reg_io_0x02 & 0x08) ? "enabled" : "disabled");
2308 v4l2_info(sd, "Color space conversion: %s\n",
2309 csc_coeff_sel_rb[cp_read(sd, info->cp_csc) >> 4]);
2310
2311 if (!is_digital_input(sd))
2312 return 0;
2313
2314 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
2315 v4l2_info(sd, "Digital video port selected: %c\n",
2316 (hdmi_read(sd, 0x00) & 0x03) + 'A');
2317 v4l2_info(sd, "HDCP encrypted content: %s\n",
2318 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
2319 v4l2_info(sd, "HDCP keys read: %s%s\n",
2320 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
2321 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
2322 if (is_hdmi(sd)) {
2323 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
2324 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
2325 bool audio_mute = io_read(sd, 0x65) & 0x40;
2326
2327 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
2328 audio_pll_locked ? "locked" : "not locked",
2329 audio_sample_packet_detect ? "detected" : "not detected",
2330 audio_mute ? "muted" : "enabled");
2331 if (audio_pll_locked && audio_sample_packet_detect) {
2332 v4l2_info(sd, "Audio format: %s\n",
2333 (hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo");
2334 }
2335 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
2336 (hdmi_read(sd, 0x5c) << 8) +
2337 (hdmi_read(sd, 0x5d) & 0xf0));
2338 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
2339 (hdmi_read(sd, 0x5e) << 8) +
2340 hdmi_read(sd, 0x5f));
2341 v4l2_info(sd, "AV Mute: %s\n", (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
2342
2343 v4l2_info(sd, "Deep color mode: %s\n", deep_color_mode_txt[(hdmi_read(sd, 0x0b) & 0x60) >> 5]);
2344 v4l2_info(sd, "HDMI colorspace: %s\n", hdmi_color_space_txt[hdmi_read(sd, 0x53) & 0xf]);
2345
2346 adv76xx_log_infoframes(sd);
2347 }
2348
2349 return 0;
2350 }
2351
2352 static int adv76xx_subscribe_event(struct v4l2_subdev *sd,
2353 struct v4l2_fh *fh,
2354 struct v4l2_event_subscription *sub)
2355 {
2356 switch (sub->type) {
2357 case V4L2_EVENT_SOURCE_CHANGE:
2358 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
2359 case V4L2_EVENT_CTRL:
2360 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
2361 default:
2362 return -EINVAL;
2363 }
2364 }
2365
2366 /* ----------------------------------------------------------------------- */
2367
2368 static const struct v4l2_ctrl_ops adv76xx_ctrl_ops = {
2369 .s_ctrl = adv76xx_s_ctrl,
2370 .g_volatile_ctrl = adv76xx_g_volatile_ctrl,
2371 };
2372
2373 static const struct v4l2_subdev_core_ops adv76xx_core_ops = {
2374 .log_status = adv76xx_log_status,
2375 .interrupt_service_routine = adv76xx_isr,
2376 .subscribe_event = adv76xx_subscribe_event,
2377 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
2378 #ifdef CONFIG_VIDEO_ADV_DEBUG
2379 .g_register = adv76xx_g_register,
2380 .s_register = adv76xx_s_register,
2381 #endif
2382 };
2383
2384 static const struct v4l2_subdev_video_ops adv76xx_video_ops = {
2385 .s_routing = adv76xx_s_routing,
2386 .g_input_status = adv76xx_g_input_status,
2387 .s_dv_timings = adv76xx_s_dv_timings,
2388 .g_dv_timings = adv76xx_g_dv_timings,
2389 .query_dv_timings = adv76xx_query_dv_timings,
2390 };
2391
2392 static const struct v4l2_subdev_pad_ops adv76xx_pad_ops = {
2393 .enum_mbus_code = adv76xx_enum_mbus_code,
2394 .get_selection = adv76xx_get_selection,
2395 .get_fmt = adv76xx_get_format,
2396 .set_fmt = adv76xx_set_format,
2397 .get_edid = adv76xx_get_edid,
2398 .set_edid = adv76xx_set_edid,
2399 .dv_timings_cap = adv76xx_dv_timings_cap,
2400 .enum_dv_timings = adv76xx_enum_dv_timings,
2401 };
2402
2403 static const struct v4l2_subdev_ops adv76xx_ops = {
2404 .core = &adv76xx_core_ops,
2405 .video = &adv76xx_video_ops,
2406 .pad = &adv76xx_pad_ops,
2407 };
2408
2409 /* -------------------------- custom ctrls ---------------------------------- */
2410
2411 static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = {
2412 .ops = &adv76xx_ctrl_ops,
2413 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
2414 .name = "Analog Sampling Phase",
2415 .type = V4L2_CTRL_TYPE_INTEGER,
2416 .min = 0,
2417 .max = 0x1f,
2418 .step = 1,
2419 .def = 0,
2420 };
2421
2422 static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color_manual = {
2423 .ops = &adv76xx_ctrl_ops,
2424 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
2425 .name = "Free Running Color, Manual",
2426 .type = V4L2_CTRL_TYPE_BOOLEAN,
2427 .min = false,
2428 .max = true,
2429 .step = 1,
2430 .def = false,
2431 };
2432
2433 static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color = {
2434 .ops = &adv76xx_ctrl_ops,
2435 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
2436 .name = "Free Running Color",
2437 .type = V4L2_CTRL_TYPE_INTEGER,
2438 .min = 0x0,
2439 .max = 0xffffff,
2440 .step = 0x1,
2441 .def = 0x0,
2442 };
2443
2444 /* ----------------------------------------------------------------------- */
2445
2446 static int adv76xx_core_init(struct v4l2_subdev *sd)
2447 {
2448 struct adv76xx_state *state = to_state(sd);
2449 const struct adv76xx_chip_info *info = state->info;
2450 struct adv76xx_platform_data *pdata = &state->pdata;
2451
2452 hdmi_write(sd, 0x48,
2453 (pdata->disable_pwrdnb ? 0x80 : 0) |
2454 (pdata->disable_cable_det_rst ? 0x40 : 0));
2455
2456 disable_input(sd);
2457
2458 if (pdata->default_input >= 0 &&
2459 pdata->default_input < state->source_pad) {
2460 state->selected_input = pdata->default_input;
2461 select_input(sd);
2462 enable_input(sd);
2463 }
2464
2465 /* power */
2466 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */
2467 io_write(sd, 0x0b, 0x44); /* Power down ESDP block */
2468 cp_write(sd, 0xcf, 0x01); /* Power down macrovision */
2469
2470 /* video format */
2471 io_write_clr_set(sd, 0x02, 0x0f,
2472 pdata->alt_gamma << 3 |
2473 pdata->op_656_range << 2 |
2474 pdata->alt_data_sat << 0);
2475 io_write_clr_set(sd, 0x05, 0x0e, pdata->blank_data << 3 |
2476 pdata->insert_av_codes << 2 |
2477 pdata->replicate_av_codes << 1);
2478 adv76xx_setup_format(state);
2479
2480 cp_write(sd, 0x69, 0x30); /* Enable CP CSC */
2481
2482 /* VS, HS polarities */
2483 io_write(sd, 0x06, 0xa0 | pdata->inv_vs_pol << 2 |
2484 pdata->inv_hs_pol << 1 | pdata->inv_llc_pol);
2485
2486 /* Adjust drive strength */
2487 io_write(sd, 0x14, 0x40 | pdata->dr_str_data << 4 |
2488 pdata->dr_str_clk << 2 |
2489 pdata->dr_str_sync);
2490
2491 cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */
2492 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
2493 cp_write(sd, 0xf9, 0x23); /* STDI ch. 1 - LCVS change threshold -
2494 ADI recommended setting [REF_01, c. 2.3.3] */
2495 cp_write(sd, 0x45, 0x23); /* STDI ch. 2 - LCVS change threshold -
2496 ADI recommended setting [REF_01, c. 2.3.3] */
2497 cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution
2498 for digital formats */
2499
2500 /* HDMI audio */
2501 hdmi_write_clr_set(sd, 0x15, 0x03, 0x03); /* Mute on FIFO over-/underflow [REF_01, c. 1.2.18] */
2502 hdmi_write_clr_set(sd, 0x1a, 0x0e, 0x08); /* Wait 1 s before unmute */
2503 hdmi_write_clr_set(sd, 0x68, 0x06, 0x06); /* FIFO reset on over-/underflow [REF_01, c. 1.2.19] */
2504
2505 /* TODO from platform data */
2506 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */
2507
2508 if (adv76xx_has_afe(state)) {
2509 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
2510 io_write_clr_set(sd, 0x30, 1 << 4, pdata->output_bus_lsb_to_msb << 4);
2511 }
2512
2513 /* interrupts */
2514 io_write(sd, 0x40, 0xc0 | pdata->int1_config); /* Configure INT1 */
2515 io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */
2516 io_write(sd, 0x6e, info->fmt_change_digital_mask); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
2517 io_write(sd, 0x73, info->cable_det_mask); /* Enable cable detection (+5v) interrupts */
2518 info->setup_irqs(sd);
2519
2520 return v4l2_ctrl_handler_setup(sd->ctrl_handler);
2521 }
2522
2523 static void adv7604_setup_irqs(struct v4l2_subdev *sd)
2524 {
2525 io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */
2526 }
2527
2528 static void adv7611_setup_irqs(struct v4l2_subdev *sd)
2529 {
2530 io_write(sd, 0x41, 0xd0); /* STDI irq for any change, disable INT2 */
2531 }
2532
2533 static void adv7612_setup_irqs(struct v4l2_subdev *sd)
2534 {
2535 io_write(sd, 0x41, 0xd0); /* disable INT2 */
2536 }
2537
2538 static void adv76xx_unregister_clients(struct adv76xx_state *state)
2539 {
2540 unsigned int i;
2541
2542 for (i = 1; i < ARRAY_SIZE(state->i2c_clients); ++i) {
2543 if (state->i2c_clients[i])
2544 i2c_unregister_device(state->i2c_clients[i]);
2545 }
2546 }
2547
2548 static struct i2c_client *adv76xx_dummy_client(struct v4l2_subdev *sd,
2549 u8 addr, u8 io_reg)
2550 {
2551 struct i2c_client *client = v4l2_get_subdevdata(sd);
2552
2553 if (addr)
2554 io_write(sd, io_reg, addr << 1);
2555 return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1);
2556 }
2557
2558 static const struct adv76xx_reg_seq adv7604_recommended_settings_afe[] = {
2559 /* reset ADI recommended settings for HDMI: */
2560 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
2561 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
2562 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
2563 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x00 }, /* DDC bus active pull-up control */
2564 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x74 }, /* TMDS PLL optimization */
2565 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
2566 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0x74 }, /* TMDS PLL optimization */
2567 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x63 }, /* TMDS PLL optimization */
2568 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
2569 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
2570 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x88 }, /* equaliser */
2571 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2e }, /* equaliser */
2572 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x00 }, /* enable automatic EQ changing */
2573
2574 /* set ADI recommended settings for digitizer */
2575 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
2576 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0x7b }, /* ADC noise shaping filter controls */
2577 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x1f }, /* CP core gain controls */
2578 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x3e), 0x04 }, /* CP core pre-gain control */
2579 { ADV76XX_REG(ADV76XX_PAGE_CP, 0xc3), 0x39 }, /* CP coast control. Graphics mode */
2580 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x40), 0x5c }, /* CP core pre-gain control. Graphics mode */
2581
2582 { ADV76XX_REG_SEQ_TERM, 0 },
2583 };
2584
2585 static const struct adv76xx_reg_seq adv7604_recommended_settings_hdmi[] = {
2586 /* set ADI recommended settings for HDMI: */
2587 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
2588 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x84 }, /* HDMI filter optimization */
2589 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x10 }, /* DDC bus active pull-up control */
2590 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x39 }, /* TMDS PLL optimization */
2591 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
2592 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xb6 }, /* TMDS PLL optimization */
2593 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x03 }, /* TMDS PLL optimization */
2594 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
2595 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
2596 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x8b }, /* equaliser */
2597 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2d }, /* equaliser */
2598 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x01 }, /* enable automatic EQ changing */
2599
2600 /* reset ADI recommended settings for digitizer */
2601 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
2602 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0xfb }, /* ADC noise shaping filter controls */
2603 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x0d }, /* CP core gain controls */
2604
2605 { ADV76XX_REG_SEQ_TERM, 0 },
2606 };
2607
2608 static const struct adv76xx_reg_seq adv7611_recommended_settings_hdmi[] = {
2609 /* ADV7611 Register Settings Recommendations Rev 1.5, May 2014 */
2610 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 },
2611 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 },
2612 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 },
2613 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f },
2614 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 },
2615 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda },
2616 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 },
2617 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 },
2618 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 },
2619 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x04 },
2620 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x1e },
2621
2622 { ADV76XX_REG_SEQ_TERM, 0 },
2623 };
2624
2625 static const struct adv76xx_reg_seq adv7612_recommended_settings_hdmi[] = {
2626 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 },
2627 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 },
2628 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 },
2629 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f },
2630 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 },
2631 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda },
2632 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 },
2633 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 },
2634 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 },
2635 { ADV76XX_REG_SEQ_TERM, 0 },
2636 };
2637
2638 static const struct adv76xx_chip_info adv76xx_chip_info[] = {
2639 [ADV7604] = {
2640 .type = ADV7604,
2641 .has_afe = true,
2642 .max_port = ADV7604_PAD_VGA_COMP,
2643 .num_dv_ports = 4,
2644 .edid_enable_reg = 0x77,
2645 .edid_status_reg = 0x7d,
2646 .lcf_reg = 0xb3,
2647 .tdms_lock_mask = 0xe0,
2648 .cable_det_mask = 0x1e,
2649 .fmt_change_digital_mask = 0xc1,
2650 .cp_csc = 0xfc,
2651 .formats = adv7604_formats,
2652 .nformats = ARRAY_SIZE(adv7604_formats),
2653 .set_termination = adv7604_set_termination,
2654 .setup_irqs = adv7604_setup_irqs,
2655 .read_hdmi_pixelclock = adv7604_read_hdmi_pixelclock,
2656 .read_cable_det = adv7604_read_cable_det,
2657 .recommended_settings = {
2658 [0] = adv7604_recommended_settings_afe,
2659 [1] = adv7604_recommended_settings_hdmi,
2660 },
2661 .num_recommended_settings = {
2662 [0] = ARRAY_SIZE(adv7604_recommended_settings_afe),
2663 [1] = ARRAY_SIZE(adv7604_recommended_settings_hdmi),
2664 },
2665 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV7604_PAGE_AVLINK) |
2666 BIT(ADV76XX_PAGE_CEC) | BIT(ADV76XX_PAGE_INFOFRAME) |
2667 BIT(ADV7604_PAGE_ESDP) | BIT(ADV7604_PAGE_DPP) |
2668 BIT(ADV76XX_PAGE_AFE) | BIT(ADV76XX_PAGE_REP) |
2669 BIT(ADV76XX_PAGE_EDID) | BIT(ADV76XX_PAGE_HDMI) |
2670 BIT(ADV76XX_PAGE_TEST) | BIT(ADV76XX_PAGE_CP) |
2671 BIT(ADV7604_PAGE_VDP),
2672 .linewidth_mask = 0xfff,
2673 .field0_height_mask = 0xfff,
2674 .field1_height_mask = 0xfff,
2675 .hfrontporch_mask = 0x3ff,
2676 .hsync_mask = 0x3ff,
2677 .hbackporch_mask = 0x3ff,
2678 .field0_vfrontporch_mask = 0x1fff,
2679 .field0_vsync_mask = 0x1fff,
2680 .field0_vbackporch_mask = 0x1fff,
2681 .field1_vfrontporch_mask = 0x1fff,
2682 .field1_vsync_mask = 0x1fff,
2683 .field1_vbackporch_mask = 0x1fff,
2684 },
2685 [ADV7611] = {
2686 .type = ADV7611,
2687 .has_afe = false,
2688 .max_port = ADV76XX_PAD_HDMI_PORT_A,
2689 .num_dv_ports = 1,
2690 .edid_enable_reg = 0x74,
2691 .edid_status_reg = 0x76,
2692 .lcf_reg = 0xa3,
2693 .tdms_lock_mask = 0x43,
2694 .cable_det_mask = 0x01,
2695 .fmt_change_digital_mask = 0x03,
2696 .cp_csc = 0xf4,
2697 .formats = adv7611_formats,
2698 .nformats = ARRAY_SIZE(adv7611_formats),
2699 .set_termination = adv7611_set_termination,
2700 .setup_irqs = adv7611_setup_irqs,
2701 .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock,
2702 .read_cable_det = adv7611_read_cable_det,
2703 .recommended_settings = {
2704 [1] = adv7611_recommended_settings_hdmi,
2705 },
2706 .num_recommended_settings = {
2707 [1] = ARRAY_SIZE(adv7611_recommended_settings_hdmi),
2708 },
2709 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) |
2710 BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) |
2711 BIT(ADV76XX_PAGE_REP) | BIT(ADV76XX_PAGE_EDID) |
2712 BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP),
2713 .linewidth_mask = 0x1fff,
2714 .field0_height_mask = 0x1fff,
2715 .field1_height_mask = 0x1fff,
2716 .hfrontporch_mask = 0x1fff,
2717 .hsync_mask = 0x1fff,
2718 .hbackporch_mask = 0x1fff,
2719 .field0_vfrontporch_mask = 0x3fff,
2720 .field0_vsync_mask = 0x3fff,
2721 .field0_vbackporch_mask = 0x3fff,
2722 .field1_vfrontporch_mask = 0x3fff,
2723 .field1_vsync_mask = 0x3fff,
2724 .field1_vbackporch_mask = 0x3fff,
2725 },
2726 [ADV7612] = {
2727 .type = ADV7612,
2728 .has_afe = false,
2729 .max_port = ADV76XX_PAD_HDMI_PORT_A, /* B not supported */
2730 .num_dv_ports = 1, /* normally 2 */
2731 .edid_enable_reg = 0x74,
2732 .edid_status_reg = 0x76,
2733 .lcf_reg = 0xa3,
2734 .tdms_lock_mask = 0x43,
2735 .cable_det_mask = 0x01,
2736 .fmt_change_digital_mask = 0x03,
2737 .cp_csc = 0xf4,
2738 .formats = adv7612_formats,
2739 .nformats = ARRAY_SIZE(adv7612_formats),
2740 .set_termination = adv7611_set_termination,
2741 .setup_irqs = adv7612_setup_irqs,
2742 .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock,
2743 .read_cable_det = adv7612_read_cable_det,
2744 .recommended_settings = {
2745 [1] = adv7612_recommended_settings_hdmi,
2746 },
2747 .num_recommended_settings = {
2748 [1] = ARRAY_SIZE(adv7612_recommended_settings_hdmi),
2749 },
2750 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) |
2751 BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) |
2752 BIT(ADV76XX_PAGE_REP) | BIT(ADV76XX_PAGE_EDID) |
2753 BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP),
2754 .linewidth_mask = 0x1fff,
2755 .field0_height_mask = 0x1fff,
2756 .field1_height_mask = 0x1fff,
2757 .hfrontporch_mask = 0x1fff,
2758 .hsync_mask = 0x1fff,
2759 .hbackporch_mask = 0x1fff,
2760 .field0_vfrontporch_mask = 0x3fff,
2761 .field0_vsync_mask = 0x3fff,
2762 .field0_vbackporch_mask = 0x3fff,
2763 .field1_vfrontporch_mask = 0x3fff,
2764 .field1_vsync_mask = 0x3fff,
2765 .field1_vbackporch_mask = 0x3fff,
2766 },
2767 };
2768
2769 static const struct i2c_device_id adv76xx_i2c_id[] = {
2770 { "adv7604", (kernel_ulong_t)&adv76xx_chip_info[ADV7604] },
2771 { "adv7611", (kernel_ulong_t)&adv76xx_chip_info[ADV7611] },
2772 { "adv7612", (kernel_ulong_t)&adv76xx_chip_info[ADV7612] },
2773 { }
2774 };
2775 MODULE_DEVICE_TABLE(i2c, adv76xx_i2c_id);
2776
2777 static const struct of_device_id adv76xx_of_id[] __maybe_unused = {
2778 { .compatible = "adi,adv7611", .data = &adv76xx_chip_info[ADV7611] },
2779 { .compatible = "adi,adv7612", .data = &adv76xx_chip_info[ADV7612] },
2780 { }
2781 };
2782 MODULE_DEVICE_TABLE(of, adv76xx_of_id);
2783
2784 static int adv76xx_parse_dt(struct adv76xx_state *state)
2785 {
2786 struct v4l2_of_endpoint bus_cfg;
2787 struct device_node *endpoint;
2788 struct device_node *np;
2789 unsigned int flags;
2790 int ret;
2791 u32 v;
2792
2793 np = state->i2c_clients[ADV76XX_PAGE_IO]->dev.of_node;
2794
2795 /* Parse the endpoint. */
2796 endpoint = of_graph_get_next_endpoint(np, NULL);
2797 if (!endpoint)
2798 return -EINVAL;
2799
2800 ret = v4l2_of_parse_endpoint(endpoint, &bus_cfg);
2801 if (ret) {
2802 of_node_put(endpoint);
2803 return ret;
2804 }
2805
2806 if (!of_property_read_u32(endpoint, "default-input", &v))
2807 state->pdata.default_input = v;
2808 else
2809 state->pdata.default_input = -1;
2810
2811 of_node_put(endpoint);
2812
2813 flags = bus_cfg.bus.parallel.flags;
2814
2815 if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
2816 state->pdata.inv_hs_pol = 1;
2817
2818 if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
2819 state->pdata.inv_vs_pol = 1;
2820
2821 if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
2822 state->pdata.inv_llc_pol = 1;
2823
2824 if (bus_cfg.bus_type == V4L2_MBUS_BT656) {
2825 state->pdata.insert_av_codes = 1;
2826 state->pdata.op_656_range = 1;
2827 }
2828
2829 /* Disable the interrupt for now as no DT-based board uses it. */
2830 state->pdata.int1_config = ADV76XX_INT1_CONFIG_DISABLED;
2831
2832 /* Use the default I2C addresses. */
2833 state->pdata.i2c_addresses[ADV7604_PAGE_AVLINK] = 0x42;
2834 state->pdata.i2c_addresses[ADV76XX_PAGE_CEC] = 0x40;
2835 state->pdata.i2c_addresses[ADV76XX_PAGE_INFOFRAME] = 0x3e;
2836 state->pdata.i2c_addresses[ADV7604_PAGE_ESDP] = 0x38;
2837 state->pdata.i2c_addresses[ADV7604_PAGE_DPP] = 0x3c;
2838 state->pdata.i2c_addresses[ADV76XX_PAGE_AFE] = 0x26;
2839 state->pdata.i2c_addresses[ADV76XX_PAGE_REP] = 0x32;
2840 state->pdata.i2c_addresses[ADV76XX_PAGE_EDID] = 0x36;
2841 state->pdata.i2c_addresses[ADV76XX_PAGE_HDMI] = 0x34;
2842 state->pdata.i2c_addresses[ADV76XX_PAGE_TEST] = 0x30;
2843 state->pdata.i2c_addresses[ADV76XX_PAGE_CP] = 0x22;
2844 state->pdata.i2c_addresses[ADV7604_PAGE_VDP] = 0x24;
2845
2846 /* Hardcode the remaining platform data fields. */
2847 state->pdata.disable_pwrdnb = 0;
2848 state->pdata.disable_cable_det_rst = 0;
2849 state->pdata.blank_data = 1;
2850 state->pdata.alt_data_sat = 1;
2851 state->pdata.op_format_mode_sel = ADV7604_OP_FORMAT_MODE0;
2852 state->pdata.bus_order = ADV7604_BUS_ORDER_RGB;
2853
2854 return 0;
2855 }
2856
2857 static const struct regmap_config adv76xx_regmap_cnf[] = {
2858 {
2859 .name = "io",
2860 .reg_bits = 8,
2861 .val_bits = 8,
2862
2863 .max_register = 0xff,
2864 .cache_type = REGCACHE_NONE,
2865 },
2866 {
2867 .name = "avlink",
2868 .reg_bits = 8,
2869 .val_bits = 8,
2870
2871 .max_register = 0xff,
2872 .cache_type = REGCACHE_NONE,
2873 },
2874 {
2875 .name = "cec",
2876 .reg_bits = 8,
2877 .val_bits = 8,
2878
2879 .max_register = 0xff,
2880 .cache_type = REGCACHE_NONE,
2881 },
2882 {
2883 .name = "infoframe",
2884 .reg_bits = 8,
2885 .val_bits = 8,
2886
2887 .max_register = 0xff,
2888 .cache_type = REGCACHE_NONE,
2889 },
2890 {
2891 .name = "esdp",
2892 .reg_bits = 8,
2893 .val_bits = 8,
2894
2895 .max_register = 0xff,
2896 .cache_type = REGCACHE_NONE,
2897 },
2898 {
2899 .name = "epp",
2900 .reg_bits = 8,
2901 .val_bits = 8,
2902
2903 .max_register = 0xff,
2904 .cache_type = REGCACHE_NONE,
2905 },
2906 {
2907 .name = "afe",
2908 .reg_bits = 8,
2909 .val_bits = 8,
2910
2911 .max_register = 0xff,
2912 .cache_type = REGCACHE_NONE,
2913 },
2914 {
2915 .name = "rep",
2916 .reg_bits = 8,
2917 .val_bits = 8,
2918
2919 .max_register = 0xff,
2920 .cache_type = REGCACHE_NONE,
2921 },
2922 {
2923 .name = "edid",
2924 .reg_bits = 8,
2925 .val_bits = 8,
2926
2927 .max_register = 0xff,
2928 .cache_type = REGCACHE_NONE,
2929 },
2930
2931 {
2932 .name = "hdmi",
2933 .reg_bits = 8,
2934 .val_bits = 8,
2935
2936 .max_register = 0xff,
2937 .cache_type = REGCACHE_NONE,
2938 },
2939 {
2940 .name = "test",
2941 .reg_bits = 8,
2942 .val_bits = 8,
2943
2944 .max_register = 0xff,
2945 .cache_type = REGCACHE_NONE,
2946 },
2947 {
2948 .name = "cp",
2949 .reg_bits = 8,
2950 .val_bits = 8,
2951
2952 .max_register = 0xff,
2953 .cache_type = REGCACHE_NONE,
2954 },
2955 {
2956 .name = "vdp",
2957 .reg_bits = 8,
2958 .val_bits = 8,
2959
2960 .max_register = 0xff,
2961 .cache_type = REGCACHE_NONE,
2962 },
2963 };
2964
2965 static int configure_regmap(struct adv76xx_state *state, int region)
2966 {
2967 int err;
2968
2969 if (!state->i2c_clients[region])
2970 return -ENODEV;
2971
2972 state->regmap[region] =
2973 devm_regmap_init_i2c(state->i2c_clients[region],
2974 &adv76xx_regmap_cnf[region]);
2975
2976 if (IS_ERR(state->regmap[region])) {
2977 err = PTR_ERR(state->regmap[region]);
2978 v4l_err(state->i2c_clients[region],
2979 "Error initializing regmap %d with error %d\n",
2980 region, err);
2981 return -EINVAL;
2982 }
2983
2984 return 0;
2985 }
2986
2987 static int configure_regmaps(struct adv76xx_state *state)
2988 {
2989 int i, err;
2990
2991 for (i = ADV7604_PAGE_AVLINK ; i < ADV76XX_PAGE_MAX; i++) {
2992 err = configure_regmap(state, i);
2993 if (err && (err != -ENODEV))
2994 return err;
2995 }
2996 return 0;
2997 }
2998
2999 static int adv76xx_probe(struct i2c_client *client,
3000 const struct i2c_device_id *id)
3001 {
3002 static const struct v4l2_dv_timings cea640x480 =
3003 V4L2_DV_BT_CEA_640X480P59_94;
3004 struct adv76xx_state *state;
3005 struct v4l2_ctrl_handler *hdl;
3006 struct v4l2_ctrl *ctrl;
3007 struct v4l2_subdev *sd;
3008 unsigned int i;
3009 unsigned int val, val2;
3010 int err;
3011
3012 /* Check if the adapter supports the needed features */
3013 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
3014 return -EIO;
3015 v4l_dbg(1, debug, client, "detecting adv76xx client on address 0x%x\n",
3016 client->addr << 1);
3017
3018 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
3019 if (!state) {
3020 v4l_err(client, "Could not allocate adv76xx_state memory!\n");
3021 return -ENOMEM;
3022 }
3023
3024 state->i2c_clients[ADV76XX_PAGE_IO] = client;
3025
3026 /* initialize variables */
3027 state->restart_stdi_once = true;
3028 state->selected_input = ~0;
3029
3030 if (IS_ENABLED(CONFIG_OF) && client->dev.of_node) {
3031 const struct of_device_id *oid;
3032
3033 oid = of_match_node(adv76xx_of_id, client->dev.of_node);
3034 state->info = oid->data;
3035
3036 err = adv76xx_parse_dt(state);
3037 if (err < 0) {
3038 v4l_err(client, "DT parsing error\n");
3039 return err;
3040 }
3041 } else if (client->dev.platform_data) {
3042 struct adv76xx_platform_data *pdata = client->dev.platform_data;
3043
3044 state->info = (const struct adv76xx_chip_info *)id->driver_data;
3045 state->pdata = *pdata;
3046 } else {
3047 v4l_err(client, "No platform data!\n");
3048 return -ENODEV;
3049 }
3050
3051 /* Request GPIOs. */
3052 for (i = 0; i < state->info->num_dv_ports; ++i) {
3053 state->hpd_gpio[i] =
3054 devm_gpiod_get_index_optional(&client->dev, "hpd", i,
3055 GPIOD_OUT_LOW);
3056 if (IS_ERR(state->hpd_gpio[i]))
3057 return PTR_ERR(state->hpd_gpio[i]);
3058
3059 if (state->hpd_gpio[i])
3060 v4l_info(client, "Handling HPD %u GPIO\n", i);
3061 }
3062
3063 state->timings = cea640x480;
3064 state->format = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
3065
3066 sd = &state->sd;
3067 v4l2_i2c_subdev_init(sd, client, &adv76xx_ops);
3068 snprintf(sd->name, sizeof(sd->name), "%s %d-%04x",
3069 id->name, i2c_adapter_id(client->adapter),
3070 client->addr);
3071 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
3072
3073 /* Configure IO Regmap region */
3074 err = configure_regmap(state, ADV76XX_PAGE_IO);
3075
3076 if (err) {
3077 v4l2_err(sd, "Error configuring IO regmap region\n");
3078 return -ENODEV;
3079 }
3080
3081 /*
3082 * Verify that the chip is present. On ADV7604 the RD_INFO register only
3083 * identifies the revision, while on ADV7611 it identifies the model as
3084 * well. Use the HDMI slave address on ADV7604 and RD_INFO on ADV7611.
3085 */
3086 switch (state->info->type) {
3087 case ADV7604:
3088 err = regmap_read(state->regmap[ADV76XX_PAGE_IO], 0xfb, &val);
3089 if (err) {
3090 v4l2_err(sd, "Error %d reading IO Regmap\n", err);
3091 return -ENODEV;
3092 }
3093 if (val != 0x68) {
3094 v4l2_err(sd, "not an adv7604 on address 0x%x\n",
3095 client->addr << 1);
3096 return -ENODEV;
3097 }
3098 break;
3099 case ADV7611:
3100 case ADV7612:
3101 err = regmap_read(state->regmap[ADV76XX_PAGE_IO],
3102 0xea,
3103 &val);
3104 if (err) {
3105 v4l2_err(sd, "Error %d reading IO Regmap\n", err);
3106 return -ENODEV;
3107 }
3108 val2 = val << 8;
3109 err = regmap_read(state->regmap[ADV76XX_PAGE_IO],
3110 0xeb,
3111 &val);
3112 if (err) {
3113 v4l2_err(sd, "Error %d reading IO Regmap\n", err);
3114 return -ENODEV;
3115 }
3116 val |= val2;
3117 if ((state->info->type == ADV7611 && val != 0x2051) ||
3118 (state->info->type == ADV7612 && val != 0x2041)) {
3119 v4l2_err(sd, "not an adv761x on address 0x%x\n",
3120 client->addr << 1);
3121 return -ENODEV;
3122 }
3123 break;
3124 }
3125
3126 /* control handlers */
3127 hdl = &state->hdl;
3128 v4l2_ctrl_handler_init(hdl, adv76xx_has_afe(state) ? 9 : 8);
3129
3130 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
3131 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
3132 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
3133 V4L2_CID_CONTRAST, 0, 255, 1, 128);
3134 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
3135 V4L2_CID_SATURATION, 0, 255, 1, 128);
3136 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
3137 V4L2_CID_HUE, 0, 128, 1, 0);
3138 ctrl = v4l2_ctrl_new_std_menu(hdl, &adv76xx_ctrl_ops,
3139 V4L2_CID_DV_RX_IT_CONTENT_TYPE, V4L2_DV_IT_CONTENT_TYPE_NO_ITC,
3140 0, V4L2_DV_IT_CONTENT_TYPE_NO_ITC);
3141 if (ctrl)
3142 ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE;
3143
3144 /* private controls */
3145 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
3146 V4L2_CID_DV_RX_POWER_PRESENT, 0,
3147 (1 << state->info->num_dv_ports) - 1, 0, 0);
3148 state->rgb_quantization_range_ctrl =
3149 v4l2_ctrl_new_std_menu(hdl, &adv76xx_ctrl_ops,
3150 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
3151 0, V4L2_DV_RGB_RANGE_AUTO);
3152
3153 /* custom controls */
3154 if (adv76xx_has_afe(state))
3155 state->analog_sampling_phase_ctrl =
3156 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL);
3157 state->free_run_color_manual_ctrl =
3158 v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color_manual, NULL);
3159 state->free_run_color_ctrl =
3160 v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color, NULL);
3161
3162 sd->ctrl_handler = hdl;
3163 if (hdl->error) {
3164 err = hdl->error;
3165 goto err_hdl;
3166 }
3167 state->detect_tx_5v_ctrl->is_private = true;
3168 state->rgb_quantization_range_ctrl->is_private = true;
3169 if (adv76xx_has_afe(state))
3170 state->analog_sampling_phase_ctrl->is_private = true;
3171 state->free_run_color_manual_ctrl->is_private = true;
3172 state->free_run_color_ctrl->is_private = true;
3173
3174 if (adv76xx_s_detect_tx_5v_ctrl(sd)) {
3175 err = -ENODEV;
3176 goto err_hdl;
3177 }
3178
3179 for (i = 1; i < ADV76XX_PAGE_MAX; ++i) {
3180 if (!(BIT(i) & state->info->page_mask))
3181 continue;
3182
3183 state->i2c_clients[i] =
3184 adv76xx_dummy_client(sd, state->pdata.i2c_addresses[i],
3185 0xf2 + i);
3186 if (state->i2c_clients[i] == NULL) {
3187 err = -ENOMEM;
3188 v4l2_err(sd, "failed to create i2c client %u\n", i);
3189 goto err_i2c;
3190 }
3191 }
3192
3193 /* work queues */
3194 state->work_queues = create_singlethread_workqueue(client->name);
3195 if (!state->work_queues) {
3196 v4l2_err(sd, "Could not create work queue\n");
3197 err = -ENOMEM;
3198 goto err_i2c;
3199 }
3200
3201 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
3202 adv76xx_delayed_work_enable_hotplug);
3203
3204 state->source_pad = state->info->num_dv_ports
3205 + (state->info->has_afe ? 2 : 0);
3206 for (i = 0; i < state->source_pad; ++i)
3207 state->pads[i].flags = MEDIA_PAD_FL_SINK;
3208 state->pads[state->source_pad].flags = MEDIA_PAD_FL_SOURCE;
3209
3210 err = media_entity_pads_init(&sd->entity, state->source_pad + 1,
3211 state->pads);
3212 if (err)
3213 goto err_work_queues;
3214
3215 /* Configure regmaps */
3216 err = configure_regmaps(state);
3217 if (err)
3218 goto err_entity;
3219
3220 err = adv76xx_core_init(sd);
3221 if (err)
3222 goto err_entity;
3223 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
3224 client->addr << 1, client->adapter->name);
3225
3226 err = v4l2_async_register_subdev(sd);
3227 if (err)
3228 goto err_entity;
3229
3230 return 0;
3231
3232 err_entity:
3233 media_entity_cleanup(&sd->entity);
3234 err_work_queues:
3235 cancel_delayed_work(&state->delayed_work_enable_hotplug);
3236 destroy_workqueue(state->work_queues);
3237 err_i2c:
3238 adv76xx_unregister_clients(state);
3239 err_hdl:
3240 v4l2_ctrl_handler_free(hdl);
3241 return err;
3242 }
3243
3244 /* ----------------------------------------------------------------------- */
3245
3246 static int adv76xx_remove(struct i2c_client *client)
3247 {
3248 struct v4l2_subdev *sd = i2c_get_clientdata(client);
3249 struct adv76xx_state *state = to_state(sd);
3250
3251 cancel_delayed_work(&state->delayed_work_enable_hotplug);
3252 destroy_workqueue(state->work_queues);
3253 v4l2_async_unregister_subdev(sd);
3254 media_entity_cleanup(&sd->entity);
3255 adv76xx_unregister_clients(to_state(sd));
3256 v4l2_ctrl_handler_free(sd->ctrl_handler);
3257 return 0;
3258 }
3259
3260 /* ----------------------------------------------------------------------- */
3261
3262 static struct i2c_driver adv76xx_driver = {
3263 .driver = {
3264 .name = "adv7604",
3265 .of_match_table = of_match_ptr(adv76xx_of_id),
3266 },
3267 .probe = adv76xx_probe,
3268 .remove = adv76xx_remove,
3269 .id_table = adv76xx_i2c_id,
3270 };
3271
3272 module_i2c_driver(adv76xx_driver);
Linux with added FPC-III support