2 * clk-dfll.h - prototypes and macros for the Tegra DFLL clocksource driver
3 * Copyright (C) 2013 NVIDIA Corporation. All rights reserved.
5 * Aleksandr Frid <afrid@nvidia.com>
6 * Paul Walmsley <pwalmsley@nvidia.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 #ifndef __DRIVERS_CLK_TEGRA_CLK_DFLL_H
19 #define __DRIVERS_CLK_TEGRA_CLK_DFLL_H
21 #include <linux/platform_device.h>
22 #include <linux/reset.h>
23 #include <linux/types.h>
26 * struct tegra_dfll_soc_data - SoC-specific hooks/integration for the DFLL driver
27 * @dev: struct device * that holds the OPP table for the DFLL
28 * @max_freq: maximum frequency supported on this SoC
29 * @cvb: CPU frequency table for this SoC
30 * @init_clock_trimmers: callback to initialize clock trimmers
31 * @set_clock_trimmers_high: callback to tune clock trimmers for high voltage
32 * @set_clock_trimmers_low: callback to tune clock trimmers for low voltage
34 struct tegra_dfll_soc_data
{
36 unsigned long max_freq
;
37 const struct cvb_table
*cvb
;
39 void (*init_clock_trimmers
)(void);
40 void (*set_clock_trimmers_high
)(void);
41 void (*set_clock_trimmers_low
)(void);
44 int tegra_dfll_register(struct platform_device
*pdev
,
45 struct tegra_dfll_soc_data
*soc
);
46 int tegra_dfll_unregister(struct platform_device
*pdev
);
47 int tegra_dfll_runtime_suspend(struct device
*dev
);
48 int tegra_dfll_runtime_resume(struct device
*dev
);
50 #endif /* __DRIVERS_CLK_TEGRA_CLK_DFLL_H */