drivers/pinctrl/sh-pfc/pfc-r8a7779.c

   1 /*
   2  * r8a7779 processor support - PFC hardware block
   3  *
   4  * Copyright (C) 2011, 2013  Renesas Solutions Corp.
   5  * Copyright (C) 2011  Magnus Damm
   6  * Copyright (C) 2013  Cogent Embedded, Inc.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  20  */
  21
  22 #include <linux/kernel.h>
  23
  24 #include "sh_pfc.h"
  25
  26 #define CPU_ALL_PORT(fn, sfx)                                           \
  27         PORT_GP_32(0, fn, sfx),                                         \
  28         PORT_GP_32(1, fn, sfx),                                         \
  29         PORT_GP_32(2, fn, sfx),                                         \
  30         PORT_GP_32(3, fn, sfx),                                         \
  31         PORT_GP_32(4, fn, sfx),                                         \
  32         PORT_GP_32(5, fn, sfx),                                         \
  33         PORT_GP_9(6, fn, sfx)
  34
  35 enum {
  36         PINMUX_RESERVED = 0,
  37
  38         PINMUX_DATA_BEGIN,
  39         GP_ALL(DATA), /* GP_0_0_DATA -> GP_6_8_DATA */
  40         PINMUX_DATA_END,
  41
  42         PINMUX_FUNCTION_BEGIN,
  43         GP_ALL(FN), /* GP_0_0_FN -> GP_6_8_FN */
  44
  45         /* GPSR0 */
  46         FN_AVS1, FN_AVS2, FN_IP0_7_6, FN_A17,
  47         FN_A18, FN_A19, FN_IP0_9_8, FN_IP0_11_10,
  48         FN_IP0_13_12, FN_IP0_15_14, FN_IP0_18_16, FN_IP0_22_19,
  49         FN_IP0_24_23, FN_IP0_25, FN_IP0_27_26, FN_IP1_1_0,
  50         FN_IP1_3_2, FN_IP1_6_4, FN_IP1_10_7, FN_IP1_14_11,
  51         FN_IP1_18_15, FN_IP0_5_3, FN_IP0_30_28, FN_IP2_18_16,
  52         FN_IP2_21_19, FN_IP2_30_28, FN_IP3_2_0, FN_IP3_11_9,
  53         FN_IP3_14_12, FN_IP3_22_21, FN_IP3_26_24, FN_IP3_31_29,
  54
  55         /* GPSR1 */
  56         FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5, FN_IP4_10_8,
  57         FN_IP4_11, FN_IP4_12, FN_IP4_13, FN_IP4_14,
  58         FN_IP4_15, FN_IP4_16, FN_IP4_19_17, FN_IP4_22_20,
  59         FN_IP4_23, FN_IP4_24, FN_IP4_25, FN_IP4_26,
  60         FN_IP4_27, FN_IP4_28, FN_IP4_31_29, FN_IP5_2_0,
  61         FN_IP5_3, FN_IP5_4, FN_IP5_5, FN_IP5_6,
  62         FN_IP5_7, FN_IP5_8, FN_IP5_10_9, FN_IP5_12_11,
  63         FN_IP5_14_13, FN_IP5_16_15, FN_IP5_20_17, FN_IP5_23_21,
  64
  65         /* GPSR2 */
  66         FN_IP5_27_24, FN_IP8_20, FN_IP8_22_21, FN_IP8_24_23,
  67         FN_IP8_27_25, FN_IP8_30_28, FN_IP9_1_0, FN_IP9_3_2,
  68         FN_IP9_4, FN_IP9_5, FN_IP9_6, FN_IP9_7,
  69         FN_IP9_9_8, FN_IP9_11_10, FN_IP9_13_12, FN_IP9_15_14,
  70         FN_IP9_18_16, FN_IP9_21_19, FN_IP9_23_22, FN_IP9_25_24,
  71         FN_IP9_27_26, FN_IP9_29_28, FN_IP10_2_0, FN_IP10_5_3,
  72         FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_17_15,
  73         FN_IP10_20_18, FN_IP10_23_21, FN_IP10_25_24, FN_IP10_28_26,
  74
  75         /* GPSR3 */
  76         FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6,
  77         FN_IP11_11_9, FN_IP11_14_12, FN_IP11_17_15, FN_IP11_20_18,
  78         FN_IP11_23_21, FN_IP11_26_24, FN_IP11_29_27, FN_IP12_2_0,
  79         FN_IP12_5_3, FN_IP12_8_6, FN_IP12_11_9, FN_IP12_14_12,
  80         FN_IP12_17_15, FN_IP7_16_15, FN_IP7_18_17, FN_IP7_28_27,
  81         FN_IP7_30_29, FN_IP7_20_19, FN_IP7_22_21, FN_IP7_24_23,
  82         FN_IP7_26_25, FN_IP1_20_19, FN_IP1_22_21, FN_IP1_24_23,
  83         FN_IP5_28, FN_IP5_30_29, FN_IP6_1_0, FN_IP6_3_2,
  84
  85         /* GPSR4 */
  86         FN_IP6_5_4, FN_IP6_7_6, FN_IP6_8, FN_IP6_11_9,
  87         FN_IP6_14_12, FN_IP6_17_15, FN_IP6_19_18, FN_IP6_22_20,
  88         FN_IP6_24_23, FN_IP6_26_25, FN_IP6_30_29, FN_IP7_1_0,
  89         FN_IP7_3_2, FN_IP7_6_4, FN_IP7_9_7, FN_IP7_12_10,
  90         FN_IP7_14_13, FN_IP2_7_4, FN_IP2_11_8, FN_IP2_15_12,
  91         FN_IP1_28_25, FN_IP2_3_0, FN_IP8_3_0, FN_IP8_7_4,
  92         FN_IP8_11_8, FN_IP8_15_12, FN_USB_PENC0, FN_USB_PENC1,
  93         FN_IP0_2_0, FN_IP8_17_16, FN_IP8_18, FN_IP8_19,
  94
  95         /* GPSR5 */
  96         FN_A1, FN_A2, FN_A3, FN_A4,
  97         FN_A5, FN_A6, FN_A7, FN_A8,
  98         FN_A9, FN_A10, FN_A11, FN_A12,
  99         FN_A13, FN_A14, FN_A15, FN_A16,
 100         FN_RD, FN_WE0, FN_WE1, FN_EX_WAIT0,
 101         FN_IP3_23, FN_IP3_27, FN_IP3_28, FN_IP2_22,
 102         FN_IP2_23, FN_IP2_24, FN_IP2_25, FN_IP2_26,
 103         FN_IP2_27, FN_IP3_3, FN_IP3_4, FN_IP3_5,
 104
 105         /* GPSR6 */
 106         FN_IP3_6, FN_IP3_7, FN_IP3_8, FN_IP3_15,
 107         FN_IP3_16, FN_IP3_17, FN_IP3_18, FN_IP3_19,
 108         FN_IP3_20,
 109
 110         /* IPSR0 */
 111         FN_RD_WR, FN_FWE, FN_ATAG0, FN_VI1_R7,
 112         FN_HRTS1, FN_RX4_C,
 113         FN_CS1_A26, FN_HSPI_TX2, FN_SDSELF_B,
 114         FN_CS0, FN_HSPI_CS2_B,
 115         FN_CLKOUT, FN_TX3C_IRDA_TX_C, FN_PWM0_B,
 116         FN_A25, FN_SD1_WP, FN_MMC0_D5, FN_FD5,
 117         FN_HSPI_RX2, FN_VI1_R3, FN_TX5_B, FN_SSI_SDATA7_B,
 118         FN_CTS0_B,
 119         FN_A24, FN_SD1_CD, FN_MMC0_D4, FN_FD4,
 120         FN_HSPI_CS2, FN_VI1_R2, FN_SSI_WS78_B,
 121         FN_A23, FN_FCLE, FN_HSPI_CLK2, FN_VI1_R1,
 122         FN_A22, FN_RX5_D, FN_HSPI_RX2_B, FN_VI1_R0,
 123         FN_A21, FN_SCK5_D, FN_HSPI_CLK2_B,
 124         FN_A20, FN_TX5_D, FN_HSPI_TX2_B,
 125         FN_A0, FN_SD1_DAT3, FN_MMC0_D3, FN_FD3,
 126         FN_BS, FN_SD1_DAT2, FN_MMC0_D2, FN_FD2,
 127         FN_ATADIR0, FN_SDSELF, FN_HCTS1, FN_TX4_C,
 128         FN_USB_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
 129         FN_SCIF_CLK, FN_TCLK0_C,
 130
 131         /* IPSR1 */
 132         FN_EX_CS0, FN_RX3_C_IRDA_RX_C, FN_MMC0_D6,
 133         FN_FD6, FN_EX_CS1, FN_MMC0_D7, FN_FD7,
 134         FN_EX_CS2, FN_SD1_CLK, FN_MMC0_CLK, FN_FALE,
 135         FN_ATACS00, FN_EX_CS3, FN_SD1_CMD, FN_MMC0_CMD,
 136         FN_FRE, FN_ATACS10, FN_VI1_R4, FN_RX5_B,
 137         FN_HSCK1, FN_SSI_SDATA8_B, FN_RTS0_B_TANS_B, FN_SSI_SDATA9,
 138         FN_EX_CS4, FN_SD1_DAT0, FN_MMC0_D0, FN_FD0,
 139         FN_ATARD0, FN_VI1_R5, FN_SCK5_B, FN_HTX1,
 140         FN_TX2_E, FN_TX0_B, FN_SSI_SCK9, FN_EX_CS5,
 141         FN_SD1_DAT1, FN_MMC0_D1, FN_FD1, FN_ATAWR0,
 142         FN_VI1_R6, FN_HRX1, FN_RX2_E, FN_RX0_B,
 143         FN_SSI_WS9, FN_MLB_CLK, FN_PWM2, FN_SCK4,
 144         FN_MLB_SIG, FN_PWM3, FN_TX4, FN_MLB_DAT,
 145         FN_PWM4, FN_RX4, FN_HTX0, FN_TX1,
 146         FN_SDATA, FN_CTS0_C, FN_SUB_TCK, FN_CC5_STATE2,
 147         FN_CC5_STATE10, FN_CC5_STATE18, FN_CC5_STATE26, FN_CC5_STATE34,
 148
 149         /* IPSR2 */
 150         FN_HRX0, FN_RX1, FN_SCKZ, FN_RTS0_C_TANS_C,
 151         FN_SUB_TDI, FN_CC5_STATE3, FN_CC5_STATE11, FN_CC5_STATE19,
 152         FN_CC5_STATE27, FN_CC5_STATE35, FN_HSCK0, FN_SCK1,
 153         FN_MTS, FN_PWM5, FN_SCK0_C, FN_SSI_SDATA9_B,
 154         FN_SUB_TDO, FN_CC5_STATE0, FN_CC5_STATE8, FN_CC5_STATE16,
 155         FN_CC5_STATE24, FN_CC5_STATE32, FN_HCTS0, FN_CTS1,
 156         FN_STM, FN_PWM0_D, FN_RX0_C, FN_SCIF_CLK_C,
 157         FN_SUB_TRST, FN_TCLK1_B, FN_CC5_OSCOUT, FN_HRTS0,
 158         FN_RTS1_TANS, FN_MDATA, FN_TX0_C, FN_SUB_TMS,
 159         FN_CC5_STATE1, FN_CC5_STATE9, FN_CC5_STATE17, FN_CC5_STATE25,
 160         FN_CC5_STATE33, FN_DU0_DR0, FN_LCDOUT0, FN_DREQ0,
 161         FN_GPS_CLK_B, FN_AUDATA0, FN_TX5_C, FN_DU0_DR1,
 162         FN_LCDOUT1, FN_DACK0, FN_DRACK0, FN_GPS_SIGN_B,
 163         FN_AUDATA1, FN_RX5_C, FN_DU0_DR2, FN_LCDOUT2,
 164         FN_DU0_DR3, FN_LCDOUT3, FN_DU0_DR4, FN_LCDOUT4,
 165         FN_DU0_DR5, FN_LCDOUT5, FN_DU0_DR6, FN_LCDOUT6,
 166         FN_DU0_DR7, FN_LCDOUT7, FN_DU0_DG0, FN_LCDOUT8,
 167         FN_DREQ1, FN_SCL2, FN_AUDATA2,
 168
 169         /* IPSR3 */
 170         FN_DU0_DG1, FN_LCDOUT9, FN_DACK1, FN_SDA2,
 171         FN_AUDATA3, FN_DU0_DG2, FN_LCDOUT10, FN_DU0_DG3,
 172         FN_LCDOUT11, FN_DU0_DG4, FN_LCDOUT12, FN_DU0_DG5,
 173         FN_LCDOUT13, FN_DU0_DG6, FN_LCDOUT14, FN_DU0_DG7,
 174         FN_LCDOUT15, FN_DU0_DB0, FN_LCDOUT16, FN_EX_WAIT1,
 175         FN_SCL1, FN_TCLK1, FN_AUDATA4, FN_DU0_DB1,
 176         FN_LCDOUT17, FN_EX_WAIT2, FN_SDA1, FN_GPS_MAG_B,
 177         FN_AUDATA5, FN_SCK5_C, FN_DU0_DB2, FN_LCDOUT18,
 178         FN_DU0_DB3, FN_LCDOUT19, FN_DU0_DB4, FN_LCDOUT20,
 179         FN_DU0_DB5, FN_LCDOUT21, FN_DU0_DB6, FN_LCDOUT22,
 180         FN_DU0_DB7, FN_LCDOUT23, FN_DU0_DOTCLKIN, FN_QSTVA_QVS,
 181         FN_TX3_D_IRDA_TX_D, FN_SCL3_B, FN_DU0_DOTCLKOUT0, FN_QCLK,
 182         FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, FN_RX3_D_IRDA_RX_D, FN_SDA3_B,
 183         FN_SDA2_C, FN_DACK0_B, FN_DRACK0_B, FN_DU0_EXHSYNC_DU0_HSYNC,
 184         FN_QSTH_QHS, FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE,
 185         FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CAN1_TX,
 186         FN_TX2_C, FN_SCL2_C, FN_REMOCON,
 187
 188         /* IPSR4 */
 189         FN_DU0_DISP, FN_QPOLA, FN_CAN_CLK_C, FN_SCK2_C,
 190         FN_DU0_CDE, FN_QPOLB, FN_CAN1_RX, FN_RX2_C,
 191         FN_DREQ0_B, FN_SSI_SCK78_B, FN_SCK0_B, FN_DU1_DR0,
 192         FN_VI2_DATA0_VI2_B0, FN_PWM6, FN_SD3_CLK, FN_TX3_E_IRDA_TX_E,
 193         FN_AUDCK, FN_PWMFSW0_B, FN_DU1_DR1, FN_VI2_DATA1_VI2_B1,
 194         FN_PWM0, FN_SD3_CMD, FN_RX3_E_IRDA_RX_E, FN_AUDSYNC,
 195         FN_CTS0_D, FN_DU1_DR2, FN_VI2_G0, FN_DU1_DR3,
 196         FN_VI2_G1, FN_DU1_DR4, FN_VI2_G2, FN_DU1_DR5,
 197         FN_VI2_G3, FN_DU1_DR6, FN_VI2_G4, FN_DU1_DR7,
 198         FN_VI2_G5, FN_DU1_DG0, FN_VI2_DATA2_VI2_B2, FN_SCL1_B,
 199         FN_SD3_DAT2, FN_SCK3_E, FN_AUDATA6, FN_TX0_D,
 200         FN_DU1_DG1, FN_VI2_DATA3_VI2_B3, FN_SDA1_B, FN_SD3_DAT3,
 201         FN_SCK5, FN_AUDATA7, FN_RX0_D, FN_DU1_DG2,
 202         FN_VI2_G6, FN_DU1_DG3, FN_VI2_G7, FN_DU1_DG4,
 203         FN_VI2_R0, FN_DU1_DG5, FN_VI2_R1, FN_DU1_DG6,
 204         FN_VI2_R2, FN_DU1_DG7, FN_VI2_R3, FN_DU1_DB0,
 205         FN_VI2_DATA4_VI2_B4, FN_SCL2_B, FN_SD3_DAT0, FN_TX5,
 206         FN_SCK0_D,
 207
 208         /* IPSR5 */
 209         FN_DU1_DB1, FN_VI2_DATA5_VI2_B5, FN_SDA2_B, FN_SD3_DAT1,
 210         FN_RX5, FN_RTS0_D_TANS_D, FN_DU1_DB2, FN_VI2_R4,
 211         FN_DU1_DB3, FN_VI2_R5, FN_DU1_DB4, FN_VI2_R6,
 212         FN_DU1_DB5, FN_VI2_R7, FN_DU1_DB6, FN_SCL2_D,
 213         FN_DU1_DB7, FN_SDA2_D, FN_DU1_DOTCLKIN, FN_VI2_CLKENB,
 214         FN_HSPI_CS1, FN_SCL1_D, FN_DU1_DOTCLKOUT, FN_VI2_FIELD,
 215         FN_SDA1_D, FN_DU1_EXHSYNC_DU1_HSYNC, FN_VI2_HSYNC,
 216         FN_VI3_HSYNC, FN_DU1_EXVSYNC_DU1_VSYNC, FN_VI2_VSYNC, FN_VI3_VSYNC,
 217         FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_VI2_CLK, FN_TX3_B_IRDA_TX_B,
 218         FN_SD3_CD, FN_HSPI_TX1, FN_VI1_CLKENB, FN_VI3_CLKENB,
 219         FN_AUDIO_CLKC, FN_TX2_D, FN_SPEEDIN, FN_GPS_SIGN_D,
 220         FN_DU1_DISP, FN_VI2_DATA6_VI2_B6, FN_TCLK0, FN_QSTVA_B_QVS_B,
 221         FN_HSPI_CLK1, FN_SCK2_D, FN_AUDIO_CLKOUT_B, FN_GPS_MAG_D,
 222         FN_DU1_CDE, FN_VI2_DATA7_VI2_B7, FN_RX3_B_IRDA_RX_B,
 223         FN_SD3_WP, FN_HSPI_RX1, FN_VI1_FIELD, FN_VI3_FIELD,
 224         FN_AUDIO_CLKOUT, FN_RX2_D, FN_GPS_CLK_C, FN_GPS_CLK_D,
 225         FN_AUDIO_CLKA, FN_CAN_TXCLK, FN_AUDIO_CLKB, FN_USB_OVC2,
 226         FN_CAN_DEBUGOUT0, FN_MOUT0,
 227
 228         /* IPSR6 */
 229         FN_SSI_SCK0129, FN_CAN_DEBUGOUT1, FN_MOUT1, FN_SSI_WS0129,
 230         FN_CAN_DEBUGOUT2, FN_MOUT2, FN_SSI_SDATA0, FN_CAN_DEBUGOUT3,
 231         FN_MOUT5, FN_SSI_SDATA1, FN_CAN_DEBUGOUT4, FN_MOUT6,
 232         FN_SSI_SDATA2, FN_CAN_DEBUGOUT5, FN_SSI_SCK34, FN_CAN_DEBUGOUT6,
 233         FN_CAN0_TX_B, FN_IERX, FN_SSI_SCK9_C, FN_SSI_WS34,
 234         FN_CAN_DEBUGOUT7, FN_CAN0_RX_B, FN_IETX, FN_SSI_WS9_C,
 235         FN_SSI_SDATA3, FN_PWM0_C, FN_CAN_DEBUGOUT8, FN_CAN_CLK_B,
 236         FN_IECLK, FN_SCIF_CLK_B, FN_TCLK0_B, FN_SSI_SDATA4,
 237         FN_CAN_DEBUGOUT9, FN_SSI_SDATA9_C, FN_SSI_SCK5, FN_ADICLK,
 238         FN_CAN_DEBUGOUT10, FN_SCK3, FN_TCLK0_D, FN_SSI_WS5,
 239         FN_ADICS_SAMP, FN_CAN_DEBUGOUT11, FN_TX3_IRDA_TX, FN_SSI_SDATA5,
 240         FN_ADIDATA, FN_CAN_DEBUGOUT12, FN_RX3_IRDA_RX, FN_SSI_SCK6,
 241         FN_ADICHS0, FN_CAN0_TX, FN_IERX_B,
 242
 243         /* IPSR7 */
 244         FN_SSI_WS6, FN_ADICHS1, FN_CAN0_RX, FN_IETX_B,
 245         FN_SSI_SDATA6, FN_ADICHS2, FN_CAN_CLK, FN_IECLK_B,
 246         FN_SSI_SCK78, FN_CAN_DEBUGOUT13, FN_IRQ0_B, FN_SSI_SCK9_B,
 247         FN_HSPI_CLK1_C, FN_SSI_WS78, FN_CAN_DEBUGOUT14, FN_IRQ1_B,
 248         FN_SSI_WS9_B, FN_HSPI_CS1_C, FN_SSI_SDATA7, FN_CAN_DEBUGOUT15,
 249         FN_IRQ2_B, FN_TCLK1_C, FN_HSPI_TX1_C, FN_SSI_SDATA8,
 250         FN_VSP, FN_IRQ3_B, FN_HSPI_RX1_C, FN_SD0_CLK,
 251         FN_ATACS01, FN_SCK1_B, FN_SD0_CMD, FN_ATACS11,
 252         FN_TX1_B, FN_CC5_TDO, FN_SD0_DAT0, FN_ATADIR1,
 253         FN_RX1_B, FN_CC5_TRST, FN_SD0_DAT1, FN_ATAG1,
 254         FN_SCK2_B, FN_CC5_TMS, FN_SD0_DAT2, FN_ATARD1,
 255         FN_TX2_B, FN_CC5_TCK, FN_SD0_DAT3, FN_ATAWR1,
 256         FN_RX2_B, FN_CC5_TDI, FN_SD0_CD, FN_DREQ2,
 257         FN_RTS1_B_TANS_B, FN_SD0_WP, FN_DACK2, FN_CTS1_B,
 258
 259         /* IPSR8 */
 260         FN_HSPI_CLK0, FN_CTS0, FN_USB_OVC0, FN_AD_CLK,
 261         FN_CC5_STATE4, FN_CC5_STATE12, FN_CC5_STATE20, FN_CC5_STATE28,
 262         FN_CC5_STATE36, FN_HSPI_CS0, FN_RTS0_TANS, FN_USB_OVC1,
 263         FN_AD_DI, FN_CC5_STATE5, FN_CC5_STATE13, FN_CC5_STATE21,
 264         FN_CC5_STATE29, FN_CC5_STATE37, FN_HSPI_TX0, FN_TX0,
 265         FN_CAN_DEBUG_HW_TRIGGER, FN_AD_DO, FN_CC5_STATE6, FN_CC5_STATE14,
 266         FN_CC5_STATE22, FN_CC5_STATE30, FN_CC5_STATE38, FN_HSPI_RX0,
 267         FN_RX0, FN_CAN_STEP0, FN_AD_NCS, FN_CC5_STATE7,
 268         FN_CC5_STATE15, FN_CC5_STATE23, FN_CC5_STATE31, FN_CC5_STATE39,
 269         FN_FMCLK, FN_RDS_CLK, FN_PCMOE, FN_BPFCLK,
 270         FN_PCMWE, FN_FMIN, FN_RDS_DATA, FN_VI0_CLK,
 271         FN_MMC1_CLK, FN_VI0_CLKENB, FN_TX1_C, FN_HTX1_B,
 272         FN_MT1_SYNC, FN_VI0_FIELD, FN_RX1_C, FN_HRX1_B,
 273         FN_VI0_HSYNC, FN_VI0_DATA0_B_VI0_B0_B, FN_CTS1_C, FN_TX4_D,
 274         FN_MMC1_CMD, FN_HSCK1_B, FN_VI0_VSYNC, FN_VI0_DATA1_B_VI0_B1_B,
 275         FN_RTS1_C_TANS_C, FN_RX4_D, FN_PWMFSW0_C,
 276
 277         /* IPSR9 */
 278         FN_VI0_DATA0_VI0_B0, FN_HRTS1_B, FN_MT1_VCXO, FN_VI0_DATA1_VI0_B1,
 279         FN_HCTS1_B, FN_MT1_PWM, FN_VI0_DATA2_VI0_B2, FN_MMC1_D0,
 280         FN_VI0_DATA3_VI0_B3, FN_MMC1_D1, FN_VI0_DATA4_VI0_B4, FN_MMC1_D2,
 281         FN_VI0_DATA5_VI0_B5, FN_MMC1_D3, FN_VI0_DATA6_VI0_B6, FN_MMC1_D4,
 282         FN_ARM_TRACEDATA_0, FN_VI0_DATA7_VI0_B7, FN_MMC1_D5,
 283         FN_ARM_TRACEDATA_1, FN_VI0_G0, FN_SSI_SCK78_C, FN_IRQ0,
 284         FN_ARM_TRACEDATA_2, FN_VI0_G1, FN_SSI_WS78_C, FN_IRQ1,
 285         FN_ARM_TRACEDATA_3, FN_VI0_G2, FN_ETH_TXD1, FN_MMC1_D6,
 286         FN_ARM_TRACEDATA_4, FN_TS_SPSYNC0, FN_VI0_G3, FN_ETH_CRS_DV,
 287         FN_MMC1_D7, FN_ARM_TRACEDATA_5, FN_TS_SDAT0, FN_VI0_G4,
 288         FN_ETH_TX_EN, FN_SD2_DAT0_B, FN_ARM_TRACEDATA_6, FN_VI0_G5,
 289         FN_ETH_RX_ER, FN_SD2_DAT1_B, FN_ARM_TRACEDATA_7, FN_VI0_G6,
 290         FN_ETH_RXD0, FN_SD2_DAT2_B, FN_ARM_TRACEDATA_8, FN_VI0_G7,
 291         FN_ETH_RXD1, FN_SD2_DAT3_B, FN_ARM_TRACEDATA_9,
 292
 293         /* IPSR10 */
 294         FN_VI0_R0, FN_SSI_SDATA7_C, FN_SCK1_C, FN_DREQ1_B,
 295         FN_ARM_TRACEDATA_10, FN_DREQ0_C, FN_VI0_R1, FN_SSI_SDATA8_C,
 296         FN_DACK1_B, FN_ARM_TRACEDATA_11, FN_DACK0_C, FN_DRACK0_C,
 297         FN_VI0_R2, FN_ETH_LINK, FN_SD2_CLK_B, FN_IRQ2,
 298         FN_ARM_TRACEDATA_12, FN_VI0_R3, FN_ETH_MAGIC, FN_SD2_CMD_B,
 299         FN_IRQ3, FN_ARM_TRACEDATA_13, FN_VI0_R4, FN_ETH_REFCLK,
 300         FN_SD2_CD_B, FN_HSPI_CLK1_B, FN_ARM_TRACEDATA_14, FN_MT1_CLK,
 301         FN_TS_SCK0, FN_VI0_R5, FN_ETH_TXD0, FN_SD2_WP_B, FN_HSPI_CS1_B,
 302         FN_ARM_TRACEDATA_15, FN_MT1_D, FN_TS_SDEN0, FN_VI0_R6,
 303         FN_ETH_MDC, FN_DREQ2_C, FN_HSPI_TX1_B, FN_TRACECLK,
 304         FN_MT1_BEN, FN_PWMFSW0_D, FN_VI0_R7, FN_ETH_MDIO,
 305         FN_DACK2_C, FN_HSPI_RX1_B, FN_SCIF_CLK_D, FN_TRACECTL,
 306         FN_MT1_PEN, FN_VI1_CLK, FN_SIM_D, FN_SDA3,
 307         FN_VI1_HSYNC, FN_VI3_CLK, FN_SSI_SCK4, FN_GPS_SIGN_C,
 308         FN_PWMFSW0_E, FN_VI1_VSYNC, FN_AUDIO_CLKOUT_C, FN_SSI_WS4,
 309         FN_SIM_CLK, FN_GPS_MAG_C, FN_SPV_TRST, FN_SCL3,
 310
 311         /* IPSR11 */
 312         FN_VI1_DATA0_VI1_B0, FN_SD2_DAT0, FN_SIM_RST, FN_SPV_TCK,
 313         FN_ADICLK_B, FN_VI1_DATA1_VI1_B1, FN_SD2_DAT1, FN_MT0_CLK,
 314         FN_SPV_TMS, FN_ADICS_B_SAMP_B, FN_VI1_DATA2_VI1_B2, FN_SD2_DAT2,
 315         FN_MT0_D, FN_SPVTDI, FN_ADIDATA_B, FN_VI1_DATA3_VI1_B3,
 316         FN_SD2_DAT3, FN_MT0_BEN, FN_SPV_TDO, FN_ADICHS0_B,
 317         FN_VI1_DATA4_VI1_B4, FN_SD2_CLK, FN_MT0_PEN, FN_SPA_TRST,
 318         FN_HSPI_CLK1_D, FN_ADICHS1_B, FN_VI1_DATA5_VI1_B5, FN_SD2_CMD,
 319         FN_MT0_SYNC, FN_SPA_TCK, FN_HSPI_CS1_D, FN_ADICHS2_B,
 320         FN_VI1_DATA6_VI1_B6, FN_SD2_CD, FN_MT0_VCXO, FN_SPA_TMS,
 321         FN_HSPI_TX1_D, FN_VI1_DATA7_VI1_B7, FN_SD2_WP, FN_MT0_PWM,
 322         FN_SPA_TDI, FN_HSPI_RX1_D, FN_VI1_G0, FN_VI3_DATA0,
 323         FN_TS_SCK1, FN_DREQ2_B, FN_TX2,
 324         FN_SPA_TDO, FN_HCTS0_B, FN_VI1_G1, FN_VI3_DATA1,
 325         FN_SSI_SCK1, FN_TS_SDEN1, FN_DACK2_B, FN_RX2, FN_HRTS0_B,
 326
 327         /* IPSR12 */
 328         FN_VI1_G2, FN_VI3_DATA2, FN_SSI_WS1, FN_TS_SPSYNC1,
 329         FN_SCK2, FN_HSCK0_B, FN_VI1_G3, FN_VI3_DATA3,
 330         FN_SSI_SCK2, FN_TS_SDAT1, FN_SCL1_C, FN_HTX0_B,
 331         FN_VI1_G4, FN_VI3_DATA4, FN_SSI_WS2, FN_SDA1_C,
 332         FN_SIM_RST_B, FN_HRX0_B, FN_VI1_G5, FN_VI3_DATA5,
 333         FN_GPS_CLK, FN_FSE, FN_TX4_B, FN_SIM_D_B,
 334         FN_VI1_G6, FN_VI3_DATA6, FN_GPS_SIGN, FN_FRB,
 335         FN_RX4_B, FN_SIM_CLK_B, FN_VI1_G7, FN_VI3_DATA7,
 336         FN_GPS_MAG, FN_FCE, FN_SCK4_B,
 337
 338         FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
 339         FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
 340         FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2,
 341         FN_SEL_SCIF3_3, FN_SEL_SCIF3_4,
 342         FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
 343         FN_SEL_SCIF2_3, FN_SEL_SCIF2_4,
 344         FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2,
 345         FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
 346         FN_SEL_SSI9_0, FN_SEL_SSI9_1, FN_SEL_SSI9_2,
 347         FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2,
 348         FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2,
 349         FN_SEL_VI0_0, FN_SEL_VI0_1,
 350         FN_SEL_SD2_0, FN_SEL_SD2_1,
 351         FN_SEL_INT3_0, FN_SEL_INT3_1,
 352         FN_SEL_INT2_0, FN_SEL_INT2_1,
 353         FN_SEL_INT1_0, FN_SEL_INT1_1,
 354         FN_SEL_INT0_0, FN_SEL_INT0_1,
 355         FN_SEL_IE_0, FN_SEL_IE_1,
 356         FN_SEL_EXBUS2_0, FN_SEL_EXBUS2_1, FN_SEL_EXBUS2_2,
 357         FN_SEL_EXBUS1_0, FN_SEL_EXBUS1_1,
 358         FN_SEL_EXBUS0_0, FN_SEL_EXBUS0_1, FN_SEL_EXBUS0_2,
 359
 360         FN_SEL_TMU1_0, FN_SEL_TMU1_1, FN_SEL_TMU1_2,
 361         FN_SEL_TMU0_0, FN_SEL_TMU0_1, FN_SEL_TMU0_2, FN_SEL_TMU0_3,
 362         FN_SEL_SCIF_0, FN_SEL_SCIF_1, FN_SEL_SCIF_2, FN_SEL_SCIF_3,
 363         FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2,
 364         FN_SEL_CAN0_0, FN_SEL_CAN0_1,
 365         FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
 366         FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
 367         FN_SEL_PWMFSW_0, FN_SEL_PWMFSW_1, FN_SEL_PWMFSW_2,
 368         FN_SEL_PWMFSW_3, FN_SEL_PWMFSW_4,
 369         FN_SEL_ADI_0, FN_SEL_ADI_1,
 370         FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
 371         FN_SEL_SIM_0, FN_SEL_SIM_1,
 372         FN_SEL_HSPI2_0, FN_SEL_HSPI2_1,
 373         FN_SEL_HSPI1_0, FN_SEL_HSPI1_1, FN_SEL_HSPI1_2, FN_SEL_HSPI1_3,
 374         FN_SEL_I2C3_0, FN_SEL_I2C3_1,
 375         FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
 376         FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3,
 377         PINMUX_FUNCTION_END,
 378
 379         PINMUX_MARK_BEGIN,
 380         AVS1_MARK, AVS2_MARK, A17_MARK, A18_MARK,
 381         A19_MARK,
 382
 383         RD_WR_MARK, FWE_MARK, ATAG0_MARK, VI1_R7_MARK,
 384         HRTS1_MARK, RX4_C_MARK,
 385         CS1_A26_MARK, HSPI_TX2_MARK, SDSELF_B_MARK,
 386         CS0_MARK, HSPI_CS2_B_MARK,
 387         CLKOUT_MARK, TX3C_IRDA_TX_C_MARK, PWM0_B_MARK,
 388         A25_MARK, SD1_WP_MARK, MMC0_D5_MARK, FD5_MARK,
 389         HSPI_RX2_MARK, VI1_R3_MARK, TX5_B_MARK, SSI_SDATA7_B_MARK, CTS0_B_MARK,
 390         A24_MARK, SD1_CD_MARK, MMC0_D4_MARK, FD4_MARK,
 391         HSPI_CS2_MARK, VI1_R2_MARK, SSI_WS78_B_MARK,
 392         A23_MARK, FCLE_MARK, HSPI_CLK2_MARK, VI1_R1_MARK,
 393         A22_MARK, RX5_D_MARK, HSPI_RX2_B_MARK, VI1_R0_MARK,
 394         A21_MARK, SCK5_D_MARK, HSPI_CLK2_B_MARK,
 395         A20_MARK, TX5_D_MARK, HSPI_TX2_B_MARK,
 396         A0_MARK, SD1_DAT3_MARK, MMC0_D3_MARK, FD3_MARK,
 397         BS_MARK, SD1_DAT2_MARK, MMC0_D2_MARK, FD2_MARK,
 398         ATADIR0_MARK, SDSELF_MARK, HCTS1_MARK, TX4_C_MARK,
 399         USB_PENC0_MARK, USB_PENC1_MARK, USB_PENC2_MARK,
 400         SCK0_MARK, PWM1_MARK, PWMFSW0_MARK,
 401         SCIF_CLK_MARK, TCLK0_C_MARK,
 402
 403         EX_CS0_MARK, RX3_C_IRDA_RX_C_MARK, MMC0_D6_MARK,
 404         FD6_MARK, EX_CS1_MARK, MMC0_D7_MARK, FD7_MARK,
 405         EX_CS2_MARK, SD1_CLK_MARK, MMC0_CLK_MARK, FALE_MARK,
 406         ATACS00_MARK, EX_CS3_MARK, SD1_CMD_MARK, MMC0_CMD_MARK,
 407         FRE_MARK, ATACS10_MARK, VI1_R4_MARK, RX5_B_MARK,
 408         HSCK1_MARK, SSI_SDATA8_B_MARK, RTS0_B_TANS_B_MARK, SSI_SDATA9_MARK,
 409         EX_CS4_MARK, SD1_DAT0_MARK, MMC0_D0_MARK, FD0_MARK,
 410         ATARD0_MARK, VI1_R5_MARK, SCK5_B_MARK, HTX1_MARK,
 411         TX2_E_MARK, TX0_B_MARK, SSI_SCK9_MARK, EX_CS5_MARK,
 412         SD1_DAT1_MARK, MMC0_D1_MARK, FD1_MARK, ATAWR0_MARK,
 413         VI1_R6_MARK, HRX1_MARK, RX2_E_MARK, RX0_B_MARK,
 414         SSI_WS9_MARK, MLB_CLK_MARK, PWM2_MARK, SCK4_MARK,
 415         MLB_SIG_MARK, PWM3_MARK, TX4_MARK, MLB_DAT_MARK,
 416         PWM4_MARK, RX4_MARK, HTX0_MARK, TX1_MARK,
 417         SDATA_MARK, CTS0_C_MARK, SUB_TCK_MARK, CC5_STATE2_MARK,
 418         CC5_STATE10_MARK, CC5_STATE18_MARK, CC5_STATE26_MARK, CC5_STATE34_MARK,
 419
 420         HRX0_MARK, RX1_MARK, SCKZ_MARK, RTS0_C_TANS_C_MARK,
 421         SUB_TDI_MARK, CC5_STATE3_MARK, CC5_STATE11_MARK, CC5_STATE19_MARK,
 422         CC5_STATE27_MARK, CC5_STATE35_MARK, HSCK0_MARK, SCK1_MARK,
 423         MTS_MARK, PWM5_MARK, SCK0_C_MARK, SSI_SDATA9_B_MARK,
 424         SUB_TDO_MARK, CC5_STATE0_MARK, CC5_STATE8_MARK, CC5_STATE16_MARK,
 425         CC5_STATE24_MARK, CC5_STATE32_MARK, HCTS0_MARK, CTS1_MARK,
 426         STM_MARK, PWM0_D_MARK, RX0_C_MARK, SCIF_CLK_C_MARK,
 427         SUB_TRST_MARK, TCLK1_B_MARK, CC5_OSCOUT_MARK, HRTS0_MARK,
 428         RTS1_TANS_MARK, MDATA_MARK, TX0_C_MARK, SUB_TMS_MARK,
 429         CC5_STATE1_MARK, CC5_STATE9_MARK, CC5_STATE17_MARK, CC5_STATE25_MARK,
 430         CC5_STATE33_MARK, DU0_DR0_MARK, LCDOUT0_MARK, DREQ0_MARK,
 431         GPS_CLK_B_MARK, AUDATA0_MARK, TX5_C_MARK, DU0_DR1_MARK,
 432         LCDOUT1_MARK, DACK0_MARK, DRACK0_MARK, GPS_SIGN_B_MARK,
 433         AUDATA1_MARK, RX5_C_MARK, DU0_DR2_MARK, LCDOUT2_MARK,
 434         DU0_DR3_MARK, LCDOUT3_MARK, DU0_DR4_MARK, LCDOUT4_MARK,
 435         DU0_DR5_MARK, LCDOUT5_MARK, DU0_DR6_MARK, LCDOUT6_MARK,
 436         DU0_DR7_MARK, LCDOUT7_MARK, DU0_DG0_MARK, LCDOUT8_MARK,
 437         DREQ1_MARK, SCL2_MARK, AUDATA2_MARK,
 438
 439         DU0_DG1_MARK, LCDOUT9_MARK, DACK1_MARK, SDA2_MARK,
 440         AUDATA3_MARK, DU0_DG2_MARK, LCDOUT10_MARK, DU0_DG3_MARK,
 441         LCDOUT11_MARK, DU0_DG4_MARK, LCDOUT12_MARK, DU0_DG5_MARK,
 442         LCDOUT13_MARK, DU0_DG6_MARK, LCDOUT14_MARK, DU0_DG7_MARK,
 443         LCDOUT15_MARK, DU0_DB0_MARK, LCDOUT16_MARK, EX_WAIT1_MARK,
 444         SCL1_MARK, TCLK1_MARK, AUDATA4_MARK, DU0_DB1_MARK,
 445         LCDOUT17_MARK, EX_WAIT2_MARK, SDA1_MARK, GPS_MAG_B_MARK,
 446         AUDATA5_MARK, SCK5_C_MARK, DU0_DB2_MARK, LCDOUT18_MARK,
 447         DU0_DB3_MARK, LCDOUT19_MARK, DU0_DB4_MARK, LCDOUT20_MARK,
 448         DU0_DB5_MARK, LCDOUT21_MARK, DU0_DB6_MARK, LCDOUT22_MARK,
 449         DU0_DB7_MARK, LCDOUT23_MARK, DU0_DOTCLKIN_MARK, QSTVA_QVS_MARK,
 450         TX3_D_IRDA_TX_D_MARK, SCL3_B_MARK, DU0_DOTCLKOUT0_MARK, QCLK_MARK,
 451         DU0_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, RX3_D_IRDA_RX_D_MARK, SDA3_B_MARK,
 452         SDA2_C_MARK, DACK0_B_MARK, DRACK0_B_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK,
 453         QSTH_QHS_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK,
 454         DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, CAN1_TX_MARK,
 455         TX2_C_MARK, SCL2_C_MARK, REMOCON_MARK,
 456
 457         DU0_DISP_MARK, QPOLA_MARK, CAN_CLK_C_MARK, SCK2_C_MARK,
 458         DU0_CDE_MARK, QPOLB_MARK, CAN1_RX_MARK, RX2_C_MARK,
 459         DREQ0_B_MARK, SSI_SCK78_B_MARK, SCK0_B_MARK, DU1_DR0_MARK,
 460         VI2_DATA0_VI2_B0_MARK, PWM6_MARK, SD3_CLK_MARK, TX3_E_IRDA_TX_E_MARK,
 461         AUDCK_MARK, PWMFSW0_B_MARK, DU1_DR1_MARK, VI2_DATA1_VI2_B1_MARK,
 462         PWM0_MARK, SD3_CMD_MARK, RX3_E_IRDA_RX_E_MARK, AUDSYNC_MARK,
 463         CTS0_D_MARK, DU1_DR2_MARK, VI2_G0_MARK, DU1_DR3_MARK,
 464         VI2_G1_MARK, DU1_DR4_MARK, VI2_G2_MARK, DU1_DR5_MARK,
 465         VI2_G3_MARK, DU1_DR6_MARK, VI2_G4_MARK, DU1_DR7_MARK,
 466         VI2_G5_MARK, DU1_DG0_MARK, VI2_DATA2_VI2_B2_MARK, SCL1_B_MARK,
 467         SD3_DAT2_MARK, SCK3_E_MARK, AUDATA6_MARK, TX0_D_MARK,
 468         DU1_DG1_MARK, VI2_DATA3_VI2_B3_MARK, SDA1_B_MARK, SD3_DAT3_MARK,
 469         SCK5_MARK, AUDATA7_MARK, RX0_D_MARK, DU1_DG2_MARK,
 470         VI2_G6_MARK, DU1_DG3_MARK, VI2_G7_MARK, DU1_DG4_MARK,
 471         VI2_R0_MARK, DU1_DG5_MARK, VI2_R1_MARK, DU1_DG6_MARK,
 472         VI2_R2_MARK, DU1_DG7_MARK, VI2_R3_MARK, DU1_DB0_MARK,
 473         VI2_DATA4_VI2_B4_MARK, SCL2_B_MARK, SD3_DAT0_MARK, TX5_MARK,
 474         SCK0_D_MARK,
 475
 476         DU1_DB1_MARK, VI2_DATA5_VI2_B5_MARK, SDA2_B_MARK, SD3_DAT1_MARK,
 477         RX5_MARK, RTS0_D_TANS_D_MARK, DU1_DB2_MARK, VI2_R4_MARK,
 478         DU1_DB3_MARK, VI2_R5_MARK, DU1_DB4_MARK, VI2_R6_MARK,
 479         DU1_DB5_MARK, VI2_R7_MARK, DU1_DB6_MARK, SCL2_D_MARK,
 480         DU1_DB7_MARK, SDA2_D_MARK, DU1_DOTCLKIN_MARK, VI2_CLKENB_MARK,
 481         HSPI_CS1_MARK, SCL1_D_MARK, DU1_DOTCLKOUT_MARK, VI2_FIELD_MARK,
 482         SDA1_D_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, VI2_HSYNC_MARK,
 483         VI3_HSYNC_MARK, DU1_EXVSYNC_DU1_VSYNC_MARK, VI2_VSYNC_MARK,
 484         VI3_VSYNC_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, VI2_CLK_MARK,
 485         TX3_B_IRDA_TX_B_MARK, SD3_CD_MARK, HSPI_TX1_MARK, VI1_CLKENB_MARK,
 486         VI3_CLKENB_MARK, AUDIO_CLKC_MARK, TX2_D_MARK, SPEEDIN_MARK,
 487         GPS_SIGN_D_MARK, DU1_DISP_MARK, VI2_DATA6_VI2_B6_MARK, TCLK0_MARK,
 488         QSTVA_B_QVS_B_MARK, HSPI_CLK1_MARK, SCK2_D_MARK, AUDIO_CLKOUT_B_MARK,
 489         GPS_MAG_D_MARK, DU1_CDE_MARK, VI2_DATA7_VI2_B7_MARK,
 490         RX3_B_IRDA_RX_B_MARK, SD3_WP_MARK, HSPI_RX1_MARK, VI1_FIELD_MARK,
 491         VI3_FIELD_MARK, AUDIO_CLKOUT_MARK, RX2_D_MARK, GPS_CLK_C_MARK,
 492         GPS_CLK_D_MARK, AUDIO_CLKA_MARK, CAN_TXCLK_MARK, AUDIO_CLKB_MARK,
 493         USB_OVC2_MARK, CAN_DEBUGOUT0_MARK, MOUT0_MARK,
 494
 495         SSI_SCK0129_MARK, CAN_DEBUGOUT1_MARK, MOUT1_MARK, SSI_WS0129_MARK,
 496         CAN_DEBUGOUT2_MARK, MOUT2_MARK, SSI_SDATA0_MARK, CAN_DEBUGOUT3_MARK,
 497         MOUT5_MARK, SSI_SDATA1_MARK, CAN_DEBUGOUT4_MARK, MOUT6_MARK,
 498         SSI_SDATA2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK34_MARK,
 499         CAN_DEBUGOUT6_MARK, CAN0_TX_B_MARK, IERX_MARK, SSI_SCK9_C_MARK,
 500         SSI_WS34_MARK, CAN_DEBUGOUT7_MARK, CAN0_RX_B_MARK, IETX_MARK,
 501         SSI_WS9_C_MARK, SSI_SDATA3_MARK, PWM0_C_MARK, CAN_DEBUGOUT8_MARK,
 502         CAN_CLK_B_MARK, IECLK_MARK, SCIF_CLK_B_MARK, TCLK0_B_MARK,
 503         SSI_SDATA4_MARK, CAN_DEBUGOUT9_MARK, SSI_SDATA9_C_MARK, SSI_SCK5_MARK,
 504         ADICLK_MARK, CAN_DEBUGOUT10_MARK, SCK3_MARK, TCLK0_D_MARK,
 505         SSI_WS5_MARK, ADICS_SAMP_MARK, CAN_DEBUGOUT11_MARK, TX3_IRDA_TX_MARK,
 506         SSI_SDATA5_MARK, ADIDATA_MARK, CAN_DEBUGOUT12_MARK, RX3_IRDA_RX_MARK,
 507         SSI_SCK6_MARK, ADICHS0_MARK, CAN0_TX_MARK, IERX_B_MARK,
 508
 509         SSI_WS6_MARK, ADICHS1_MARK, CAN0_RX_MARK, IETX_B_MARK,
 510         SSI_SDATA6_MARK, ADICHS2_MARK, CAN_CLK_MARK, IECLK_B_MARK,
 511         SSI_SCK78_MARK, CAN_DEBUGOUT13_MARK, IRQ0_B_MARK, SSI_SCK9_B_MARK,
 512         HSPI_CLK1_C_MARK, SSI_WS78_MARK, CAN_DEBUGOUT14_MARK, IRQ1_B_MARK,
 513         SSI_WS9_B_MARK, HSPI_CS1_C_MARK, SSI_SDATA7_MARK, CAN_DEBUGOUT15_MARK,
 514         IRQ2_B_MARK, TCLK1_C_MARK, HSPI_TX1_C_MARK, SSI_SDATA8_MARK,
 515         VSP_MARK, IRQ3_B_MARK, HSPI_RX1_C_MARK, SD0_CLK_MARK,
 516         ATACS01_MARK, SCK1_B_MARK, SD0_CMD_MARK, ATACS11_MARK,
 517         TX1_B_MARK, CC5_TDO_MARK, SD0_DAT0_MARK, ATADIR1_MARK,
 518         RX1_B_MARK, CC5_TRST_MARK, SD0_DAT1_MARK, ATAG1_MARK,
 519         SCK2_B_MARK, CC5_TMS_MARK, SD0_DAT2_MARK, ATARD1_MARK,
 520         TX2_B_MARK, CC5_TCK_MARK, SD0_DAT3_MARK, ATAWR1_MARK,
 521         RX2_B_MARK, CC5_TDI_MARK, SD0_CD_MARK, DREQ2_MARK,
 522         RTS1_B_TANS_B_MARK, SD0_WP_MARK, DACK2_MARK, CTS1_B_MARK,
 523
 524         HSPI_CLK0_MARK, CTS0_MARK, USB_OVC0_MARK, AD_CLK_MARK,
 525         CC5_STATE4_MARK, CC5_STATE12_MARK, CC5_STATE20_MARK, CC5_STATE28_MARK,
 526         CC5_STATE36_MARK, HSPI_CS0_MARK, RTS0_TANS_MARK, USB_OVC1_MARK,
 527         AD_DI_MARK, CC5_STATE5_MARK, CC5_STATE13_MARK, CC5_STATE21_MARK,
 528         CC5_STATE29_MARK, CC5_STATE37_MARK, HSPI_TX0_MARK, TX0_MARK,
 529         CAN_DEBUG_HW_TRIGGER_MARK, AD_DO_MARK, CC5_STATE6_MARK,
 530         CC5_STATE14_MARK, CC5_STATE22_MARK, CC5_STATE30_MARK,
 531         CC5_STATE38_MARK, HSPI_RX0_MARK, RX0_MARK, CAN_STEP0_MARK,
 532         AD_NCS_MARK, CC5_STATE7_MARK, CC5_STATE15_MARK, CC5_STATE23_MARK,
 533         CC5_STATE31_MARK, CC5_STATE39_MARK, FMCLK_MARK, RDS_CLK_MARK,
 534         PCMOE_MARK, BPFCLK_MARK, PCMWE_MARK, FMIN_MARK, RDS_DATA_MARK,
 535         VI0_CLK_MARK, MMC1_CLK_MARK, VI0_CLKENB_MARK, TX1_C_MARK, HTX1_B_MARK,
 536         MT1_SYNC_MARK, VI0_FIELD_MARK, RX1_C_MARK, HRX1_B_MARK,
 537         VI0_HSYNC_MARK, VI0_DATA0_B_VI0_B0_B_MARK, CTS1_C_MARK, TX4_D_MARK,
 538         MMC1_CMD_MARK, HSCK1_B_MARK, VI0_VSYNC_MARK, VI0_DATA1_B_VI0_B1_B_MARK,
 539         RTS1_C_TANS_C_MARK, RX4_D_MARK, PWMFSW0_C_MARK,
 540
 541         VI0_DATA0_VI0_B0_MARK, HRTS1_B_MARK, MT1_VCXO_MARK,
 542         VI0_DATA1_VI0_B1_MARK, HCTS1_B_MARK, MT1_PWM_MARK,
 543         VI0_DATA2_VI0_B2_MARK, MMC1_D0_MARK, VI0_DATA3_VI0_B3_MARK,
 544         MMC1_D1_MARK, VI0_DATA4_VI0_B4_MARK, MMC1_D2_MARK,
 545         VI0_DATA5_VI0_B5_MARK, MMC1_D3_MARK, VI0_DATA6_VI0_B6_MARK,
 546         MMC1_D4_MARK, ARM_TRACEDATA_0_MARK, VI0_DATA7_VI0_B7_MARK,
 547         MMC1_D5_MARK, ARM_TRACEDATA_1_MARK, VI0_G0_MARK, SSI_SCK78_C_MARK,
 548         IRQ0_MARK, ARM_TRACEDATA_2_MARK, VI0_G1_MARK, SSI_WS78_C_MARK,
 549         IRQ1_MARK, ARM_TRACEDATA_3_MARK, VI0_G2_MARK, ETH_TXD1_MARK,
 550         MMC1_D6_MARK, ARM_TRACEDATA_4_MARK, TS_SPSYNC0_MARK, VI0_G3_MARK,
 551         ETH_CRS_DV_MARK, MMC1_D7_MARK, ARM_TRACEDATA_5_MARK, TS_SDAT0_MARK,
 552         VI0_G4_MARK, ETH_TX_EN_MARK, SD2_DAT0_B_MARK, ARM_TRACEDATA_6_MARK,
 553         VI0_G5_MARK, ETH_RX_ER_MARK, SD2_DAT1_B_MARK, ARM_TRACEDATA_7_MARK,
 554         VI0_G6_MARK, ETH_RXD0_MARK, SD2_DAT2_B_MARK, ARM_TRACEDATA_8_MARK,
 555         VI0_G7_MARK, ETH_RXD1_MARK, SD2_DAT3_B_MARK, ARM_TRACEDATA_9_MARK,
 556
 557         VI0_R0_MARK, SSI_SDATA7_C_MARK, SCK1_C_MARK, DREQ1_B_MARK,
 558         ARM_TRACEDATA_10_MARK, DREQ0_C_MARK, VI0_R1_MARK, SSI_SDATA8_C_MARK,
 559         DACK1_B_MARK, ARM_TRACEDATA_11_MARK, DACK0_C_MARK, DRACK0_C_MARK,
 560         VI0_R2_MARK, ETH_LINK_MARK, SD2_CLK_B_MARK, IRQ2_MARK,
 561         ARM_TRACEDATA_12_MARK, VI0_R3_MARK, ETH_MAGIC_MARK, SD2_CMD_B_MARK,
 562         IRQ3_MARK, ARM_TRACEDATA_13_MARK, VI0_R4_MARK, ETH_REFCLK_MARK,
 563         SD2_CD_B_MARK, HSPI_CLK1_B_MARK, ARM_TRACEDATA_14_MARK, MT1_CLK_MARK,
 564         TS_SCK0_MARK, VI0_R5_MARK, ETH_TXD0_MARK, SD2_WP_B_MARK,
 565         HSPI_CS1_B_MARK, ARM_TRACEDATA_15_MARK, MT1_D_MARK, TS_SDEN0_MARK,
 566         VI0_R6_MARK, ETH_MDC_MARK, DREQ2_C_MARK, HSPI_TX1_B_MARK,
 567         TRACECLK_MARK, MT1_BEN_MARK, PWMFSW0_D_MARK, VI0_R7_MARK,
 568         ETH_MDIO_MARK, DACK2_C_MARK, HSPI_RX1_B_MARK, SCIF_CLK_D_MARK,
 569         TRACECTL_MARK, MT1_PEN_MARK, VI1_CLK_MARK, SIM_D_MARK, SDA3_MARK,
 570         VI1_HSYNC_MARK, VI3_CLK_MARK, SSI_SCK4_MARK, GPS_SIGN_C_MARK,
 571         PWMFSW0_E_MARK, VI1_VSYNC_MARK, AUDIO_CLKOUT_C_MARK, SSI_WS4_MARK,
 572         SIM_CLK_MARK, GPS_MAG_C_MARK, SPV_TRST_MARK, SCL3_MARK,
 573
 574         VI1_DATA0_VI1_B0_MARK, SD2_DAT0_MARK, SIM_RST_MARK, SPV_TCK_MARK,
 575         ADICLK_B_MARK, VI1_DATA1_VI1_B1_MARK, SD2_DAT1_MARK, MT0_CLK_MARK,
 576         SPV_TMS_MARK, ADICS_B_SAMP_B_MARK, VI1_DATA2_VI1_B2_MARK,
 577         SD2_DAT2_MARK, MT0_D_MARK, SPVTDI_MARK, ADIDATA_B_MARK,
 578         VI1_DATA3_VI1_B3_MARK, SD2_DAT3_MARK, MT0_BEN_MARK, SPV_TDO_MARK,
 579         ADICHS0_B_MARK, VI1_DATA4_VI1_B4_MARK, SD2_CLK_MARK, MT0_PEN_MARK,
 580         SPA_TRST_MARK, HSPI_CLK1_D_MARK, ADICHS1_B_MARK,
 581         VI1_DATA5_VI1_B5_MARK, SD2_CMD_MARK, MT0_SYNC_MARK, SPA_TCK_MARK,
 582         HSPI_CS1_D_MARK, ADICHS2_B_MARK, VI1_DATA6_VI1_B6_MARK, SD2_CD_MARK,
 583         MT0_VCXO_MARK, SPA_TMS_MARK, HSPI_TX1_D_MARK, VI1_DATA7_VI1_B7_MARK,
 584         SD2_WP_MARK, MT0_PWM_MARK, SPA_TDI_MARK, HSPI_RX1_D_MARK,
 585         VI1_G0_MARK, VI3_DATA0_MARK, TS_SCK1_MARK,
 586         DREQ2_B_MARK, TX2_MARK, SPA_TDO_MARK, HCTS0_B_MARK,
 587         VI1_G1_MARK, VI3_DATA1_MARK, SSI_SCK1_MARK, TS_SDEN1_MARK,
 588         DACK2_B_MARK, RX2_MARK, HRTS0_B_MARK,
 589
 590         VI1_G2_MARK, VI3_DATA2_MARK, SSI_WS1_MARK, TS_SPSYNC1_MARK,
 591         SCK2_MARK, HSCK0_B_MARK, VI1_G3_MARK, VI3_DATA3_MARK,
 592         SSI_SCK2_MARK, TS_SDAT1_MARK, SCL1_C_MARK, HTX0_B_MARK,
 593         VI1_G4_MARK, VI3_DATA4_MARK, SSI_WS2_MARK, SDA1_C_MARK,
 594         SIM_RST_B_MARK, HRX0_B_MARK, VI1_G5_MARK, VI3_DATA5_MARK,
 595         GPS_CLK_MARK, FSE_MARK, TX4_B_MARK, SIM_D_B_MARK,
 596         VI1_G6_MARK, VI3_DATA6_MARK, GPS_SIGN_MARK, FRB_MARK,
 597         RX4_B_MARK, SIM_CLK_B_MARK, VI1_G7_MARK, VI3_DATA7_MARK,
 598         GPS_MAG_MARK, FCE_MARK, SCK4_B_MARK,
 599         PINMUX_MARK_END,
 600 };
 601
 602 static const u16 pinmux_data[] = {
 603         PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
 604
 605         PINMUX_SINGLE(AVS1),
 606         PINMUX_SINGLE(AVS1),
 607         PINMUX_SINGLE(A17),
 608         PINMUX_SINGLE(A18),
 609         PINMUX_SINGLE(A19),
 610
 611         PINMUX_SINGLE(USB_PENC0),
 612         PINMUX_SINGLE(USB_PENC1),
 613
 614         PINMUX_IPSR_GPSR(IP0_2_0, USB_PENC2),
 615         PINMUX_IPSR_MSEL(IP0_2_0, SCK0, SEL_SCIF0_0),
 616         PINMUX_IPSR_GPSR(IP0_2_0, PWM1),
 617         PINMUX_IPSR_MSEL(IP0_2_0, PWMFSW0, SEL_PWMFSW_0),
 618         PINMUX_IPSR_MSEL(IP0_2_0, SCIF_CLK, SEL_SCIF_0),
 619         PINMUX_IPSR_MSEL(IP0_2_0, TCLK0_C, SEL_TMU0_2),
 620         PINMUX_IPSR_GPSR(IP0_5_3, BS),
 621         PINMUX_IPSR_GPSR(IP0_5_3, SD1_DAT2),
 622         PINMUX_IPSR_GPSR(IP0_5_3, MMC0_D2),
 623         PINMUX_IPSR_GPSR(IP0_5_3, FD2),
 624         PINMUX_IPSR_GPSR(IP0_5_3, ATADIR0),
 625         PINMUX_IPSR_GPSR(IP0_5_3, SDSELF),
 626         PINMUX_IPSR_MSEL(IP0_5_3, HCTS1, SEL_HSCIF1_0),
 627         PINMUX_IPSR_GPSR(IP0_5_3, TX4_C),
 628         PINMUX_IPSR_GPSR(IP0_7_6, A0),
 629         PINMUX_IPSR_GPSR(IP0_7_6, SD1_DAT3),
 630         PINMUX_IPSR_GPSR(IP0_7_6, MMC0_D3),
 631         PINMUX_IPSR_GPSR(IP0_7_6, FD3),
 632         PINMUX_IPSR_GPSR(IP0_9_8, A20),
 633         PINMUX_IPSR_GPSR(IP0_9_8, TX5_D),
 634         PINMUX_IPSR_GPSR(IP0_9_8, HSPI_TX2_B),
 635         PINMUX_IPSR_GPSR(IP0_11_10, A21),
 636         PINMUX_IPSR_MSEL(IP0_11_10, SCK5_D, SEL_SCIF5_3),
 637         PINMUX_IPSR_MSEL(IP0_11_10, HSPI_CLK2_B, SEL_HSPI2_1),
 638         PINMUX_IPSR_GPSR(IP0_13_12, A22),
 639         PINMUX_IPSR_MSEL(IP0_13_12, RX5_D, SEL_SCIF5_3),
 640         PINMUX_IPSR_MSEL(IP0_13_12, HSPI_RX2_B, SEL_HSPI2_1),
 641         PINMUX_IPSR_GPSR(IP0_13_12, VI1_R0),
 642         PINMUX_IPSR_GPSR(IP0_15_14, A23),
 643         PINMUX_IPSR_GPSR(IP0_15_14, FCLE),
 644         PINMUX_IPSR_MSEL(IP0_15_14, HSPI_CLK2, SEL_HSPI2_0),
 645         PINMUX_IPSR_GPSR(IP0_15_14, VI1_R1),
 646         PINMUX_IPSR_GPSR(IP0_18_16, A24),
 647         PINMUX_IPSR_GPSR(IP0_18_16, SD1_CD),
 648         PINMUX_IPSR_GPSR(IP0_18_16, MMC0_D4),
 649         PINMUX_IPSR_GPSR(IP0_18_16, FD4),
 650         PINMUX_IPSR_MSEL(IP0_18_16, HSPI_CS2, SEL_HSPI2_0),
 651         PINMUX_IPSR_GPSR(IP0_18_16, VI1_R2),
 652         PINMUX_IPSR_MSEL(IP0_18_16, SSI_WS78_B, SEL_SSI7_1),
 653         PINMUX_IPSR_GPSR(IP0_22_19, A25),
 654         PINMUX_IPSR_GPSR(IP0_22_19, SD1_WP),
 655         PINMUX_IPSR_GPSR(IP0_22_19, MMC0_D5),
 656         PINMUX_IPSR_GPSR(IP0_22_19, FD5),
 657         PINMUX_IPSR_MSEL(IP0_22_19, HSPI_RX2, SEL_HSPI2_0),
 658         PINMUX_IPSR_GPSR(IP0_22_19, VI1_R3),
 659         PINMUX_IPSR_GPSR(IP0_22_19, TX5_B),
 660         PINMUX_IPSR_MSEL(IP0_22_19, SSI_SDATA7_B, SEL_SSI7_1),
 661         PINMUX_IPSR_MSEL(IP0_22_19, CTS0_B, SEL_SCIF0_1),
 662         PINMUX_IPSR_GPSR(IP0_24_23, CLKOUT),
 663         PINMUX_IPSR_GPSR(IP0_24_23, TX3C_IRDA_TX_C),
 664         PINMUX_IPSR_GPSR(IP0_24_23, PWM0_B),
 665         PINMUX_IPSR_GPSR(IP0_25, CS0),
 666         PINMUX_IPSR_MSEL(IP0_25, HSPI_CS2_B, SEL_HSPI2_1),
 667         PINMUX_IPSR_GPSR(IP0_27_26, CS1_A26),
 668         PINMUX_IPSR_GPSR(IP0_27_26, HSPI_TX2),
 669         PINMUX_IPSR_GPSR(IP0_27_26, SDSELF_B),
 670         PINMUX_IPSR_GPSR(IP0_30_28, RD_WR),
 671         PINMUX_IPSR_GPSR(IP0_30_28, FWE),
 672         PINMUX_IPSR_GPSR(IP0_30_28, ATAG0),
 673         PINMUX_IPSR_GPSR(IP0_30_28, VI1_R7),
 674         PINMUX_IPSR_MSEL(IP0_30_28, HRTS1, SEL_HSCIF1_0),
 675         PINMUX_IPSR_MSEL(IP0_30_28, RX4_C, SEL_SCIF4_2),
 676
 677         PINMUX_IPSR_GPSR(IP1_1_0, EX_CS0),
 678         PINMUX_IPSR_MSEL(IP1_1_0, RX3_C_IRDA_RX_C, SEL_SCIF3_2),
 679         PINMUX_IPSR_GPSR(IP1_1_0, MMC0_D6),
 680         PINMUX_IPSR_GPSR(IP1_1_0, FD6),
 681         PINMUX_IPSR_GPSR(IP1_3_2, EX_CS1),
 682         PINMUX_IPSR_GPSR(IP1_3_2, MMC0_D7),
 683         PINMUX_IPSR_GPSR(IP1_3_2, FD7),
 684         PINMUX_IPSR_GPSR(IP1_6_4, EX_CS2),
 685         PINMUX_IPSR_GPSR(IP1_6_4, SD1_CLK),
 686         PINMUX_IPSR_GPSR(IP1_6_4, MMC0_CLK),
 687         PINMUX_IPSR_GPSR(IP1_6_4, FALE),
 688         PINMUX_IPSR_GPSR(IP1_6_4, ATACS00),
 689         PINMUX_IPSR_GPSR(IP1_10_7, EX_CS3),
 690         PINMUX_IPSR_GPSR(IP1_10_7, SD1_CMD),
 691         PINMUX_IPSR_GPSR(IP1_10_7, MMC0_CMD),
 692         PINMUX_IPSR_GPSR(IP1_10_7, FRE),
 693         PINMUX_IPSR_GPSR(IP1_10_7, ATACS10),
 694         PINMUX_IPSR_GPSR(IP1_10_7, VI1_R4),
 695         PINMUX_IPSR_MSEL(IP1_10_7, RX5_B, SEL_SCIF5_1),
 696         PINMUX_IPSR_MSEL(IP1_10_7, HSCK1, SEL_HSCIF1_0),
 697         PINMUX_IPSR_MSEL(IP1_10_7, SSI_SDATA8_B, SEL_SSI8_1),
 698         PINMUX_IPSR_MSEL(IP1_10_7, RTS0_B_TANS_B, SEL_SCIF0_1),
 699         PINMUX_IPSR_MSEL(IP1_10_7, SSI_SDATA9, SEL_SSI9_0),
 700         PINMUX_IPSR_GPSR(IP1_14_11, EX_CS4),
 701         PINMUX_IPSR_GPSR(IP1_14_11, SD1_DAT0),
 702         PINMUX_IPSR_GPSR(IP1_14_11, MMC0_D0),
 703         PINMUX_IPSR_GPSR(IP1_14_11, FD0),
 704         PINMUX_IPSR_GPSR(IP1_14_11, ATARD0),
 705         PINMUX_IPSR_GPSR(IP1_14_11, VI1_R5),
 706         PINMUX_IPSR_MSEL(IP1_14_11, SCK5_B, SEL_SCIF5_1),
 707         PINMUX_IPSR_GPSR(IP1_14_11, HTX1),
 708         PINMUX_IPSR_GPSR(IP1_14_11, TX2_E),
 709         PINMUX_IPSR_GPSR(IP1_14_11, TX0_B),
 710         PINMUX_IPSR_MSEL(IP1_14_11, SSI_SCK9, SEL_SSI9_0),
 711         PINMUX_IPSR_GPSR(IP1_18_15, EX_CS5),
 712         PINMUX_IPSR_GPSR(IP1_18_15, SD1_DAT1),
 713         PINMUX_IPSR_GPSR(IP1_18_15, MMC0_D1),
 714         PINMUX_IPSR_GPSR(IP1_18_15, FD1),
 715         PINMUX_IPSR_GPSR(IP1_18_15, ATAWR0),
 716         PINMUX_IPSR_GPSR(IP1_18_15, VI1_R6),
 717         PINMUX_IPSR_MSEL(IP1_18_15, HRX1, SEL_HSCIF1_0),
 718         PINMUX_IPSR_MSEL(IP1_18_15, RX2_E, SEL_SCIF2_4),
 719         PINMUX_IPSR_MSEL(IP1_18_15, RX0_B, SEL_SCIF0_1),
 720         PINMUX_IPSR_MSEL(IP1_18_15, SSI_WS9, SEL_SSI9_0),
 721         PINMUX_IPSR_GPSR(IP1_20_19, MLB_CLK),
 722         PINMUX_IPSR_GPSR(IP1_20_19, PWM2),
 723         PINMUX_IPSR_MSEL(IP1_20_19, SCK4, SEL_SCIF4_0),
 724         PINMUX_IPSR_GPSR(IP1_22_21, MLB_SIG),
 725         PINMUX_IPSR_GPSR(IP1_22_21, PWM3),
 726         PINMUX_IPSR_GPSR(IP1_22_21, TX4),
 727         PINMUX_IPSR_GPSR(IP1_24_23, MLB_DAT),
 728         PINMUX_IPSR_GPSR(IP1_24_23, PWM4),
 729         PINMUX_IPSR_MSEL(IP1_24_23, RX4, SEL_SCIF4_0),
 730         PINMUX_IPSR_GPSR(IP1_28_25, HTX0),
 731         PINMUX_IPSR_GPSR(IP1_28_25, TX1),
 732         PINMUX_IPSR_GPSR(IP1_28_25, SDATA),
 733         PINMUX_IPSR_MSEL(IP1_28_25, CTS0_C, SEL_SCIF0_2),
 734         PINMUX_IPSR_GPSR(IP1_28_25, SUB_TCK),
 735         PINMUX_IPSR_GPSR(IP1_28_25, CC5_STATE2),
 736         PINMUX_IPSR_GPSR(IP1_28_25, CC5_STATE10),
 737         PINMUX_IPSR_GPSR(IP1_28_25, CC5_STATE18),
 738         PINMUX_IPSR_GPSR(IP1_28_25, CC5_STATE26),
 739         PINMUX_IPSR_GPSR(IP1_28_25, CC5_STATE34),
 740
 741         PINMUX_IPSR_MSEL(IP2_3_0, HRX0, SEL_HSCIF0_0),
 742         PINMUX_IPSR_MSEL(IP2_3_0, RX1, SEL_SCIF1_0),
 743         PINMUX_IPSR_GPSR(IP2_3_0, SCKZ),
 744         PINMUX_IPSR_MSEL(IP2_3_0, RTS0_C_TANS_C, SEL_SCIF0_2),
 745         PINMUX_IPSR_GPSR(IP2_3_0, SUB_TDI),
 746         PINMUX_IPSR_GPSR(IP2_3_0, CC5_STATE3),
 747         PINMUX_IPSR_GPSR(IP2_3_0, CC5_STATE11),
 748         PINMUX_IPSR_GPSR(IP2_3_0, CC5_STATE19),
 749         PINMUX_IPSR_GPSR(IP2_3_0, CC5_STATE27),
 750         PINMUX_IPSR_GPSR(IP2_3_0, CC5_STATE35),
 751         PINMUX_IPSR_MSEL(IP2_7_4, HSCK0, SEL_HSCIF0_0),
 752         PINMUX_IPSR_MSEL(IP2_7_4, SCK1, SEL_SCIF1_0),
 753         PINMUX_IPSR_GPSR(IP2_7_4, MTS),
 754         PINMUX_IPSR_GPSR(IP2_7_4, PWM5),
 755         PINMUX_IPSR_MSEL(IP2_7_4, SCK0_C, SEL_SCIF0_2),
 756         PINMUX_IPSR_MSEL(IP2_7_4, SSI_SDATA9_B, SEL_SSI9_1),
 757         PINMUX_IPSR_GPSR(IP2_7_4, SUB_TDO),
 758         PINMUX_IPSR_GPSR(IP2_7_4, CC5_STATE0),
 759         PINMUX_IPSR_GPSR(IP2_7_4, CC5_STATE8),
 760         PINMUX_IPSR_GPSR(IP2_7_4, CC5_STATE16),
 761         PINMUX_IPSR_GPSR(IP2_7_4, CC5_STATE24),
 762         PINMUX_IPSR_GPSR(IP2_7_4, CC5_STATE32),
 763         PINMUX_IPSR_MSEL(IP2_11_8, HCTS0, SEL_HSCIF0_0),
 764         PINMUX_IPSR_MSEL(IP2_11_8, CTS1, SEL_SCIF1_0),
 765         PINMUX_IPSR_GPSR(IP2_11_8, STM),
 766         PINMUX_IPSR_GPSR(IP2_11_8, PWM0_D),
 767         PINMUX_IPSR_MSEL(IP2_11_8, RX0_C, SEL_SCIF0_2),
 768         PINMUX_IPSR_MSEL(IP2_11_8, SCIF_CLK_C, SEL_SCIF_2),
 769         PINMUX_IPSR_GPSR(IP2_11_8, SUB_TRST),
 770         PINMUX_IPSR_MSEL(IP2_11_8, TCLK1_B, SEL_TMU1_1),
 771         PINMUX_IPSR_GPSR(IP2_11_8, CC5_OSCOUT),
 772         PINMUX_IPSR_MSEL(IP2_15_12, HRTS0, SEL_HSCIF0_0),
 773         PINMUX_IPSR_MSEL(IP2_15_12, RTS1_TANS, SEL_SCIF1_0),
 774         PINMUX_IPSR_GPSR(IP2_15_12, MDATA),
 775         PINMUX_IPSR_GPSR(IP2_15_12, TX0_C),
 776         PINMUX_IPSR_GPSR(IP2_15_12, SUB_TMS),
 777         PINMUX_IPSR_GPSR(IP2_15_12, CC5_STATE1),
 778         PINMUX_IPSR_GPSR(IP2_15_12, CC5_STATE9),
 779         PINMUX_IPSR_GPSR(IP2_15_12, CC5_STATE17),
 780         PINMUX_IPSR_GPSR(IP2_15_12, CC5_STATE25),
 781         PINMUX_IPSR_GPSR(IP2_15_12, CC5_STATE33),
 782         PINMUX_IPSR_GPSR(IP2_18_16, DU0_DR0),
 783         PINMUX_IPSR_GPSR(IP2_18_16, LCDOUT0),
 784         PINMUX_IPSR_MSEL(IP2_18_16, DREQ0, SEL_EXBUS0_0),
 785         PINMUX_IPSR_MSEL(IP2_18_16, GPS_CLK_B, SEL_GPS_1),
 786         PINMUX_IPSR_GPSR(IP2_18_16, AUDATA0),
 787         PINMUX_IPSR_GPSR(IP2_18_16, TX5_C),
 788         PINMUX_IPSR_GPSR(IP2_21_19, DU0_DR1),
 789         PINMUX_IPSR_GPSR(IP2_21_19, LCDOUT1),
 790         PINMUX_IPSR_GPSR(IP2_21_19, DACK0),
 791         PINMUX_IPSR_GPSR(IP2_21_19, DRACK0),
 792         PINMUX_IPSR_MSEL(IP2_21_19, GPS_SIGN_B, SEL_GPS_1),
 793         PINMUX_IPSR_GPSR(IP2_21_19, AUDATA1),
 794         PINMUX_IPSR_MSEL(IP2_21_19, RX5_C, SEL_SCIF5_2),
 795         PINMUX_IPSR_GPSR(IP2_22, DU0_DR2),
 796         PINMUX_IPSR_GPSR(IP2_22, LCDOUT2),
 797         PINMUX_IPSR_GPSR(IP2_23, DU0_DR3),
 798         PINMUX_IPSR_GPSR(IP2_23, LCDOUT3),
 799         PINMUX_IPSR_GPSR(IP2_24, DU0_DR4),
 800         PINMUX_IPSR_GPSR(IP2_24, LCDOUT4),
 801         PINMUX_IPSR_GPSR(IP2_25, DU0_DR5),
 802         PINMUX_IPSR_GPSR(IP2_25, LCDOUT5),
 803         PINMUX_IPSR_GPSR(IP2_26, DU0_DR6),
 804         PINMUX_IPSR_GPSR(IP2_26, LCDOUT6),
 805         PINMUX_IPSR_GPSR(IP2_27, DU0_DR7),
 806         PINMUX_IPSR_GPSR(IP2_27, LCDOUT7),
 807         PINMUX_IPSR_GPSR(IP2_30_28, DU0_DG0),
 808         PINMUX_IPSR_GPSR(IP2_30_28, LCDOUT8),
 809         PINMUX_IPSR_MSEL(IP2_30_28, DREQ1, SEL_EXBUS1_0),
 810         PINMUX_IPSR_MSEL(IP2_30_28, SCL2, SEL_I2C2_0),
 811         PINMUX_IPSR_GPSR(IP2_30_28, AUDATA2),
 812
 813         PINMUX_IPSR_GPSR(IP3_2_0, DU0_DG1),
 814         PINMUX_IPSR_GPSR(IP3_2_0, LCDOUT9),
 815         PINMUX_IPSR_GPSR(IP3_2_0, DACK1),
 816         PINMUX_IPSR_MSEL(IP3_2_0, SDA2, SEL_I2C2_0),
 817         PINMUX_IPSR_GPSR(IP3_2_0, AUDATA3),
 818         PINMUX_IPSR_GPSR(IP3_3, DU0_DG2),
 819         PINMUX_IPSR_GPSR(IP3_3, LCDOUT10),
 820         PINMUX_IPSR_GPSR(IP3_4, DU0_DG3),
 821         PINMUX_IPSR_GPSR(IP3_4, LCDOUT11),
 822         PINMUX_IPSR_GPSR(IP3_5, DU0_DG4),
 823         PINMUX_IPSR_GPSR(IP3_5, LCDOUT12),
 824         PINMUX_IPSR_GPSR(IP3_6, DU0_DG5),
 825         PINMUX_IPSR_GPSR(IP3_6, LCDOUT13),
 826         PINMUX_IPSR_GPSR(IP3_7, DU0_DG6),
 827         PINMUX_IPSR_GPSR(IP3_7, LCDOUT14),
 828         PINMUX_IPSR_GPSR(IP3_8, DU0_DG7),
 829         PINMUX_IPSR_GPSR(IP3_8, LCDOUT15),
 830         PINMUX_IPSR_GPSR(IP3_11_9, DU0_DB0),
 831         PINMUX_IPSR_GPSR(IP3_11_9, LCDOUT16),
 832         PINMUX_IPSR_GPSR(IP3_11_9, EX_WAIT1),
 833         PINMUX_IPSR_MSEL(IP3_11_9, SCL1, SEL_I2C1_0),
 834         PINMUX_IPSR_MSEL(IP3_11_9, TCLK1, SEL_TMU1_0),
 835         PINMUX_IPSR_GPSR(IP3_11_9, AUDATA4),
 836         PINMUX_IPSR_GPSR(IP3_14_12, DU0_DB1),
 837         PINMUX_IPSR_GPSR(IP3_14_12, LCDOUT17),
 838         PINMUX_IPSR_GPSR(IP3_14_12, EX_WAIT2),
 839         PINMUX_IPSR_MSEL(IP3_14_12, SDA1, SEL_I2C1_0),
 840         PINMUX_IPSR_MSEL(IP3_14_12, GPS_MAG_B, SEL_GPS_1),
 841         PINMUX_IPSR_GPSR(IP3_14_12, AUDATA5),
 842         PINMUX_IPSR_MSEL(IP3_14_12, SCK5_C, SEL_SCIF5_2),
 843         PINMUX_IPSR_GPSR(IP3_15, DU0_DB2),
 844         PINMUX_IPSR_GPSR(IP3_15, LCDOUT18),
 845         PINMUX_IPSR_GPSR(IP3_16, DU0_DB3),
 846         PINMUX_IPSR_GPSR(IP3_16, LCDOUT19),
 847         PINMUX_IPSR_GPSR(IP3_17, DU0_DB4),
 848         PINMUX_IPSR_GPSR(IP3_17, LCDOUT20),
 849         PINMUX_IPSR_GPSR(IP3_18, DU0_DB5),
 850         PINMUX_IPSR_GPSR(IP3_18, LCDOUT21),
 851         PINMUX_IPSR_GPSR(IP3_19, DU0_DB6),
 852         PINMUX_IPSR_GPSR(IP3_19, LCDOUT22),
 853         PINMUX_IPSR_GPSR(IP3_20, DU0_DB7),
 854         PINMUX_IPSR_GPSR(IP3_20, LCDOUT23),
 855         PINMUX_IPSR_GPSR(IP3_22_21, DU0_DOTCLKIN),
 856         PINMUX_IPSR_GPSR(IP3_22_21, QSTVA_QVS),
 857         PINMUX_IPSR_GPSR(IP3_22_21, TX3_D_IRDA_TX_D),
 858         PINMUX_IPSR_MSEL(IP3_22_21, SCL3_B, SEL_I2C3_1),
 859         PINMUX_IPSR_GPSR(IP3_23, DU0_DOTCLKOUT0),
 860         PINMUX_IPSR_GPSR(IP3_23, QCLK),
 861         PINMUX_IPSR_GPSR(IP3_26_24, DU0_DOTCLKOUT1),
 862         PINMUX_IPSR_GPSR(IP3_26_24, QSTVB_QVE),
 863         PINMUX_IPSR_MSEL(IP3_26_24, RX3_D_IRDA_RX_D, SEL_SCIF3_3),
 864         PINMUX_IPSR_MSEL(IP3_26_24, SDA3_B, SEL_I2C3_1),
 865         PINMUX_IPSR_MSEL(IP3_26_24, SDA2_C, SEL_I2C2_2),
 866         PINMUX_IPSR_GPSR(IP3_26_24, DACK0_B),
 867         PINMUX_IPSR_GPSR(IP3_26_24, DRACK0_B),
 868         PINMUX_IPSR_GPSR(IP3_27, DU0_EXHSYNC_DU0_HSYNC),
 869         PINMUX_IPSR_GPSR(IP3_27, QSTH_QHS),
 870         PINMUX_IPSR_GPSR(IP3_28, DU0_EXVSYNC_DU0_VSYNC),
 871         PINMUX_IPSR_GPSR(IP3_28, QSTB_QHE),
 872         PINMUX_IPSR_GPSR(IP3_31_29, DU0_EXODDF_DU0_ODDF_DISP_CDE),
 873         PINMUX_IPSR_GPSR(IP3_31_29, QCPV_QDE),
 874         PINMUX_IPSR_GPSR(IP3_31_29, CAN1_TX),
 875         PINMUX_IPSR_GPSR(IP3_31_29, TX2_C),
 876         PINMUX_IPSR_MSEL(IP3_31_29, SCL2_C, SEL_I2C2_2),
 877         PINMUX_IPSR_GPSR(IP3_31_29, REMOCON),
 878
 879         PINMUX_IPSR_GPSR(IP4_1_0, DU0_DISP),
 880         PINMUX_IPSR_GPSR(IP4_1_0, QPOLA),
 881         PINMUX_IPSR_MSEL(IP4_1_0, CAN_CLK_C, SEL_CANCLK_2),
 882         PINMUX_IPSR_MSEL(IP4_1_0, SCK2_C, SEL_SCIF2_2),
 883         PINMUX_IPSR_GPSR(IP4_4_2, DU0_CDE),
 884         PINMUX_IPSR_GPSR(IP4_4_2, QPOLB),
 885         PINMUX_IPSR_GPSR(IP4_4_2, CAN1_RX),
 886         PINMUX_IPSR_MSEL(IP4_4_2, RX2_C, SEL_SCIF2_2),
 887         PINMUX_IPSR_MSEL(IP4_4_2, DREQ0_B, SEL_EXBUS0_1),
 888         PINMUX_IPSR_MSEL(IP4_4_2, SSI_SCK78_B, SEL_SSI7_1),
 889         PINMUX_IPSR_MSEL(IP4_4_2, SCK0_B, SEL_SCIF0_1),
 890         PINMUX_IPSR_GPSR(IP4_7_5, DU1_DR0),
 891         PINMUX_IPSR_GPSR(IP4_7_5, VI2_DATA0_VI2_B0),
 892         PINMUX_IPSR_GPSR(IP4_7_5, PWM6),
 893         PINMUX_IPSR_GPSR(IP4_7_5, SD3_CLK),
 894         PINMUX_IPSR_GPSR(IP4_7_5, TX3_E_IRDA_TX_E),
 895         PINMUX_IPSR_GPSR(IP4_7_5, AUDCK),
 896         PINMUX_IPSR_MSEL(IP4_7_5, PWMFSW0_B, SEL_PWMFSW_1),
 897         PINMUX_IPSR_GPSR(IP4_10_8, DU1_DR1),
 898         PINMUX_IPSR_GPSR(IP4_10_8, VI2_DATA1_VI2_B1),
 899         PINMUX_IPSR_GPSR(IP4_10_8, PWM0),
 900         PINMUX_IPSR_GPSR(IP4_10_8, SD3_CMD),
 901         PINMUX_IPSR_MSEL(IP4_10_8, RX3_E_IRDA_RX_E, SEL_SCIF3_4),
 902         PINMUX_IPSR_GPSR(IP4_10_8, AUDSYNC),
 903         PINMUX_IPSR_MSEL(IP4_10_8, CTS0_D, SEL_SCIF0_3),
 904         PINMUX_IPSR_GPSR(IP4_11, DU1_DR2),
 905         PINMUX_IPSR_GPSR(IP4_11, VI2_G0),
 906         PINMUX_IPSR_GPSR(IP4_12, DU1_DR3),
 907         PINMUX_IPSR_GPSR(IP4_12, VI2_G1),
 908         PINMUX_IPSR_GPSR(IP4_13, DU1_DR4),
 909         PINMUX_IPSR_GPSR(IP4_13, VI2_G2),
 910         PINMUX_IPSR_GPSR(IP4_14, DU1_DR5),
 911         PINMUX_IPSR_GPSR(IP4_14, VI2_G3),
 912         PINMUX_IPSR_GPSR(IP4_15, DU1_DR6),
 913         PINMUX_IPSR_GPSR(IP4_15, VI2_G4),
 914         PINMUX_IPSR_GPSR(IP4_16, DU1_DR7),
 915         PINMUX_IPSR_GPSR(IP4_16, VI2_G5),
 916         PINMUX_IPSR_GPSR(IP4_19_17, DU1_DG0),
 917         PINMUX_IPSR_GPSR(IP4_19_17, VI2_DATA2_VI2_B2),
 918         PINMUX_IPSR_MSEL(IP4_19_17, SCL1_B, SEL_I2C1_1),
 919         PINMUX_IPSR_GPSR(IP4_19_17, SD3_DAT2),
 920         PINMUX_IPSR_MSEL(IP4_19_17, SCK3_E, SEL_SCIF3_4),
 921         PINMUX_IPSR_GPSR(IP4_19_17, AUDATA6),
 922         PINMUX_IPSR_GPSR(IP4_19_17, TX0_D),
 923         PINMUX_IPSR_GPSR(IP4_22_20, DU1_DG1),
 924         PINMUX_IPSR_GPSR(IP4_22_20, VI2_DATA3_VI2_B3),
 925         PINMUX_IPSR_MSEL(IP4_22_20, SDA1_B, SEL_I2C1_1),
 926         PINMUX_IPSR_GPSR(IP4_22_20, SD3_DAT3),
 927         PINMUX_IPSR_MSEL(IP4_22_20, SCK5, SEL_SCIF5_0),
 928         PINMUX_IPSR_GPSR(IP4_22_20, AUDATA7),
 929         PINMUX_IPSR_MSEL(IP4_22_20, RX0_D, SEL_SCIF0_3),
 930         PINMUX_IPSR_GPSR(IP4_23, DU1_DG2),
 931         PINMUX_IPSR_GPSR(IP4_23, VI2_G6),
 932         PINMUX_IPSR_GPSR(IP4_24, DU1_DG3),
 933         PINMUX_IPSR_GPSR(IP4_24, VI2_G7),
 934         PINMUX_IPSR_GPSR(IP4_25, DU1_DG4),
 935         PINMUX_IPSR_GPSR(IP4_25, VI2_R0),
 936         PINMUX_IPSR_GPSR(IP4_26, DU1_DG5),
 937         PINMUX_IPSR_GPSR(IP4_26, VI2_R1),
 938         PINMUX_IPSR_GPSR(IP4_27, DU1_DG6),
 939         PINMUX_IPSR_GPSR(IP4_27, VI2_R2),
 940         PINMUX_IPSR_GPSR(IP4_28, DU1_DG7),
 941         PINMUX_IPSR_GPSR(IP4_28, VI2_R3),
 942         PINMUX_IPSR_GPSR(IP4_31_29, DU1_DB0),
 943         PINMUX_IPSR_GPSR(IP4_31_29, VI2_DATA4_VI2_B4),
 944         PINMUX_IPSR_MSEL(IP4_31_29, SCL2_B, SEL_I2C2_1),
 945         PINMUX_IPSR_GPSR(IP4_31_29, SD3_DAT0),
 946         PINMUX_IPSR_GPSR(IP4_31_29, TX5),
 947         PINMUX_IPSR_MSEL(IP4_31_29, SCK0_D, SEL_SCIF0_3),
 948
 949         PINMUX_IPSR_GPSR(IP5_2_0, DU1_DB1),
 950         PINMUX_IPSR_GPSR(IP5_2_0, VI2_DATA5_VI2_B5),
 951         PINMUX_IPSR_MSEL(IP5_2_0, SDA2_B, SEL_I2C2_1),
 952         PINMUX_IPSR_GPSR(IP5_2_0, SD3_DAT1),
 953         PINMUX_IPSR_MSEL(IP5_2_0, RX5, SEL_SCIF5_0),
 954         PINMUX_IPSR_MSEL(IP5_2_0, RTS0_D_TANS_D, SEL_SCIF0_3),
 955         PINMUX_IPSR_GPSR(IP5_3, DU1_DB2),
 956         PINMUX_IPSR_GPSR(IP5_3, VI2_R4),
 957         PINMUX_IPSR_GPSR(IP5_4, DU1_DB3),
 958         PINMUX_IPSR_GPSR(IP5_4, VI2_R5),
 959         PINMUX_IPSR_GPSR(IP5_5, DU1_DB4),
 960         PINMUX_IPSR_GPSR(IP5_5, VI2_R6),
 961         PINMUX_IPSR_GPSR(IP5_6, DU1_DB5),
 962         PINMUX_IPSR_GPSR(IP5_6, VI2_R7),
 963         PINMUX_IPSR_GPSR(IP5_7, DU1_DB6),
 964         PINMUX_IPSR_MSEL(IP5_7, SCL2_D, SEL_I2C2_3),
 965         PINMUX_IPSR_GPSR(IP5_8, DU1_DB7),
 966         PINMUX_IPSR_MSEL(IP5_8, SDA2_D, SEL_I2C2_3),
 967         PINMUX_IPSR_GPSR(IP5_10_9, DU1_DOTCLKIN),
 968         PINMUX_IPSR_GPSR(IP5_10_9, VI2_CLKENB),
 969         PINMUX_IPSR_MSEL(IP5_10_9, HSPI_CS1, SEL_HSPI1_0),
 970         PINMUX_IPSR_MSEL(IP5_10_9, SCL1_D, SEL_I2C1_3),
 971         PINMUX_IPSR_GPSR(IP5_12_11, DU1_DOTCLKOUT),
 972         PINMUX_IPSR_GPSR(IP5_12_11, VI2_FIELD),
 973         PINMUX_IPSR_MSEL(IP5_12_11, SDA1_D, SEL_I2C1_3),
 974         PINMUX_IPSR_GPSR(IP5_14_13, DU1_EXHSYNC_DU1_HSYNC),
 975         PINMUX_IPSR_GPSR(IP5_14_13, VI2_HSYNC),
 976         PINMUX_IPSR_GPSR(IP5_14_13, VI3_HSYNC),
 977         PINMUX_IPSR_GPSR(IP5_16_15, DU1_EXVSYNC_DU1_VSYNC),
 978         PINMUX_IPSR_GPSR(IP5_16_15, VI2_VSYNC),
 979         PINMUX_IPSR_GPSR(IP5_16_15, VI3_VSYNC),
 980         PINMUX_IPSR_GPSR(IP5_20_17, DU1_EXODDF_DU1_ODDF_DISP_CDE),
 981         PINMUX_IPSR_GPSR(IP5_20_17, VI2_CLK),
 982         PINMUX_IPSR_GPSR(IP5_20_17, TX3_B_IRDA_TX_B),
 983         PINMUX_IPSR_GPSR(IP5_20_17, SD3_CD),
 984         PINMUX_IPSR_GPSR(IP5_20_17, HSPI_TX1),
 985         PINMUX_IPSR_GPSR(IP5_20_17, VI1_CLKENB),
 986         PINMUX_IPSR_GPSR(IP5_20_17, VI3_CLKENB),
 987         PINMUX_IPSR_GPSR(IP5_20_17, AUDIO_CLKC),
 988         PINMUX_IPSR_GPSR(IP5_20_17, TX2_D),
 989         PINMUX_IPSR_GPSR(IP5_20_17, SPEEDIN),
 990         PINMUX_IPSR_MSEL(IP5_20_17, GPS_SIGN_D, SEL_GPS_3),
 991         PINMUX_IPSR_GPSR(IP5_23_21, DU1_DISP),
 992         PINMUX_IPSR_GPSR(IP5_23_21, VI2_DATA6_VI2_B6),
 993         PINMUX_IPSR_MSEL(IP5_23_21, TCLK0, SEL_TMU0_0),
 994         PINMUX_IPSR_GPSR(IP5_23_21, QSTVA_B_QVS_B),
 995         PINMUX_IPSR_MSEL(IP5_23_21, HSPI_CLK1, SEL_HSPI1_0),
 996         PINMUX_IPSR_MSEL(IP5_23_21, SCK2_D, SEL_SCIF2_3),
 997         PINMUX_IPSR_GPSR(IP5_23_21, AUDIO_CLKOUT_B),
 998         PINMUX_IPSR_MSEL(IP5_23_21, GPS_MAG_D, SEL_GPS_3),
 999         PINMUX_IPSR_GPSR(IP5_27_24, DU1_CDE),
1000         PINMUX_IPSR_GPSR(IP5_27_24, VI2_DATA7_VI2_B7),
1001         PINMUX_IPSR_MSEL(IP5_27_24, RX3_B_IRDA_RX_B, SEL_SCIF3_1),
1002         PINMUX_IPSR_GPSR(IP5_27_24, SD3_WP),
1003         PINMUX_IPSR_MSEL(IP5_27_24, HSPI_RX1, SEL_HSPI1_0),
1004         PINMUX_IPSR_GPSR(IP5_27_24, VI1_FIELD),
1005         PINMUX_IPSR_GPSR(IP5_27_24, VI3_FIELD),
1006         PINMUX_IPSR_GPSR(IP5_27_24, AUDIO_CLKOUT),
1007         PINMUX_IPSR_MSEL(IP5_27_24, RX2_D, SEL_SCIF2_3),
1008         PINMUX_IPSR_MSEL(IP5_27_24, GPS_CLK_C, SEL_GPS_2),
1009         PINMUX_IPSR_MSEL(IP5_27_24, GPS_CLK_D, SEL_GPS_3),
1010         PINMUX_IPSR_GPSR(IP5_28, AUDIO_CLKA),
1011         PINMUX_IPSR_GPSR(IP5_28, CAN_TXCLK),
1012         PINMUX_IPSR_GPSR(IP5_30_29, AUDIO_CLKB),
1013         PINMUX_IPSR_GPSR(IP5_30_29, USB_OVC2),
1014         PINMUX_IPSR_GPSR(IP5_30_29, CAN_DEBUGOUT0),
1015         PINMUX_IPSR_GPSR(IP5_30_29, MOUT0),
1016
1017         PINMUX_IPSR_GPSR(IP6_1_0, SSI_SCK0129),
1018         PINMUX_IPSR_GPSR(IP6_1_0, CAN_DEBUGOUT1),
1019         PINMUX_IPSR_GPSR(IP6_1_0, MOUT1),
1020         PINMUX_IPSR_GPSR(IP6_3_2, SSI_WS0129),
1021         PINMUX_IPSR_GPSR(IP6_3_2, CAN_DEBUGOUT2),
1022         PINMUX_IPSR_GPSR(IP6_3_2, MOUT2),
1023         PINMUX_IPSR_GPSR(IP6_5_4, SSI_SDATA0),
1024         PINMUX_IPSR_GPSR(IP6_5_4, CAN_DEBUGOUT3),
1025         PINMUX_IPSR_GPSR(IP6_5_4, MOUT5),
1026         PINMUX_IPSR_GPSR(IP6_7_6, SSI_SDATA1),
1027         PINMUX_IPSR_GPSR(IP6_7_6, CAN_DEBUGOUT4),
1028         PINMUX_IPSR_GPSR(IP6_7_6, MOUT6),
1029         PINMUX_IPSR_GPSR(IP6_8, SSI_SDATA2),
1030         PINMUX_IPSR_GPSR(IP6_8, CAN_DEBUGOUT5),
1031         PINMUX_IPSR_GPSR(IP6_11_9, SSI_SCK34),
1032         PINMUX_IPSR_GPSR(IP6_11_9, CAN_DEBUGOUT6),
1033         PINMUX_IPSR_GPSR(IP6_11_9, CAN0_TX_B),
1034         PINMUX_IPSR_MSEL(IP6_11_9, IERX, SEL_IE_0),
1035         PINMUX_IPSR_MSEL(IP6_11_9, SSI_SCK9_C, SEL_SSI9_2),
1036         PINMUX_IPSR_GPSR(IP6_14_12, SSI_WS34),
1037         PINMUX_IPSR_GPSR(IP6_14_12, CAN_DEBUGOUT7),
1038         PINMUX_IPSR_MSEL(IP6_14_12, CAN0_RX_B, SEL_CAN0_1),
1039         PINMUX_IPSR_GPSR(IP6_14_12, IETX),
1040         PINMUX_IPSR_MSEL(IP6_14_12, SSI_WS9_C, SEL_SSI9_2),
1041         PINMUX_IPSR_GPSR(IP6_17_15, SSI_SDATA3),
1042         PINMUX_IPSR_GPSR(IP6_17_15, PWM0_C),
1043         PINMUX_IPSR_GPSR(IP6_17_15, CAN_DEBUGOUT8),
1044         PINMUX_IPSR_MSEL(IP6_17_15, CAN_CLK_B, SEL_CANCLK_1),
1045         PINMUX_IPSR_MSEL(IP6_17_15, IECLK, SEL_IE_0),
1046         PINMUX_IPSR_MSEL(IP6_17_15, SCIF_CLK_B, SEL_SCIF_1),
1047         PINMUX_IPSR_MSEL(IP6_17_15, TCLK0_B, SEL_TMU0_1),
1048         PINMUX_IPSR_GPSR(IP6_19_18, SSI_SDATA4),
1049         PINMUX_IPSR_GPSR(IP6_19_18, CAN_DEBUGOUT9),
1050         PINMUX_IPSR_MSEL(IP6_19_18, SSI_SDATA9_C, SEL_SSI9_2),
1051         PINMUX_IPSR_GPSR(IP6_22_20, SSI_SCK5),
1052         PINMUX_IPSR_GPSR(IP6_22_20, ADICLK),
1053         PINMUX_IPSR_GPSR(IP6_22_20, CAN_DEBUGOUT10),
1054         PINMUX_IPSR_MSEL(IP6_22_20, SCK3, SEL_SCIF3_0),
1055         PINMUX_IPSR_MSEL(IP6_22_20, TCLK0_D, SEL_TMU0_3),
1056         PINMUX_IPSR_GPSR(IP6_24_23, SSI_WS5),
1057         PINMUX_IPSR_MSEL(IP6_24_23, ADICS_SAMP, SEL_ADI_0),
1058         PINMUX_IPSR_GPSR(IP6_24_23, CAN_DEBUGOUT11),
1059         PINMUX_IPSR_GPSR(IP6_24_23, TX3_IRDA_TX),
1060         PINMUX_IPSR_GPSR(IP6_26_25, SSI_SDATA5),
1061         PINMUX_IPSR_MSEL(IP6_26_25, ADIDATA, SEL_ADI_0),
1062         PINMUX_IPSR_GPSR(IP6_26_25, CAN_DEBUGOUT12),
1063         PINMUX_IPSR_MSEL(IP6_26_25, RX3_IRDA_RX, SEL_SCIF3_0),
1064         PINMUX_IPSR_GPSR(IP6_30_29, SSI_SCK6),
1065         PINMUX_IPSR_GPSR(IP6_30_29, ADICHS0),
1066         PINMUX_IPSR_GPSR(IP6_30_29, CAN0_TX),
1067         PINMUX_IPSR_MSEL(IP6_30_29, IERX_B, SEL_IE_1),
1068
1069         PINMUX_IPSR_GPSR(IP7_1_0, SSI_WS6),
1070         PINMUX_IPSR_GPSR(IP7_1_0, ADICHS1),
1071         PINMUX_IPSR_MSEL(IP7_1_0, CAN0_RX, SEL_CAN0_0),
1072         PINMUX_IPSR_GPSR(IP7_1_0, IETX_B),
1073         PINMUX_IPSR_GPSR(IP7_3_2, SSI_SDATA6),
1074         PINMUX_IPSR_GPSR(IP7_3_2, ADICHS2),
1075         PINMUX_IPSR_MSEL(IP7_3_2, CAN_CLK, SEL_CANCLK_0),
1076         PINMUX_IPSR_MSEL(IP7_3_2, IECLK_B, SEL_IE_1),
1077         PINMUX_IPSR_MSEL(IP7_6_4, SSI_SCK78, SEL_SSI7_0),
1078         PINMUX_IPSR_GPSR(IP7_6_4, CAN_DEBUGOUT13),
1079         PINMUX_IPSR_MSEL(IP7_6_4, IRQ0_B, SEL_INT0_1),
1080         PINMUX_IPSR_MSEL(IP7_6_4, SSI_SCK9_B, SEL_SSI9_1),
1081         PINMUX_IPSR_MSEL(IP7_6_4, HSPI_CLK1_C, SEL_HSPI1_2),
1082         PINMUX_IPSR_MSEL(IP7_9_7, SSI_WS78, SEL_SSI7_0),
1083         PINMUX_IPSR_GPSR(IP7_9_7, CAN_DEBUGOUT14),
1084         PINMUX_IPSR_MSEL(IP7_9_7, IRQ1_B, SEL_INT1_1),
1085         PINMUX_IPSR_MSEL(IP7_9_7, SSI_WS9_B, SEL_SSI9_1),
1086         PINMUX_IPSR_MSEL(IP7_9_7, HSPI_CS1_C, SEL_HSPI1_2),
1087         PINMUX_IPSR_MSEL(IP7_12_10, SSI_SDATA7, SEL_SSI7_0),
1088         PINMUX_IPSR_GPSR(IP7_12_10, CAN_DEBUGOUT15),
1089         PINMUX_IPSR_MSEL(IP7_12_10, IRQ2_B, SEL_INT2_1),
1090         PINMUX_IPSR_MSEL(IP7_12_10, TCLK1_C, SEL_TMU1_2),
1091         PINMUX_IPSR_GPSR(IP7_12_10, HSPI_TX1_C),
1092         PINMUX_IPSR_MSEL(IP7_14_13, SSI_SDATA8, SEL_SSI8_0),
1093         PINMUX_IPSR_GPSR(IP7_14_13, VSP),
1094         PINMUX_IPSR_MSEL(IP7_14_13, IRQ3_B, SEL_INT3_1),
1095         PINMUX_IPSR_MSEL(IP7_14_13, HSPI_RX1_C, SEL_HSPI1_2),
1096         PINMUX_IPSR_GPSR(IP7_16_15, SD0_CLK),
1097         PINMUX_IPSR_GPSR(IP7_16_15, ATACS01),
1098         PINMUX_IPSR_MSEL(IP7_16_15, SCK1_B, SEL_SCIF1_1),
1099         PINMUX_IPSR_GPSR(IP7_18_17, SD0_CMD),
1100         PINMUX_IPSR_GPSR(IP7_18_17, ATACS11),
1101         PINMUX_IPSR_GPSR(IP7_18_17, TX1_B),
1102         PINMUX_IPSR_GPSR(IP7_18_17, CC5_TDO),
1103         PINMUX_IPSR_GPSR(IP7_20_19, SD0_DAT0),
1104         PINMUX_IPSR_GPSR(IP7_20_19, ATADIR1),
1105         PINMUX_IPSR_MSEL(IP7_20_19, RX1_B, SEL_SCIF1_1),
1106         PINMUX_IPSR_GPSR(IP7_20_19, CC5_TRST),
1107         PINMUX_IPSR_GPSR(IP7_22_21, SD0_DAT1),
1108         PINMUX_IPSR_GPSR(IP7_22_21, ATAG1),
1109         PINMUX_IPSR_MSEL(IP7_22_21, SCK2_B, SEL_SCIF2_1),
1110         PINMUX_IPSR_GPSR(IP7_22_21, CC5_TMS),
1111         PINMUX_IPSR_GPSR(IP7_24_23, SD0_DAT2),
1112         PINMUX_IPSR_GPSR(IP7_24_23, ATARD1),
1113         PINMUX_IPSR_GPSR(IP7_24_23, TX2_B),
1114         PINMUX_IPSR_GPSR(IP7_24_23, CC5_TCK),
1115         PINMUX_IPSR_GPSR(IP7_26_25, SD0_DAT3),
1116         PINMUX_IPSR_GPSR(IP7_26_25, ATAWR1),
1117         PINMUX_IPSR_MSEL(IP7_26_25, RX2_B, SEL_SCIF2_1),
1118         PINMUX_IPSR_GPSR(IP7_26_25, CC5_TDI),
1119         PINMUX_IPSR_GPSR(IP7_28_27, SD0_CD),
1120         PINMUX_IPSR_MSEL(IP7_28_27, DREQ2, SEL_EXBUS2_0),
1121         PINMUX_IPSR_MSEL(IP7_28_27, RTS1_B_TANS_B, SEL_SCIF1_1),
1122         PINMUX_IPSR_GPSR(IP7_30_29, SD0_WP),
1123         PINMUX_IPSR_GPSR(IP7_30_29, DACK2),
1124         PINMUX_IPSR_MSEL(IP7_30_29, CTS1_B, SEL_SCIF1_1),
1125
1126         PINMUX_IPSR_GPSR(IP8_3_0, HSPI_CLK0),
1127         PINMUX_IPSR_MSEL(IP8_3_0, CTS0, SEL_SCIF0_0),
1128         PINMUX_IPSR_GPSR(IP8_3_0, USB_OVC0),
1129         PINMUX_IPSR_GPSR(IP8_3_0, AD_CLK),
1130         PINMUX_IPSR_GPSR(IP8_3_0, CC5_STATE4),
1131         PINMUX_IPSR_GPSR(IP8_3_0, CC5_STATE12),
1132         PINMUX_IPSR_GPSR(IP8_3_0, CC5_STATE20),
1133         PINMUX_IPSR_GPSR(IP8_3_0, CC5_STATE28),
1134         PINMUX_IPSR_GPSR(IP8_3_0, CC5_STATE36),
1135         PINMUX_IPSR_GPSR(IP8_7_4, HSPI_CS0),
1136         PINMUX_IPSR_MSEL(IP8_7_4, RTS0_TANS, SEL_SCIF0_0),
1137         PINMUX_IPSR_GPSR(IP8_7_4, USB_OVC1),
1138         PINMUX_IPSR_GPSR(IP8_7_4, AD_DI),
1139         PINMUX_IPSR_GPSR(IP8_7_4, CC5_STATE5),
1140         PINMUX_IPSR_GPSR(IP8_7_4, CC5_STATE13),
1141         PINMUX_IPSR_GPSR(IP8_7_4, CC5_STATE21),
1142         PINMUX_IPSR_GPSR(IP8_7_4, CC5_STATE29),
1143         PINMUX_IPSR_GPSR(IP8_7_4, CC5_STATE37),
1144         PINMUX_IPSR_GPSR(IP8_11_8, HSPI_TX0),
1145         PINMUX_IPSR_GPSR(IP8_11_8, TX0),
1146         PINMUX_IPSR_GPSR(IP8_11_8, CAN_DEBUG_HW_TRIGGER),
1147         PINMUX_IPSR_GPSR(IP8_11_8, AD_DO),
1148         PINMUX_IPSR_GPSR(IP8_11_8, CC5_STATE6),
1149         PINMUX_IPSR_GPSR(IP8_11_8, CC5_STATE14),
1150         PINMUX_IPSR_GPSR(IP8_11_8, CC5_STATE22),
1151         PINMUX_IPSR_GPSR(IP8_11_8, CC5_STATE30),
1152         PINMUX_IPSR_GPSR(IP8_11_8, CC5_STATE38),
1153         PINMUX_IPSR_GPSR(IP8_15_12, HSPI_RX0),
1154         PINMUX_IPSR_MSEL(IP8_15_12, RX0, SEL_SCIF0_0),
1155         PINMUX_IPSR_GPSR(IP8_15_12, CAN_STEP0),
1156         PINMUX_IPSR_GPSR(IP8_15_12, AD_NCS),
1157         PINMUX_IPSR_GPSR(IP8_15_12, CC5_STATE7),
1158         PINMUX_IPSR_GPSR(IP8_15_12, CC5_STATE15),
1159         PINMUX_IPSR_GPSR(IP8_15_12, CC5_STATE23),
1160         PINMUX_IPSR_GPSR(IP8_15_12, CC5_STATE31),
1161         PINMUX_IPSR_GPSR(IP8_15_12, CC5_STATE39),
1162         PINMUX_IPSR_GPSR(IP8_17_16, FMCLK),
1163         PINMUX_IPSR_GPSR(IP8_17_16, RDS_CLK),
1164         PINMUX_IPSR_GPSR(IP8_17_16, PCMOE),
1165         PINMUX_IPSR_GPSR(IP8_18, BPFCLK),
1166         PINMUX_IPSR_GPSR(IP8_18, PCMWE),
1167         PINMUX_IPSR_GPSR(IP8_19, FMIN),
1168         PINMUX_IPSR_GPSR(IP8_19, RDS_DATA),
1169         PINMUX_IPSR_GPSR(IP8_20, VI0_CLK),
1170         PINMUX_IPSR_GPSR(IP8_20, MMC1_CLK),
1171         PINMUX_IPSR_GPSR(IP8_22_21, VI0_CLKENB),
1172         PINMUX_IPSR_GPSR(IP8_22_21, TX1_C),
1173         PINMUX_IPSR_GPSR(IP8_22_21, HTX1_B),
1174         PINMUX_IPSR_GPSR(IP8_22_21, MT1_SYNC),
1175         PINMUX_IPSR_GPSR(IP8_24_23, VI0_FIELD),
1176         PINMUX_IPSR_MSEL(IP8_24_23, RX1_C, SEL_SCIF1_2),
1177         PINMUX_IPSR_MSEL(IP8_24_23, HRX1_B, SEL_HSCIF1_1),
1178         PINMUX_IPSR_GPSR(IP8_27_25, VI0_HSYNC),
1179         PINMUX_IPSR_MSEL(IP8_27_25, VI0_DATA0_B_VI0_B0_B, SEL_VI0_1),
1180         PINMUX_IPSR_MSEL(IP8_27_25, CTS1_C, SEL_SCIF1_2),
1181         PINMUX_IPSR_GPSR(IP8_27_25, TX4_D),
1182         PINMUX_IPSR_GPSR(IP8_27_25, MMC1_CMD),
1183         PINMUX_IPSR_MSEL(IP8_27_25, HSCK1_B, SEL_HSCIF1_1),
1184         PINMUX_IPSR_GPSR(IP8_30_28, VI0_VSYNC),
1185         PINMUX_IPSR_MSEL(IP8_30_28, VI0_DATA1_B_VI0_B1_B, SEL_VI0_1),
1186         PINMUX_IPSR_MSEL(IP8_30_28, RTS1_C_TANS_C, SEL_SCIF1_2),
1187         PINMUX_IPSR_MSEL(IP8_30_28, RX4_D, SEL_SCIF4_3),
1188         PINMUX_IPSR_MSEL(IP8_30_28, PWMFSW0_C, SEL_PWMFSW_2),
1189
1190         PINMUX_IPSR_MSEL(IP9_1_0, VI0_DATA0_VI0_B0, SEL_VI0_0),
1191         PINMUX_IPSR_MSEL(IP9_1_0, HRTS1_B, SEL_HSCIF1_1),
1192         PINMUX_IPSR_GPSR(IP9_1_0, MT1_VCXO),
1193         PINMUX_IPSR_MSEL(IP9_3_2, VI0_DATA1_VI0_B1, SEL_VI0_0),
1194         PINMUX_IPSR_MSEL(IP9_3_2, HCTS1_B, SEL_HSCIF1_1),
1195         PINMUX_IPSR_GPSR(IP9_3_2, MT1_PWM),
1196         PINMUX_IPSR_GPSR(IP9_4, VI0_DATA2_VI0_B2),
1197         PINMUX_IPSR_GPSR(IP9_4, MMC1_D0),
1198         PINMUX_IPSR_GPSR(IP9_5, VI0_DATA3_VI0_B3),
1199         PINMUX_IPSR_GPSR(IP9_5, MMC1_D1),
1200         PINMUX_IPSR_GPSR(IP9_6, VI0_DATA4_VI0_B4),
1201         PINMUX_IPSR_GPSR(IP9_6, MMC1_D2),
1202         PINMUX_IPSR_GPSR(IP9_7, VI0_DATA5_VI0_B5),
1203         PINMUX_IPSR_GPSR(IP9_7, MMC1_D3),
1204         PINMUX_IPSR_GPSR(IP9_9_8, VI0_DATA6_VI0_B6),
1205         PINMUX_IPSR_GPSR(IP9_9_8, MMC1_D4),
1206         PINMUX_IPSR_GPSR(IP9_9_8, ARM_TRACEDATA_0),
1207         PINMUX_IPSR_GPSR(IP9_11_10, VI0_DATA7_VI0_B7),
1208         PINMUX_IPSR_GPSR(IP9_11_10, MMC1_D5),
1209         PINMUX_IPSR_GPSR(IP9_11_10, ARM_TRACEDATA_1),
1210         PINMUX_IPSR_GPSR(IP9_13_12, VI0_G0),
1211         PINMUX_IPSR_MSEL(IP9_13_12, SSI_SCK78_C, SEL_SSI7_2),
1212         PINMUX_IPSR_MSEL(IP9_13_12, IRQ0, SEL_INT0_0),
1213         PINMUX_IPSR_GPSR(IP9_13_12, ARM_TRACEDATA_2),
1214         PINMUX_IPSR_GPSR(IP9_15_14, VI0_G1),
1215         PINMUX_IPSR_MSEL(IP9_15_14, SSI_WS78_C, SEL_SSI7_2),
1216         PINMUX_IPSR_MSEL(IP9_15_14, IRQ1, SEL_INT1_0),
1217         PINMUX_IPSR_GPSR(IP9_15_14, ARM_TRACEDATA_3),
1218         PINMUX_IPSR_GPSR(IP9_18_16, VI0_G2),
1219         PINMUX_IPSR_GPSR(IP9_18_16, ETH_TXD1),
1220         PINMUX_IPSR_GPSR(IP9_18_16, MMC1_D6),
1221         PINMUX_IPSR_GPSR(IP9_18_16, ARM_TRACEDATA_4),
1222         PINMUX_IPSR_GPSR(IP9_18_16, TS_SPSYNC0),
1223         PINMUX_IPSR_GPSR(IP9_21_19, VI0_G3),
1224         PINMUX_IPSR_GPSR(IP9_21_19, ETH_CRS_DV),
1225         PINMUX_IPSR_GPSR(IP9_21_19, MMC1_D7),
1226         PINMUX_IPSR_GPSR(IP9_21_19, ARM_TRACEDATA_5),
1227         PINMUX_IPSR_GPSR(IP9_21_19, TS_SDAT0),
1228         PINMUX_IPSR_GPSR(IP9_23_22, VI0_G4),
1229         PINMUX_IPSR_GPSR(IP9_23_22, ETH_TX_EN),
1230         PINMUX_IPSR_MSEL(IP9_23_22, SD2_DAT0_B, SEL_SD2_1),
1231         PINMUX_IPSR_GPSR(IP9_23_22, ARM_TRACEDATA_6),
1232         PINMUX_IPSR_GPSR(IP9_25_24, VI0_G5),
1233         PINMUX_IPSR_GPSR(IP9_25_24, ETH_RX_ER),
1234         PINMUX_IPSR_MSEL(IP9_25_24, SD2_DAT1_B, SEL_SD2_1),
1235         PINMUX_IPSR_GPSR(IP9_25_24, ARM_TRACEDATA_7),
1236         PINMUX_IPSR_GPSR(IP9_27_26, VI0_G6),
1237         PINMUX_IPSR_GPSR(IP9_27_26, ETH_RXD0),
1238         PINMUX_IPSR_MSEL(IP9_27_26, SD2_DAT2_B, SEL_SD2_1),
1239         PINMUX_IPSR_GPSR(IP9_27_26, ARM_TRACEDATA_8),
1240         PINMUX_IPSR_GPSR(IP9_29_28, VI0_G7),
1241         PINMUX_IPSR_GPSR(IP9_29_28, ETH_RXD1),
1242         PINMUX_IPSR_MSEL(IP9_29_28, SD2_DAT3_B, SEL_SD2_1),
1243         PINMUX_IPSR_GPSR(IP9_29_28, ARM_TRACEDATA_9),
1244
1245         PINMUX_IPSR_GPSR(IP10_2_0, VI0_R0),
1246         PINMUX_IPSR_MSEL(IP10_2_0, SSI_SDATA7_C, SEL_SSI7_2),
1247         PINMUX_IPSR_MSEL(IP10_2_0, SCK1_C, SEL_SCIF1_2),
1248         PINMUX_IPSR_MSEL(IP10_2_0, DREQ1_B, SEL_EXBUS1_0),
1249         PINMUX_IPSR_GPSR(IP10_2_0, ARM_TRACEDATA_10),
1250         PINMUX_IPSR_MSEL(IP10_2_0, DREQ0_C, SEL_EXBUS0_2),
1251         PINMUX_IPSR_GPSR(IP10_5_3, VI0_R1),
1252         PINMUX_IPSR_MSEL(IP10_5_3, SSI_SDATA8_C, SEL_SSI8_2),
1253         PINMUX_IPSR_GPSR(IP10_5_3, DACK1_B),
1254         PINMUX_IPSR_GPSR(IP10_5_3, ARM_TRACEDATA_11),
1255         PINMUX_IPSR_GPSR(IP10_5_3, DACK0_C),
1256         PINMUX_IPSR_GPSR(IP10_5_3, DRACK0_C),
1257         PINMUX_IPSR_GPSR(IP10_8_6, VI0_R2),
1258         PINMUX_IPSR_GPSR(IP10_8_6, ETH_LINK),
1259         PINMUX_IPSR_GPSR(IP10_8_6, SD2_CLK_B),
1260         PINMUX_IPSR_MSEL(IP10_8_6, IRQ2, SEL_INT2_0),
1261         PINMUX_IPSR_GPSR(IP10_8_6, ARM_TRACEDATA_12),
1262         PINMUX_IPSR_GPSR(IP10_11_9, VI0_R3),
1263         PINMUX_IPSR_GPSR(IP10_11_9, ETH_MAGIC),
1264         PINMUX_IPSR_MSEL(IP10_11_9, SD2_CMD_B, SEL_SD2_1),
1265         PINMUX_IPSR_MSEL(IP10_11_9, IRQ3, SEL_INT3_0),
1266         PINMUX_IPSR_GPSR(IP10_11_9, ARM_TRACEDATA_13),
1267         PINMUX_IPSR_GPSR(IP10_14_12, VI0_R4),
1268         PINMUX_IPSR_GPSR(IP10_14_12, ETH_REFCLK),
1269         PINMUX_IPSR_MSEL(IP10_14_12, SD2_CD_B, SEL_SD2_1),
1270         PINMUX_IPSR_MSEL(IP10_14_12, HSPI_CLK1_B, SEL_HSPI1_1),
1271         PINMUX_IPSR_GPSR(IP10_14_12, ARM_TRACEDATA_14),
1272         PINMUX_IPSR_GPSR(IP10_14_12, MT1_CLK),
1273         PINMUX_IPSR_GPSR(IP10_14_12, TS_SCK0),
1274         PINMUX_IPSR_GPSR(IP10_17_15, VI0_R5),
1275         PINMUX_IPSR_GPSR(IP10_17_15, ETH_TXD0),
1276         PINMUX_IPSR_MSEL(IP10_17_15, SD2_WP_B, SEL_SD2_1),
1277         PINMUX_IPSR_MSEL(IP10_17_15, HSPI_CS1_B, SEL_HSPI1_1),
1278         PINMUX_IPSR_GPSR(IP10_17_15, ARM_TRACEDATA_15),
1279         PINMUX_IPSR_GPSR(IP10_17_15, MT1_D),
1280         PINMUX_IPSR_GPSR(IP10_17_15, TS_SDEN0),
1281         PINMUX_IPSR_GPSR(IP10_20_18, VI0_R6),
1282         PINMUX_IPSR_GPSR(IP10_20_18, ETH_MDC),
1283         PINMUX_IPSR_MSEL(IP10_20_18, DREQ2_C, SEL_EXBUS2_2),
1284         PINMUX_IPSR_GPSR(IP10_20_18, HSPI_TX1_B),
1285         PINMUX_IPSR_GPSR(IP10_20_18, TRACECLK),
1286         PINMUX_IPSR_GPSR(IP10_20_18, MT1_BEN),
1287         PINMUX_IPSR_MSEL(IP10_20_18, PWMFSW0_D, SEL_PWMFSW_3),
1288         PINMUX_IPSR_GPSR(IP10_23_21, VI0_R7),
1289         PINMUX_IPSR_GPSR(IP10_23_21, ETH_MDIO),
1290         PINMUX_IPSR_GPSR(IP10_23_21, DACK2_C),
1291         PINMUX_IPSR_MSEL(IP10_23_21, HSPI_RX1_B, SEL_HSPI1_1),
1292         PINMUX_IPSR_MSEL(IP10_23_21, SCIF_CLK_D, SEL_SCIF_3),
1293         PINMUX_IPSR_GPSR(IP10_23_21, TRACECTL),
1294         PINMUX_IPSR_GPSR(IP10_23_21, MT1_PEN),
1295         PINMUX_IPSR_GPSR(IP10_25_24, VI1_CLK),
1296         PINMUX_IPSR_MSEL(IP10_25_24, SIM_D, SEL_SIM_0),
1297         PINMUX_IPSR_MSEL(IP10_25_24, SDA3, SEL_I2C3_0),
1298         PINMUX_IPSR_GPSR(IP10_28_26, VI1_HSYNC),
1299         PINMUX_IPSR_GPSR(IP10_28_26, VI3_CLK),
1300         PINMUX_IPSR_GPSR(IP10_28_26, SSI_SCK4),
1301         PINMUX_IPSR_MSEL(IP10_28_26, GPS_SIGN_C, SEL_GPS_2),
1302         PINMUX_IPSR_MSEL(IP10_28_26, PWMFSW0_E, SEL_PWMFSW_4),
1303         PINMUX_IPSR_GPSR(IP10_31_29, VI1_VSYNC),
1304         PINMUX_IPSR_GPSR(IP10_31_29, AUDIO_CLKOUT_C),
1305         PINMUX_IPSR_GPSR(IP10_31_29, SSI_WS4),
1306         PINMUX_IPSR_GPSR(IP10_31_29, SIM_CLK),
1307         PINMUX_IPSR_MSEL(IP10_31_29, GPS_MAG_C, SEL_GPS_2),
1308         PINMUX_IPSR_GPSR(IP10_31_29, SPV_TRST),
1309         PINMUX_IPSR_MSEL(IP10_31_29, SCL3, SEL_I2C3_0),
1310
1311         PINMUX_IPSR_GPSR(IP11_2_0, VI1_DATA0_VI1_B0),
1312         PINMUX_IPSR_MSEL(IP11_2_0, SD2_DAT0, SEL_SD2_0),
1313         PINMUX_IPSR_GPSR(IP11_2_0, SIM_RST),
1314         PINMUX_IPSR_GPSR(IP11_2_0, SPV_TCK),
1315         PINMUX_IPSR_GPSR(IP11_2_0, ADICLK_B),
1316         PINMUX_IPSR_GPSR(IP11_5_3, VI1_DATA1_VI1_B1),
1317         PINMUX_IPSR_MSEL(IP11_5_3, SD2_DAT1, SEL_SD2_0),
1318         PINMUX_IPSR_GPSR(IP11_5_3, MT0_CLK),
1319         PINMUX_IPSR_GPSR(IP11_5_3, SPV_TMS),
1320         PINMUX_IPSR_MSEL(IP11_5_3, ADICS_B_SAMP_B, SEL_ADI_1),
1321         PINMUX_IPSR_GPSR(IP11_8_6, VI1_DATA2_VI1_B2),
1322         PINMUX_IPSR_MSEL(IP11_8_6, SD2_DAT2, SEL_SD2_0),
1323         PINMUX_IPSR_GPSR(IP11_8_6, MT0_D),
1324         PINMUX_IPSR_GPSR(IP11_8_6, SPVTDI),
1325         PINMUX_IPSR_MSEL(IP11_8_6, ADIDATA_B, SEL_ADI_1),
1326         PINMUX_IPSR_GPSR(IP11_11_9, VI1_DATA3_VI1_B3),
1327         PINMUX_IPSR_MSEL(IP11_11_9, SD2_DAT3, SEL_SD2_0),
1328         PINMUX_IPSR_GPSR(IP11_11_9, MT0_BEN),
1329         PINMUX_IPSR_GPSR(IP11_11_9, SPV_TDO),
1330         PINMUX_IPSR_GPSR(IP11_11_9, ADICHS0_B),
1331         PINMUX_IPSR_GPSR(IP11_14_12, VI1_DATA4_VI1_B4),
1332         PINMUX_IPSR_GPSR(IP11_14_12, SD2_CLK),
1333         PINMUX_IPSR_GPSR(IP11_14_12, MT0_PEN),
1334         PINMUX_IPSR_GPSR(IP11_14_12, SPA_TRST),
1335         PINMUX_IPSR_MSEL(IP11_14_12, HSPI_CLK1_D, SEL_HSPI1_3),
1336         PINMUX_IPSR_GPSR(IP11_14_12, ADICHS1_B),
1337         PINMUX_IPSR_GPSR(IP11_17_15, VI1_DATA5_VI1_B5),
1338         PINMUX_IPSR_MSEL(IP11_17_15, SD2_CMD, SEL_SD2_0),
1339         PINMUX_IPSR_GPSR(IP11_17_15, MT0_SYNC),
1340         PINMUX_IPSR_GPSR(IP11_17_15, SPA_TCK),
1341         PINMUX_IPSR_MSEL(IP11_17_15, HSPI_CS1_D, SEL_HSPI1_3),
1342         PINMUX_IPSR_GPSR(IP11_17_15, ADICHS2_B),
1343         PINMUX_IPSR_GPSR(IP11_20_18, VI1_DATA6_VI1_B6),
1344         PINMUX_IPSR_MSEL(IP11_20_18, SD2_CD, SEL_SD2_0),
1345         PINMUX_IPSR_GPSR(IP11_20_18, MT0_VCXO),
1346         PINMUX_IPSR_GPSR(IP11_20_18, SPA_TMS),
1347         PINMUX_IPSR_GPSR(IP11_20_18, HSPI_TX1_D),
1348         PINMUX_IPSR_GPSR(IP11_23_21, VI1_DATA7_VI1_B7),
1349         PINMUX_IPSR_MSEL(IP11_23_21, SD2_WP, SEL_SD2_0),
1350         PINMUX_IPSR_GPSR(IP11_23_21, MT0_PWM),
1351         PINMUX_IPSR_GPSR(IP11_23_21, SPA_TDI),
1352         PINMUX_IPSR_MSEL(IP11_23_21, HSPI_RX1_D, SEL_HSPI1_3),
1353         PINMUX_IPSR_GPSR(IP11_26_24, VI1_G0),
1354         PINMUX_IPSR_GPSR(IP11_26_24, VI3_DATA0),
1355         PINMUX_IPSR_GPSR(IP11_26_24, TS_SCK1),
1356         PINMUX_IPSR_MSEL(IP11_26_24, DREQ2_B, SEL_EXBUS2_1),
1357         PINMUX_IPSR_GPSR(IP11_26_24, TX2),
1358         PINMUX_IPSR_GPSR(IP11_26_24, SPA_TDO),
1359         PINMUX_IPSR_MSEL(IP11_26_24, HCTS0_B, SEL_HSCIF0_1),
1360         PINMUX_IPSR_GPSR(IP11_29_27, VI1_G1),
1361         PINMUX_IPSR_GPSR(IP11_29_27, VI3_DATA1),
1362         PINMUX_IPSR_GPSR(IP11_29_27, SSI_SCK1),
1363         PINMUX_IPSR_GPSR(IP11_29_27, TS_SDEN1),
1364         PINMUX_IPSR_GPSR(IP11_29_27, DACK2_B),
1365         PINMUX_IPSR_MSEL(IP11_29_27, RX2, SEL_SCIF2_0),
1366         PINMUX_IPSR_MSEL(IP11_29_27, HRTS0_B, SEL_HSCIF0_1),
1367
1368         PINMUX_IPSR_GPSR(IP12_2_0, VI1_G2),
1369         PINMUX_IPSR_GPSR(IP12_2_0, VI3_DATA2),
1370         PINMUX_IPSR_GPSR(IP12_2_0, SSI_WS1),
1371         PINMUX_IPSR_GPSR(IP12_2_0, TS_SPSYNC1),
1372         PINMUX_IPSR_MSEL(IP12_2_0, SCK2, SEL_SCIF2_0),
1373         PINMUX_IPSR_MSEL(IP12_2_0, HSCK0_B, SEL_HSCIF0_1),
1374         PINMUX_IPSR_GPSR(IP12_5_3, VI1_G3),
1375         PINMUX_IPSR_GPSR(IP12_5_3, VI3_DATA3),
1376         PINMUX_IPSR_GPSR(IP12_5_3, SSI_SCK2),
1377         PINMUX_IPSR_GPSR(IP12_5_3, TS_SDAT1),
1378         PINMUX_IPSR_MSEL(IP12_5_3, SCL1_C, SEL_I2C1_2),
1379         PINMUX_IPSR_GPSR(IP12_5_3, HTX0_B),
1380         PINMUX_IPSR_GPSR(IP12_8_6, VI1_G4),
1381         PINMUX_IPSR_GPSR(IP12_8_6, VI3_DATA4),
1382         PINMUX_IPSR_GPSR(IP12_8_6, SSI_WS2),
1383         PINMUX_IPSR_MSEL(IP12_8_6, SDA1_C, SEL_I2C1_2),
1384         PINMUX_IPSR_GPSR(IP12_8_6, SIM_RST_B),
1385         PINMUX_IPSR_MSEL(IP12_8_6, HRX0_B, SEL_HSCIF0_1),
1386         PINMUX_IPSR_GPSR(IP12_11_9, VI1_G5),
1387         PINMUX_IPSR_GPSR(IP12_11_9, VI3_DATA5),
1388         PINMUX_IPSR_MSEL(IP12_11_9, GPS_CLK, SEL_GPS_0),
1389         PINMUX_IPSR_GPSR(IP12_11_9, FSE),
1390         PINMUX_IPSR_GPSR(IP12_11_9, TX4_B),
1391         PINMUX_IPSR_MSEL(IP12_11_9, SIM_D_B, SEL_SIM_1),
1392         PINMUX_IPSR_GPSR(IP12_14_12, VI1_G6),
1393         PINMUX_IPSR_GPSR(IP12_14_12, VI3_DATA6),
1394         PINMUX_IPSR_MSEL(IP12_14_12, GPS_SIGN, SEL_GPS_0),
1395         PINMUX_IPSR_GPSR(IP12_14_12, FRB),
1396         PINMUX_IPSR_MSEL(IP12_14_12, RX4_B, SEL_SCIF4_1),
1397         PINMUX_IPSR_GPSR(IP12_14_12, SIM_CLK_B),
1398         PINMUX_IPSR_GPSR(IP12_17_15, VI1_G7),
1399         PINMUX_IPSR_GPSR(IP12_17_15, VI3_DATA7),
1400         PINMUX_IPSR_MSEL(IP12_17_15, GPS_MAG, SEL_GPS_0),
1401         PINMUX_IPSR_GPSR(IP12_17_15, FCE),
1402         PINMUX_IPSR_MSEL(IP12_17_15, SCK4_B, SEL_SCIF4_1),
1403 };
1404
1405 static const struct sh_pfc_pin pinmux_pins[] = {
1406         PINMUX_GPIO_GP_ALL(),
1407 };
1408
1409 /* - DU0 -------------------------------------------------------------------- */
1410 static const unsigned int du0_rgb666_pins[] = {
1411         /* R[7:2], G[7:2], B[7:2] */
1412         RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 26),
1413         RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
1414         RCAR_GP_PIN(6, 2),  RCAR_GP_PIN(6, 1),  RCAR_GP_PIN(6, 0),
1415         RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 29),
1416         RCAR_GP_PIN(6, 8),  RCAR_GP_PIN(6, 7),  RCAR_GP_PIN(6, 6),
1417         RCAR_GP_PIN(6, 5),  RCAR_GP_PIN(6, 4),  RCAR_GP_PIN(6, 3),
1418 };
1419 static const unsigned int du0_rgb666_mux[] = {
1420         DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
1421         DU0_DR3_MARK, DU0_DR2_MARK,
1422         DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
1423         DU0_DG3_MARK, DU0_DG2_MARK,
1424         DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
1425         DU0_DB3_MARK, DU0_DB2_MARK,
1426 };
1427 static const unsigned int du0_rgb888_pins[] = {
1428         /* R[7:0], G[7:0], B[7:0] */
1429         RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 26),
1430         RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
1431         RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 23), RCAR_GP_PIN(6, 2),
1432         RCAR_GP_PIN(6, 1),  RCAR_GP_PIN(6, 0),  RCAR_GP_PIN(5, 31),
1433         RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 29), RCAR_GP_PIN(0, 26),
1434         RCAR_GP_PIN(0, 25), RCAR_GP_PIN(6, 8),  RCAR_GP_PIN(6, 7),
1435         RCAR_GP_PIN(6, 6),  RCAR_GP_PIN(6, 5),  RCAR_GP_PIN(6, 4),
1436         RCAR_GP_PIN(6, 3),  RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 27),
1437 };
1438 static const unsigned int du0_rgb888_mux[] = {
1439         DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
1440         DU0_DR3_MARK, DU0_DR2_MARK, DU0_DR1_MARK, DU0_DR0_MARK,
1441         DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
1442         DU0_DG3_MARK, DU0_DG2_MARK, DU0_DG1_MARK, DU0_DG0_MARK,
1443         DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
1444         DU0_DB3_MARK, DU0_DB2_MARK, DU0_DB1_MARK, DU0_DB0_MARK,
1445 };
1446 static const unsigned int du0_clk_in_pins[] = {
1447         /* CLKIN */
1448         RCAR_GP_PIN(0, 29),
1449 };
1450 static const unsigned int du0_clk_in_mux[] = {
1451         DU0_DOTCLKIN_MARK,
1452 };
1453 static const unsigned int du0_clk_out_0_pins[] = {
1454         /* CLKOUT */
1455         RCAR_GP_PIN(5, 20),
1456 };
1457 static const unsigned int du0_clk_out_0_mux[] = {
1458         DU0_DOTCLKOUT0_MARK,
1459 };
1460 static const unsigned int du0_clk_out_1_pins[] = {
1461         /* CLKOUT */
1462         RCAR_GP_PIN(0, 30),
1463 };
1464 static const unsigned int du0_clk_out_1_mux[] = {
1465         DU0_DOTCLKOUT1_MARK,
1466 };
1467 static const unsigned int du0_sync_0_pins[] = {
1468         /* VSYNC, HSYNC, DISP */
1469         RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 21), RCAR_GP_PIN(0, 31),
1470 };
1471 static const unsigned int du0_sync_0_mux[] = {
1472         DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK,
1473         DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK
1474 };
1475 static const unsigned int du0_sync_1_pins[] = {
1476         /* VSYNC, HSYNC, DISP */
1477         RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 21), RCAR_GP_PIN(1, 0),
1478 };
1479 static const unsigned int du0_sync_1_mux[] = {
1480         DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK,
1481         DU0_DISP_MARK
1482 };
1483 static const unsigned int du0_oddf_pins[] = {
1484         /* ODDF */
1485         RCAR_GP_PIN(0, 31),
1486 };
1487 static const unsigned int du0_oddf_mux[] = {
1488         DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK
1489 };
1490 static const unsigned int du0_cde_pins[] = {
1491         /* CDE */
1492         RCAR_GP_PIN(1, 1),
1493 };
1494 static const unsigned int du0_cde_mux[] = {
1495         DU0_CDE_MARK
1496 };
1497 /* - DU1 -------------------------------------------------------------------- */
1498 static const unsigned int du1_rgb666_pins[] = {
1499         /* R[7:2], G[7:2], B[7:2] */
1500         RCAR_GP_PIN(1, 9),  RCAR_GP_PIN(1, 8),  RCAR_GP_PIN(1, 7),
1501         RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),  RCAR_GP_PIN(1, 4),
1502         RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15),
1503         RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12),
1504         RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23),
1505         RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 20),
1506 };
1507 static const unsigned int du1_rgb666_mux[] = {
1508         DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1509         DU1_DR3_MARK, DU1_DR2_MARK,
1510         DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1511         DU1_DG3_MARK, DU1_DG2_MARK,
1512         DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1513         DU1_DB3_MARK, DU1_DB2_MARK,
1514 };
1515 static const unsigned int du1_rgb888_pins[] = {
1516         /* R[7:0], G[7:0], B[7:0] */
1517         RCAR_GP_PIN(1, 9),  RCAR_GP_PIN(1, 8),  RCAR_GP_PIN(1, 7),
1518         RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),  RCAR_GP_PIN(1, 4),
1519         RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),  RCAR_GP_PIN(1, 17),
1520         RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
1521         RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 11),
1522         RCAR_GP_PIN(1, 0),  RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 24),
1523         RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
1524         RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1525 };
1526 static const unsigned int du1_rgb888_mux[] = {
1527         DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1528         DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
1529         DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1530         DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
1531         DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1532         DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
1533 };
1534 static const unsigned int du1_clk_in_pins[] = {
1535         /* CLKIN */
1536         RCAR_GP_PIN(1, 26),
1537 };
1538 static const unsigned int du1_clk_in_mux[] = {
1539         DU1_DOTCLKIN_MARK,
1540 };
1541 static const unsigned int du1_clk_out_pins[] = {
1542         /* CLKOUT */
1543         RCAR_GP_PIN(1, 27),
1544 };
1545 static const unsigned int du1_clk_out_mux[] = {
1546         DU1_DOTCLKOUT_MARK,
1547 };
1548 static const unsigned int du1_sync_0_pins[] = {
1549         /* VSYNC, HSYNC, DISP */
1550         RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 30),
1551 };
1552 static const unsigned int du1_sync_0_mux[] = {
1553         DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
1554         DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK
1555 };
1556 static const unsigned int du1_sync_1_pins[] = {
1557         /* VSYNC, HSYNC, DISP */
1558         RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 31),
1559 };
1560 static const unsigned int du1_sync_1_mux[] = {
1561         DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
1562         DU1_DISP_MARK
1563 };
1564 static const unsigned int du1_oddf_pins[] = {
1565         /* ODDF */
1566         RCAR_GP_PIN(1, 30),
1567 };
1568 static const unsigned int du1_oddf_mux[] = {
1569         DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK
1570 };
1571 static const unsigned int du1_cde_pins[] = {
1572         /* CDE */
1573         RCAR_GP_PIN(2, 0),
1574 };
1575 static const unsigned int du1_cde_mux[] = {
1576         DU1_CDE_MARK
1577 };
1578 /* - Ether ------------------------------------------------------------------ */
1579 static const unsigned int ether_rmii_pins[] = {
1580         /*
1581          * ETH_TXD0, ETH_TXD1, ETH_TX_EN,  ETH_REFCLK,
1582          * ETH_RXD0, ETH_RXD1, ETH_CRS_DV, ETH_RX_ER,
1583          * ETH_MDIO, ETH_MDC
1584          */
1585         RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 18),
1586         RCAR_GP_PIN(2, 26),
1587         RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 17),
1588         RCAR_GP_PIN(2, 19),
1589         RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 28),
1590 };
1591 static const unsigned int ether_rmii_mux[] = {
1592         ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK,  ETH_REFCLK_MARK,
1593         ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_CRS_DV_MARK, ETH_RX_ER_MARK,
1594         ETH_MDIO_MARK, ETH_MDC_MARK,
1595 };
1596 static const unsigned int ether_link_pins[] = {
1597         /* ETH_LINK */
1598         RCAR_GP_PIN(2, 24),
1599 };
1600 static const unsigned int ether_link_mux[] = {
1601         ETH_LINK_MARK,
1602 };
1603 static const unsigned int ether_magic_pins[] = {
1604         /* ETH_MAGIC */
1605         RCAR_GP_PIN(2, 25),
1606 };
1607 static const unsigned int ether_magic_mux[] = {
1608         ETH_MAGIC_MARK,
1609 };
1610 /* - HSPI0 ------------------------------------------------------------------ */
1611 static const unsigned int hspi0_pins[] = {
1612         /* CLK, CS, RX, TX */
1613         RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 25),
1614         RCAR_GP_PIN(4, 24),
1615 };
1616 static const unsigned int hspi0_mux[] = {
1617         HSPI_CLK0_MARK, HSPI_CS0_MARK, HSPI_RX0_MARK, HSPI_TX0_MARK,
1618 };
1619 /* - HSPI1 ------------------------------------------------------------------ */
1620 static const unsigned int hspi1_pins[] = {
1621         /* CLK, CS, RX, TX */
1622         RCAR_GP_PIN(1, 31), RCAR_GP_PIN(1, 26), RCAR_GP_PIN(2, 0),
1623         RCAR_GP_PIN(1, 30),
1624 };
1625 static const unsigned int hspi1_mux[] = {
1626         HSPI_CLK1_MARK, HSPI_CS1_MARK, HSPI_RX1_MARK, HSPI_TX1_MARK,
1627 };
1628 static const unsigned int hspi1_b_pins[] = {
1629         /* CLK, CS, RX, TX */
1630         RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 29),
1631         RCAR_GP_PIN(2, 28),
1632 };
1633 static const unsigned int hspi1_b_mux[] = {
1634         HSPI_CLK1_B_MARK, HSPI_CS1_B_MARK, HSPI_RX1_B_MARK, HSPI_TX1_B_MARK,
1635 };
1636 static const unsigned int hspi1_c_pins[] = {
1637         /* CLK, CS, RX, TX */
1638         RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 16),
1639         RCAR_GP_PIN(4, 15),
1640 };
1641 static const unsigned int hspi1_c_mux[] = {
1642         HSPI_CLK1_C_MARK, HSPI_CS1_C_MARK, HSPI_RX1_C_MARK, HSPI_TX1_C_MARK,
1643 };
1644 static const unsigned int hspi1_d_pins[] = {
1645         /* CLK, CS, RX, TX */
1646         RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 8),
1647         RCAR_GP_PIN(3, 7),
1648 };
1649 static const unsigned int hspi1_d_mux[] = {
1650         HSPI_CLK1_D_MARK, HSPI_CS1_D_MARK, HSPI_RX1_D_MARK, HSPI_TX1_D_MARK,
1651 };
1652 /* - HSPI2 ------------------------------------------------------------------ */
1653 static const unsigned int hspi2_pins[] = {
1654         /* CLK, CS, RX, TX */
1655         RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
1656         RCAR_GP_PIN(0, 14),
1657 };
1658 static const unsigned int hspi2_mux[] = {
1659         HSPI_CLK2_MARK, HSPI_CS2_MARK, HSPI_RX2_MARK, HSPI_TX2_MARK,
1660 };
1661 static const unsigned int hspi2_b_pins[] = {
1662         /* CLK, CS, RX, TX */
1663         RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 8),
1664         RCAR_GP_PIN(0, 6),
1665 };
1666 static const unsigned int hspi2_b_mux[] = {
1667         HSPI_CLK2_B_MARK, HSPI_CS2_B_MARK, HSPI_RX2_B_MARK, HSPI_TX2_B_MARK,
1668 };
1669 /* - I2C1 ------------------------------------------------------------------ */
1670 static const unsigned int i2c1_pins[] = {
1671         /* SCL, SDA, */
1672         RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
1673 };
1674 static const unsigned int i2c1_mux[] = {
1675         SCL1_MARK, SDA1_MARK,
1676 };
1677 static const unsigned int i2c1_b_pins[] = {
1678         /* SCL, SDA, */
1679         RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11),
1680 };
1681 static const unsigned int i2c1_b_mux[] = {
1682         SCL1_B_MARK, SDA1_B_MARK,
1683 };
1684 static const unsigned int i2c1_c_pins[] = {
1685         /* SCL, SDA, */
1686         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
1687 };
1688 static const unsigned int i2c1_c_mux[] = {
1689         SCL1_C_MARK, SDA1_C_MARK,
1690 };
1691 static const unsigned int i2c1_d_pins[] = {
1692         /* SCL, SDA, */
1693         RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 27),
1694 };
1695 static const unsigned int i2c1_d_mux[] = {
1696         SCL1_D_MARK, SDA1_D_MARK,
1697 };
1698 /* - I2C2 ------------------------------------------------------------------ */
1699 static const unsigned int i2c2_pins[] = {
1700         /* SCL, SDA, */
1701         RCAR_GP_PIN(0, 25), RCAR_GP_PIN(0, 26),
1702 };
1703 static const unsigned int i2c2_mux[] = {
1704         SCL2_MARK, SDA2_MARK,
1705 };
1706 static const unsigned int i2c2_b_pins[] = {
1707         /* SCL, SDA, */
1708         RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
1709 };
1710 static const unsigned int i2c2_b_mux[] = {
1711         SCL2_B_MARK, SDA2_B_MARK,
1712 };
1713 static const unsigned int i2c2_c_pins[] = {
1714         /* SCL, SDA */
1715         RCAR_GP_PIN(0, 31), RCAR_GP_PIN(0, 30),
1716 };
1717 static const unsigned int i2c2_c_mux[] = {
1718         SCL2_C_MARK, SDA2_C_MARK,
1719 };
1720 static const unsigned int i2c2_d_pins[] = {
1721         /* SCL, SDA */
1722         RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 25),
1723 };
1724 static const unsigned int i2c2_d_mux[] = {
1725         SCL2_D_MARK, SDA2_D_MARK,
1726 };
1727 /* - I2C3 ------------------------------------------------------------------ */
1728 static const unsigned int i2c3_pins[] = {
1729         /* SCL, SDA, */
1730         RCAR_GP_PIN(3, 0), RCAR_GP_PIN(2, 30),
1731 };
1732 static const unsigned int i2c3_mux[] = {
1733         SCL3_MARK, SDA3_MARK,
1734 };
1735 static const unsigned int i2c3_b_pins[] = {
1736         /* SCL, SDA, */
1737         RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 30),
1738 };
1739 static const unsigned int i2c3_b_mux[] = {
1740         SCL3_B_MARK, SDA3_B_MARK,
1741 };
1742 /* - INTC ------------------------------------------------------------------- */
1743 static const unsigned int intc_irq0_pins[] = {
1744         /* IRQ */
1745         RCAR_GP_PIN(2, 14),
1746 };
1747 static const unsigned int intc_irq0_mux[] = {
1748         IRQ0_MARK,
1749 };
1750 static const unsigned int intc_irq0_b_pins[] = {
1751         /* IRQ */
1752         RCAR_GP_PIN(4, 13),
1753 };
1754 static const unsigned int intc_irq0_b_mux[] = {
1755         IRQ0_B_MARK,
1756 };
1757 static const unsigned int intc_irq1_pins[] = {
1758         /* IRQ */
1759         RCAR_GP_PIN(2, 15),
1760 };
1761 static const unsigned int intc_irq1_mux[] = {
1762         IRQ1_MARK,
1763 };
1764 static const unsigned int intc_irq1_b_pins[] = {
1765         /* IRQ */
1766         RCAR_GP_PIN(4, 14),
1767 };
1768 static const unsigned int intc_irq1_b_mux[] = {
1769         IRQ1_B_MARK,
1770 };
1771 static const unsigned int intc_irq2_pins[] = {
1772         /* IRQ */
1773         RCAR_GP_PIN(2, 24),
1774 };
1775 static const unsigned int intc_irq2_mux[] = {
1776         IRQ2_MARK,
1777 };
1778 static const unsigned int intc_irq2_b_pins[] = {
1779         /* IRQ */
1780         RCAR_GP_PIN(4, 15),
1781 };
1782 static const unsigned int intc_irq2_b_mux[] = {
1783         IRQ2_B_MARK,
1784 };
1785 static const unsigned int intc_irq3_pins[] = {
1786         /* IRQ */
1787         RCAR_GP_PIN(2, 25),
1788 };
1789 static const unsigned int intc_irq3_mux[] = {
1790         IRQ3_MARK,
1791 };
1792 static const unsigned int intc_irq3_b_pins[] = {
1793         /* IRQ */
1794         RCAR_GP_PIN(4, 16),
1795 };
1796 static const unsigned int intc_irq3_b_mux[] = {
1797         IRQ3_B_MARK,
1798 };
1799 /* - LSBC ------------------------------------------------------------------- */
1800 static const unsigned int lbsc_cs0_pins[] = {
1801         /* CS */
1802         RCAR_GP_PIN(0, 13),
1803 };
1804 static const unsigned int lbsc_cs0_mux[] = {
1805         CS0_MARK,
1806 };
1807 static const unsigned int lbsc_cs1_pins[] = {
1808         /* CS */
1809         RCAR_GP_PIN(0, 14),
1810 };
1811 static const unsigned int lbsc_cs1_mux[] = {
1812         CS1_A26_MARK,
1813 };
1814 static const unsigned int lbsc_ex_cs0_pins[] = {
1815         /* CS */
1816         RCAR_GP_PIN(0, 15),
1817 };
1818 static const unsigned int lbsc_ex_cs0_mux[] = {
1819         EX_CS0_MARK,
1820 };
1821 static const unsigned int lbsc_ex_cs1_pins[] = {
1822         /* CS */
1823         RCAR_GP_PIN(0, 16),
1824 };
1825 static const unsigned int lbsc_ex_cs1_mux[] = {
1826         EX_CS1_MARK,
1827 };
1828 static const unsigned int lbsc_ex_cs2_pins[] = {
1829         /* CS */
1830         RCAR_GP_PIN(0, 17),
1831 };
1832 static const unsigned int lbsc_ex_cs2_mux[] = {
1833         EX_CS2_MARK,
1834 };
1835 static const unsigned int lbsc_ex_cs3_pins[] = {
1836         /* CS */
1837         RCAR_GP_PIN(0, 18),
1838 };
1839 static const unsigned int lbsc_ex_cs3_mux[] = {
1840         EX_CS3_MARK,
1841 };
1842 static const unsigned int lbsc_ex_cs4_pins[] = {
1843         /* CS */
1844         RCAR_GP_PIN(0, 19),
1845 };
1846 static const unsigned int lbsc_ex_cs4_mux[] = {
1847         EX_CS4_MARK,
1848 };
1849 static const unsigned int lbsc_ex_cs5_pins[] = {
1850         /* CS */
1851         RCAR_GP_PIN(0, 20),
1852 };
1853 static const unsigned int lbsc_ex_cs5_mux[] = {
1854         EX_CS5_MARK,
1855 };
1856 /* - MMCIF ------------------------------------------------------------------ */
1857 static const unsigned int mmc0_data1_pins[] = {
1858         /* D[0] */
1859         RCAR_GP_PIN(0, 19),
1860 };
1861 static const unsigned int mmc0_data1_mux[] = {
1862         MMC0_D0_MARK,
1863 };
1864 static const unsigned int mmc0_data4_pins[] = {
1865         /* D[0:3] */
1866         RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21),
1867         RCAR_GP_PIN(0, 2),
1868 };
1869 static const unsigned int mmc0_data4_mux[] = {
1870         MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
1871 };
1872 static const unsigned int mmc0_data8_pins[] = {
1873         /* D[0:7] */
1874         RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21),
1875         RCAR_GP_PIN(0, 2),  RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
1876         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
1877 };
1878 static const unsigned int mmc0_data8_mux[] = {
1879         MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
1880         MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK,
1881 };
1882 static const unsigned int mmc0_ctrl_pins[] = {
1883         /* CMD, CLK */
1884         RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 17),
1885 };
1886 static const unsigned int mmc0_ctrl_mux[] = {
1887         MMC0_CMD_MARK, MMC0_CLK_MARK,
1888 };
1889 static const unsigned int mmc1_data1_pins[] = {
1890         /* D[0] */
1891         RCAR_GP_PIN(2, 8),
1892 };
1893 static const unsigned int mmc1_data1_mux[] = {
1894         MMC1_D0_MARK,
1895 };
1896 static const unsigned int mmc1_data4_pins[] = {
1897         /* D[0:3] */
1898         RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
1899         RCAR_GP_PIN(2, 11),
1900 };
1901 static const unsigned int mmc1_data4_mux[] = {
1902         MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
1903 };
1904 static const unsigned int mmc1_data8_pins[] = {
1905         /* D[0:7] */
1906         RCAR_GP_PIN(2, 8),  RCAR_GP_PIN(2, 9),  RCAR_GP_PIN(2, 10),
1907         RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
1908         RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
1909 };
1910 static const unsigned int mmc1_data8_mux[] = {
1911         MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
1912         MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK,
1913 };
1914 static const unsigned int mmc1_ctrl_pins[] = {
1915         /* CMD, CLK */
1916         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 1),
1917 };
1918 static const unsigned int mmc1_ctrl_mux[] = {
1919         MMC1_CMD_MARK, MMC1_CLK_MARK,
1920 };
1921 /* - SCIF0 ------------------------------------------------------------------ */
1922 static const unsigned int scif0_data_pins[] = {
1923         /* RXD, TXD */
1924         RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24),
1925 };
1926 static const unsigned int scif0_data_mux[] = {
1927         RX0_MARK, TX0_MARK,
1928 };
1929 static const unsigned int scif0_clk_pins[] = {
1930         /* SCK */
1931         RCAR_GP_PIN(4, 28),
1932 };
1933 static const unsigned int scif0_clk_mux[] = {
1934         SCK0_MARK,
1935 };
1936 static const unsigned int scif0_ctrl_pins[] = {
1937         /* RTS, CTS */
1938         RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 22),
1939 };
1940 static const unsigned int scif0_ctrl_mux[] = {
1941         RTS0_TANS_MARK, CTS0_MARK,
1942 };
1943 static const unsigned int scif0_data_b_pins[] = {
1944         /* RXD, TXD */
1945         RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
1946 };
1947 static const unsigned int scif0_data_b_mux[] = {
1948         RX0_B_MARK, TX0_B_MARK,
1949 };
1950 static const unsigned int scif0_clk_b_pins[] = {
1951         /* SCK */
1952         RCAR_GP_PIN(1, 1),
1953 };
1954 static const unsigned int scif0_clk_b_mux[] = {
1955         SCK0_B_MARK,
1956 };
1957 static const unsigned int scif0_ctrl_b_pins[] = {
1958         /* RTS, CTS */
1959         RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 11),
1960 };
1961 static const unsigned int scif0_ctrl_b_mux[] = {
1962         RTS0_B_TANS_B_MARK, CTS0_B_MARK,
1963 };
1964 static const unsigned int scif0_data_c_pins[] = {
1965         /* RXD, TXD */
1966         RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 19),
1967 };
1968 static const unsigned int scif0_data_c_mux[] = {
1969         RX0_C_MARK, TX0_C_MARK,
1970 };
1971 static const unsigned int scif0_clk_c_pins[] = {
1972         /* SCK */
1973         RCAR_GP_PIN(4, 17),
1974 };
1975 static const unsigned int scif0_clk_c_mux[] = {
1976         SCK0_C_MARK,
1977 };
1978 static const unsigned int scif0_ctrl_c_pins[] = {
1979         /* RTS, CTS */
1980         RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
1981 };
1982 static const unsigned int scif0_ctrl_c_mux[] = {
1983         RTS0_C_TANS_C_MARK, CTS0_C_MARK,
1984 };
1985 static const unsigned int scif0_data_d_pins[] = {
1986         /* RXD, TXD */
1987         RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10),
1988 };
1989 static const unsigned int scif0_data_d_mux[] = {
1990         RX0_D_MARK, TX0_D_MARK,
1991 };
1992 static const unsigned int scif0_clk_d_pins[] = {
1993         /* SCK */
1994         RCAR_GP_PIN(1, 18),
1995 };
1996 static const unsigned int scif0_clk_d_mux[] = {
1997         SCK0_D_MARK,
1998 };
1999 static const unsigned int scif0_ctrl_d_pins[] = {
2000         /* RTS, CTS */
2001         RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 3),
2002 };
2003 static const unsigned int scif0_ctrl_d_mux[] = {
2004         RTS0_D_TANS_D_MARK, CTS0_D_MARK,
2005 };
2006 /* - SCIF1 ------------------------------------------------------------------ */
2007 static const unsigned int scif1_data_pins[] = {
2008         /* RXD, TXD */
2009         RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
2010 };
2011 static const unsigned int scif1_data_mux[] = {
2012         RX1_MARK, TX1_MARK,
2013 };
2014 static const unsigned int scif1_clk_pins[] = {
2015         /* SCK */
2016         RCAR_GP_PIN(4, 17),
2017 };
2018 static const unsigned int scif1_clk_mux[] = {
2019         SCK1_MARK,
2020 };
2021 static const unsigned int scif1_ctrl_pins[] = {
2022         /* RTS, CTS */
2023         RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
2024 };
2025 static const unsigned int scif1_ctrl_mux[] = {
2026         RTS1_TANS_MARK, CTS1_MARK,
2027 };
2028 static const unsigned int scif1_data_b_pins[] = {
2029         /* RXD, TXD */
2030         RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 18),
2031 };
2032 static const unsigned int scif1_data_b_mux[] = {
2033         RX1_B_MARK, TX1_B_MARK,
2034 };
2035 static const unsigned int scif1_clk_b_pins[] = {
2036         /* SCK */
2037         RCAR_GP_PIN(3, 17),
2038 };
2039 static const unsigned int scif1_clk_b_mux[] = {
2040         SCK1_B_MARK,
2041 };
2042 static const unsigned int scif1_ctrl_b_pins[] = {
2043         /* RTS, CTS */
2044         RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
2045 };
2046 static const unsigned int scif1_ctrl_b_mux[] = {
2047         RTS1_B_TANS_B_MARK, CTS1_B_MARK,
2048 };
2049 static const unsigned int scif1_data_c_pins[] = {
2050         /* RXD, TXD */
2051         RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
2052 };
2053 static const unsigned int scif1_data_c_mux[] = {
2054         RX1_C_MARK, TX1_C_MARK,
2055 };
2056 static const unsigned int scif1_clk_c_pins[] = {
2057         /* SCK */
2058         RCAR_GP_PIN(2, 22),
2059 };
2060 static const unsigned int scif1_clk_c_mux[] = {
2061         SCK1_C_MARK,
2062 };
2063 static const unsigned int scif1_ctrl_c_pins[] = {
2064         /* RTS, CTS */
2065         RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2066 };
2067 static const unsigned int scif1_ctrl_c_mux[] = {
2068         RTS1_C_TANS_C_MARK, CTS1_C_MARK,
2069 };
2070 /* - SCIF2 ------------------------------------------------------------------ */
2071 static const unsigned int scif2_data_pins[] = {
2072         /* RXD, TXD */
2073         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 9),
2074 };
2075 static const unsigned int scif2_data_mux[] = {
2076         RX2_MARK, TX2_MARK,
2077 };
2078 static const unsigned int scif2_clk_pins[] = {
2079         /* SCK */
2080         RCAR_GP_PIN(3, 11),
2081 };
2082 static const unsigned int scif2_clk_mux[] = {
2083         SCK2_MARK,
2084 };
2085 static const unsigned int scif2_data_b_pins[] = {
2086         /* RXD, TXD */
2087         RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 23),
2088 };
2089 static const unsigned int scif2_data_b_mux[] = {
2090         RX2_B_MARK, TX2_B_MARK,
2091 };
2092 static const unsigned int scif2_clk_b_pins[] = {
2093         /* SCK */
2094         RCAR_GP_PIN(3, 22),
2095 };
2096 static const unsigned int scif2_clk_b_mux[] = {
2097         SCK2_B_MARK,
2098 };
2099 static const unsigned int scif2_data_c_pins[] = {
2100         /* RXD, TXD */
2101         RCAR_GP_PIN(1, 1), RCAR_GP_PIN(0, 31),
2102 };
2103 static const unsigned int scif2_data_c_mux[] = {
2104         RX2_C_MARK, TX2_C_MARK,
2105 };
2106 static const unsigned int scif2_clk_c_pins[] = {
2107         /* SCK */
2108         RCAR_GP_PIN(1, 0),
2109 };
2110 static const unsigned int scif2_clk_c_mux[] = {
2111         SCK2_C_MARK,
2112 };
2113 static const unsigned int scif2_data_d_pins[] = {
2114         /* RXD, TXD */
2115         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(1, 30),
2116 };
2117 static const unsigned int scif2_data_d_mux[] = {
2118         RX2_D_MARK, TX2_D_MARK,
2119 };
2120 static const unsigned int scif2_clk_d_pins[] = {
2121         /* SCK */
2122         RCAR_GP_PIN(1, 31),
2123 };
2124 static const unsigned int scif2_clk_d_mux[] = {
2125         SCK2_D_MARK,
2126 };
2127 static const unsigned int scif2_data_e_pins[] = {
2128         /* RXD, TXD */
2129         RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
2130 };
2131 static const unsigned int scif2_data_e_mux[] = {
2132         RX2_E_MARK, TX2_E_MARK,
2133 };
2134 /* - SCIF3 ------------------------------------------------------------------ */
2135 static const unsigned int scif3_data_pins[] = {
2136         /* RXD, TXD */
2137         RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 8),
2138 };
2139 static const unsigned int scif3_data_mux[] = {
2140         RX3_IRDA_RX_MARK, TX3_IRDA_TX_MARK,
2141 };
2142 static const unsigned int scif3_clk_pins[] = {
2143         /* SCK */
2144         RCAR_GP_PIN(4, 7),
2145 };
2146 static const unsigned int scif3_clk_mux[] = {
2147         SCK3_MARK,
2148 };
2149
2150 static const unsigned int scif3_data_b_pins[] = {
2151         /* RXD, TXD */
2152         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(1, 30),
2153 };
2154 static const unsigned int scif3_data_b_mux[] = {
2155         RX3_B_IRDA_RX_B_MARK, TX3_B_IRDA_TX_B_MARK,
2156 };
2157 static const unsigned int scif3_data_c_pins[] = {
2158         /* RXD, TXD */
2159         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 12),
2160 };
2161 static const unsigned int scif3_data_c_mux[] = {
2162         RX3_C_IRDA_RX_C_MARK, TX3C_IRDA_TX_C_MARK,
2163 };
2164 static const unsigned int scif3_data_d_pins[] = {
2165         /* RXD, TXD */
2166         RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 29),
2167 };
2168 static const unsigned int scif3_data_d_mux[] = {
2169         RX3_D_IRDA_RX_D_MARK, TX3_D_IRDA_TX_D_MARK,
2170 };
2171 static const unsigned int scif3_data_e_pins[] = {
2172         /* RXD, TXD */
2173         RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2174 };
2175 static const unsigned int scif3_data_e_mux[] = {
2176         RX3_E_IRDA_RX_E_MARK, TX3_E_IRDA_TX_E_MARK,
2177 };
2178 static const unsigned int scif3_clk_e_pins[] = {
2179         /* SCK */
2180         RCAR_GP_PIN(1, 10),
2181 };
2182 static const unsigned int scif3_clk_e_mux[] = {
2183         SCK3_E_MARK,
2184 };
2185 /* - SCIF4 ------------------------------------------------------------------ */
2186 static const unsigned int scif4_data_pins[] = {
2187         /* RXD, TXD */
2188         RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 26),
2189 };
2190 static const unsigned int scif4_data_mux[] = {
2191         RX4_MARK, TX4_MARK,
2192 };
2193 static const unsigned int scif4_clk_pins[] = {
2194         /* SCK */
2195         RCAR_GP_PIN(3, 25),
2196 };
2197 static const unsigned int scif4_clk_mux[] = {
2198         SCK4_MARK,
2199 };
2200 static const unsigned int scif4_data_b_pins[] = {
2201         /* RXD, TXD */
2202         RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14),
2203 };
2204 static const unsigned int scif4_data_b_mux[] = {
2205         RX4_B_MARK, TX4_B_MARK,
2206 };
2207 static const unsigned int scif4_clk_b_pins[] = {
2208         /* SCK */
2209         RCAR_GP_PIN(3, 16),
2210 };
2211 static const unsigned int scif4_clk_b_mux[] = {
2212         SCK4_B_MARK,
2213 };
2214 static const unsigned int scif4_data_c_pins[] = {
2215         /* RXD, TXD */
2216         RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 21),
2217 };
2218 static const unsigned int scif4_data_c_mux[] = {
2219         RX4_C_MARK, TX4_C_MARK,
2220 };
2221 static const unsigned int scif4_data_d_pins[] = {
2222         /* RXD, TXD */
2223         RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2224 };
2225 static const unsigned int scif4_data_d_mux[] = {
2226         RX4_D_MARK, TX4_D_MARK,
2227 };
2228 /* - SCIF5 ------------------------------------------------------------------ */
2229 static const unsigned int scif5_data_pins[] = {
2230         /* RXD, TXD */
2231         RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2232 };
2233 static const unsigned int scif5_data_mux[] = {
2234         RX5_MARK, TX5_MARK,
2235 };
2236 static const unsigned int scif5_clk_pins[] = {
2237         /* SCK */
2238         RCAR_GP_PIN(1, 11),
2239 };
2240 static const unsigned int scif5_clk_mux[] = {
2241         SCK5_MARK,
2242 };
2243 static const unsigned int scif5_data_b_pins[] = {
2244         /* RXD, TXD */
2245         RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 11),
2246 };
2247 static const unsigned int scif5_data_b_mux[] = {
2248         RX5_B_MARK, TX5_B_MARK,
2249 };
2250 static const unsigned int scif5_clk_b_pins[] = {
2251         /* SCK */
2252         RCAR_GP_PIN(0, 19),
2253 };
2254 static const unsigned int scif5_clk_b_mux[] = {
2255         SCK5_B_MARK,
2256 };
2257 static const unsigned int scif5_data_c_pins[] = {
2258         /* RXD, TXD */
2259         RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 23),
2260 };
2261 static const unsigned int scif5_data_c_mux[] = {
2262         RX5_C_MARK, TX5_C_MARK,
2263 };
2264 static const unsigned int scif5_clk_c_pins[] = {
2265         /* SCK */
2266         RCAR_GP_PIN(0, 28),
2267 };
2268 static const unsigned int scif5_clk_c_mux[] = {
2269         SCK5_C_MARK,
2270 };
2271 static const unsigned int scif5_data_d_pins[] = {
2272         /* RXD, TXD */
2273         RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 6),
2274 };
2275 static const unsigned int scif5_data_d_mux[] = {
2276         RX5_D_MARK, TX5_D_MARK,
2277 };
2278 static const unsigned int scif5_clk_d_pins[] = {
2279         /* SCK */
2280         RCAR_GP_PIN(0, 7),
2281 };
2282 static const unsigned int scif5_clk_d_mux[] = {
2283         SCK5_D_MARK,
2284 };
2285 /* - SCIF Clock ------------------------------------------------------------- */
2286 static const unsigned int scif_clk_pins[] = {
2287         /* SCIF_CLK */
2288         RCAR_GP_PIN(4, 28),
2289 };
2290 static const unsigned int scif_clk_mux[] = {
2291         SCIF_CLK_MARK,
2292 };
2293 static const unsigned int scif_clk_b_pins[] = {
2294         /* SCIF_CLK */
2295         RCAR_GP_PIN(4, 5),
2296 };
2297 static const unsigned int scif_clk_b_mux[] = {
2298         SCIF_CLK_B_MARK,
2299 };
2300 static const unsigned int scif_clk_c_pins[] = {
2301         /* SCIF_CLK */
2302         RCAR_GP_PIN(4, 18),
2303 };
2304 static const unsigned int scif_clk_c_mux[] = {
2305         SCIF_CLK_C_MARK,
2306 };
2307 static const unsigned int scif_clk_d_pins[] = {
2308         /* SCIF_CLK */
2309         RCAR_GP_PIN(2, 29),
2310 };
2311 static const unsigned int scif_clk_d_mux[] = {
2312         SCIF_CLK_D_MARK,
2313 };
2314 /* - SDHI0 ------------------------------------------------------------------ */
2315 static const unsigned int sdhi0_data1_pins[] = {
2316         /* D0 */
2317         RCAR_GP_PIN(3, 21),
2318 };
2319 static const unsigned int sdhi0_data1_mux[] = {
2320         SD0_DAT0_MARK,
2321 };
2322 static const unsigned int sdhi0_data4_pins[] = {
2323         /* D[0:3] */
2324         RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
2325         RCAR_GP_PIN(3, 24),
2326 };
2327 static const unsigned int sdhi0_data4_mux[] = {
2328         SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
2329 };
2330 static const unsigned int sdhi0_ctrl_pins[] = {
2331         /* CMD, CLK */
2332         RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 17),
2333 };
2334 static const unsigned int sdhi0_ctrl_mux[] = {
2335         SD0_CMD_MARK, SD0_CLK_MARK,
2336 };
2337 static const unsigned int sdhi0_cd_pins[] = {
2338         /* CD */
2339         RCAR_GP_PIN(3, 19),
2340 };
2341 static const unsigned int sdhi0_cd_mux[] = {
2342         SD0_CD_MARK,
2343 };
2344 static const unsigned int sdhi0_wp_pins[] = {
2345         /* WP */
2346         RCAR_GP_PIN(3, 20),
2347 };
2348 static const unsigned int sdhi0_wp_mux[] = {
2349         SD0_WP_MARK,
2350 };
2351 /* - SDHI1 ------------------------------------------------------------------ */
2352 static const unsigned int sdhi1_data1_pins[] = {
2353         /* D0 */
2354         RCAR_GP_PIN(0, 19),
2355 };
2356 static const unsigned int sdhi1_data1_mux[] = {
2357         SD1_DAT0_MARK,
2358 };
2359 static const unsigned int sdhi1_data4_pins[] = {
2360         /* D[0:3] */
2361         RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21),
2362         RCAR_GP_PIN(0, 2),
2363 };
2364 static const unsigned int sdhi1_data4_mux[] = {
2365         SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK,
2366 };
2367 static const unsigned int sdhi1_ctrl_pins[] = {
2368         /* CMD, CLK */
2369         RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 17),
2370 };
2371 static const unsigned int sdhi1_ctrl_mux[] = {
2372         SD1_CMD_MARK, SD1_CLK_MARK,
2373 };
2374 static const unsigned int sdhi1_cd_pins[] = {
2375         /* CD */
2376         RCAR_GP_PIN(0, 10),
2377 };
2378 static const unsigned int sdhi1_cd_mux[] = {
2379         SD1_CD_MARK,
2380 };
2381 static const unsigned int sdhi1_wp_pins[] = {
2382         /* WP */
2383         RCAR_GP_PIN(0, 11),
2384 };
2385 static const unsigned int sdhi1_wp_mux[] = {
2386         SD1_WP_MARK,
2387 };
2388 /* - SDHI2 ------------------------------------------------------------------ */
2389 static const unsigned int sdhi2_data1_pins[] = {
2390         /* D0 */
2391         RCAR_GP_PIN(3, 1),
2392 };
2393 static const unsigned int sdhi2_data1_mux[] = {
2394         SD2_DAT0_MARK,
2395 };
2396 static const unsigned int sdhi2_data4_pins[] = {
2397         /* D[0:3] */
2398         RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
2399         RCAR_GP_PIN(3, 4),
2400 };
2401 static const unsigned int sdhi2_data4_mux[] = {
2402         SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
2403 };
2404 static const unsigned int sdhi2_ctrl_pins[] = {
2405         /* CMD, CLK */
2406         RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 5),
2407 };
2408 static const unsigned int sdhi2_ctrl_mux[] = {
2409         SD2_CMD_MARK, SD2_CLK_MARK,
2410 };
2411 static const unsigned int sdhi2_cd_pins[] = {
2412         /* CD */
2413         RCAR_GP_PIN(3, 7),
2414 };
2415 static const unsigned int sdhi2_cd_mux[] = {
2416         SD2_CD_MARK,
2417 };
2418 static const unsigned int sdhi2_wp_pins[] = {
2419         /* WP */
2420         RCAR_GP_PIN(3, 8),
2421 };
2422 static const unsigned int sdhi2_wp_mux[] = {
2423         SD2_WP_MARK,
2424 };
2425 /* - SDHI3 ------------------------------------------------------------------ */
2426 static const unsigned int sdhi3_data1_pins[] = {
2427         /* D0 */
2428         RCAR_GP_PIN(1, 18),
2429 };
2430 static const unsigned int sdhi3_data1_mux[] = {
2431         SD3_DAT0_MARK,
2432 };
2433 static const unsigned int sdhi3_data4_pins[] = {
2434         /* D[0:3] */
2435         RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 20),
2436         RCAR_GP_PIN(1, 21),
2437 };
2438 static const unsigned int sdhi3_data4_mux[] = {
2439         SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK,
2440 };
2441 static const unsigned int sdhi3_ctrl_pins[] = {
2442         /* CMD, CLK */
2443         RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2444 };
2445 static const unsigned int sdhi3_ctrl_mux[] = {
2446         SD3_CMD_MARK, SD3_CLK_MARK,
2447 };
2448 static const unsigned int sdhi3_cd_pins[] = {
2449         /* CD */
2450         RCAR_GP_PIN(1, 30),
2451 };
2452 static const unsigned int sdhi3_cd_mux[] = {
2453         SD3_CD_MARK,
2454 };
2455 static const unsigned int sdhi3_wp_pins[] = {
2456         /* WP */
2457         RCAR_GP_PIN(2, 0),
2458 };
2459 static const unsigned int sdhi3_wp_mux[] = {
2460         SD3_WP_MARK,
2461 };
2462 /* - USB0 ------------------------------------------------------------------- */
2463 static const unsigned int usb0_pins[] = {
2464         /* PENC */
2465         RCAR_GP_PIN(4, 26),
2466 };
2467 static const unsigned int usb0_mux[] = {
2468         USB_PENC0_MARK,
2469 };
2470 static const unsigned int usb0_ovc_pins[] = {
2471         /* USB_OVC */
2472         RCAR_GP_PIN(4, 22),
2473 };
2474 static const unsigned int usb0_ovc_mux[] = {
2475         USB_OVC0_MARK,
2476 };
2477 /* - USB1 ------------------------------------------------------------------- */
2478 static const unsigned int usb1_pins[] = {
2479         /* PENC */
2480         RCAR_GP_PIN(4, 27),
2481 };
2482 static const unsigned int usb1_mux[] = {
2483         USB_PENC1_MARK,
2484 };
2485 static const unsigned int usb1_ovc_pins[] = {
2486         /* USB_OVC */
2487         RCAR_GP_PIN(4, 24),
2488 };
2489 static const unsigned int usb1_ovc_mux[] = {
2490         USB_OVC1_MARK,
2491 };
2492 /* - USB2 ------------------------------------------------------------------- */
2493 static const unsigned int usb2_pins[] = {
2494         /* PENC */
2495         RCAR_GP_PIN(4, 28),
2496 };
2497 static const unsigned int usb2_mux[] = {
2498         USB_PENC2_MARK,
2499 };
2500 static const unsigned int usb2_ovc_pins[] = {
2501         /* USB_OVC */
2502         RCAR_GP_PIN(3, 29),
2503 };
2504 static const unsigned int usb2_ovc_mux[] = {
2505         USB_OVC2_MARK,
2506 };
2507 /* - VIN0 ------------------------------------------------------------------- */
2508 static const unsigned int vin0_data8_pins[] = {
2509         /* D[0:7] */
2510         RCAR_GP_PIN(2, 6),  RCAR_GP_PIN(2, 7),  RCAR_GP_PIN(2, 8),
2511         RCAR_GP_PIN(2, 9),  RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
2512         RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
2513 };
2514 static const unsigned int vin0_data8_mux[] = {
2515         VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, VI0_DATA2_VI0_B2_MARK,
2516         VI0_DATA3_VI0_B3_MARK, VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
2517         VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
2518 };
2519 static const unsigned int vin0_clk_pins[] = {
2520         /* CLK */
2521         RCAR_GP_PIN(2, 1),
2522 };
2523 static const unsigned int vin0_clk_mux[] = {
2524         VI0_CLK_MARK,
2525 };
2526 static const unsigned int vin0_sync_pins[] = {
2527         /* HSYNC, VSYNC */
2528         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
2529 };
2530 static const unsigned int vin0_sync_mux[] = {
2531         VI0_HSYNC_MARK, VI0_VSYNC_MARK,
2532 };
2533 /* - VIN1 ------------------------------------------------------------------- */
2534 static const unsigned int vin1_data8_pins[] = {
2535         /* D[0:7] */
2536         RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
2537         RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
2538         RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
2539 };
2540 static const unsigned int vin1_data8_mux[] = {
2541         VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK, VI1_DATA2_VI1_B2_MARK,
2542         VI1_DATA3_VI1_B3_MARK, VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
2543         VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
2544 };
2545 static const unsigned int vin1_clk_pins[] = {
2546         /* CLK */
2547         RCAR_GP_PIN(2, 30),
2548 };
2549 static const unsigned int vin1_clk_mux[] = {
2550         VI1_CLK_MARK,
2551 };
2552 static const unsigned int vin1_sync_pins[] = {
2553         /* HSYNC, VSYNC */
2554         RCAR_GP_PIN(2, 31), RCAR_GP_PIN(3, 0),
2555 };
2556 static const unsigned int vin1_sync_mux[] = {
2557         VI1_HSYNC_MARK, VI1_VSYNC_MARK,
2558 };
2559 /* - VIN2 ------------------------------------------------------------------- */
2560 static const unsigned int vin2_data8_pins[] = {
2561         /* D[0:7] */
2562         RCAR_GP_PIN(1, 2),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 10),
2563         RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
2564         RCAR_GP_PIN(1, 31), RCAR_GP_PIN(2, 0),
2565 };
2566 static const unsigned int vin2_data8_mux[] = {
2567         VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK, VI2_DATA2_VI2_B2_MARK,
2568         VI2_DATA3_VI2_B3_MARK, VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
2569         VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
2570 };
2571 static const unsigned int vin2_clk_pins[] = {
2572         /* CLK */
2573         RCAR_GP_PIN(1, 30),
2574 };
2575 static const unsigned int vin2_clk_mux[] = {
2576         VI2_CLK_MARK,
2577 };
2578 static const unsigned int vin2_sync_pins[] = {
2579         /* HSYNC, VSYNC */
2580         RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 29),
2581 };
2582 static const unsigned int vin2_sync_mux[] = {
2583         VI2_HSYNC_MARK, VI2_VSYNC_MARK,
2584 };
2585 /* - VIN3 ------------------------------------------------------------------- */
2586 static const unsigned int vin3_data8_pins[] = {
2587         /* D[0:7] */
2588         RCAR_GP_PIN(3, 9),  RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
2589         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
2590         RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
2591 };
2592 static const unsigned int vin3_data8_mux[] = {
2593         VI3_DATA0_MARK, VI3_DATA1_MARK, VI3_DATA2_MARK,
2594         VI3_DATA3_MARK, VI3_DATA4_MARK, VI3_DATA5_MARK,
2595         VI3_DATA6_MARK, VI3_DATA7_MARK,
2596 };
2597 static const unsigned int vin3_clk_pins[] = {
2598         /* CLK */
2599         RCAR_GP_PIN(2, 31),
2600 };
2601 static const unsigned int vin3_clk_mux[] = {
2602         VI3_CLK_MARK,
2603 };
2604 static const unsigned int vin3_sync_pins[] = {
2605         /* HSYNC, VSYNC */
2606         RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 29),
2607 };
2608 static const unsigned int vin3_sync_mux[] = {
2609         VI3_HSYNC_MARK, VI3_VSYNC_MARK,
2610 };
2611
2612 static const struct sh_pfc_pin_group pinmux_groups[] = {
2613         SH_PFC_PIN_GROUP(du0_rgb666),
2614         SH_PFC_PIN_GROUP(du0_rgb888),
2615         SH_PFC_PIN_GROUP(du0_clk_in),
2616         SH_PFC_PIN_GROUP(du0_clk_out_0),
2617         SH_PFC_PIN_GROUP(du0_clk_out_1),
2618         SH_PFC_PIN_GROUP(du0_sync_0),
2619         SH_PFC_PIN_GROUP(du0_sync_1),
2620         SH_PFC_PIN_GROUP(du0_oddf),
2621         SH_PFC_PIN_GROUP(du0_cde),
2622         SH_PFC_PIN_GROUP(du1_rgb666),
2623         SH_PFC_PIN_GROUP(du1_rgb888),
2624         SH_PFC_PIN_GROUP(du1_clk_in),
2625         SH_PFC_PIN_GROUP(du1_clk_out),
2626         SH_PFC_PIN_GROUP(du1_sync_0),
2627         SH_PFC_PIN_GROUP(du1_sync_1),
2628         SH_PFC_PIN_GROUP(du1_oddf),
2629         SH_PFC_PIN_GROUP(du1_cde),
2630         SH_PFC_PIN_GROUP(ether_rmii),
2631         SH_PFC_PIN_GROUP(ether_link),
2632         SH_PFC_PIN_GROUP(ether_magic),
2633         SH_PFC_PIN_GROUP(hspi0),
2634         SH_PFC_PIN_GROUP(hspi1),
2635         SH_PFC_PIN_GROUP(hspi1_b),
2636         SH_PFC_PIN_GROUP(hspi1_c),
2637         SH_PFC_PIN_GROUP(hspi1_d),
2638         SH_PFC_PIN_GROUP(hspi2),
2639         SH_PFC_PIN_GROUP(hspi2_b),
2640         SH_PFC_PIN_GROUP(i2c1),
2641         SH_PFC_PIN_GROUP(i2c1_b),
2642         SH_PFC_PIN_GROUP(i2c1_c),
2643         SH_PFC_PIN_GROUP(i2c1_d),
2644         SH_PFC_PIN_GROUP(i2c2),
2645         SH_PFC_PIN_GROUP(i2c2_b),
2646         SH_PFC_PIN_GROUP(i2c2_c),
2647         SH_PFC_PIN_GROUP(i2c2_d),
2648         SH_PFC_PIN_GROUP(i2c3),
2649         SH_PFC_PIN_GROUP(i2c3_b),
2650         SH_PFC_PIN_GROUP(intc_irq0),
2651         SH_PFC_PIN_GROUP(intc_irq0_b),
2652         SH_PFC_PIN_GROUP(intc_irq1),
2653         SH_PFC_PIN_GROUP(intc_irq1_b),
2654         SH_PFC_PIN_GROUP(intc_irq2),
2655         SH_PFC_PIN_GROUP(intc_irq2_b),
2656         SH_PFC_PIN_GROUP(intc_irq3),
2657         SH_PFC_PIN_GROUP(intc_irq3_b),
2658         SH_PFC_PIN_GROUP(lbsc_cs0),
2659         SH_PFC_PIN_GROUP(lbsc_cs1),
2660         SH_PFC_PIN_GROUP(lbsc_ex_cs0),
2661         SH_PFC_PIN_GROUP(lbsc_ex_cs1),
2662         SH_PFC_PIN_GROUP(lbsc_ex_cs2),
2663         SH_PFC_PIN_GROUP(lbsc_ex_cs3),
2664         SH_PFC_PIN_GROUP(lbsc_ex_cs4),
2665         SH_PFC_PIN_GROUP(lbsc_ex_cs5),
2666         SH_PFC_PIN_GROUP(mmc0_data1),
2667         SH_PFC_PIN_GROUP(mmc0_data4),
2668         SH_PFC_PIN_GROUP(mmc0_data8),
2669         SH_PFC_PIN_GROUP(mmc0_ctrl),
2670         SH_PFC_PIN_GROUP(mmc1_data1),
2671         SH_PFC_PIN_GROUP(mmc1_data4),
2672         SH_PFC_PIN_GROUP(mmc1_data8),
2673         SH_PFC_PIN_GROUP(mmc1_ctrl),
2674         SH_PFC_PIN_GROUP(scif0_data),
2675         SH_PFC_PIN_GROUP(scif0_clk),
2676         SH_PFC_PIN_GROUP(scif0_ctrl),
2677         SH_PFC_PIN_GROUP(scif0_data_b),
2678         SH_PFC_PIN_GROUP(scif0_clk_b),
2679         SH_PFC_PIN_GROUP(scif0_ctrl_b),
2680         SH_PFC_PIN_GROUP(scif0_data_c),
2681         SH_PFC_PIN_GROUP(scif0_clk_c),
2682         SH_PFC_PIN_GROUP(scif0_ctrl_c),
2683         SH_PFC_PIN_GROUP(scif0_data_d),
2684         SH_PFC_PIN_GROUP(scif0_clk_d),
2685         SH_PFC_PIN_GROUP(scif0_ctrl_d),
2686         SH_PFC_PIN_GROUP(scif1_data),
2687         SH_PFC_PIN_GROUP(scif1_clk),
2688         SH_PFC_PIN_GROUP(scif1_ctrl),
2689         SH_PFC_PIN_GROUP(scif1_data_b),
2690         SH_PFC_PIN_GROUP(scif1_clk_b),
2691         SH_PFC_PIN_GROUP(scif1_ctrl_b),
2692         SH_PFC_PIN_GROUP(scif1_data_c),
2693         SH_PFC_PIN_GROUP(scif1_clk_c),
2694         SH_PFC_PIN_GROUP(scif1_ctrl_c),
2695         SH_PFC_PIN_GROUP(scif2_data),
2696         SH_PFC_PIN_GROUP(scif2_clk),
2697         SH_PFC_PIN_GROUP(scif2_data_b),
2698         SH_PFC_PIN_GROUP(scif2_clk_b),
2699         SH_PFC_PIN_GROUP(scif2_data_c),
2700         SH_PFC_PIN_GROUP(scif2_clk_c),
2701         SH_PFC_PIN_GROUP(scif2_data_d),
2702         SH_PFC_PIN_GROUP(scif2_clk_d),
2703         SH_PFC_PIN_GROUP(scif2_data_e),
2704         SH_PFC_PIN_GROUP(scif3_data),
2705         SH_PFC_PIN_GROUP(scif3_clk),
2706         SH_PFC_PIN_GROUP(scif3_data_b),
2707         SH_PFC_PIN_GROUP(scif3_data_c),
2708         SH_PFC_PIN_GROUP(scif3_data_d),
2709         SH_PFC_PIN_GROUP(scif3_data_e),
2710         SH_PFC_PIN_GROUP(scif3_clk_e),
2711         SH_PFC_PIN_GROUP(scif4_data),
2712         SH_PFC_PIN_GROUP(scif4_clk),
2713         SH_PFC_PIN_GROUP(scif4_data_b),
2714         SH_PFC_PIN_GROUP(scif4_clk_b),
2715         SH_PFC_PIN_GROUP(scif4_data_c),
2716         SH_PFC_PIN_GROUP(scif4_data_d),
2717         SH_PFC_PIN_GROUP(scif5_data),
2718         SH_PFC_PIN_GROUP(scif5_clk),
2719         SH_PFC_PIN_GROUP(scif5_data_b),
2720         SH_PFC_PIN_GROUP(scif5_clk_b),
2721         SH_PFC_PIN_GROUP(scif5_data_c),
2722         SH_PFC_PIN_GROUP(scif5_clk_c),
2723         SH_PFC_PIN_GROUP(scif5_data_d),
2724         SH_PFC_PIN_GROUP(scif5_clk_d),
2725         SH_PFC_PIN_GROUP(scif_clk),
2726         SH_PFC_PIN_GROUP(scif_clk_b),
2727         SH_PFC_PIN_GROUP(scif_clk_c),
2728         SH_PFC_PIN_GROUP(scif_clk_d),
2729         SH_PFC_PIN_GROUP(sdhi0_data1),
2730         SH_PFC_PIN_GROUP(sdhi0_data4),
2731         SH_PFC_PIN_GROUP(sdhi0_ctrl),
2732         SH_PFC_PIN_GROUP(sdhi0_cd),
2733         SH_PFC_PIN_GROUP(sdhi0_wp),
2734         SH_PFC_PIN_GROUP(sdhi1_data1),
2735         SH_PFC_PIN_GROUP(sdhi1_data4),
2736         SH_PFC_PIN_GROUP(sdhi1_ctrl),
2737         SH_PFC_PIN_GROUP(sdhi1_cd),
2738         SH_PFC_PIN_GROUP(sdhi1_wp),
2739         SH_PFC_PIN_GROUP(sdhi2_data1),
2740         SH_PFC_PIN_GROUP(sdhi2_data4),
2741         SH_PFC_PIN_GROUP(sdhi2_ctrl),
2742         SH_PFC_PIN_GROUP(sdhi2_cd),
2743         SH_PFC_PIN_GROUP(sdhi2_wp),
2744         SH_PFC_PIN_GROUP(sdhi3_data1),
2745         SH_PFC_PIN_GROUP(sdhi3_data4),
2746         SH_PFC_PIN_GROUP(sdhi3_ctrl),
2747         SH_PFC_PIN_GROUP(sdhi3_cd),
2748         SH_PFC_PIN_GROUP(sdhi3_wp),
2749         SH_PFC_PIN_GROUP(usb0),
2750         SH_PFC_PIN_GROUP(usb0_ovc),
2751         SH_PFC_PIN_GROUP(usb1),
2752         SH_PFC_PIN_GROUP(usb1_ovc),
2753         SH_PFC_PIN_GROUP(usb2),
2754         SH_PFC_PIN_GROUP(usb2_ovc),
2755         SH_PFC_PIN_GROUP(vin0_data8),
2756         SH_PFC_PIN_GROUP(vin0_clk),
2757         SH_PFC_PIN_GROUP(vin0_sync),
2758         SH_PFC_PIN_GROUP(vin1_data8),
2759         SH_PFC_PIN_GROUP(vin1_clk),
2760         SH_PFC_PIN_GROUP(vin1_sync),
2761         SH_PFC_PIN_GROUP(vin2_data8),
2762         SH_PFC_PIN_GROUP(vin2_clk),
2763         SH_PFC_PIN_GROUP(vin2_sync),
2764         SH_PFC_PIN_GROUP(vin3_data8),
2765         SH_PFC_PIN_GROUP(vin3_clk),
2766         SH_PFC_PIN_GROUP(vin3_sync),
2767 };
2768
2769 static const char * const du0_groups[] = {
2770         "du0_rgb666",
2771         "du0_rgb888",
2772         "du0_clk_in",
2773         "du0_clk_out_0",
2774         "du0_clk_out_1",
2775         "du0_sync_0",
2776         "du0_sync_1",
2777         "du0_oddf",
2778         "du0_cde",
2779 };
2780
2781 static const char * const du1_groups[] = {
2782         "du1_rgb666",
2783         "du1_rgb888",
2784         "du1_clk_in",
2785         "du1_clk_out",
2786         "du1_sync_0",
2787         "du1_sync_1",
2788         "du1_oddf",
2789         "du1_cde",
2790 };
2791
2792 static const char * const ether_groups[] = {
2793         "ether_rmii",
2794         "ether_link",
2795         "ether_magic",
2796 };
2797
2798 static const char * const hspi0_groups[] = {
2799         "hspi0",
2800 };
2801
2802 static const char * const hspi1_groups[] = {
2803         "hspi1",
2804         "hspi1_b",
2805         "hspi1_c",
2806         "hspi1_d",
2807 };
2808
2809 static const char * const hspi2_groups[] = {
2810         "hspi2",
2811         "hspi2_b",
2812 };
2813
2814 static const char * const i2c1_groups[] = {
2815         "i2c1",
2816         "i2c1_b",
2817         "i2c1_c",
2818         "i2c1_d",
2819 };
2820
2821 static const char * const i2c2_groups[] = {
2822         "i2c2",
2823         "i2c2_b",
2824         "i2c2_c",
2825         "i2c2_d",
2826 };
2827
2828 static const char * const i2c3_groups[] = {
2829         "i2c3",
2830         "i2c3_b",
2831 };
2832
2833 static const char * const intc_groups[] = {
2834         "intc_irq0",
2835         "intc_irq0_b",
2836         "intc_irq1",
2837         "intc_irq1_b",
2838         "intc_irq2",
2839         "intc_irq2_b",
2840         "intc_irq3",
2841         "intc_irq3_b",
2842 };
2843
2844 static const char * const lbsc_groups[] = {
2845         "lbsc_cs0",
2846         "lbsc_cs1",
2847         "lbsc_ex_cs0",
2848         "lbsc_ex_cs1",
2849         "lbsc_ex_cs2",
2850         "lbsc_ex_cs3",
2851         "lbsc_ex_cs4",
2852         "lbsc_ex_cs5",
2853 };
2854
2855 static const char * const mmc0_groups[] = {
2856         "mmc0_data1",
2857         "mmc0_data4",
2858         "mmc0_data8",
2859         "mmc0_ctrl",
2860 };
2861
2862 static const char * const mmc1_groups[] = {
2863         "mmc1_data1",
2864         "mmc1_data4",
2865         "mmc1_data8",
2866         "mmc1_ctrl",
2867 };
2868
2869 static const char * const scif0_groups[] = {
2870         "scif0_data",
2871         "scif0_clk",
2872         "scif0_ctrl",
2873         "scif0_data_b",
2874         "scif0_clk_b",
2875         "scif0_ctrl_b",
2876         "scif0_data_c",
2877         "scif0_clk_c",
2878         "scif0_ctrl_c",
2879         "scif0_data_d",
2880         "scif0_clk_d",
2881         "scif0_ctrl_d",
2882 };
2883
2884 static const char * const scif1_groups[] = {
2885         "scif1_data",
2886         "scif1_clk",
2887         "scif1_ctrl",
2888         "scif1_data_b",
2889         "scif1_clk_b",
2890         "scif1_ctrl_b",
2891         "scif1_data_c",
2892         "scif1_clk_c",
2893         "scif1_ctrl_c",
2894 };
2895
2896 static const char * const scif2_groups[] = {
2897         "scif2_data",
2898         "scif2_clk",
2899         "scif2_data_b",
2900         "scif2_clk_b",
2901         "scif2_data_c",
2902         "scif2_clk_c",
2903         "scif2_data_d",
2904         "scif2_clk_d",
2905         "scif2_data_e",
2906 };
2907
2908 static const char * const scif3_groups[] = {
2909         "scif3_data",
2910         "scif3_clk",
2911         "scif3_data_b",
2912         "scif3_data_c",
2913         "scif3_data_d",
2914         "scif3_data_e",
2915         "scif3_clk_e",
2916 };
2917
2918 static const char * const scif4_groups[] = {
2919         "scif4_data",
2920         "scif4_clk",
2921         "scif4_data_b",
2922         "scif4_clk_b",
2923         "scif4_data_c",
2924         "scif4_data_d",
2925 };
2926
2927 static const char * const scif5_groups[] = {
2928         "scif5_data",
2929         "scif5_clk",
2930         "scif5_data_b",
2931         "scif5_clk_b",
2932         "scif5_data_c",
2933         "scif5_clk_c",
2934         "scif5_data_d",
2935         "scif5_clk_d",
2936 };
2937
2938 static const char * const scif_clk_groups[] = {
2939         "scif_clk",
2940         "scif_clk_b",
2941         "scif_clk_c",
2942         "scif_clk_d",
2943 };
2944
2945 static const char * const sdhi0_groups[] = {
2946         "sdhi0_data1",
2947         "sdhi0_data4",
2948         "sdhi0_ctrl",
2949         "sdhi0_cd",
2950         "sdhi0_wp",
2951 };
2952
2953 static const char * const sdhi1_groups[] = {
2954         "sdhi1_data1",
2955         "sdhi1_data4",
2956         "sdhi1_ctrl",
2957         "sdhi1_cd",
2958         "sdhi1_wp",
2959 };
2960
2961 static const char * const sdhi2_groups[] = {
2962         "sdhi2_data1",
2963         "sdhi2_data4",
2964         "sdhi2_ctrl",
2965         "sdhi2_cd",
2966         "sdhi2_wp",
2967 };
2968
2969 static const char * const sdhi3_groups[] = {
2970         "sdhi3_data1",
2971         "sdhi3_data4",
2972         "sdhi3_ctrl",
2973         "sdhi3_cd",
2974         "sdhi3_wp",
2975 };
2976
2977 static const char * const usb0_groups[] = {
2978         "usb0",
2979         "usb0_ovc",
2980 };
2981
2982 static const char * const usb1_groups[] = {
2983         "usb1",
2984         "usb1_ovc",
2985 };
2986
2987 static const char * const usb2_groups[] = {
2988         "usb2",
2989         "usb2_ovc",
2990 };
2991
2992 static const char * const vin0_groups[] = {
2993         "vin0_data8",
2994         "vin0_clk",
2995         "vin0_sync",
2996 };
2997
2998 static const char * const vin1_groups[] = {
2999         "vin1_data8",
3000         "vin1_clk",
3001         "vin1_sync",
3002 };
3003
3004 static const char * const vin2_groups[] = {
3005         "vin2_data8",
3006         "vin2_clk",
3007         "vin2_sync",
3008 };
3009
3010 static const char * const vin3_groups[] = {
3011         "vin3_data8",
3012         "vin3_clk",
3013         "vin3_sync",
3014 };
3015
3016 static const struct sh_pfc_function pinmux_functions[] = {
3017         SH_PFC_FUNCTION(du0),
3018         SH_PFC_FUNCTION(du1),
3019         SH_PFC_FUNCTION(ether),
3020         SH_PFC_FUNCTION(hspi0),
3021         SH_PFC_FUNCTION(hspi1),
3022         SH_PFC_FUNCTION(hspi2),
3023         SH_PFC_FUNCTION(i2c1),
3024         SH_PFC_FUNCTION(i2c2),
3025         SH_PFC_FUNCTION(i2c3),
3026         SH_PFC_FUNCTION(intc),
3027         SH_PFC_FUNCTION(lbsc),
3028         SH_PFC_FUNCTION(mmc0),
3029         SH_PFC_FUNCTION(mmc1),
3030         SH_PFC_FUNCTION(sdhi0),
3031         SH_PFC_FUNCTION(sdhi1),
3032         SH_PFC_FUNCTION(sdhi2),
3033         SH_PFC_FUNCTION(sdhi3),
3034         SH_PFC_FUNCTION(scif0),
3035         SH_PFC_FUNCTION(scif1),
3036         SH_PFC_FUNCTION(scif2),
3037         SH_PFC_FUNCTION(scif3),
3038         SH_PFC_FUNCTION(scif4),
3039         SH_PFC_FUNCTION(scif5),
3040         SH_PFC_FUNCTION(scif_clk),
3041         SH_PFC_FUNCTION(usb0),
3042         SH_PFC_FUNCTION(usb1),
3043         SH_PFC_FUNCTION(usb2),
3044         SH_PFC_FUNCTION(vin0),
3045         SH_PFC_FUNCTION(vin1),
3046         SH_PFC_FUNCTION(vin2),
3047         SH_PFC_FUNCTION(vin3),
3048 };
3049
3050 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3051         { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) {
3052                 GP_0_31_FN, FN_IP3_31_29,
3053                 GP_0_30_FN, FN_IP3_26_24,
3054                 GP_0_29_FN, FN_IP3_22_21,
3055                 GP_0_28_FN, FN_IP3_14_12,
3056                 GP_0_27_FN, FN_IP3_11_9,
3057                 GP_0_26_FN, FN_IP3_2_0,
3058                 GP_0_25_FN, FN_IP2_30_28,
3059                 GP_0_24_FN, FN_IP2_21_19,
3060                 GP_0_23_FN, FN_IP2_18_16,
3061                 GP_0_22_FN, FN_IP0_30_28,
3062                 GP_0_21_FN, FN_IP0_5_3,
3063                 GP_0_20_FN, FN_IP1_18_15,
3064                 GP_0_19_FN, FN_IP1_14_11,
3065                 GP_0_18_FN, FN_IP1_10_7,
3066                 GP_0_17_FN, FN_IP1_6_4,
3067                 GP_0_16_FN, FN_IP1_3_2,
3068                 GP_0_15_FN, FN_IP1_1_0,
3069                 GP_0_14_FN, FN_IP0_27_26,
3070                 GP_0_13_FN, FN_IP0_25,
3071                 GP_0_12_FN, FN_IP0_24_23,
3072                 GP_0_11_FN, FN_IP0_22_19,
3073                 GP_0_10_FN, FN_IP0_18_16,
3074                 GP_0_9_FN, FN_IP0_15_14,
3075                 GP_0_8_FN, FN_IP0_13_12,
3076                 GP_0_7_FN, FN_IP0_11_10,
3077                 GP_0_6_FN, FN_IP0_9_8,
3078                 GP_0_5_FN, FN_A19,
3079                 GP_0_4_FN, FN_A18,
3080                 GP_0_3_FN, FN_A17,
3081                 GP_0_2_FN, FN_IP0_7_6,
3082                 GP_0_1_FN, FN_AVS2,
3083                 GP_0_0_FN, FN_AVS1 }
3084         },
3085         { PINMUX_CFG_REG("GPSR1", 0xfffc0008, 32, 1) {
3086                 GP_1_31_FN, FN_IP5_23_21,
3087                 GP_1_30_FN, FN_IP5_20_17,
3088                 GP_1_29_FN, FN_IP5_16_15,
3089                 GP_1_28_FN, FN_IP5_14_13,
3090                 GP_1_27_FN, FN_IP5_12_11,
3091                 GP_1_26_FN, FN_IP5_10_9,
3092                 GP_1_25_FN, FN_IP5_8,
3093                 GP_1_24_FN, FN_IP5_7,
3094                 GP_1_23_FN, FN_IP5_6,
3095                 GP_1_22_FN, FN_IP5_5,
3096                 GP_1_21_FN, FN_IP5_4,
3097                 GP_1_20_FN, FN_IP5_3,
3098                 GP_1_19_FN, FN_IP5_2_0,
3099                 GP_1_18_FN, FN_IP4_31_29,
3100                 GP_1_17_FN, FN_IP4_28,
3101                 GP_1_16_FN, FN_IP4_27,
3102                 GP_1_15_FN, FN_IP4_26,
3103                 GP_1_14_FN, FN_IP4_25,
3104                 GP_1_13_FN, FN_IP4_24,
3105                 GP_1_12_FN, FN_IP4_23,
3106                 GP_1_11_FN, FN_IP4_22_20,
3107                 GP_1_10_FN, FN_IP4_19_17,
3108                 GP_1_9_FN, FN_IP4_16,
3109                 GP_1_8_FN, FN_IP4_15,
3110                 GP_1_7_FN, FN_IP4_14,
3111                 GP_1_6_FN, FN_IP4_13,
3112                 GP_1_5_FN, FN_IP4_12,
3113                 GP_1_4_FN, FN_IP4_11,
3114                 GP_1_3_FN, FN_IP4_10_8,
3115                 GP_1_2_FN, FN_IP4_7_5,
3116                 GP_1_1_FN, FN_IP4_4_2,
3117                 GP_1_0_FN, FN_IP4_1_0 }
3118         },
3119         { PINMUX_CFG_REG("GPSR2", 0xfffc000c, 32, 1) {
3120                 GP_2_31_FN, FN_IP10_28_26,
3121                 GP_2_30_FN, FN_IP10_25_24,
3122                 GP_2_29_FN, FN_IP10_23_21,
3123                 GP_2_28_FN, FN_IP10_20_18,
3124                 GP_2_27_FN, FN_IP10_17_15,
3125                 GP_2_26_FN, FN_IP10_14_12,
3126                 GP_2_25_FN, FN_IP10_11_9,
3127                 GP_2_24_FN, FN_IP10_8_6,
3128                 GP_2_23_FN, FN_IP10_5_3,
3129                 GP_2_22_FN, FN_IP10_2_0,
3130                 GP_2_21_FN, FN_IP9_29_28,
3131                 GP_2_20_FN, FN_IP9_27_26,
3132                 GP_2_19_FN, FN_IP9_25_24,
3133                 GP_2_18_FN, FN_IP9_23_22,
3134                 GP_2_17_FN, FN_IP9_21_19,
3135                 GP_2_16_FN, FN_IP9_18_16,
3136                 GP_2_15_FN, FN_IP9_15_14,
3137                 GP_2_14_FN, FN_IP9_13_12,
3138                 GP_2_13_FN, FN_IP9_11_10,
3139                 GP_2_12_FN, FN_IP9_9_8,
3140                 GP_2_11_FN, FN_IP9_7,
3141                 GP_2_10_FN, FN_IP9_6,
3142                 GP_2_9_FN, FN_IP9_5,
3143                 GP_2_8_FN, FN_IP9_4,
3144                 GP_2_7_FN, FN_IP9_3_2,
3145                 GP_2_6_FN, FN_IP9_1_0,
3146                 GP_2_5_FN, FN_IP8_30_28,
3147                 GP_2_4_FN, FN_IP8_27_25,
3148                 GP_2_3_FN, FN_IP8_24_23,
3149                 GP_2_2_FN, FN_IP8_22_21,
3150                 GP_2_1_FN, FN_IP8_20,
3151                 GP_2_0_FN, FN_IP5_27_24 }
3152         },
3153         { PINMUX_CFG_REG("GPSR3", 0xfffc0010, 32, 1) {
3154                 GP_3_31_FN, FN_IP6_3_2,
3155                 GP_3_30_FN, FN_IP6_1_0,
3156                 GP_3_29_FN, FN_IP5_30_29,
3157                 GP_3_28_FN, FN_IP5_28,
3158                 GP_3_27_FN, FN_IP1_24_23,
3159                 GP_3_26_FN, FN_IP1_22_21,
3160                 GP_3_25_FN, FN_IP1_20_19,
3161                 GP_3_24_FN, FN_IP7_26_25,
3162                 GP_3_23_FN, FN_IP7_24_23,
3163                 GP_3_22_FN, FN_IP7_22_21,
3164                 GP_3_21_FN, FN_IP7_20_19,
3165                 GP_3_20_FN, FN_IP7_30_29,
3166                 GP_3_19_FN, FN_IP7_28_27,
3167                 GP_3_18_FN, FN_IP7_18_17,
3168                 GP_3_17_FN, FN_IP7_16_15,
3169                 GP_3_16_FN, FN_IP12_17_15,
3170                 GP_3_15_FN, FN_IP12_14_12,
3171                 GP_3_14_FN, FN_IP12_11_9,
3172                 GP_3_13_FN, FN_IP12_8_6,
3173                 GP_3_12_FN, FN_IP12_5_3,
3174                 GP_3_11_FN, FN_IP12_2_0,
3175                 GP_3_10_FN, FN_IP11_29_27,
3176                 GP_3_9_FN, FN_IP11_26_24,
3177                 GP_3_8_FN, FN_IP11_23_21,
3178                 GP_3_7_FN, FN_IP11_20_18,
3179                 GP_3_6_FN, FN_IP11_17_15,
3180                 GP_3_5_FN, FN_IP11_14_12,
3181                 GP_3_4_FN, FN_IP11_11_9,
3182                 GP_3_3_FN, FN_IP11_8_6,
3183                 GP_3_2_FN, FN_IP11_5_3,
3184                 GP_3_1_FN, FN_IP11_2_0,
3185                 GP_3_0_FN, FN_IP10_31_29 }
3186         },
3187         { PINMUX_CFG_REG("GPSR4", 0xfffc0014, 32, 1) {
3188                 GP_4_31_FN, FN_IP8_19,
3189                 GP_4_30_FN, FN_IP8_18,
3190                 GP_4_29_FN, FN_IP8_17_16,
3191                 GP_4_28_FN, FN_IP0_2_0,
3192                 GP_4_27_FN, FN_USB_PENC1,
3193                 GP_4_26_FN, FN_USB_PENC0,
3194                 GP_4_25_FN, FN_IP8_15_12,
3195                 GP_4_24_FN, FN_IP8_11_8,
3196                 GP_4_23_FN, FN_IP8_7_4,
3197                 GP_4_22_FN, FN_IP8_3_0,
3198                 GP_4_21_FN, FN_IP2_3_0,
3199                 GP_4_20_FN, FN_IP1_28_25,
3200                 GP_4_19_FN, FN_IP2_15_12,
3201                 GP_4_18_FN, FN_IP2_11_8,
3202                 GP_4_17_FN, FN_IP2_7_4,
3203                 GP_4_16_FN, FN_IP7_14_13,
3204                 GP_4_15_FN, FN_IP7_12_10,
3205                 GP_4_14_FN, FN_IP7_9_7,
3206                 GP_4_13_FN, FN_IP7_6_4,
3207                 GP_4_12_FN, FN_IP7_3_2,
3208                 GP_4_11_FN, FN_IP7_1_0,
3209                 GP_4_10_FN, FN_IP6_30_29,
3210                 GP_4_9_FN, FN_IP6_26_25,
3211                 GP_4_8_FN, FN_IP6_24_23,
3212                 GP_4_7_FN, FN_IP6_22_20,
3213                 GP_4_6_FN, FN_IP6_19_18,
3214                 GP_4_5_FN, FN_IP6_17_15,
3215                 GP_4_4_FN, FN_IP6_14_12,
3216                 GP_4_3_FN, FN_IP6_11_9,
3217                 GP_4_2_FN, FN_IP6_8,
3218                 GP_4_1_FN, FN_IP6_7_6,
3219                 GP_4_0_FN, FN_IP6_5_4 }
3220         },
3221         { PINMUX_CFG_REG("GPSR5", 0xfffc0018, 32, 1) {
3222                 GP_5_31_FN, FN_IP3_5,
3223                 GP_5_30_FN, FN_IP3_4,
3224                 GP_5_29_FN, FN_IP3_3,
3225                 GP_5_28_FN, FN_IP2_27,
3226                 GP_5_27_FN, FN_IP2_26,
3227                 GP_5_26_FN, FN_IP2_25,
3228                 GP_5_25_FN, FN_IP2_24,
3229                 GP_5_24_FN, FN_IP2_23,
3230                 GP_5_23_FN, FN_IP2_22,
3231                 GP_5_22_FN, FN_IP3_28,
3232                 GP_5_21_FN, FN_IP3_27,
3233                 GP_5_20_FN, FN_IP3_23,
3234                 GP_5_19_FN, FN_EX_WAIT0,
3235                 GP_5_18_FN, FN_WE1,
3236                 GP_5_17_FN, FN_WE0,
3237                 GP_5_16_FN, FN_RD,
3238                 GP_5_15_FN, FN_A16,
3239                 GP_5_14_FN, FN_A15,
3240                 GP_5_13_FN, FN_A14,
3241                 GP_5_12_FN, FN_A13,
3242                 GP_5_11_FN, FN_A12,
3243                 GP_5_10_FN, FN_A11,
3244                 GP_5_9_FN, FN_A10,
3245                 GP_5_8_FN, FN_A9,
3246                 GP_5_7_FN, FN_A8,
3247                 GP_5_6_FN, FN_A7,
3248                 GP_5_5_FN, FN_A6,
3249                 GP_5_4_FN, FN_A5,
3250                 GP_5_3_FN, FN_A4,
3251                 GP_5_2_FN, FN_A3,
3252                 GP_5_1_FN, FN_A2,
3253                 GP_5_0_FN, FN_A1 }
3254         },
3255         { PINMUX_CFG_REG("GPSR6", 0xfffc001c, 32, 1) {
3256                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3257                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3258                 0, 0, 0, 0, 0, 0, 0, 0,
3259                 0, 0,
3260                 0, 0,
3261                 0, 0,
3262                 GP_6_8_FN, FN_IP3_20,
3263                 GP_6_7_FN, FN_IP3_19,
3264                 GP_6_6_FN, FN_IP3_18,
3265                 GP_6_5_FN, FN_IP3_17,
3266                 GP_6_4_FN, FN_IP3_16,
3267                 GP_6_3_FN, FN_IP3_15,
3268                 GP_6_2_FN, FN_IP3_8,
3269                 GP_6_1_FN, FN_IP3_7,
3270                 GP_6_0_FN, FN_IP3_6 }
3271         },
3272
3273         { PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32,
3274                              1, 3, 2, 1, 2, 4, 3, 2, 2, 2, 2, 2, 3, 3) {
3275                 /* IP0_31 [1] */
3276                 0, 0,
3277                 /* IP0_30_28 [3] */
3278                 FN_RD_WR, FN_FWE, FN_ATAG0, FN_VI1_R7,
3279                 FN_HRTS1, FN_RX4_C, 0, 0,
3280                 /* IP0_27_26 [2] */
3281                 FN_CS1_A26, FN_HSPI_TX2, FN_SDSELF_B, 0,
3282                 /* IP0_25 [1] */
3283                 FN_CS0, FN_HSPI_CS2_B,
3284                 /* IP0_24_23 [2] */
3285                 FN_CLKOUT, FN_TX3C_IRDA_TX_C, FN_PWM0_B, 0,
3286                 /* IP0_22_19 [4] */
3287                 FN_A25, FN_SD1_WP, FN_MMC0_D5, FN_FD5,
3288                 FN_HSPI_RX2, FN_VI1_R3, FN_TX5_B, FN_SSI_SDATA7_B,
3289                 FN_CTS0_B, 0, 0, 0,
3290                 0, 0, 0, 0,
3291                 /* IP0_18_16 [3] */
3292                 FN_A24, FN_SD1_CD, FN_MMC0_D4, FN_FD4,
3293                 FN_HSPI_CS2, FN_VI1_R2, FN_SSI_WS78_B, 0,
3294                 /* IP0_15_14 [2] */
3295                 FN_A23, FN_FCLE, FN_HSPI_CLK2, FN_VI1_R1,
3296                 /* IP0_13_12 [2] */
3297                 FN_A22, FN_RX5_D, FN_HSPI_RX2_B, FN_VI1_R0,
3298                 /* IP0_11_10 [2] */
3299                 FN_A21, FN_SCK5_D, FN_HSPI_CLK2_B, 0,
3300                 /* IP0_9_8 [2] */
3301                 FN_A20, FN_TX5_D, FN_HSPI_TX2_B, 0,
3302                 /* IP0_7_6 [2] */
3303                 FN_A0, FN_SD1_DAT3, FN_MMC0_D3, FN_FD3,
3304                 /* IP0_5_3 [3] */
3305                 FN_BS, FN_SD1_DAT2, FN_MMC0_D2, FN_FD2,
3306                 FN_ATADIR0, FN_SDSELF, FN_HCTS1, FN_TX4_C,
3307                 /* IP0_2_0 [3] */
3308                 FN_USB_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
3309                 FN_SCIF_CLK, FN_TCLK0_C, 0, 0 }
3310         },
3311         { PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
3312                              3, 4, 2, 2, 2, 4, 4, 4, 3, 2, 2) {
3313                 /* IP1_31_29 [3] */
3314                 0, 0, 0, 0, 0, 0, 0, 0,
3315                 /* IP1_28_25 [4] */
3316                 FN_HTX0, FN_TX1, FN_SDATA, FN_CTS0_C,
3317                 FN_SUB_TCK, FN_CC5_STATE2, FN_CC5_STATE10, FN_CC5_STATE18,
3318                 FN_CC5_STATE26, FN_CC5_STATE34, 0, 0,
3319                 0, 0, 0, 0,
3320                 /* IP1_24_23 [2] */
3321                 FN_MLB_DAT, FN_PWM4, FN_RX4, 0,
3322                 /* IP1_22_21 [2] */
3323                 FN_MLB_SIG, FN_PWM3, FN_TX4, 0,
3324                 /* IP1_20_19 [2] */
3325                 FN_MLB_CLK, FN_PWM2, FN_SCK4, 0,
3326                 /* IP1_18_15 [4] */
3327                 FN_EX_CS5, FN_SD1_DAT1, FN_MMC0_D1, FN_FD1,
3328                 FN_ATAWR0, FN_VI1_R6, FN_HRX1, FN_RX2_E,
3329                 FN_RX0_B, FN_SSI_WS9, 0, 0,
3330                 0, 0, 0, 0,
3331                 /* IP1_14_11 [4] */
3332                 FN_EX_CS4, FN_SD1_DAT0, FN_MMC0_D0, FN_FD0,
3333                 FN_ATARD0, FN_VI1_R5, FN_SCK5_B, FN_HTX1,
3334                 FN_TX2_E, FN_TX0_B, FN_SSI_SCK9, 0,
3335                 0, 0, 0, 0,
3336                 /* IP1_10_7 [4] */
3337                 FN_EX_CS3, FN_SD1_CMD, FN_MMC0_CMD, FN_FRE,
3338                 FN_ATACS10, FN_VI1_R4, FN_RX5_B, FN_HSCK1,
3339                 FN_SSI_SDATA8_B, FN_RTS0_B_TANS_B, FN_SSI_SDATA9, 0,
3340                 0, 0, 0, 0,
3341                 /* IP1_6_4 [3] */
3342                 FN_EX_CS2, FN_SD1_CLK, FN_MMC0_CLK, FN_FALE,
3343                 FN_ATACS00, 0, 0, 0,
3344                 /* IP1_3_2 [2] */
3345                 FN_EX_CS1, FN_MMC0_D7, FN_FD7, 0,
3346                 /* IP1_1_0 [2] */
3347                 FN_EX_CS0, FN_RX3_C_IRDA_RX_C, FN_MMC0_D6, FN_FD6 }
3348         },
3349         { PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32,
3350                              1, 3, 1, 1, 1, 1, 1, 1, 3, 3, 4, 4, 4, 4) {
3351                 /* IP2_31 [1] */
3352                 0, 0,
3353                 /* IP2_30_28 [3] */
3354                 FN_DU0_DG0, FN_LCDOUT8, FN_DREQ1, FN_SCL2,
3355                 FN_AUDATA2, 0, 0, 0,
3356                 /* IP2_27 [1] */
3357                 FN_DU0_DR7, FN_LCDOUT7,
3358                 /* IP2_26 [1] */
3359                 FN_DU0_DR6, FN_LCDOUT6,
3360                 /* IP2_25 [1] */
3361                 FN_DU0_DR5, FN_LCDOUT5,
3362                 /* IP2_24 [1] */
3363                 FN_DU0_DR4, FN_LCDOUT4,
3364                 /* IP2_23 [1] */
3365                 FN_DU0_DR3, FN_LCDOUT3,
3366                 /* IP2_22 [1] */
3367                 FN_DU0_DR2, FN_LCDOUT2,
3368                 /* IP2_21_19 [3] */
3369                 FN_DU0_DR1, FN_LCDOUT1, FN_DACK0, FN_DRACK0,
3370                 FN_GPS_SIGN_B, FN_AUDATA1, FN_RX5_C, 0,
3371                 /* IP2_18_16 [3] */
3372                 FN_DU0_DR0, FN_LCDOUT0, FN_DREQ0, FN_GPS_CLK_B,
3373                 FN_AUDATA0, FN_TX5_C, 0, 0,
3374                 /* IP2_15_12 [4] */
3375                 FN_HRTS0, FN_RTS1_TANS, FN_MDATA, FN_TX0_C,
3376                 FN_SUB_TMS, FN_CC5_STATE1, FN_CC5_STATE9, FN_CC5_STATE17,
3377                 FN_CC5_STATE25, FN_CC5_STATE33, 0, 0,
3378                 0, 0, 0, 0,
3379                 /* IP2_11_8 [4] */
3380                 FN_HCTS0, FN_CTS1, FN_STM, FN_PWM0_D,
3381                 FN_RX0_C, FN_SCIF_CLK_C, FN_SUB_TRST, FN_TCLK1_B,
3382                 FN_CC5_OSCOUT, 0, 0, 0,
3383                 0, 0, 0, 0,
3384                 /* IP2_7_4 [4] */
3385                 FN_HSCK0, FN_SCK1, FN_MTS, FN_PWM5,
3386                 FN_SCK0_C, FN_SSI_SDATA9_B, FN_SUB_TDO, FN_CC5_STATE0,
3387                 FN_CC5_STATE8, FN_CC5_STATE16, FN_CC5_STATE24, FN_CC5_STATE32,
3388                 0, 0, 0, 0,
3389                 /* IP2_3_0 [4] */
3390                 FN_HRX0, FN_RX1, FN_SCKZ, FN_RTS0_C_TANS_C,
3391                 FN_SUB_TDI, FN_CC5_STATE3, FN_CC5_STATE11, FN_CC5_STATE19,
3392                 FN_CC5_STATE27, FN_CC5_STATE35, 0, 0,
3393                 0, 0, 0, 0 }
3394         },
3395         { PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32,
3396                              3, 1, 1, 3, 1, 2, 1, 1, 1, 1, 1,
3397                              1, 3, 3, 1, 1, 1, 1, 1, 1, 3) {
3398             /* IP3_31_29 [3] */
3399             FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CAN1_TX, FN_TX2_C,
3400             FN_SCL2_C, FN_REMOCON, 0, 0,
3401             /* IP3_28 [1] */
3402             FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE,
3403             /* IP3_27 [1] */
3404             FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS,
3405             /* IP3_26_24 [3] */
3406             FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, FN_RX3_D_IRDA_RX_D, FN_SDA3_B,
3407             FN_SDA2_C, FN_DACK0_B, FN_DRACK0_B, 0,
3408             /* IP3_23 [1] */
3409             FN_DU0_DOTCLKOUT0, FN_QCLK,
3410             /* IP3_22_21 [2] */
3411             FN_DU0_DOTCLKIN, FN_QSTVA_QVS, FN_TX3_D_IRDA_TX_D, FN_SCL3_B,
3412             /* IP3_20 [1] */
3413             FN_DU0_DB7, FN_LCDOUT23,
3414             /* IP3_19 [1] */
3415             FN_DU0_DB6, FN_LCDOUT22,
3416             /* IP3_18 [1] */
3417             FN_DU0_DB5, FN_LCDOUT21,
3418             /* IP3_17 [1] */
3419             FN_DU0_DB4, FN_LCDOUT20,
3420             /* IP3_16 [1] */
3421             FN_DU0_DB3, FN_LCDOUT19,
3422             /* IP3_15 [1] */
3423             FN_DU0_DB2, FN_LCDOUT18,
3424             /* IP3_14_12 [3] */
3425             FN_DU0_DB1, FN_LCDOUT17, FN_EX_WAIT2, FN_SDA1,
3426             FN_GPS_MAG_B, FN_AUDATA5, FN_SCK5_C, 0,
3427             /* IP3_11_9 [3] */
3428             FN_DU0_DB0, FN_LCDOUT16, FN_EX_WAIT1, FN_SCL1,
3429             FN_TCLK1, FN_AUDATA4, 0, 0,
3430             /* IP3_8 [1] */
3431             FN_DU0_DG7, FN_LCDOUT15,
3432             /* IP3_7 [1] */
3433             FN_DU0_DG6, FN_LCDOUT14,
3434             /* IP3_6 [1] */
3435             FN_DU0_DG5, FN_LCDOUT13,
3436             /* IP3_5 [1] */
3437             FN_DU0_DG4, FN_LCDOUT12,
3438             /* IP3_4 [1] */
3439             FN_DU0_DG3, FN_LCDOUT11,
3440             /* IP3_3 [1] */
3441             FN_DU0_DG2, FN_LCDOUT10,
3442             /* IP3_2_0 [3] */
3443             FN_DU0_DG1, FN_LCDOUT9, FN_DACK1, FN_SDA2,
3444             FN_AUDATA3, 0, 0, 0 }
3445         },
3446         { PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32,
3447                              3, 1, 1, 1, 1, 1, 1, 3, 3,
3448                              1, 1, 1, 1, 1, 1, 3, 3, 3, 2) {
3449             /* IP4_31_29 [3] */
3450             FN_DU1_DB0, FN_VI2_DATA4_VI2_B4, FN_SCL2_B, FN_SD3_DAT0,
3451             FN_TX5, FN_SCK0_D, 0, 0,
3452             /* IP4_28 [1] */
3453             FN_DU1_DG7, FN_VI2_R3,
3454             /* IP4_27 [1] */
3455             FN_DU1_DG6, FN_VI2_R2,
3456             /* IP4_26 [1] */
3457             FN_DU1_DG5, FN_VI2_R1,
3458             /* IP4_25 [1] */
3459             FN_DU1_DG4, FN_VI2_R0,
3460             /* IP4_24 [1] */
3461             FN_DU1_DG3, FN_VI2_G7,
3462             /* IP4_23 [1] */
3463             FN_DU1_DG2, FN_VI2_G6,
3464             /* IP4_22_20 [3] */
3465             FN_DU1_DG1, FN_VI2_DATA3_VI2_B3, FN_SDA1_B, FN_SD3_DAT3,
3466             FN_SCK5, FN_AUDATA7, FN_RX0_D, 0,
3467             /* IP4_19_17 [3] */
3468             FN_DU1_DG0, FN_VI2_DATA2_VI2_B2, FN_SCL1_B, FN_SD3_DAT2,
3469             FN_SCK3_E, FN_AUDATA6, FN_TX0_D, 0,
3470             /* IP4_16 [1] */
3471             FN_DU1_DR7, FN_VI2_G5,
3472             /* IP4_15 [1] */
3473             FN_DU1_DR6, FN_VI2_G4,
3474             /* IP4_14 [1] */
3475             FN_DU1_DR5, FN_VI2_G3,
3476             /* IP4_13 [1] */
3477             FN_DU1_DR4, FN_VI2_G2,
3478             /* IP4_12 [1] */
3479             FN_DU1_DR3, FN_VI2_G1,
3480             /* IP4_11 [1] */
3481             FN_DU1_DR2, FN_VI2_G0,
3482             /* IP4_10_8 [3] */
3483             FN_DU1_DR1, FN_VI2_DATA1_VI2_B1, FN_PWM0, FN_SD3_CMD,
3484             FN_RX3_E_IRDA_RX_E, FN_AUDSYNC, FN_CTS0_D, 0,
3485             /* IP4_7_5 [3] */
3486             FN_DU1_DR0, FN_VI2_DATA0_VI2_B0, FN_PWM6, FN_SD3_CLK,
3487             FN_TX3_E_IRDA_TX_E, FN_AUDCK, FN_PWMFSW0_B, 0,
3488             /* IP4_4_2 [3] */
3489             FN_DU0_CDE, FN_QPOLB, FN_CAN1_RX, FN_RX2_C,
3490             FN_DREQ0_B, FN_SSI_SCK78_B, FN_SCK0_B, 0,
3491             /* IP4_1_0 [2] */
3492             FN_DU0_DISP, FN_QPOLA, FN_CAN_CLK_C, FN_SCK2_C }
3493         },
3494         { PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32,
3495                              1, 2, 1, 4, 3, 4, 2, 2,
3496                              2, 2, 1, 1, 1, 1, 1, 1, 3) {
3497             /* IP5_31 [1] */
3498             0, 0,
3499             /* IP5_30_29 [2] */
3500             FN_AUDIO_CLKB, FN_USB_OVC2, FN_CAN_DEBUGOUT0, FN_MOUT0,
3501             /* IP5_28 [1] */
3502             FN_AUDIO_CLKA, FN_CAN_TXCLK,
3503             /* IP5_27_24 [4] */
3504             FN_DU1_CDE, FN_VI2_DATA7_VI2_B7, FN_RX3_B_IRDA_RX_B, FN_SD3_WP,
3505             FN_HSPI_RX1, FN_VI1_FIELD, FN_VI3_FIELD, FN_AUDIO_CLKOUT,
3506             FN_RX2_D, FN_GPS_CLK_C, FN_GPS_CLK_D, 0,
3507             0, 0, 0, 0,
3508             /* IP5_23_21 [3] */
3509             FN_DU1_DISP, FN_VI2_DATA6_VI2_B6, FN_TCLK0, FN_QSTVA_B_QVS_B,
3510             FN_HSPI_CLK1, FN_SCK2_D, FN_AUDIO_CLKOUT_B, FN_GPS_MAG_D,
3511             /* IP5_20_17 [4] */
3512             FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_VI2_CLK, FN_TX3_B_IRDA_TX_B,
3513             FN_SD3_CD, FN_HSPI_TX1, FN_VI1_CLKENB, FN_VI3_CLKENB,
3514             FN_AUDIO_CLKC, FN_TX2_D, FN_SPEEDIN, FN_GPS_SIGN_D, 0,
3515             0, 0, 0, 0,
3516             /* IP5_16_15 [2] */
3517             FN_DU1_EXVSYNC_DU1_VSYNC, FN_VI2_VSYNC, FN_VI3_VSYNC, 0,
3518             /* IP5_14_13 [2] */
3519             FN_DU1_EXHSYNC_DU1_HSYNC, FN_VI2_HSYNC, FN_VI3_HSYNC, 0,
3520             /* IP5_12_11 [2] */
3521             FN_DU1_DOTCLKOUT, FN_VI2_FIELD, FN_SDA1_D, 0,
3522             /* IP5_10_9 [2] */
3523             FN_DU1_DOTCLKIN, FN_VI2_CLKENB, FN_HSPI_CS1, FN_SCL1_D,
3524             /* IP5_8 [1] */
3525             FN_DU1_DB7, FN_SDA2_D,
3526             /* IP5_7 [1] */
3527             FN_DU1_DB6, FN_SCL2_D,
3528             /* IP5_6 [1] */
3529             FN_DU1_DB5, FN_VI2_R7,
3530             /* IP5_5 [1] */
3531             FN_DU1_DB4, FN_VI2_R6,
3532             /* IP5_4 [1] */
3533             FN_DU1_DB3, FN_VI2_R5,
3534             /* IP5_3 [1] */
3535             FN_DU1_DB2, FN_VI2_R4,
3536             /* IP5_2_0 [3] */
3537             FN_DU1_DB1, FN_VI2_DATA5_VI2_B5, FN_SDA2_B, FN_SD3_DAT1,
3538             FN_RX5, FN_RTS0_D_TANS_D, 0, 0 }
3539         },
3540         { PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32,
3541                              1, 2, 2, 2, 2, 3, 2, 3, 3, 3, 1, 2, 2, 2, 2) {
3542             /* IP6_31 [1] */
3543             0, 0,
3544             /* IP6_30_29 [2] */
3545             FN_SSI_SCK6, FN_ADICHS0, FN_CAN0_TX, FN_IERX_B,
3546             /* IP_28_27 [2] */
3547             0, 0, 0, 0,
3548             /* IP6_26_25 [2] */
3549             FN_SSI_SDATA5, FN_ADIDATA, FN_CAN_DEBUGOUT12, FN_RX3_IRDA_RX,
3550             /* IP6_24_23 [2] */
3551             FN_SSI_WS5, FN_ADICS_SAMP, FN_CAN_DEBUGOUT11, FN_TX3_IRDA_TX,
3552             /* IP6_22_20 [3] */
3553             FN_SSI_SCK5, FN_ADICLK, FN_CAN_DEBUGOUT10, FN_SCK3,
3554             FN_TCLK0_D, 0, 0, 0,
3555             /* IP6_19_18 [2] */
3556             FN_SSI_SDATA4, FN_CAN_DEBUGOUT9, FN_SSI_SDATA9_C, 0,
3557             /* IP6_17_15 [3] */
3558             FN_SSI_SDATA3, FN_PWM0_C, FN_CAN_DEBUGOUT8, FN_CAN_CLK_B,
3559             FN_IECLK, FN_SCIF_CLK_B, FN_TCLK0_B, 0,
3560             /* IP6_14_12 [3] */
3561             FN_SSI_WS34, FN_CAN_DEBUGOUT7, FN_CAN0_RX_B, FN_IETX,
3562             FN_SSI_WS9_C, 0, 0, 0,
3563             /* IP6_11_9 [3] */
3564             FN_SSI_SCK34, FN_CAN_DEBUGOUT6, FN_CAN0_TX_B, FN_IERX,
3565             FN_SSI_SCK9_C, 0, 0, 0,
3566             /* IP6_8 [1] */
3567             FN_SSI_SDATA2, FN_CAN_DEBUGOUT5,
3568             /* IP6_7_6 [2] */
3569             FN_SSI_SDATA1, FN_CAN_DEBUGOUT4, FN_MOUT6, 0,
3570             /* IP6_5_4 [2] */
3571             FN_SSI_SDATA0, FN_CAN_DEBUGOUT3, FN_MOUT5, 0,
3572             /* IP6_3_2 [2] */
3573             FN_SSI_WS0129, FN_CAN_DEBUGOUT2, FN_MOUT2, 0,
3574             /* IP6_1_0 [2] */
3575             FN_SSI_SCK0129, FN_CAN_DEBUGOUT1, FN_MOUT1, 0 }
3576         },
3577         { PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32,
3578                              1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 2, 2) {
3579             /* IP7_31 [1] */
3580             0, 0,
3581             /* IP7_30_29 [2] */
3582             FN_SD0_WP, FN_DACK2, FN_CTS1_B, 0,
3583             /* IP7_28_27 [2] */
3584             FN_SD0_CD, FN_DREQ2, FN_RTS1_B_TANS_B, 0,
3585             /* IP7_26_25 [2] */
3586             FN_SD0_DAT3, FN_ATAWR1, FN_RX2_B, FN_CC5_TDI,
3587             /* IP7_24_23 [2] */
3588             FN_SD0_DAT2, FN_ATARD1, FN_TX2_B, FN_CC5_TCK,
3589             /* IP7_22_21 [2] */
3590             FN_SD0_DAT1, FN_ATAG1, FN_SCK2_B, FN_CC5_TMS,
3591             /* IP7_20_19 [2] */
3592             FN_SD0_DAT0, FN_ATADIR1, FN_RX1_B, FN_CC5_TRST,
3593             /* IP7_18_17 [2] */
3594             FN_SD0_CMD, FN_ATACS11, FN_TX1_B, FN_CC5_TDO,
3595             /* IP7_16_15 [2] */
3596             FN_SD0_CLK, FN_ATACS01, FN_SCK1_B, 0,
3597             /* IP7_14_13 [2] */
3598             FN_SSI_SDATA8, FN_VSP, FN_IRQ3_B, FN_HSPI_RX1_C,
3599             /* IP7_12_10 [3] */
3600             FN_SSI_SDATA7, FN_CAN_DEBUGOUT15, FN_IRQ2_B, FN_TCLK1_C,
3601             FN_HSPI_TX1_C, 0, 0, 0,
3602             /* IP7_9_7 [3] */
3603             FN_SSI_WS78, FN_CAN_DEBUGOUT14, FN_IRQ1_B, FN_SSI_WS9_B,
3604             FN_HSPI_CS1_C, 0, 0, 0,
3605             /* IP7_6_4 [3] */
3606             FN_SSI_SCK78, FN_CAN_DEBUGOUT13, FN_IRQ0_B, FN_SSI_SCK9_B,
3607             FN_HSPI_CLK1_C, 0, 0, 0,
3608             /* IP7_3_2 [2] */
3609             FN_SSI_SDATA6, FN_ADICHS2, FN_CAN_CLK, FN_IECLK_B,
3610             /* IP7_1_0 [2] */
3611             FN_SSI_WS6, FN_ADICHS1, FN_CAN0_RX, FN_IETX_B }
3612         },
3613         { PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32,
3614                              1, 3, 3, 2, 2, 1, 1, 1, 2, 4, 4, 4, 4) {
3615             /* IP8_31 [1] */
3616             0, 0,
3617             /* IP8_30_28 [3] */
3618             FN_VI0_VSYNC, FN_VI0_DATA1_B_VI0_B1_B, FN_RTS1_C_TANS_C, FN_RX4_D,
3619             FN_PWMFSW0_C, 0, 0, 0,
3620             /* IP8_27_25 [3] */
3621             FN_VI0_HSYNC, FN_VI0_DATA0_B_VI0_B0_B, FN_CTS1_C, FN_TX4_D,
3622             FN_MMC1_CMD, FN_HSCK1_B, 0, 0,
3623             /* IP8_24_23 [2] */
3624             FN_VI0_FIELD, FN_RX1_C, FN_HRX1_B, 0,
3625             /* IP8_22_21 [2] */
3626             FN_VI0_CLKENB, FN_TX1_C, FN_HTX1_B, FN_MT1_SYNC,
3627             /* IP8_20 [1] */
3628             FN_VI0_CLK, FN_MMC1_CLK,
3629             /* IP8_19 [1] */
3630             FN_FMIN, FN_RDS_DATA,
3631             /* IP8_18 [1] */
3632             FN_BPFCLK, FN_PCMWE,
3633             /* IP8_17_16 [2] */
3634             FN_FMCLK, FN_RDS_CLK, FN_PCMOE, 0,
3635             /* IP8_15_12 [4] */
3636             FN_HSPI_RX0, FN_RX0, FN_CAN_STEP0, FN_AD_NCS,
3637             FN_CC5_STATE7, FN_CC5_STATE15, FN_CC5_STATE23, FN_CC5_STATE31,
3638             FN_CC5_STATE39, 0, 0, 0,
3639             0, 0, 0, 0,
3640             /* IP8_11_8 [4] */
3641             FN_HSPI_TX0, FN_TX0, FN_CAN_DEBUG_HW_TRIGGER, FN_AD_DO,
3642             FN_CC5_STATE6, FN_CC5_STATE14, FN_CC5_STATE22, FN_CC5_STATE30,
3643             FN_CC5_STATE38, 0, 0, 0,
3644             0, 0, 0, 0,
3645             /* IP8_7_4 [4] */
3646             FN_HSPI_CS0, FN_RTS0_TANS, FN_USB_OVC1, FN_AD_DI,
3647             FN_CC5_STATE5, FN_CC5_STATE13, FN_CC5_STATE21, FN_CC5_STATE29,
3648             FN_CC5_STATE37, 0, 0, 0,
3649             0, 0, 0, 0,
3650             /* IP8_3_0 [4] */
3651             FN_HSPI_CLK0, FN_CTS0, FN_USB_OVC0, FN_AD_CLK,
3652             FN_CC5_STATE4, FN_CC5_STATE12, FN_CC5_STATE20, FN_CC5_STATE28,
3653             FN_CC5_STATE36, 0, 0, 0,
3654             0, 0, 0, 0 }
3655         },
3656         { PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32,
3657                              2, 2, 2, 2, 2, 3, 3, 2, 2,
3658                              2, 2, 1, 1, 1, 1, 2, 2) {
3659             /* IP9_31_30 [2] */
3660             0, 0, 0, 0,
3661             /* IP9_29_28 [2] */
3662             FN_VI0_G7, FN_ETH_RXD1, FN_SD2_DAT3_B, FN_ARM_TRACEDATA_9,
3663             /* IP9_27_26 [2] */
3664             FN_VI0_G6, FN_ETH_RXD0, FN_SD2_DAT2_B, FN_ARM_TRACEDATA_8,
3665             /* IP9_25_24 [2] */
3666             FN_VI0_G5, FN_ETH_RX_ER, FN_SD2_DAT1_B, FN_ARM_TRACEDATA_7,
3667             /* IP9_23_22 [2] */
3668             FN_VI0_G4, FN_ETH_TX_EN, FN_SD2_DAT0_B, FN_ARM_TRACEDATA_6,
3669             /* IP9_21_19 [3] */
3670             FN_VI0_G3, FN_ETH_CRS_DV, FN_MMC1_D7, FN_ARM_TRACEDATA_5,
3671             FN_TS_SDAT0, 0, 0, 0,
3672             /* IP9_18_16 [3] */
3673             FN_VI0_G2, FN_ETH_TXD1, FN_MMC1_D6, FN_ARM_TRACEDATA_4,
3674             FN_TS_SPSYNC0, 0, 0, 0,
3675             /* IP9_15_14 [2] */
3676             FN_VI0_G1, FN_SSI_WS78_C, FN_IRQ1, FN_ARM_TRACEDATA_3,
3677             /* IP9_13_12 [2] */
3678             FN_VI0_G0, FN_SSI_SCK78_C, FN_IRQ0, FN_ARM_TRACEDATA_2,
3679             /* IP9_11_10 [2] */
3680             FN_VI0_DATA7_VI0_B7, FN_MMC1_D5, FN_ARM_TRACEDATA_1, 0,
3681             /* IP9_9_8 [2] */
3682             FN_VI0_DATA6_VI0_B6, FN_MMC1_D4, FN_ARM_TRACEDATA_0, 0,
3683             /* IP9_7 [1] */
3684             FN_VI0_DATA5_VI0_B5, FN_MMC1_D3,
3685             /* IP9_6 [1] */
3686             FN_VI0_DATA4_VI0_B4, FN_MMC1_D2,
3687             /* IP9_5 [1] */
3688             FN_VI0_DATA3_VI0_B3, FN_MMC1_D1,
3689             /* IP9_4 [1] */
3690             FN_VI0_DATA2_VI0_B2, FN_MMC1_D0,
3691             /* IP9_3_2 [2] */
3692             FN_VI0_DATA1_VI0_B1, FN_HCTS1_B, FN_MT1_PWM, 0,
3693             /* IP9_1_0 [2] */
3694             FN_VI0_DATA0_VI0_B0, FN_HRTS1_B, FN_MT1_VCXO, 0 }
3695         },
3696         { PINMUX_CFG_REG_VAR("IPSR10", 0xfffc0048, 32,
3697                              3, 3, 2, 3, 3, 3, 3, 3, 3, 3, 3) {
3698             /* IP10_31_29 [3] */
3699             FN_VI1_VSYNC, FN_AUDIO_CLKOUT_C, FN_SSI_WS4, FN_SIM_CLK,
3700             FN_GPS_MAG_C, FN_SPV_TRST, FN_SCL3, 0,
3701             /* IP10_28_26 [3] */
3702             FN_VI1_HSYNC, FN_VI3_CLK, FN_SSI_SCK4, FN_GPS_SIGN_C,
3703             FN_PWMFSW0_E, 0, 0, 0,
3704             /* IP10_25_24 [2] */
3705             FN_VI1_CLK, FN_SIM_D, FN_SDA3, 0,
3706             /* IP10_23_21 [3] */
3707             FN_VI0_R7, FN_ETH_MDIO, FN_DACK2_C, FN_HSPI_RX1_B,
3708             FN_SCIF_CLK_D, FN_TRACECTL, FN_MT1_PEN, 0,
3709             /* IP10_20_18 [3] */
3710             FN_VI0_R6, FN_ETH_MDC, FN_DREQ2_C, FN_HSPI_TX1_B,
3711             FN_TRACECLK, FN_MT1_BEN, FN_PWMFSW0_D, 0,
3712             /* IP10_17_15 [3] */
3713             FN_VI0_R5, FN_ETH_TXD0, FN_SD2_WP_B, FN_HSPI_CS1_B,
3714             FN_ARM_TRACEDATA_15, FN_MT1_D, FN_TS_SDEN0, 0,
3715             /* IP10_14_12 [3] */
3716             FN_VI0_R4, FN_ETH_REFCLK, FN_SD2_CD_B, FN_HSPI_CLK1_B,
3717             FN_ARM_TRACEDATA_14, FN_MT1_CLK, FN_TS_SCK0, 0,
3718             /* IP10_11_9 [3] */
3719             FN_VI0_R3, FN_ETH_MAGIC, FN_SD2_CMD_B, FN_IRQ3,
3720             FN_ARM_TRACEDATA_13, 0, 0, 0,
3721             /* IP10_8_6 [3] */
3722             FN_VI0_R2, FN_ETH_LINK, FN_SD2_CLK_B, FN_IRQ2,
3723             FN_ARM_TRACEDATA_12, 0, 0, 0,
3724             /* IP10_5_3 [3] */
3725             FN_VI0_R1, FN_SSI_SDATA8_C, FN_DACK1_B, FN_ARM_TRACEDATA_11,
3726             FN_DACK0_C, FN_DRACK0_C, 0, 0,
3727             /* IP10_2_0 [3] */
3728             FN_VI0_R0, FN_SSI_SDATA7_C, FN_SCK1_C, FN_DREQ1_B,
3729             FN_ARM_TRACEDATA_10, FN_DREQ0_C, 0, 0 }
3730         },
3731         { PINMUX_CFG_REG_VAR("IPSR11", 0xfffc004c, 32,
3732                              2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
3733             /* IP11_31_30 [2] */
3734             0, 0, 0, 0,
3735             /* IP11_29_27 [3] */
3736             FN_VI1_G1, FN_VI3_DATA1, FN_SSI_SCK1, FN_TS_SDEN1,
3737             FN_DACK2_B, FN_RX2, FN_HRTS0_B, 0,
3738             /* IP11_26_24 [3] */
3739             FN_VI1_G0, FN_VI3_DATA0, 0, FN_TS_SCK1,
3740             FN_DREQ2_B, FN_TX2, FN_SPA_TDO, FN_HCTS0_B,
3741             /* IP11_23_21 [3] */
3742             FN_VI1_DATA7_VI1_B7, FN_SD2_WP, FN_MT0_PWM, FN_SPA_TDI,
3743             FN_HSPI_RX1_D, 0, 0, 0,
3744             /* IP11_20_18 [3] */
3745             FN_VI1_DATA6_VI1_B6, FN_SD2_CD, FN_MT0_VCXO, FN_SPA_TMS,
3746             FN_HSPI_TX1_D, 0, 0, 0,
3747             /* IP11_17_15 [3] */
3748             FN_VI1_DATA5_VI1_B5, FN_SD2_CMD, FN_MT0_SYNC, FN_SPA_TCK,
3749             FN_HSPI_CS1_D, FN_ADICHS2_B, 0, 0,
3750             /* IP11_14_12 [3] */
3751             FN_VI1_DATA4_VI1_B4, FN_SD2_CLK, FN_MT0_PEN, FN_SPA_TRST,
3752             FN_HSPI_CLK1_D, FN_ADICHS1_B, 0, 0,
3753             /* IP11_11_9 [3] */
3754             FN_VI1_DATA3_VI1_B3, FN_SD2_DAT3, FN_MT0_BEN, FN_SPV_TDO,
3755             FN_ADICHS0_B, 0, 0, 0,
3756             /* IP11_8_6 [3] */
3757             FN_VI1_DATA2_VI1_B2, FN_SD2_DAT2, FN_MT0_D, FN_SPVTDI,
3758             FN_ADIDATA_B, 0, 0, 0,
3759             /* IP11_5_3 [3] */
3760             FN_VI1_DATA1_VI1_B1, FN_SD2_DAT1, FN_MT0_CLK, FN_SPV_TMS,
3761             FN_ADICS_B_SAMP_B, 0, 0, 0,
3762             /* IP11_2_0 [3] */
3763             FN_VI1_DATA0_VI1_B0, FN_SD2_DAT0, FN_SIM_RST, FN_SPV_TCK,
3764             FN_ADICLK_B, 0, 0, 0 }
3765         },
3766         { PINMUX_CFG_REG_VAR("IPSR12", 0xfffc0050, 32,
3767                              4, 4, 4, 2, 3, 3, 3, 3, 3, 3) {
3768             /* IP12_31_28 [4] */
3769             0, 0, 0, 0, 0, 0, 0, 0,
3770             0, 0, 0, 0, 0, 0, 0, 0,
3771             /* IP12_27_24 [4] */
3772             0, 0, 0, 0, 0, 0, 0, 0,
3773             0, 0, 0, 0, 0, 0, 0, 0,
3774             /* IP12_23_20 [4] */
3775             0, 0, 0, 0, 0, 0, 0, 0,
3776             0, 0, 0, 0, 0, 0, 0, 0,
3777             /* IP12_19_18 [2] */
3778             0, 0, 0, 0,
3779             /* IP12_17_15 [3] */
3780             FN_VI1_G7, FN_VI3_DATA7, FN_GPS_MAG, FN_FCE,
3781             FN_SCK4_B, 0, 0, 0,
3782             /* IP12_14_12 [3] */
3783             FN_VI1_G6, FN_VI3_DATA6, FN_GPS_SIGN, FN_FRB,
3784             FN_RX4_B, FN_SIM_CLK_B, 0, 0,
3785             /* IP12_11_9 [3] */
3786             FN_VI1_G5, FN_VI3_DATA5, FN_GPS_CLK, FN_FSE,
3787             FN_TX4_B, FN_SIM_D_B, 0, 0,
3788             /* IP12_8_6 [3] */
3789             FN_VI1_G4, FN_VI3_DATA4, FN_SSI_WS2, FN_SDA1_C,
3790             FN_SIM_RST_B, FN_HRX0_B, 0, 0,
3791             /* IP12_5_3 [3] */
3792             FN_VI1_G3, FN_VI3_DATA3, FN_SSI_SCK2, FN_TS_SDAT1,
3793             FN_SCL1_C, FN_HTX0_B, 0, 0,
3794             /* IP12_2_0 [3] */
3795             FN_VI1_G2, FN_VI3_DATA2, FN_SSI_WS1, FN_TS_SPSYNC1,
3796             FN_SCK2, FN_HSCK0_B, 0, 0 }
3797         },
3798         { PINMUX_CFG_REG_VAR("MOD_SEL", 0xfffc0090, 32,
3799                              2, 2, 3, 3, 2, 2, 2, 2, 2,
3800                              1, 1, 1, 1, 1, 1, 1, 2, 1, 2) {
3801             /* SEL_SCIF5 [2] */
3802             FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
3803             /* SEL_SCIF4 [2] */
3804             FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
3805             /* SEL_SCIF3 [3] */
3806             FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
3807             FN_SEL_SCIF3_4, 0, 0, 0,
3808             /* SEL_SCIF2 [3] */
3809             FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3,
3810             FN_SEL_SCIF2_4, 0, 0, 0,
3811             /* SEL_SCIF1 [2] */
3812             FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, 0,
3813             /* SEL_SCIF0 [2] */
3814             FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
3815             /* SEL_SSI9 [2] */
3816             FN_SEL_SSI9_0, FN_SEL_SSI9_1, FN_SEL_SSI9_2, 0,
3817             /* SEL_SSI8 [2] */
3818             FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0,
3819             /* SEL_SSI7 [2] */
3820             FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0,
3821             /* SEL_VI0 [1] */
3822             FN_SEL_VI0_0, FN_SEL_VI0_1,
3823             /* SEL_SD2 [1] */
3824             FN_SEL_SD2_0, FN_SEL_SD2_1,
3825             /* SEL_INT3 [1] */
3826             FN_SEL_INT3_0, FN_SEL_INT3_1,
3827             /* SEL_INT2 [1] */
3828             FN_SEL_INT2_0, FN_SEL_INT2_1,
3829             /* SEL_INT1 [1] */
3830             FN_SEL_INT1_0, FN_SEL_INT1_1,
3831             /* SEL_INT0 [1] */
3832             FN_SEL_INT0_0, FN_SEL_INT0_1,
3833             /* SEL_IE [1] */
3834             FN_SEL_IE_0, FN_SEL_IE_1,
3835             /* SEL_EXBUS2 [2] */
3836             FN_SEL_EXBUS2_0, FN_SEL_EXBUS2_1, FN_SEL_EXBUS2_2, 0,
3837             /* SEL_EXBUS1 [1] */
3838             FN_SEL_EXBUS1_0, FN_SEL_EXBUS1_1,
3839             /* SEL_EXBUS0 [2] */
3840             FN_SEL_EXBUS0_0, FN_SEL_EXBUS0_1, FN_SEL_EXBUS0_2, 0 }
3841         },
3842         { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xfffc0094, 32,
3843                              2, 2, 2, 2, 1, 1, 1, 3, 1,
3844                              2, 2, 2, 2, 1, 1, 2, 1, 2, 2) {
3845             /* SEL_TMU1 [2] */
3846             FN_SEL_TMU1_0, FN_SEL_TMU1_1, FN_SEL_TMU1_2, 0,
3847             /* SEL_TMU0 [2] */
3848             FN_SEL_TMU0_0, FN_SEL_TMU0_1, FN_SEL_TMU0_2, FN_SEL_TMU0_3,
3849             /* SEL_SCIF [2] */
3850             FN_SEL_SCIF_0, FN_SEL_SCIF_1, FN_SEL_SCIF_2, FN_SEL_SCIF_3,
3851             /* SEL_CANCLK [2] */
3852             FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, 0,
3853             /* SEL_CAN0 [1] */
3854             FN_SEL_CAN0_0, FN_SEL_CAN0_1,
3855             /* SEL_HSCIF1 [1] */
3856             FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
3857             /* SEL_HSCIF0 [1] */
3858             FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
3859             /* SEL_PWMFSW [3] */
3860             FN_SEL_PWMFSW_0, FN_SEL_PWMFSW_1, FN_SEL_PWMFSW_2,
3861             FN_SEL_PWMFSW_3, FN_SEL_PWMFSW_4, 0, 0, 0,
3862             /* SEL_ADI [1] */
3863             FN_SEL_ADI_0, FN_SEL_ADI_1,
3864             /* [2] */
3865             0, 0, 0, 0,
3866             /* [2] */
3867             0, 0, 0, 0,
3868             /* [2] */
3869             0, 0, 0, 0,
3870             /* SEL_GPS [2] */
3871             FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
3872             /* SEL_SIM [1] */
3873             FN_SEL_SIM_0, FN_SEL_SIM_1,
3874             /* SEL_HSPI2 [1] */
3875             FN_SEL_HSPI2_0, FN_SEL_HSPI2_1,
3876             /* SEL_HSPI1 [2] */
3877             FN_SEL_HSPI1_0, FN_SEL_HSPI1_1, FN_SEL_HSPI1_2, FN_SEL_HSPI1_3,
3878             /* SEL_I2C3 [1] */
3879             FN_SEL_I2C3_0, FN_SEL_I2C3_1,
3880             /* SEL_I2C2 [2] */
3881             FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
3882             /* SEL_I2C1 [2] */
3883             FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3 }
3884         },
3885         { },
3886 };
3887
3888 const struct sh_pfc_soc_info r8a7779_pinmux_info = {
3889         .name = "r8a7779_pfc",
3890
3891         .unlock_reg = 0xfffc0000, /* PMMR */
3892
3893         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
3894
3895         .pins = pinmux_pins,
3896         .nr_pins = ARRAY_SIZE(pinmux_pins),
3897         .groups = pinmux_groups,
3898         .nr_groups = ARRAY_SIZE(pinmux_groups),
3899         .functions = pinmux_functions,
3900         .nr_functions = ARRAY_SIZE(pinmux_functions),
3901
3902         .cfg_regs = pinmux_config_regs,
3903
3904         .pinmux_data = pinmux_data,
3905         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
3906 };