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mm: memcontrol: use per-cpu stocks for socket memory uncharging
[linux/fpc-iii.git] / drivers / pinctrl / sh-pfc / pfc-r8a7792.c
blobcc3597f66605a3e2d1960534b755f3e70062353c
1 /*
2 * r8a7792 processor support - PFC hardware block.
3 *
4 * Copyright (C) 2013-2014 Renesas Electronics Corporation
5 * Copyright (C) 2016 Cogent Embedded, Inc., <source@cogentembedded.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2
9 * as published by the Free Software Foundation.
10 */
11
12 #include <linux/kernel.h>
13
14 #include "core.h"
15 #include "sh_pfc.h"
16
17 #define CPU_ALL_PORT(fn, sfx) \
18 PORT_GP_29(0, fn, sfx), \
19 PORT_GP_23(1, fn, sfx), \
20 PORT_GP_32(2, fn, sfx), \
21 PORT_GP_28(3, fn, sfx), \
22 PORT_GP_17(4, fn, sfx), \
23 PORT_GP_17(5, fn, sfx), \
24 PORT_GP_17(6, fn, sfx), \
25 PORT_GP_17(7, fn, sfx), \
26 PORT_GP_17(8, fn, sfx), \
27 PORT_GP_17(9, fn, sfx), \
28 PORT_GP_32(10, fn, sfx), \
29 PORT_GP_30(11, fn, sfx)
30
31 enum {
32 PINMUX_RESERVED = 0,
33
34 PINMUX_DATA_BEGIN,
35 GP_ALL(DATA),
36 PINMUX_DATA_END,
37
38 PINMUX_FUNCTION_BEGIN,
39 GP_ALL(FN),
40
41 /* GPSR0 */
42 FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5,
43 FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11,
44 FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_16,
45 FN_IP0_17, FN_IP0_18, FN_IP0_19, FN_IP0_20, FN_IP0_21,
46 FN_IP0_22, FN_IP0_23, FN_IP1_0, FN_IP1_1, FN_IP1_2,
47 FN_IP1_3, FN_IP1_4,
48
49 /* GPSR1 */
50 FN_IP1_5, FN_IP1_6, FN_IP1_7, FN_IP1_8, FN_IP1_9, FN_IP1_10,
51 FN_IP1_11, FN_IP1_12, FN_IP1_13, FN_IP1_14, FN_IP1_15, FN_IP1_16,
52 FN_DU1_DB2_C0_DATA12, FN_DU1_DB3_C1_DATA13, FN_DU1_DB4_C2_DATA14,
53 FN_DU1_DB5_C3_DATA15, FN_DU1_DB6_C4, FN_DU1_DB7_C5,
54 FN_DU1_EXHSYNC_DU1_HSYNC, FN_DU1_EXVSYNC_DU1_VSYNC,
55 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_DU1_DISP, FN_DU1_CDE,
56
57 /* GPSR2 */
58 FN_D0, FN_D1, FN_D2, FN_D3, FN_D4, FN_D5, FN_D6, FN_D7,
59 FN_D8, FN_D9, FN_D10, FN_D11, FN_D12, FN_D13, FN_D14, FN_D15,
60 FN_A0, FN_A1, FN_A2, FN_A3, FN_A4, FN_A5, FN_A6, FN_A7,
61 FN_A8, FN_A9, FN_A10, FN_A11, FN_A12, FN_A13, FN_A14, FN_A15,
62
63 /* GPSR3 */
64 FN_A16, FN_A17, FN_A18, FN_A19, FN_IP1_17, FN_IP1_18,
65 FN_CS1_N_A26, FN_EX_CS0_N, FN_EX_CS1_N, FN_EX_CS2_N, FN_EX_CS3_N,
66 FN_EX_CS4_N, FN_EX_CS5_N, FN_BS_N, FN_RD_N, FN_RD_WR_N,
67 FN_WE0_N, FN_WE1_N, FN_EX_WAIT0, FN_IRQ0, FN_IRQ1, FN_IRQ2, FN_IRQ3,
68 FN_IP1_19, FN_IP1_20, FN_IP1_21, FN_IP1_22, FN_CS0_N,
69
70 /* GPSR4 */
71 FN_VI0_CLK, FN_VI0_CLKENB, FN_VI0_HSYNC_N, FN_VI0_VSYNC_N,
72 FN_VI0_D0_B0_C0, FN_VI0_D1_B1_C1, FN_VI0_D2_B2_C2, FN_VI0_D3_B3_C3,
73 FN_VI0_D4_B4_C4, FN_VI0_D5_B5_C5, FN_VI0_D6_B6_C6, FN_VI0_D7_B7_C7,
74 FN_VI0_D8_G0_Y0, FN_VI0_D9_G1_Y1, FN_VI0_D10_G2_Y2, FN_VI0_D11_G3_Y3,
75 FN_VI0_FIELD,
76
77 /* GPSR5 */
78 FN_VI1_CLK, FN_VI1_CLKENB, FN_VI1_HSYNC_N, FN_VI1_VSYNC_N,
79 FN_VI1_D0_B0_C0, FN_VI1_D1_B1_C1, FN_VI1_D2_B2_C2, FN_VI1_D3_B3_C3,
80 FN_VI1_D4_B4_C4, FN_VI1_D5_B5_C5, FN_VI1_D6_B6_C6, FN_VI1_D7_B7_C7,
81 FN_VI1_D8_G0_Y0, FN_VI1_D9_G1_Y1, FN_VI1_D10_G2_Y2, FN_VI1_D11_G3_Y3,
82 FN_VI1_FIELD,
83
84 /* GPSR6 */
85 FN_IP2_0, FN_IP2_1, FN_IP2_2, FN_IP2_3, FN_IP2_4, FN_IP2_5, FN_IP2_6,
86 FN_IP2_7, FN_IP2_8, FN_IP2_9, FN_IP2_10, FN_IP2_11, FN_IP2_12,
87 FN_IP2_13, FN_IP2_14, FN_IP2_15, FN_IP2_16,
88
89 /* GPSR7 */
90 FN_IP3_0, FN_IP3_1, FN_IP3_2, FN_IP3_3, FN_IP3_4, FN_IP3_5, FN_IP3_6,
91 FN_IP3_7, FN_IP3_8, FN_IP3_9, FN_IP3_10, FN_IP3_11, FN_IP3_12,
92 FN_IP3_13, FN_VI3_D10_Y2, FN_IP3_14, FN_VI3_FIELD,
93
94 /* GPSR8 */
95 FN_VI4_CLK, FN_IP4_0, FN_IP4_1, FN_IP4_3_2, FN_IP4_4, FN_IP4_6_5,
96 FN_IP4_8_7, FN_IP4_10_9, FN_IP4_12_11, FN_IP4_14_13, FN_IP4_16_15,
97 FN_IP4_18_17, FN_IP4_20_19, FN_IP4_21, FN_IP4_22, FN_IP4_23, FN_IP4_24,
98
99 /* GPSR9 */
100 FN_VI5_CLK, FN_IP5_0, FN_IP5_1, FN_IP5_2, FN_IP5_3, FN_IP5_4, FN_IP5_5,
101 FN_IP5_6, FN_IP5_7, FN_IP5_8, FN_IP5_9, FN_IP5_10, FN_IP5_11,
102 FN_VI5_D9_Y1, FN_VI5_D10_Y2, FN_VI5_D11_Y3, FN_VI5_FIELD,
103
104 /* GPSR10 */
105 FN_IP6_0, FN_IP6_1, FN_HRTS0_N, FN_IP6_2, FN_IP6_3, FN_IP6_4, FN_IP6_5,
106 FN_HCTS1_N, FN_IP6_6, FN_IP6_7, FN_SCK0, FN_CTS0_N, FN_RTS0_N,
107 FN_TX0, FN_RX0, FN_SCK1, FN_CTS1_N, FN_RTS1_N, FN_TX1, FN_RX1,
108 FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14, FN_IP6_16,
109 FN_IP6_18_17, FN_SCIF_CLK, FN_CAN0_TX, FN_CAN0_RX, FN_CAN_CLK,
110 FN_CAN1_TX, FN_CAN1_RX,
111
112 /* GPSR11 */
113 FN_IP7_1_0, FN_IP7_3_2, FN_IP7_5_4, FN_IP7_6, FN_IP7_7, FN_SD0_CLK,
114 FN_SD0_CMD, FN_SD0_DAT0, FN_SD0_DAT1, FN_SD0_DAT2, FN_SD0_DAT3,
115 FN_SD0_CD, FN_SD0_WP, FN_IP7_9_8, FN_IP7_11_10, FN_IP7_13_12,
116 FN_IP7_15_14, FN_IP7_16, FN_IP7_17, FN_IP7_18, FN_IP7_19, FN_IP7_20,
117 FN_ADICLK, FN_ADICS_SAMP, FN_ADIDATA, FN_ADICHS0, FN_ADICHS1,
118 FN_ADICHS2, FN_AVS1, FN_AVS2,
119
120 /* IPSR0 */
121 FN_DU0_DR0_DATA0, FN_DU0_DR1_DATA1, FN_DU0_DR2_Y4_DATA2,
122 FN_DU0_DR3_Y5_DATA3, FN_DU0_DR4_Y6_DATA4, FN_DU0_DR5_Y7_DATA5,
123 FN_DU0_DR6_Y8_DATA6, FN_DU0_DR7_Y9_DATA7, FN_DU0_DG0_DATA8,
124 FN_DU0_DG1_DATA9, FN_DU0_DG2_C6_DATA10, FN_DU0_DG3_C7_DATA11,
125 FN_DU0_DG4_Y0_DATA12, FN_DU0_DG5_Y1_DATA13, FN_DU0_DG6_Y2_DATA14,
126 FN_DU0_DG7_Y3_DATA15, FN_DU0_DB0, FN_DU0_DB1, FN_DU0_DB2_C0,
127 FN_DU0_DB3_C1, FN_DU0_DB4_C2, FN_DU0_DB5_C3, FN_DU0_DB6_C4,
128 FN_DU0_DB7_C5,
129
130 /* IPSR1 */
131 FN_DU0_EXHSYNC_DU0_HSYNC, FN_DU0_EXVSYNC_DU0_VSYNC,
132 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_DU0_DISP, FN_DU0_CDE,
133 FN_DU1_DR2_Y4_DATA0, FN_DU1_DR3_Y5_DATA1, FN_DU1_DR4_Y6_DATA2,
134 FN_DU1_DR5_Y7_DATA3, FN_DU1_DR6_DATA4, FN_DU1_DR7_DATA5,
135 FN_DU1_DG2_C6_DATA6, FN_DU1_DG3_C7_DATA7, FN_DU1_DG4_Y0_DATA8,
136 FN_DU1_DG5_Y1_DATA9, FN_DU1_DG6_Y2_DATA10, FN_DU1_DG7_Y3_DATA11,
137 FN_A20, FN_MOSI_IO0, FN_A21, FN_MISO_IO1, FN_A22, FN_IO2,
138 FN_A23, FN_IO3, FN_A24, FN_SPCLK, FN_A25, FN_SSL,
139
140 /* IPSR2 */
141 FN_VI2_CLK, FN_AVB_RX_CLK, FN_VI2_CLKENB, FN_AVB_RX_DV,
142 FN_VI2_HSYNC_N, FN_AVB_RXD0, FN_VI2_VSYNC_N, FN_AVB_RXD1,
143 FN_VI2_D0_C0, FN_AVB_RXD2, FN_VI2_D1_C1, FN_AVB_RXD3,
144 FN_VI2_D2_C2, FN_AVB_RXD4, FN_VI2_D3_C3, FN_AVB_RXD5,
145 FN_VI2_D4_C4, FN_AVB_RXD6, FN_VI2_D5_C5, FN_AVB_RXD7,
146 FN_VI2_D6_C6, FN_AVB_RX_ER, FN_VI2_D7_C7, FN_AVB_COL,
147 FN_VI2_D8_Y0, FN_AVB_TXD3, FN_VI2_D9_Y1, FN_AVB_TX_EN,
148 FN_VI2_D10_Y2, FN_AVB_TXD0, FN_VI2_D11_Y3, FN_AVB_TXD1,
149 FN_VI2_FIELD, FN_AVB_TXD2,
150
151 /* IPSR3 */
152 FN_VI3_CLK, FN_AVB_TX_CLK, FN_VI3_CLKENB, FN_AVB_TXD4,
153 FN_VI3_HSYNC_N, FN_AVB_TXD5, FN_VI3_VSYNC_N, FN_AVB_TXD6,
154 FN_VI3_D0_C0, FN_AVB_TXD7, FN_VI3_D1_C1, FN_AVB_TX_ER,
155 FN_VI3_D2_C2, FN_AVB_GTX_CLK, FN_VI3_D3_C3, FN_AVB_MDC,
156 FN_VI3_D4_C4, FN_AVB_MDIO, FN_VI3_D5_C5, FN_AVB_LINK,
157 FN_VI3_D6_C6, FN_AVB_MAGIC, FN_VI3_D7_C7, FN_AVB_PHY_INT,
158 FN_VI3_D8_Y0, FN_AVB_CRS, FN_VI3_D9_Y1, FN_AVB_GTXREFCLK,
159 FN_VI3_D11_Y3, FN_AVB_AVTP_MATCH,
160
161 /* IPSR4 */
162 FN_VI4_CLKENB, FN_VI0_D12_G4_Y4, FN_VI4_HSYNC_N, FN_VI0_D13_G5_Y5,
163 FN_VI4_VSYNC_N, FN_VI0_D14_G6_Y6, FN_RDR_CLKOUT,
164 FN_VI4_D0_C0, FN_VI0_D15_G7_Y7,
165 FN_VI4_D1_C1, FN_VI0_D16_R0, FN_VI1_D12_G4_Y4,
166 FN_VI4_D2_C2, FN_VI0_D17_R1, FN_VI1_D13_G5_Y5,
167 FN_VI4_D3_C3, FN_VI0_D18_R2, FN_VI1_D14_G6_Y6,
168 FN_VI4_D4_C4, FN_VI0_D19_R3, FN_VI1_D15_G7_Y7,
169 FN_VI4_D5_C5, FN_VI0_D20_R4, FN_VI2_D12_Y4,
170 FN_VI4_D6_C6, FN_VI0_D21_R5, FN_VI2_D13_Y5,
171 FN_VI4_D7_C7, FN_VI0_D22_R6, FN_VI2_D14_Y6,
172 FN_VI4_D8_Y0, FN_VI0_D23_R7, FN_VI2_D15_Y7,
173 FN_VI4_D9_Y1, FN_VI3_D12_Y4, FN_VI4_D10_Y2, FN_VI3_D13_Y5,
174 FN_VI4_D11_Y3, FN_VI3_D14_Y6, FN_VI4_FIELD, FN_VI3_D15_Y7,
175
176 /* IPSR5 */
177 FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_B, FN_VI5_HSYNC_N, FN_VI1_D13_G5_Y5_B,
178 FN_VI5_VSYNC_N, FN_VI1_D14_G6_Y6_B, FN_VI5_D0_C0, FN_VI1_D15_G7_Y7_B,
179 FN_VI5_D1_C1, FN_VI1_D16_R0, FN_VI5_D2_C2, FN_VI1_D17_R1,
180 FN_VI5_D3_C3, FN_VI1_D18_R2, FN_VI5_D4_C4, FN_VI1_D19_R3,
181 FN_VI5_D5_C5, FN_VI1_D20_R4, FN_VI5_D6_C6, FN_VI1_D21_R5,
182 FN_VI5_D7_C7, FN_VI1_D22_R6, FN_VI5_D8_Y0, FN_VI1_D23_R7,
183
184 /* IPSR6 */
185 FN_MSIOF0_SCK, FN_HSCK0, FN_MSIOF0_SYNC, FN_HCTS0_N,
186 FN_MSIOF0_TXD, FN_HTX0, FN_MSIOF0_RXD, FN_HRX0,
187 FN_MSIOF1_SCK, FN_HSCK1, FN_MSIOF1_SYNC, FN_HRTS1_N,
188 FN_MSIOF1_TXD, FN_HTX1, FN_MSIOF1_RXD, FN_HRX1,
189 FN_DRACK0, FN_SCK2, FN_DACK0, FN_TX2, FN_DREQ0_N, FN_RX2,
190 FN_DACK1, FN_SCK3, FN_TX3, FN_DREQ1_N, FN_RX3,
191
192 /* IPSR7 */
193 FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, FN_PWM1, FN_TCLK2, FN_FSO_CFE_1,
194 FN_PWM2, FN_TCLK3, FN_FSO_TOE, FN_PWM3, FN_PWM4,
195 FN_SSI_SCK34, FN_TPU0TO0, FN_SSI_WS34, FN_TPU0TO1,
196 FN_SSI_SDATA3, FN_TPU0TO2, FN_SSI_SCK4, FN_TPU0TO3,
197 FN_SSI_WS4, FN_SSI_SDATA4, FN_AUDIO_CLKOUT,
198 FN_AUDIO_CLKA, FN_AUDIO_CLKB,
199
200 /* MOD_SEL */
201 FN_SEL_VI1_0, FN_SEL_VI1_1,
202 PINMUX_FUNCTION_END,
203
204 PINMUX_MARK_BEGIN,
205 DU1_DB2_C0_DATA12_MARK, DU1_DB3_C1_DATA13_MARK,
206 DU1_DB4_C2_DATA14_MARK, DU1_DB5_C3_DATA15_MARK,
207 DU1_DB6_C4_MARK, DU1_DB7_C5_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
208 DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
209 DU1_DISP_MARK, DU1_CDE_MARK,
210
211 D0_MARK, D1_MARK, D2_MARK, D3_MARK, D4_MARK, D5_MARK, D6_MARK,
212 D7_MARK, D8_MARK, D9_MARK, D10_MARK, D11_MARK, D12_MARK, D13_MARK,
213 D14_MARK, D15_MARK, A0_MARK, A1_MARK, A2_MARK, A3_MARK, A4_MARK,
214 A5_MARK, A6_MARK, A7_MARK, A8_MARK, A9_MARK, A10_MARK, A11_MARK,
215 A12_MARK, A13_MARK, A14_MARK, A15_MARK,
216
217 A16_MARK, A17_MARK, A18_MARK, A19_MARK, CS1_N_A26_MARK,
218 EX_CS0_N_MARK, EX_CS1_N_MARK, EX_CS2_N_MARK, EX_CS3_N_MARK,
219 EX_CS4_N_MARK, EX_CS5_N_MARK, BS_N_MARK, RD_N_MARK, RD_WR_N_MARK,
220 WE0_N_MARK, WE1_N_MARK, EX_WAIT0_MARK,
221 IRQ0_MARK, IRQ1_MARK, IRQ2_MARK, IRQ3_MARK, CS0_N_MARK,
222
223 VI0_CLK_MARK, VI0_CLKENB_MARK, VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK,
224 VI0_D0_B0_C0_MARK, VI0_D1_B1_C1_MARK, VI0_D2_B2_C2_MARK,
225 VI0_D3_B3_C3_MARK, VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK,
226 VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK, VI0_D8_G0_Y0_MARK,
227 VI0_D9_G1_Y1_MARK, VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK,
228 VI0_FIELD_MARK,
229
230 VI1_CLK_MARK, VI1_CLKENB_MARK, VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK,
231 VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK, VI1_D2_B2_C2_MARK,
232 VI1_D3_B3_C3_MARK, VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
233 VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK, VI1_D8_G0_Y0_MARK,
234 VI1_D9_G1_Y1_MARK, VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
235 VI1_FIELD_MARK,
236
237 VI3_D10_Y2_MARK, VI3_FIELD_MARK,
238
239 VI4_CLK_MARK,
240
241 VI5_CLK_MARK, VI5_D9_Y1_MARK, VI5_D10_Y2_MARK, VI5_D11_Y3_MARK,
242 VI5_FIELD_MARK,
243
244 HRTS0_N_MARK, HCTS1_N_MARK, SCK0_MARK, CTS0_N_MARK, RTS0_N_MARK,
245 TX0_MARK, RX0_MARK, SCK1_MARK, CTS1_N_MARK, RTS1_N_MARK,
246 TX1_MARK, RX1_MARK, SCIF_CLK_MARK, CAN0_TX_MARK, CAN0_RX_MARK,
247 CAN_CLK_MARK, CAN1_TX_MARK, CAN1_RX_MARK,
248
249 SD0_CLK_MARK, SD0_CMD_MARK, SD0_DAT0_MARK, SD0_DAT1_MARK,
250 SD0_DAT2_MARK, SD0_DAT3_MARK, SD0_CD_MARK, SD0_WP_MARK,
251 ADICLK_MARK, ADICS_SAMP_MARK, ADIDATA_MARK, ADICHS0_MARK,
252 ADICHS1_MARK, ADICHS2_MARK, AVS1_MARK, AVS2_MARK,
253
254 /* IPSR0 */
255 DU0_DR0_DATA0_MARK, DU0_DR1_DATA1_MARK, DU0_DR2_Y4_DATA2_MARK,
256 DU0_DR3_Y5_DATA3_MARK, DU0_DR4_Y6_DATA4_MARK, DU0_DR5_Y7_DATA5_MARK,
257 DU0_DR6_Y8_DATA6_MARK, DU0_DR7_Y9_DATA7_MARK, DU0_DG0_DATA8_MARK,
258 DU0_DG1_DATA9_MARK, DU0_DG2_C6_DATA10_MARK, DU0_DG3_C7_DATA11_MARK,
259 DU0_DG4_Y0_DATA12_MARK, DU0_DG5_Y1_DATA13_MARK, DU0_DG6_Y2_DATA14_MARK,
260 DU0_DG7_Y3_DATA15_MARK, DU0_DB0_MARK, DU0_DB1_MARK,
261 DU0_DB2_C0_MARK, DU0_DB3_C1_MARK, DU0_DB4_C2_MARK, DU0_DB5_C3_MARK,
262 DU0_DB6_C4_MARK, DU0_DB7_C5_MARK,
263
264 /* IPSR1 */
265 DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK,
266 DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, DU0_DISP_MARK, DU0_CDE_MARK,
267 DU1_DR2_Y4_DATA0_MARK, DU1_DR3_Y5_DATA1_MARK, DU1_DR4_Y6_DATA2_MARK,
268 DU1_DR5_Y7_DATA3_MARK, DU1_DR6_DATA4_MARK, DU1_DR7_DATA5_MARK,
269 DU1_DG2_C6_DATA6_MARK, DU1_DG3_C7_DATA7_MARK, DU1_DG4_Y0_DATA8_MARK,
270 DU1_DG5_Y1_DATA9_MARK, DU1_DG6_Y2_DATA10_MARK, DU1_DG7_Y3_DATA11_MARK,
271 A20_MARK, MOSI_IO0_MARK, A21_MARK, MISO_IO1_MARK, A22_MARK, IO2_MARK,
272 A23_MARK, IO3_MARK, A24_MARK, SPCLK_MARK, A25_MARK, SSL_MARK,
273
274 /* IPSR2 */
275 VI2_CLK_MARK, AVB_RX_CLK_MARK, VI2_CLKENB_MARK, AVB_RX_DV_MARK,
276 VI2_HSYNC_N_MARK, AVB_RXD0_MARK, VI2_VSYNC_N_MARK, AVB_RXD1_MARK,
277 VI2_D0_C0_MARK, AVB_RXD2_MARK, VI2_D1_C1_MARK, AVB_TX_CLK_MARK,
278 VI2_D2_C2_MARK, AVB_RXD4_MARK, VI2_D3_C3_MARK, AVB_RXD5_MARK,
279 VI2_D4_C4_MARK, AVB_RXD6_MARK, VI2_D5_C5_MARK, AVB_RXD7_MARK,
280 VI2_D6_C6_MARK, AVB_RX_ER_MARK, VI2_D7_C7_MARK, AVB_COL_MARK,
281 VI2_D8_Y0_MARK, AVB_RXD3_MARK, VI2_D9_Y1_MARK, AVB_TX_EN_MARK,
282 VI2_D10_Y2_MARK, AVB_TXD0_MARK,
283 VI2_D11_Y3_MARK, AVB_TXD1_MARK, VI2_FIELD_MARK, AVB_TXD2_MARK,
284
285 /* IPSR3 */
286 VI3_CLK_MARK, AVB_TXD3_MARK, VI3_CLKENB_MARK, AVB_TXD4_MARK,
287 VI3_HSYNC_N_MARK, AVB_TXD5_MARK, VI3_VSYNC_N_MARK, AVB_TXD6_MARK,
288 VI3_D0_C0_MARK, AVB_TXD7_MARK, VI3_D1_C1_MARK, AVB_TX_ER_MARK,
289 VI3_D2_C2_MARK, AVB_GTX_CLK_MARK, VI3_D3_C3_MARK, AVB_MDC_MARK,
290 VI3_D4_C4_MARK, AVB_MDIO_MARK, VI3_D5_C5_MARK, AVB_LINK_MARK,
291 VI3_D6_C6_MARK, AVB_MAGIC_MARK, VI3_D7_C7_MARK, AVB_PHY_INT_MARK,
292 VI3_D8_Y0_MARK, AVB_CRS_MARK, VI3_D9_Y1_MARK, AVB_GTXREFCLK_MARK,
293 VI3_D11_Y3_MARK, AVB_AVTP_MATCH_MARK,
294
295 /* IPSR4 */
296 VI4_CLKENB_MARK, VI0_D12_G4_Y4_MARK, VI4_HSYNC_N_MARK,
297 VI0_D13_G5_Y5_MARK, VI4_VSYNC_N_MARK, VI0_D14_G6_Y6_MARK,
298 RDR_CLKOUT_MARK, VI4_D0_C0_MARK, VI0_D15_G7_Y7_MARK, VI4_D1_C1_MARK,
299 VI0_D16_R0_MARK, VI1_D12_G4_Y4_MARK, VI4_D2_C2_MARK, VI0_D17_R1_MARK,
300 VI1_D13_G5_Y5_MARK, VI4_D3_C3_MARK, VI0_D18_R2_MARK, VI1_D14_G6_Y6_MARK,
301 VI4_D4_C4_MARK, VI0_D19_R3_MARK, VI1_D15_G7_Y7_MARK, VI4_D5_C5_MARK,
302 VI0_D20_R4_MARK, VI2_D12_Y4_MARK, VI4_D6_C6_MARK, VI0_D21_R5_MARK,
303 VI2_D13_Y5_MARK, VI4_D7_C7_MARK, VI0_D22_R6_MARK, VI2_D14_Y6_MARK,
304 VI4_D8_Y0_MARK, VI0_D23_R7_MARK, VI2_D15_Y7_MARK, VI4_D9_Y1_MARK,
305 VI3_D12_Y4_MARK, VI4_D10_Y2_MARK, VI3_D13_Y5_MARK, VI4_D11_Y3_MARK,
306 VI3_D14_Y6_MARK, VI4_FIELD_MARK, VI3_D15_Y7_MARK,
307
308 /* IPSR5 */
309 VI5_CLKENB_MARK, VI1_D12_G4_Y4_B_MARK, VI5_HSYNC_N_MARK,
310 VI1_D13_G5_Y5_B_MARK, VI5_VSYNC_N_MARK, VI1_D14_G6_Y6_B_MARK,
311 VI5_D0_C0_MARK, VI1_D15_G7_Y7_B_MARK, VI5_D1_C1_MARK, VI1_D16_R0_MARK,
312 VI5_D2_C2_MARK, VI1_D17_R1_MARK, VI5_D3_C3_MARK, VI1_D18_R2_MARK,
313 VI5_D4_C4_MARK, VI1_D19_R3_MARK, VI5_D5_C5_MARK, VI1_D20_R4_MARK,
314 VI5_D6_C6_MARK, VI1_D21_R5_MARK, VI5_D7_C7_MARK, VI1_D22_R6_MARK,
315 VI5_D8_Y0_MARK, VI1_D23_R7_MARK,
316
317 /* IPSR6 */
318 MSIOF0_SCK_MARK, HSCK0_MARK, MSIOF0_SYNC_MARK, HCTS0_N_MARK,
319 MSIOF0_TXD_MARK, HTX0_MARK, MSIOF0_RXD_MARK, HRX0_MARK,
320 MSIOF1_SCK_MARK, HSCK1_MARK, MSIOF1_SYNC_MARK, HRTS1_N_MARK,
321 MSIOF1_TXD_MARK, HTX1_MARK, MSIOF1_RXD_MARK, HRX1_MARK,
322 DRACK0_MARK, SCK2_MARK, DACK0_MARK, TX2_MARK, DREQ0_N_MARK,
323 RX2_MARK, DACK1_MARK, SCK3_MARK, TX3_MARK, DREQ1_N_MARK,
324 RX3_MARK,
325
326 /* IPSR7 */
327 PWM0_MARK, TCLK1_MARK, FSO_CFE_0_MARK, PWM1_MARK, TCLK2_MARK,
328 FSO_CFE_1_MARK, PWM2_MARK, TCLK3_MARK, FSO_TOE_MARK, PWM3_MARK,
329 PWM4_MARK, SSI_SCK34_MARK, TPU0TO0_MARK, SSI_WS34_MARK, TPU0TO1_MARK,
330 SSI_SDATA3_MARK, TPU0TO2_MARK, SSI_SCK4_MARK, TPU0TO3_MARK,
331 SSI_WS4_MARK, SSI_SDATA4_MARK, AUDIO_CLKOUT_MARK, AUDIO_CLKA_MARK,
332 AUDIO_CLKB_MARK,
333 PINMUX_MARK_END,
334 };
335
336 static const u16 pinmux_data[] = {
337 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
338
339 PINMUX_SINGLE(DU1_DB2_C0_DATA12),
340 PINMUX_SINGLE(DU1_DB3_C1_DATA13),
341 PINMUX_SINGLE(DU1_DB4_C2_DATA14),
342 PINMUX_SINGLE(DU1_DB5_C3_DATA15),
343 PINMUX_SINGLE(DU1_DB6_C4),
344 PINMUX_SINGLE(DU1_DB7_C5),
345 PINMUX_SINGLE(DU1_EXHSYNC_DU1_HSYNC),
346 PINMUX_SINGLE(DU1_EXVSYNC_DU1_VSYNC),
347 PINMUX_SINGLE(DU1_EXODDF_DU1_ODDF_DISP_CDE),
348 PINMUX_SINGLE(DU1_DISP),
349 PINMUX_SINGLE(DU1_CDE),
350 PINMUX_SINGLE(D0),
351 PINMUX_SINGLE(D1),
352 PINMUX_SINGLE(D2),
353 PINMUX_SINGLE(D3),
354 PINMUX_SINGLE(D4),
355 PINMUX_SINGLE(D5),
356 PINMUX_SINGLE(D6),
357 PINMUX_SINGLE(D7),
358 PINMUX_SINGLE(D8),
359 PINMUX_SINGLE(D9),
360 PINMUX_SINGLE(D10),
361 PINMUX_SINGLE(D11),
362 PINMUX_SINGLE(D12),
363 PINMUX_SINGLE(D13),
364 PINMUX_SINGLE(D14),
365 PINMUX_SINGLE(D15),
366 PINMUX_SINGLE(A0),
367 PINMUX_SINGLE(A1),
368 PINMUX_SINGLE(A2),
369 PINMUX_SINGLE(A3),
370 PINMUX_SINGLE(A4),
371 PINMUX_SINGLE(A5),
372 PINMUX_SINGLE(A6),
373 PINMUX_SINGLE(A7),
374 PINMUX_SINGLE(A8),
375 PINMUX_SINGLE(A9),
376 PINMUX_SINGLE(A10),
377 PINMUX_SINGLE(A11),
378 PINMUX_SINGLE(A12),
379 PINMUX_SINGLE(A13),
380 PINMUX_SINGLE(A14),
381 PINMUX_SINGLE(A15),
382 PINMUX_SINGLE(A16),
383 PINMUX_SINGLE(A17),
384 PINMUX_SINGLE(A18),
385 PINMUX_SINGLE(A19),
386 PINMUX_SINGLE(CS1_N_A26),
387 PINMUX_SINGLE(EX_CS0_N),
388 PINMUX_SINGLE(EX_CS1_N),
389 PINMUX_SINGLE(EX_CS2_N),
390 PINMUX_SINGLE(EX_CS3_N),
391 PINMUX_SINGLE(EX_CS4_N),
392 PINMUX_SINGLE(EX_CS5_N),
393 PINMUX_SINGLE(BS_N),
394 PINMUX_SINGLE(RD_N),
395 PINMUX_SINGLE(RD_WR_N),
396 PINMUX_SINGLE(WE0_N),
397 PINMUX_SINGLE(WE1_N),
398 PINMUX_SINGLE(EX_WAIT0),
399 PINMUX_SINGLE(IRQ0),
400 PINMUX_SINGLE(IRQ1),
401 PINMUX_SINGLE(IRQ2),
402 PINMUX_SINGLE(IRQ3),
403 PINMUX_SINGLE(CS0_N),
404 PINMUX_SINGLE(VI0_CLK),
405 PINMUX_SINGLE(VI0_CLKENB),
406 PINMUX_SINGLE(VI0_HSYNC_N),
407 PINMUX_SINGLE(VI0_VSYNC_N),
408 PINMUX_SINGLE(VI0_D0_B0_C0),
409 PINMUX_SINGLE(VI0_D1_B1_C1),
410 PINMUX_SINGLE(VI0_D2_B2_C2),
411 PINMUX_SINGLE(VI0_D3_B3_C3),
412 PINMUX_SINGLE(VI0_D4_B4_C4),
413 PINMUX_SINGLE(VI0_D5_B5_C5),
414 PINMUX_SINGLE(VI0_D6_B6_C6),
415 PINMUX_SINGLE(VI0_D7_B7_C7),
416 PINMUX_SINGLE(VI0_D8_G0_Y0),
417 PINMUX_SINGLE(VI0_D9_G1_Y1),
418 PINMUX_SINGLE(VI0_D10_G2_Y2),
419 PINMUX_SINGLE(VI0_D11_G3_Y3),
420 PINMUX_SINGLE(VI0_FIELD),
421 PINMUX_SINGLE(VI1_CLK),
422 PINMUX_SINGLE(VI1_CLKENB),
423 PINMUX_SINGLE(VI1_HSYNC_N),
424 PINMUX_SINGLE(VI1_VSYNC_N),
425 PINMUX_SINGLE(VI1_D0_B0_C0),
426 PINMUX_SINGLE(VI1_D1_B1_C1),
427 PINMUX_SINGLE(VI1_D2_B2_C2),
428 PINMUX_SINGLE(VI1_D3_B3_C3),
429 PINMUX_SINGLE(VI1_D4_B4_C4),
430 PINMUX_SINGLE(VI1_D5_B5_C5),
431 PINMUX_SINGLE(VI1_D6_B6_C6),
432 PINMUX_SINGLE(VI1_D7_B7_C7),
433 PINMUX_SINGLE(VI1_D8_G0_Y0),
434 PINMUX_SINGLE(VI1_D9_G1_Y1),
435 PINMUX_SINGLE(VI1_D10_G2_Y2),
436 PINMUX_SINGLE(VI1_D11_G3_Y3),
437 PINMUX_SINGLE(VI1_FIELD),
438 PINMUX_SINGLE(VI3_D10_Y2),
439 PINMUX_SINGLE(VI3_FIELD),
440 PINMUX_SINGLE(VI4_CLK),
441 PINMUX_SINGLE(VI5_CLK),
442 PINMUX_SINGLE(VI5_D9_Y1),
443 PINMUX_SINGLE(VI5_D10_Y2),
444 PINMUX_SINGLE(VI5_D11_Y3),
445 PINMUX_SINGLE(VI5_FIELD),
446 PINMUX_SINGLE(HRTS0_N),
447 PINMUX_SINGLE(HCTS1_N),
448 PINMUX_SINGLE(SCK0),
449 PINMUX_SINGLE(CTS0_N),
450 PINMUX_SINGLE(RTS0_N),
451 PINMUX_SINGLE(TX0),
452 PINMUX_SINGLE(RX0),
453 PINMUX_SINGLE(SCK1),
454 PINMUX_SINGLE(CTS1_N),
455 PINMUX_SINGLE(RTS1_N),
456 PINMUX_SINGLE(TX1),
457 PINMUX_SINGLE(RX1),
458 PINMUX_SINGLE(SCIF_CLK),
459 PINMUX_SINGLE(CAN0_TX),
460 PINMUX_SINGLE(CAN0_RX),
461 PINMUX_SINGLE(CAN_CLK),
462 PINMUX_SINGLE(CAN1_TX),
463 PINMUX_SINGLE(CAN1_RX),
464 PINMUX_SINGLE(SD0_CLK),
465 PINMUX_SINGLE(SD0_CMD),
466 PINMUX_SINGLE(SD0_DAT0),
467 PINMUX_SINGLE(SD0_DAT1),
468 PINMUX_SINGLE(SD0_DAT2),
469 PINMUX_SINGLE(SD0_DAT3),
470 PINMUX_SINGLE(SD0_CD),
471 PINMUX_SINGLE(SD0_WP),
472 PINMUX_SINGLE(ADICLK),
473 PINMUX_SINGLE(ADICS_SAMP),
474 PINMUX_SINGLE(ADIDATA),
475 PINMUX_SINGLE(ADICHS0),
476 PINMUX_SINGLE(ADICHS1),
477 PINMUX_SINGLE(ADICHS2),
478 PINMUX_SINGLE(AVS1),
479 PINMUX_SINGLE(AVS2),
480
481 /* IPSR0 */
482 PINMUX_IPSR_GPSR(IP0_0, DU0_DR0_DATA0),
483 PINMUX_IPSR_GPSR(IP0_1, DU0_DR1_DATA1),
484 PINMUX_IPSR_GPSR(IP0_2, DU0_DR2_Y4_DATA2),
485 PINMUX_IPSR_GPSR(IP0_3, DU0_DR3_Y5_DATA3),
486 PINMUX_IPSR_GPSR(IP0_4, DU0_DR4_Y6_DATA4),
487 PINMUX_IPSR_GPSR(IP0_5, DU0_DR5_Y7_DATA5),
488 PINMUX_IPSR_GPSR(IP0_6, DU0_DR6_Y8_DATA6),
489 PINMUX_IPSR_GPSR(IP0_7, DU0_DR7_Y9_DATA7),
490 PINMUX_IPSR_GPSR(IP0_8, DU0_DG0_DATA8),
491 PINMUX_IPSR_GPSR(IP0_9, DU0_DG1_DATA9),
492 PINMUX_IPSR_GPSR(IP0_10, DU0_DG2_C6_DATA10),
493 PINMUX_IPSR_GPSR(IP0_11, DU0_DG3_C7_DATA11),
494 PINMUX_IPSR_GPSR(IP0_12, DU0_DG4_Y0_DATA12),
495 PINMUX_IPSR_GPSR(IP0_13, DU0_DG5_Y1_DATA13),
496 PINMUX_IPSR_GPSR(IP0_14, DU0_DG6_Y2_DATA14),
497 PINMUX_IPSR_GPSR(IP0_15, DU0_DG7_Y3_DATA15),
498 PINMUX_IPSR_GPSR(IP0_16, DU0_DB0),
499 PINMUX_IPSR_GPSR(IP0_17, DU0_DB1),
500 PINMUX_IPSR_GPSR(IP0_18, DU0_DB2_C0),
501 PINMUX_IPSR_GPSR(IP0_19, DU0_DB3_C1),
502 PINMUX_IPSR_GPSR(IP0_20, DU0_DB4_C2),
503 PINMUX_IPSR_GPSR(IP0_21, DU0_DB5_C3),
504 PINMUX_IPSR_GPSR(IP0_22, DU0_DB6_C4),
505 PINMUX_IPSR_GPSR(IP0_23, DU0_DB7_C5),
506
507 /* IPSR1 */
508 PINMUX_IPSR_GPSR(IP1_0, DU0_EXHSYNC_DU0_HSYNC),
509 PINMUX_IPSR_GPSR(IP1_1, DU0_EXVSYNC_DU0_VSYNC),
510 PINMUX_IPSR_GPSR(IP1_2, DU0_EXODDF_DU0_ODDF_DISP_CDE),
511 PINMUX_IPSR_GPSR(IP1_3, DU0_DISP),
512 PINMUX_IPSR_GPSR(IP1_4, DU0_CDE),
513 PINMUX_IPSR_GPSR(IP1_5, DU1_DR2_Y4_DATA0),
514 PINMUX_IPSR_GPSR(IP1_6, DU1_DR3_Y5_DATA1),
515 PINMUX_IPSR_GPSR(IP1_7, DU1_DR4_Y6_DATA2),
516 PINMUX_IPSR_GPSR(IP1_8, DU1_DR5_Y7_DATA3),
517 PINMUX_IPSR_GPSR(IP1_9, DU1_DR6_DATA4),
518 PINMUX_IPSR_GPSR(IP1_10, DU1_DR7_DATA5),
519 PINMUX_IPSR_GPSR(IP1_11, DU1_DG2_C6_DATA6),
520 PINMUX_IPSR_GPSR(IP1_12, DU1_DG3_C7_DATA7),
521 PINMUX_IPSR_GPSR(IP1_13, DU1_DG4_Y0_DATA8),
522 PINMUX_IPSR_GPSR(IP1_14, DU1_DG5_Y1_DATA9),
523 PINMUX_IPSR_GPSR(IP1_15, DU1_DG6_Y2_DATA10),
524 PINMUX_IPSR_GPSR(IP1_16, DU1_DG7_Y3_DATA11),
525 PINMUX_IPSR_GPSR(IP1_17, A20),
526 PINMUX_IPSR_GPSR(IP1_17, MOSI_IO0),
527 PINMUX_IPSR_GPSR(IP1_18, A21),
528 PINMUX_IPSR_GPSR(IP1_18, MISO_IO1),
529 PINMUX_IPSR_GPSR(IP1_19, A22),
530 PINMUX_IPSR_GPSR(IP1_19, IO2),
531 PINMUX_IPSR_GPSR(IP1_20, A23),
532 PINMUX_IPSR_GPSR(IP1_20, IO3),
533 PINMUX_IPSR_GPSR(IP1_21, A24),
534 PINMUX_IPSR_GPSR(IP1_21, SPCLK),
535 PINMUX_IPSR_GPSR(IP1_22, A25),
536 PINMUX_IPSR_GPSR(IP1_22, SSL),
537
538 /* IPSR2 */
539 PINMUX_IPSR_GPSR(IP2_0, VI2_CLK),
540 PINMUX_IPSR_GPSR(IP2_0, AVB_RX_CLK),
541 PINMUX_IPSR_GPSR(IP2_1, VI2_CLKENB),
542 PINMUX_IPSR_GPSR(IP2_1, AVB_RX_DV),
543 PINMUX_IPSR_GPSR(IP2_2, VI2_HSYNC_N),
544 PINMUX_IPSR_GPSR(IP2_2, AVB_RXD0),
545 PINMUX_IPSR_GPSR(IP2_3, VI2_VSYNC_N),
546 PINMUX_IPSR_GPSR(IP2_3, AVB_RXD1),
547 PINMUX_IPSR_GPSR(IP2_4, VI2_D0_C0),
548 PINMUX_IPSR_GPSR(IP2_4, AVB_RXD2),
549 PINMUX_IPSR_GPSR(IP2_5, VI2_D1_C1),
550 PINMUX_IPSR_GPSR(IP2_5, AVB_RXD3),
551 PINMUX_IPSR_GPSR(IP2_6, VI2_D2_C2),
552 PINMUX_IPSR_GPSR(IP2_6, AVB_RXD4),
553 PINMUX_IPSR_GPSR(IP2_7, VI2_D3_C3),
554 PINMUX_IPSR_GPSR(IP2_7, AVB_RXD5),
555 PINMUX_IPSR_GPSR(IP2_8, VI2_D4_C4),
556 PINMUX_IPSR_GPSR(IP2_8, AVB_RXD6),
557 PINMUX_IPSR_GPSR(IP2_9, VI2_D5_C5),
558 PINMUX_IPSR_GPSR(IP2_9, AVB_RXD7),
559 PINMUX_IPSR_GPSR(IP2_10, VI2_D6_C6),
560 PINMUX_IPSR_GPSR(IP2_10, AVB_RX_ER),
561 PINMUX_IPSR_GPSR(IP2_11, VI2_D7_C7),
562 PINMUX_IPSR_GPSR(IP2_11, AVB_COL),
563 PINMUX_IPSR_GPSR(IP2_12, VI2_D8_Y0),
564 PINMUX_IPSR_GPSR(IP2_12, AVB_TXD3),
565 PINMUX_IPSR_GPSR(IP2_13, VI2_D9_Y1),
566 PINMUX_IPSR_GPSR(IP2_13, AVB_TX_EN),
567 PINMUX_IPSR_GPSR(IP2_14, VI2_D10_Y2),
568 PINMUX_IPSR_GPSR(IP2_14, AVB_TXD0),
569 PINMUX_IPSR_GPSR(IP2_15, VI2_D11_Y3),
570 PINMUX_IPSR_GPSR(IP2_15, AVB_TXD1),
571 PINMUX_IPSR_GPSR(IP2_16, VI2_FIELD),
572 PINMUX_IPSR_GPSR(IP2_16, AVB_TXD2),
573
574 /* IPSR3 */
575 PINMUX_IPSR_GPSR(IP3_0, VI3_CLK),
576 PINMUX_IPSR_GPSR(IP3_0, AVB_TX_CLK),
577 PINMUX_IPSR_GPSR(IP3_1, VI3_CLKENB),
578 PINMUX_IPSR_GPSR(IP3_1, AVB_TXD4),
579 PINMUX_IPSR_GPSR(IP3_2, VI3_HSYNC_N),
580 PINMUX_IPSR_GPSR(IP3_2, AVB_TXD5),
581 PINMUX_IPSR_GPSR(IP3_3, VI3_VSYNC_N),
582 PINMUX_IPSR_GPSR(IP3_3, AVB_TXD6),
583 PINMUX_IPSR_GPSR(IP3_4, VI3_D0_C0),
584 PINMUX_IPSR_GPSR(IP3_4, AVB_TXD7),
585 PINMUX_IPSR_GPSR(IP3_5, VI3_D1_C1),
586 PINMUX_IPSR_GPSR(IP3_5, AVB_TX_ER),
587 PINMUX_IPSR_GPSR(IP3_6, VI3_D2_C2),
588 PINMUX_IPSR_GPSR(IP3_6, AVB_GTX_CLK),
589 PINMUX_IPSR_GPSR(IP3_7, VI3_D3_C3),
590 PINMUX_IPSR_GPSR(IP3_7, AVB_MDC),
591 PINMUX_IPSR_GPSR(IP3_8, VI3_D4_C4),
592 PINMUX_IPSR_GPSR(IP3_8, AVB_MDIO),
593 PINMUX_IPSR_GPSR(IP3_9, VI3_D5_C5),
594 PINMUX_IPSR_GPSR(IP3_9, AVB_LINK),
595 PINMUX_IPSR_GPSR(IP3_10, VI3_D6_C6),
596 PINMUX_IPSR_GPSR(IP3_10, AVB_MAGIC),
597 PINMUX_IPSR_GPSR(IP3_11, VI3_D7_C7),
598 PINMUX_IPSR_GPSR(IP3_11, AVB_PHY_INT),
599 PINMUX_IPSR_GPSR(IP3_12, VI3_D8_Y0),
600 PINMUX_IPSR_GPSR(IP3_12, AVB_CRS),
601 PINMUX_IPSR_GPSR(IP3_13, VI3_D9_Y1),
602 PINMUX_IPSR_GPSR(IP3_13, AVB_GTXREFCLK),
603 PINMUX_IPSR_GPSR(IP3_14, VI3_D11_Y3),
604 PINMUX_IPSR_GPSR(IP3_14, AVB_AVTP_MATCH),
605
606 /* IPSR4 */
607 PINMUX_IPSR_GPSR(IP4_0, VI4_CLKENB),
608 PINMUX_IPSR_GPSR(IP4_0, VI0_D12_G4_Y4),
609 PINMUX_IPSR_GPSR(IP4_1, VI4_HSYNC_N),
610 PINMUX_IPSR_GPSR(IP4_1, VI0_D13_G5_Y5),
611 PINMUX_IPSR_GPSR(IP4_3_2, VI4_VSYNC_N),
612 PINMUX_IPSR_GPSR(IP4_3_2, VI0_D14_G6_Y6),
613 PINMUX_IPSR_GPSR(IP4_4, VI4_D0_C0),
614 PINMUX_IPSR_GPSR(IP4_4, VI0_D15_G7_Y7),
615 PINMUX_IPSR_GPSR(IP4_6_5, VI4_D1_C1),
616 PINMUX_IPSR_GPSR(IP4_6_5, VI0_D16_R0),
617 PINMUX_IPSR_MSEL(IP4_6_5, VI1_D12_G4_Y4, SEL_VI1_0),
618 PINMUX_IPSR_GPSR(IP4_8_7, VI4_D2_C2),
619 PINMUX_IPSR_GPSR(IP4_8_7, VI0_D17_R1),
620 PINMUX_IPSR_MSEL(IP4_8_7, VI1_D13_G5_Y5, SEL_VI1_0),
621 PINMUX_IPSR_GPSR(IP4_10_9, VI4_D3_C3),
622 PINMUX_IPSR_GPSR(IP4_10_9, VI0_D18_R2),
623 PINMUX_IPSR_MSEL(IP4_10_9, VI1_D14_G6_Y6, SEL_VI1_0),
624 PINMUX_IPSR_GPSR(IP4_12_11, VI4_D4_C4),
625 PINMUX_IPSR_GPSR(IP4_12_11, VI0_D19_R3),
626 PINMUX_IPSR_MSEL(IP4_12_11, VI1_D15_G7_Y7, SEL_VI1_0),
627 PINMUX_IPSR_GPSR(IP4_14_13, VI4_D5_C5),
628 PINMUX_IPSR_GPSR(IP4_14_13, VI0_D20_R4),
629 PINMUX_IPSR_GPSR(IP4_14_13, VI2_D12_Y4),
630 PINMUX_IPSR_GPSR(IP4_16_15, VI4_D6_C6),
631 PINMUX_IPSR_GPSR(IP4_16_15, VI0_D21_R5),
632 PINMUX_IPSR_GPSR(IP4_16_15, VI2_D13_Y5),
633 PINMUX_IPSR_GPSR(IP4_18_17, VI4_D7_C7),
634 PINMUX_IPSR_GPSR(IP4_18_17, VI0_D22_R6),
635 PINMUX_IPSR_GPSR(IP4_18_17, VI2_D14_Y6),
636 PINMUX_IPSR_GPSR(IP4_20_19, VI4_D8_Y0),
637 PINMUX_IPSR_GPSR(IP4_20_19, VI0_D23_R7),
638 PINMUX_IPSR_GPSR(IP4_20_19, VI2_D15_Y7),
639 PINMUX_IPSR_GPSR(IP4_21, VI4_D9_Y1),
640 PINMUX_IPSR_GPSR(IP4_21, VI3_D12_Y4),
641 PINMUX_IPSR_GPSR(IP4_22, VI4_D10_Y2),
642 PINMUX_IPSR_GPSR(IP4_22, VI3_D13_Y5),
643 PINMUX_IPSR_GPSR(IP4_23, VI4_D11_Y3),
644 PINMUX_IPSR_GPSR(IP4_23, VI3_D14_Y6),
645 PINMUX_IPSR_GPSR(IP4_24, VI4_FIELD),
646 PINMUX_IPSR_GPSR(IP4_24, VI3_D15_Y7),
647
648 /* IPSR5 */
649 PINMUX_IPSR_GPSR(IP5_0, VI5_CLKENB),
650 PINMUX_IPSR_MSEL(IP5_0, VI1_D12_G4_Y4_B, SEL_VI1_1),
651 PINMUX_IPSR_GPSR(IP5_1, VI5_HSYNC_N),
652 PINMUX_IPSR_MSEL(IP5_1, VI1_D13_G5_Y5_B, SEL_VI1_1),
653 PINMUX_IPSR_GPSR(IP5_2, VI5_VSYNC_N),
654 PINMUX_IPSR_MSEL(IP5_2, VI1_D14_G6_Y6_B, SEL_VI1_1),
655 PINMUX_IPSR_GPSR(IP5_3, VI5_D0_C0),
656 PINMUX_IPSR_MSEL(IP5_3, VI1_D15_G7_Y7_B, SEL_VI1_1),
657 PINMUX_IPSR_GPSR(IP5_4, VI5_D1_C1),
658 PINMUX_IPSR_GPSR(IP5_4, VI1_D16_R0),
659 PINMUX_IPSR_GPSR(IP5_5, VI5_D2_C2),
660 PINMUX_IPSR_GPSR(IP5_5, VI1_D17_R1),
661 PINMUX_IPSR_GPSR(IP5_6, VI5_D3_C3),
662 PINMUX_IPSR_GPSR(IP5_6, VI1_D18_R2),
663 PINMUX_IPSR_GPSR(IP5_7, VI5_D4_C4),
664 PINMUX_IPSR_GPSR(IP5_7, VI1_D19_R3),
665 PINMUX_IPSR_GPSR(IP5_8, VI5_D5_C5),
666 PINMUX_IPSR_GPSR(IP5_8, VI1_D20_R4),
667 PINMUX_IPSR_GPSR(IP5_9, VI5_D6_C6),
668 PINMUX_IPSR_GPSR(IP5_9, VI1_D21_R5),
669 PINMUX_IPSR_GPSR(IP5_10, VI5_D7_C7),
670 PINMUX_IPSR_GPSR(IP5_10, VI1_D22_R6),
671 PINMUX_IPSR_GPSR(IP5_11, VI5_D8_Y0),
672 PINMUX_IPSR_GPSR(IP5_11, VI1_D23_R7),
673
674 /* IPSR6 */
675 PINMUX_IPSR_GPSR(IP6_0, MSIOF0_SCK),
676 PINMUX_IPSR_GPSR(IP6_0, HSCK0),
677 PINMUX_IPSR_GPSR(IP6_1, MSIOF0_SYNC),
678 PINMUX_IPSR_GPSR(IP6_1, HCTS0_N),
679 PINMUX_IPSR_GPSR(IP6_2, MSIOF0_TXD),
680 PINMUX_IPSR_GPSR(IP6_2, HTX0),
681 PINMUX_IPSR_GPSR(IP6_3, MSIOF0_RXD),
682 PINMUX_IPSR_GPSR(IP6_3, HRX0),
683 PINMUX_IPSR_GPSR(IP6_4, MSIOF1_SCK),
684 PINMUX_IPSR_GPSR(IP6_4, HSCK1),
685 PINMUX_IPSR_GPSR(IP6_5, MSIOF1_SYNC),
686 PINMUX_IPSR_GPSR(IP6_5, HRTS1_N),
687 PINMUX_IPSR_GPSR(IP6_6, MSIOF1_TXD),
688 PINMUX_IPSR_GPSR(IP6_6, HTX1),
689 PINMUX_IPSR_GPSR(IP6_7, MSIOF1_RXD),
690 PINMUX_IPSR_GPSR(IP6_7, HRX1),
691 PINMUX_IPSR_GPSR(IP6_9_8, DRACK0),
692 PINMUX_IPSR_GPSR(IP6_9_8, SCK2),
693 PINMUX_IPSR_GPSR(IP6_11_10, DACK0),
694 PINMUX_IPSR_GPSR(IP6_11_10, TX2),
695 PINMUX_IPSR_GPSR(IP6_13_12, DREQ0_N),
696 PINMUX_IPSR_GPSR(IP6_13_12, RX2),
697 PINMUX_IPSR_GPSR(IP6_15_14, DACK1),
698 PINMUX_IPSR_GPSR(IP6_15_14, SCK3),
699 PINMUX_IPSR_GPSR(IP6_16, TX3),
700 PINMUX_IPSR_GPSR(IP6_18_17, DREQ1_N),
701 PINMUX_IPSR_GPSR(IP6_18_17, RX3),
702
703 /* IPSR7 */
704 PINMUX_IPSR_GPSR(IP7_1_0, PWM0),
705 PINMUX_IPSR_GPSR(IP7_1_0, TCLK1),
706 PINMUX_IPSR_GPSR(IP7_1_0, FSO_CFE_0),
707 PINMUX_IPSR_GPSR(IP7_3_2, PWM1),
708 PINMUX_IPSR_GPSR(IP7_3_2, TCLK2),
709 PINMUX_IPSR_GPSR(IP7_3_2, FSO_CFE_1),
710 PINMUX_IPSR_GPSR(IP7_5_4, PWM2),
711 PINMUX_IPSR_GPSR(IP7_5_4, TCLK3),
712 PINMUX_IPSR_GPSR(IP7_5_4, FSO_TOE),
713 PINMUX_IPSR_GPSR(IP7_6, PWM3),
714 PINMUX_IPSR_GPSR(IP7_7, PWM4),
715 PINMUX_IPSR_GPSR(IP7_9_8, SSI_SCK34),
716 PINMUX_IPSR_GPSR(IP7_9_8, TPU0TO0),
717 PINMUX_IPSR_GPSR(IP7_11_10, SSI_WS34),
718 PINMUX_IPSR_GPSR(IP7_11_10, TPU0TO1),
719 PINMUX_IPSR_GPSR(IP7_13_12, SSI_SDATA3),
720 PINMUX_IPSR_GPSR(IP7_13_12, TPU0TO2),
721 PINMUX_IPSR_GPSR(IP7_15_14, SSI_SCK4),
722 PINMUX_IPSR_GPSR(IP7_15_14, TPU0TO3),
723 PINMUX_IPSR_GPSR(IP7_16, SSI_WS4),
724 PINMUX_IPSR_GPSR(IP7_17, SSI_SDATA4),
725 PINMUX_IPSR_GPSR(IP7_18, AUDIO_CLKOUT),
726 PINMUX_IPSR_GPSR(IP7_19, AUDIO_CLKA),
727 PINMUX_IPSR_GPSR(IP7_20, AUDIO_CLKB),
728 };
729
730 static const struct sh_pfc_pin pinmux_pins[] = {
731 PINMUX_GPIO_GP_ALL(),
732 };
733
734 /* - AVB -------------------------------------------------------------------- */
735 static const unsigned int avb_link_pins[] = {
736 RCAR_GP_PIN(7, 9),
737 };
738 static const unsigned int avb_link_mux[] = {
739 AVB_LINK_MARK,
740 };
741 static const unsigned int avb_magic_pins[] = {
742 RCAR_GP_PIN(7, 10),
743 };
744 static const unsigned int avb_magic_mux[] = {
745 AVB_MAGIC_MARK,
746 };
747 static const unsigned int avb_phy_int_pins[] = {
748 RCAR_GP_PIN(7, 11),
749 };
750 static const unsigned int avb_phy_int_mux[] = {
751 AVB_PHY_INT_MARK,
752 };
753 static const unsigned int avb_mdio_pins[] = {
754 RCAR_GP_PIN(7, 7), RCAR_GP_PIN(7, 8),
755 };
756 static const unsigned int avb_mdio_mux[] = {
757 AVB_MDC_MARK, AVB_MDIO_MARK,
758 };
759 static const unsigned int avb_mii_pins[] = {
760 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 16),
761 RCAR_GP_PIN(6, 12),
762
763 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3), RCAR_GP_PIN(6, 4),
764 RCAR_GP_PIN(6, 5),
765
766 RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
767 RCAR_GP_PIN(7, 12), RCAR_GP_PIN(6, 13), RCAR_GP_PIN(7, 5),
768 RCAR_GP_PIN(7, 0), RCAR_GP_PIN(6, 11),
769 };
770 static const unsigned int avb_mii_mux[] = {
771 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
772 AVB_TXD3_MARK,
773
774 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
775 AVB_RXD3_MARK,
776
777 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
778 AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
779 AVB_TX_CLK_MARK, AVB_COL_MARK,
780 };
781 static const unsigned int avb_gmii_pins[] = {
782 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 16),
783 RCAR_GP_PIN(6, 12), RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 2),
784 RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4),
785
786 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3), RCAR_GP_PIN(6, 4),
787 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
788 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
789
790 RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
791 RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 13),
792 RCAR_GP_PIN(6, 13), RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 0),
793 RCAR_GP_PIN(6, 11),
794 };
795 static const unsigned int avb_gmii_mux[] = {
796 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
797 AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
798 AVB_TXD6_MARK, AVB_TXD7_MARK,
799
800 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
801 AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
802 AVB_RXD6_MARK, AVB_RXD7_MARK,
803
804 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
805 AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
806 AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
807 AVB_COL_MARK,
808 };
809 static const unsigned int avb_avtp_match_pins[] = {
810 RCAR_GP_PIN(7, 15),
811 };
812 static const unsigned int avb_avtp_match_mux[] = {
813 AVB_AVTP_MATCH_MARK,
814 };
815 /* - CAN -------------------------------------------------------------------- */
816 static const unsigned int can0_data_pins[] = {
817 /* TX, RX */
818 RCAR_GP_PIN(10, 27), RCAR_GP_PIN(10, 28),
819 };
820 static const unsigned int can0_data_mux[] = {
821 CAN0_TX_MARK, CAN0_RX_MARK,
822 };
823 static const unsigned int can1_data_pins[] = {
824 /* TX, RX */
825 RCAR_GP_PIN(10, 30), RCAR_GP_PIN(10, 31),
826 };
827 static const unsigned int can1_data_mux[] = {
828 CAN1_TX_MARK, CAN1_RX_MARK,
829 };
830 static const unsigned int can_clk_pins[] = {
831 /* CAN_CLK */
832 RCAR_GP_PIN(10, 29),
833 };
834 static const unsigned int can_clk_mux[] = {
835 CAN_CLK_MARK,
836 };
837 /* - DU --------------------------------------------------------------------- */
838 static const unsigned int du0_rgb666_pins[] = {
839 /* R[7:2], G[7:2], B[7:2] */
840 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5),
841 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2),
842 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
843 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
844 RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 21),
845 RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 18),
846 };
847 static const unsigned int du0_rgb666_mux[] = {
848 DU0_DR7_Y9_DATA7_MARK, DU0_DR6_Y8_DATA6_MARK, DU0_DR5_Y7_DATA5_MARK,
849 DU0_DR4_Y6_DATA4_MARK, DU0_DR3_Y5_DATA3_MARK, DU0_DR2_Y4_DATA2_MARK,
850 DU0_DG7_Y3_DATA15_MARK, DU0_DG6_Y2_DATA14_MARK, DU0_DG5_Y1_DATA13_MARK,
851 DU0_DG4_Y0_DATA12_MARK, DU0_DG3_C7_DATA11_MARK, DU0_DG2_C6_DATA10_MARK,
852 DU0_DB7_C5_MARK, DU0_DB6_C4_MARK, DU0_DB5_C3_MARK,
853 DU0_DB4_C2_MARK, DU0_DB3_C1_MARK, DU0_DB2_C0_MARK,
854 };
855 static const unsigned int du0_rgb888_pins[] = {
856 /* R[7:0], G[7:0], B[7:0] */
857 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5),
858 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2),
859 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
860 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
861 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
862 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
863 RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 21),
864 RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 18),
865 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
866 };
867 static const unsigned int du0_rgb888_mux[] = {
868 DU0_DR7_Y9_DATA7_MARK, DU0_DR6_Y8_DATA6_MARK, DU0_DR5_Y7_DATA5_MARK,
869 DU0_DR4_Y6_DATA4_MARK, DU0_DR3_Y5_DATA3_MARK, DU0_DR2_Y4_DATA2_MARK,
870 DU0_DR1_DATA1_MARK, DU0_DR0_DATA0_MARK,
871 DU0_DG7_Y3_DATA15_MARK, DU0_DG6_Y2_DATA14_MARK, DU0_DG5_Y1_DATA13_MARK,
872 DU0_DG4_Y0_DATA12_MARK, DU0_DG3_C7_DATA11_MARK, DU0_DG2_C6_DATA10_MARK,
873 DU0_DG1_DATA9_MARK, DU0_DG0_DATA8_MARK,
874 DU0_DB7_C5_MARK, DU0_DB6_C4_MARK, DU0_DB5_C3_MARK,
875 DU0_DB4_C2_MARK, DU0_DB3_C1_MARK, DU0_DB2_C0_MARK,
876 DU0_DB1_MARK, DU0_DB0_MARK,
877 };
878 static const unsigned int du0_sync_pins[] = {
879 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
880 RCAR_GP_PIN(0, 25), RCAR_GP_PIN(0, 24),
881 };
882 static const unsigned int du0_sync_mux[] = {
883 DU0_EXVSYNC_DU0_VSYNC_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK,
884 };
885 static const unsigned int du0_oddf_pins[] = {
886 /* EXODDF/ODDF/DISP/CDE */
887 RCAR_GP_PIN(0, 26),
888 };
889 static const unsigned int du0_oddf_mux[] = {
890 DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK
891 };
892 static const unsigned int du0_disp_pins[] = {
893 /* DISP */
894 RCAR_GP_PIN(0, 27),
895 };
896 static const unsigned int du0_disp_mux[] = {
897 DU0_DISP_MARK,
898 };
899 static const unsigned int du0_cde_pins[] = {
900 /* CDE */
901 RCAR_GP_PIN(0, 28),
902 };
903 static const unsigned int du0_cde_mux[] = {
904 DU0_CDE_MARK,
905 };
906 static const unsigned int du1_rgb666_pins[] = {
907 /* R[7:2], G[7:2], B[7:2] */
908 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3),
909 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
910 RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
911 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
912 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15),
913 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12),
914 };
915 static const unsigned int du1_rgb666_mux[] = {
916 DU1_DR7_DATA5_MARK, DU1_DR6_DATA4_MARK, DU1_DR5_Y7_DATA3_MARK,
917 DU1_DR4_Y6_DATA2_MARK, DU1_DR3_Y5_DATA1_MARK, DU1_DR2_Y4_DATA0_MARK,
918 DU1_DG7_Y3_DATA11_MARK, DU1_DG6_Y2_DATA10_MARK, DU1_DG5_Y1_DATA9_MARK,
919 DU1_DG4_Y0_DATA8_MARK, DU1_DG3_C7_DATA7_MARK, DU1_DG2_C6_DATA6_MARK,
920 DU1_DB7_C5_MARK, DU1_DB6_C4_MARK, DU1_DB5_C3_DATA15_MARK,
921 DU1_DB4_C2_DATA14_MARK, DU1_DB3_C1_DATA13_MARK, DU1_DB2_C0_DATA12_MARK,
922 };
923 static const unsigned int du1_sync_pins[] = {
924 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
925 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
926 };
927 static const unsigned int du1_sync_mux[] = {
928 DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
929 };
930 static const unsigned int du1_oddf_pins[] = {
931 /* EXODDF/ODDF/DISP/CDE */
932 RCAR_GP_PIN(1, 20),
933 };
934 static const unsigned int du1_oddf_mux[] = {
935 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK
936 };
937 static const unsigned int du1_disp_pins[] = {
938 /* DISP */
939 RCAR_GP_PIN(1, 21),
940 };
941 static const unsigned int du1_disp_mux[] = {
942 DU1_DISP_MARK,
943 };
944 static const unsigned int du1_cde_pins[] = {
945 /* CDE */
946 RCAR_GP_PIN(1, 22),
947 };
948 static const unsigned int du1_cde_mux[] = {
949 DU1_CDE_MARK,
950 };
951 /* - INTC ------------------------------------------------------------------- */
952 static const unsigned int intc_irq0_pins[] = {
953 /* IRQ0 */
954 RCAR_GP_PIN(3, 19),
955 };
956 static const unsigned int intc_irq0_mux[] = {
957 IRQ0_MARK,
958 };
959 static const unsigned int intc_irq1_pins[] = {
960 /* IRQ1 */
961 RCAR_GP_PIN(3, 20),
962 };
963 static const unsigned int intc_irq1_mux[] = {
964 IRQ1_MARK,
965 };
966 static const unsigned int intc_irq2_pins[] = {
967 /* IRQ2 */
968 RCAR_GP_PIN(3, 21),
969 };
970 static const unsigned int intc_irq2_mux[] = {
971 IRQ2_MARK,
972 };
973 static const unsigned int intc_irq3_pins[] = {
974 /* IRQ3 */
975 RCAR_GP_PIN(3, 22),
976 };
977 static const unsigned int intc_irq3_mux[] = {
978 IRQ3_MARK,
979 };
980 /* - LBSC ------------------------------------------------------------------- */
981 static const unsigned int lbsc_cs0_pins[] = {
982 /* CS0# */
983 RCAR_GP_PIN(3, 27),
984 };
985 static const unsigned int lbsc_cs0_mux[] = {
986 CS0_N_MARK,
987 };
988 static const unsigned int lbsc_cs1_pins[] = {
989 /* CS1#_A26 */
990 RCAR_GP_PIN(3, 6),
991 };
992 static const unsigned int lbsc_cs1_mux[] = {
993 CS1_N_A26_MARK,
994 };
995 static const unsigned int lbsc_ex_cs0_pins[] = {
996 /* EX_CS0# */
997 RCAR_GP_PIN(3, 7),
998 };
999 static const unsigned int lbsc_ex_cs0_mux[] = {
1000 EX_CS0_N_MARK,
1001 };
1002 static const unsigned int lbsc_ex_cs1_pins[] = {
1003 /* EX_CS1# */
1004 RCAR_GP_PIN(3, 8),
1005 };
1006 static const unsigned int lbsc_ex_cs1_mux[] = {
1007 EX_CS1_N_MARK,
1008 };
1009 static const unsigned int lbsc_ex_cs2_pins[] = {
1010 /* EX_CS2# */
1011 RCAR_GP_PIN(3, 9),
1012 };
1013 static const unsigned int lbsc_ex_cs2_mux[] = {
1014 EX_CS2_N_MARK,
1015 };
1016 static const unsigned int lbsc_ex_cs3_pins[] = {
1017 /* EX_CS3# */
1018 RCAR_GP_PIN(3, 10),
1019 };
1020 static const unsigned int lbsc_ex_cs3_mux[] = {
1021 EX_CS3_N_MARK,
1022 };
1023 static const unsigned int lbsc_ex_cs4_pins[] = {
1024 /* EX_CS4# */
1025 RCAR_GP_PIN(3, 11),
1026 };
1027 static const unsigned int lbsc_ex_cs4_mux[] = {
1028 EX_CS4_N_MARK,
1029 };
1030 static const unsigned int lbsc_ex_cs5_pins[] = {
1031 /* EX_CS5# */
1032 RCAR_GP_PIN(3, 12),
1033 };
1034 static const unsigned int lbsc_ex_cs5_mux[] = {
1035 EX_CS5_N_MARK,
1036 };
1037 /* - MSIOF0 ----------------------------------------------------------------- */
1038 static const unsigned int msiof0_clk_pins[] = {
1039 /* SCK */
1040 RCAR_GP_PIN(10, 0),
1041 };
1042 static const unsigned int msiof0_clk_mux[] = {
1043 MSIOF0_SCK_MARK,
1044 };
1045 static const unsigned int msiof0_sync_pins[] = {
1046 /* SYNC */
1047 RCAR_GP_PIN(10, 1),
1048 };
1049 static const unsigned int msiof0_sync_mux[] = {
1050 MSIOF0_SYNC_MARK,
1051 };
1052 static const unsigned int msiof0_rx_pins[] = {
1053 /* RXD */
1054 RCAR_GP_PIN(10, 4),
1055 };
1056 static const unsigned int msiof0_rx_mux[] = {
1057 MSIOF0_RXD_MARK,
1058 };
1059 static const unsigned int msiof0_tx_pins[] = {
1060 /* TXD */
1061 RCAR_GP_PIN(10, 3),
1062 };
1063 static const unsigned int msiof0_tx_mux[] = {
1064 MSIOF0_TXD_MARK,
1065 };
1066 /* - MSIOF1 ----------------------------------------------------------------- */
1067 static const unsigned int msiof1_clk_pins[] = {
1068 /* SCK */
1069 RCAR_GP_PIN(10, 5),
1070 };
1071 static const unsigned int msiof1_clk_mux[] = {
1072 MSIOF1_SCK_MARK,
1073 };
1074 static const unsigned int msiof1_sync_pins[] = {
1075 /* SYNC */
1076 RCAR_GP_PIN(10, 6),
1077 };
1078 static const unsigned int msiof1_sync_mux[] = {
1079 MSIOF1_SYNC_MARK,
1080 };
1081 static const unsigned int msiof1_rx_pins[] = {
1082 /* RXD */
1083 RCAR_GP_PIN(10, 9),
1084 };
1085 static const unsigned int msiof1_rx_mux[] = {
1086 MSIOF1_RXD_MARK,
1087 };
1088 static const unsigned int msiof1_tx_pins[] = {
1089 /* TXD */
1090 RCAR_GP_PIN(10, 8),
1091 };
1092 static const unsigned int msiof1_tx_mux[] = {
1093 MSIOF1_TXD_MARK,
1094 };
1095 /* - QSPI ------------------------------------------------------------------- */
1096 static const unsigned int qspi_ctrl_pins[] = {
1097 /* SPCLK, SSL */
1098 RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
1099 };
1100 static const unsigned int qspi_ctrl_mux[] = {
1101 SPCLK_MARK, SSL_MARK,
1102 };
1103 static const unsigned int qspi_data2_pins[] = {
1104 /* MOSI_IO0, MISO_IO1 */
1105 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1106 };
1107 static const unsigned int qspi_data2_mux[] = {
1108 MOSI_IO0_MARK, MISO_IO1_MARK,
1109 };
1110 static const unsigned int qspi_data4_pins[] = {
1111 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
1112 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 23),
1113 RCAR_GP_PIN(3, 24),
1114 };
1115 static const unsigned int qspi_data4_mux[] = {
1116 MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
1117 };
1118 /* - SCIF0 ------------------------------------------------------------------ */
1119 static const unsigned int scif0_data_pins[] = {
1120 /* RX, TX */
1121 RCAR_GP_PIN(10, 14), RCAR_GP_PIN(10, 13),
1122 };
1123 static const unsigned int scif0_data_mux[] = {
1124 RX0_MARK, TX0_MARK,
1125 };
1126 static const unsigned int scif0_clk_pins[] = {
1127 /* SCK */
1128 RCAR_GP_PIN(10, 10),
1129 };
1130 static const unsigned int scif0_clk_mux[] = {
1131 SCK0_MARK,
1132 };
1133 static const unsigned int scif0_ctrl_pins[] = {
1134 /* RTS, CTS */
1135 RCAR_GP_PIN(10, 12), RCAR_GP_PIN(10, 11),
1136 };
1137 static const unsigned int scif0_ctrl_mux[] = {
1138 RTS0_N_MARK, CTS0_N_MARK,
1139 };
1140 /* - SCIF1 ------------------------------------------------------------------ */
1141 static const unsigned int scif1_data_pins[] = {
1142 /* RX, TX */
1143 RCAR_GP_PIN(10, 19), RCAR_GP_PIN(10, 18),
1144 };
1145 static const unsigned int scif1_data_mux[] = {
1146 RX1_MARK, TX1_MARK,
1147 };
1148 static const unsigned int scif1_clk_pins[] = {
1149 /* SCK */
1150 RCAR_GP_PIN(10, 15),
1151 };
1152 static const unsigned int scif1_clk_mux[] = {
1153 SCK1_MARK,
1154 };
1155 static const unsigned int scif1_ctrl_pins[] = {
1156 /* RTS, CTS */
1157 RCAR_GP_PIN(10, 17), RCAR_GP_PIN(10, 16),
1158 };
1159 static const unsigned int scif1_ctrl_mux[] = {
1160 RTS1_N_MARK, CTS1_N_MARK,
1161 };
1162 /* - SCIF2 ------------------------------------------------------------------ */
1163 static const unsigned int scif2_data_pins[] = {
1164 /* RX, TX */
1165 RCAR_GP_PIN(10, 22), RCAR_GP_PIN(10, 21),
1166 };
1167 static const unsigned int scif2_data_mux[] = {
1168 RX2_MARK, TX2_MARK,
1169 };
1170 static const unsigned int scif2_clk_pins[] = {
1171 /* SCK */
1172 RCAR_GP_PIN(10, 20),
1173 };
1174 static const unsigned int scif2_clk_mux[] = {
1175 SCK2_MARK,
1176 };
1177 /* - SCIF3 ------------------------------------------------------------------ */
1178 static const unsigned int scif3_data_pins[] = {
1179 /* RX, TX */
1180 RCAR_GP_PIN(10, 25), RCAR_GP_PIN(10, 24),
1181 };
1182 static const unsigned int scif3_data_mux[] = {
1183 RX3_MARK, TX3_MARK,
1184 };
1185 static const unsigned int scif3_clk_pins[] = {
1186 /* SCK */
1187 RCAR_GP_PIN(10, 23),
1188 };
1189 static const unsigned int scif3_clk_mux[] = {
1190 SCK3_MARK,
1191 };
1192 /* - SDHI0 ------------------------------------------------------------------ */
1193 static const unsigned int sdhi0_data1_pins[] = {
1194 /* DAT0 */
1195 RCAR_GP_PIN(11, 7),
1196 };
1197 static const unsigned int sdhi0_data1_mux[] = {
1198 SD0_DAT0_MARK,
1199 };
1200 static const unsigned int sdhi0_data4_pins[] = {
1201 /* DAT[0-3] */
1202 RCAR_GP_PIN(11, 7), RCAR_GP_PIN(11, 8),
1203 RCAR_GP_PIN(11, 9), RCAR_GP_PIN(11, 10),
1204 };
1205 static const unsigned int sdhi0_data4_mux[] = {
1206 SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
1207 };
1208 static const unsigned int sdhi0_ctrl_pins[] = {
1209 /* CLK, CMD */
1210 RCAR_GP_PIN(11, 5), RCAR_GP_PIN(11, 6),
1211 };
1212 static const unsigned int sdhi0_ctrl_mux[] = {
1213 SD0_CLK_MARK, SD0_CMD_MARK,
1214 };
1215 static const unsigned int sdhi0_cd_pins[] = {
1216 /* CD */
1217 RCAR_GP_PIN(11, 11),
1218 };
1219 static const unsigned int sdhi0_cd_mux[] = {
1220 SD0_CD_MARK,
1221 };
1222 static const unsigned int sdhi0_wp_pins[] = {
1223 /* WP */
1224 RCAR_GP_PIN(11, 12),
1225 };
1226 static const unsigned int sdhi0_wp_mux[] = {
1227 SD0_WP_MARK,
1228 };
1229 /* - VIN0 ------------------------------------------------------------------- */
1230 static const union vin_data vin0_data_pins = {
1231 .data24 = {
1232 /* B */
1233 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1234 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
1235 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1236 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1237 /* G */
1238 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13),
1239 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
1240 RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 2),
1241 RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 4),
1242 /* R */
1243 RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),
1244 RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
1245 RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),
1246 RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
1247 },
1248 };
1249 static const union vin_data vin0_data_mux = {
1250 .data24 = {
1251 /* B */
1252 VI0_D0_B0_C0_MARK, VI0_D1_B1_C1_MARK,
1253 VI0_D2_B2_C2_MARK, VI0_D3_B3_C3_MARK,
1254 VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK,
1255 VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK,
1256 /* G */
1257 VI0_D8_G0_Y0_MARK, VI0_D9_G1_Y1_MARK,
1258 VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK,
1259 VI0_D12_G4_Y4_MARK, VI0_D13_G5_Y5_MARK,
1260 VI0_D14_G6_Y6_MARK, VI0_D15_G7_Y7_MARK,
1261 /* R */
1262 VI0_D16_R0_MARK, VI0_D17_R1_MARK,
1263 VI0_D18_R2_MARK, VI0_D19_R3_MARK,
1264 VI0_D20_R4_MARK, VI0_D21_R5_MARK,
1265 VI0_D22_R6_MARK, VI0_D23_R7_MARK,
1266 },
1267 };
1268 static const unsigned int vin0_data18_pins[] = {
1269 /* B */
1270 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
1271 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1272 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1273 /* G */
1274 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
1275 RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 2),
1276 RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 4),
1277 /* R */
1278 RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
1279 RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),
1280 RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
1281 };
1282 static const unsigned int vin0_data18_mux[] = {
1283 /* B */
1284 VI0_D2_B2_C2_MARK, VI0_D3_B3_C3_MARK,
1285 VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK,
1286 VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK,
1287 /* G */
1288 VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK,
1289 VI0_D12_G4_Y4_MARK, VI0_D13_G5_Y5_MARK,
1290 VI0_D14_G6_Y6_MARK, VI0_D15_G7_Y7_MARK,
1291 /* R */
1292 VI0_D18_R2_MARK, VI0_D19_R3_MARK,
1293 VI0_D20_R4_MARK, VI0_D21_R5_MARK,
1294 VI0_D22_R6_MARK, VI0_D23_R7_MARK,
1295 };
1296 static const unsigned int vin0_sync_pins[] = {
1297 /* HSYNC#, VSYNC# */
1298 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
1299 };
1300 static const unsigned int vin0_sync_mux[] = {
1301 VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK,
1302 };
1303 static const unsigned int vin0_field_pins[] = {
1304 RCAR_GP_PIN(4, 16),
1305 };
1306 static const unsigned int vin0_field_mux[] = {
1307 VI0_FIELD_MARK,
1308 };
1309 static const unsigned int vin0_clkenb_pins[] = {
1310 RCAR_GP_PIN(4, 1),
1311 };
1312 static const unsigned int vin0_clkenb_mux[] = {
1313 VI0_CLKENB_MARK,
1314 };
1315 static const unsigned int vin0_clk_pins[] = {
1316 RCAR_GP_PIN(4, 0),
1317 };
1318 static const unsigned int vin0_clk_mux[] = {
1319 VI0_CLK_MARK,
1320 };
1321 /* - VIN1 ------------------------------------------------------------------- */
1322 static const union vin_data vin1_data_pins = {
1323 .data24 = {
1324 /* B */
1325 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
1326 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1327 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1328 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1329 /* G */
1330 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
1331 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1332 RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),
1333 RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
1334 /* R */
1335 RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6),
1336 RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
1337 RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
1338 RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
1339 },
1340 };
1341 static const union vin_data vin1_data_mux = {
1342 .data24 = {
1343 /* B */
1344 VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK,
1345 VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
1346 VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
1347 VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
1348 /* G */
1349 VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK,
1350 VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
1351 VI1_D12_G4_Y4_MARK, VI1_D13_G5_Y5_MARK,
1352 VI1_D14_G6_Y6_MARK, VI1_D15_G7_Y7_MARK,
1353 /* R */
1354 VI1_D16_R0_MARK, VI1_D17_R1_MARK,
1355 VI1_D18_R2_MARK, VI1_D19_R3_MARK,
1356 VI1_D20_R4_MARK, VI1_D21_R5_MARK,
1357 VI1_D22_R6_MARK, VI1_D23_R7_MARK,
1358 },
1359 };
1360 static const unsigned int vin1_data18_pins[] = {
1361 /* B */
1362 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1363 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1364 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1365 /* G */
1366 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1367 RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),
1368 RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
1369 /* R */
1370 RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
1371 RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
1372 RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
1373 };
1374 static const unsigned int vin1_data18_mux[] = {
1375 /* B */
1376 VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
1377 VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
1378 VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
1379 /* G */
1380 VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
1381 VI1_D12_G4_Y4_MARK, VI1_D13_G5_Y5_MARK,
1382 VI1_D14_G6_Y6_MARK, VI1_D15_G7_Y7_MARK,
1383 /* R */
1384 VI1_D18_R2_MARK, VI1_D19_R3_MARK,
1385 VI1_D20_R4_MARK, VI1_D21_R5_MARK,
1386 VI1_D22_R6_MARK, VI1_D23_R7_MARK,
1387 };
1388 static const union vin_data vin1_data_b_pins = {
1389 .data24 = {
1390 /* B */
1391 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
1392 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1393 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1394 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1395 /* G */
1396 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
1397 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1398 RCAR_GP_PIN(9, 1), RCAR_GP_PIN(9, 2),
1399 RCAR_GP_PIN(9, 3), RCAR_GP_PIN(9, 4),
1400 /* R */
1401 RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6),
1402 RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
1403 RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
1404 RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
1405 },
1406 };
1407 static const union vin_data vin1_data_b_mux = {
1408 .data24 = {
1409 /* B */
1410 VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK,
1411 VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
1412 VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
1413 VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
1414 /* G */
1415 VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK,
1416 VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
1417 VI1_D12_G4_Y4_B_MARK, VI1_D13_G5_Y5_B_MARK,
1418 VI1_D14_G6_Y6_B_MARK, VI1_D15_G7_Y7_B_MARK,
1419 /* R */
1420 VI1_D16_R0_MARK, VI1_D17_R1_MARK,
1421 VI1_D18_R2_MARK, VI1_D19_R3_MARK,
1422 VI1_D20_R4_MARK, VI1_D21_R5_MARK,
1423 VI1_D22_R6_MARK, VI1_D23_R7_MARK,
1424 },
1425 };
1426 static const unsigned int vin1_data18_b_pins[] = {
1427 /* B */
1428 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1429 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1430 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1431 /* G */
1432 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1433 RCAR_GP_PIN(9, 1), RCAR_GP_PIN(9, 2),
1434 RCAR_GP_PIN(9, 3), RCAR_GP_PIN(9, 4),
1435 /* R */
1436 RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
1437 RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
1438 RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
1439 };
1440 static const unsigned int vin1_data18_b_mux[] = {
1441 /* B */
1442 VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
1443 VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
1444 VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
1445 /* G */
1446 VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
1447 VI1_D12_G4_Y4_B_MARK, VI1_D13_G5_Y5_B_MARK,
1448 VI1_D14_G6_Y6_B_MARK, VI1_D15_G7_Y7_B_MARK,
1449 /* R */
1450 VI1_D18_R2_MARK, VI1_D19_R3_MARK,
1451 VI1_D20_R4_MARK, VI1_D21_R5_MARK,
1452 VI1_D22_R6_MARK, VI1_D23_R7_MARK,
1453 };
1454 static const unsigned int vin1_sync_pins[] = {
1455 /* HSYNC#, VSYNC# */
1456 RCAR_GP_PIN(5, 2), RCAR_GP_PIN(5, 3),
1457 };
1458 static const unsigned int vin1_sync_mux[] = {
1459 VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK,
1460 };
1461 static const unsigned int vin1_field_pins[] = {
1462 RCAR_GP_PIN(5, 16),
1463 };
1464 static const unsigned int vin1_field_mux[] = {
1465 VI1_FIELD_MARK,
1466 };
1467 static const unsigned int vin1_clkenb_pins[] = {
1468 RCAR_GP_PIN(5, 1),
1469 };
1470 static const unsigned int vin1_clkenb_mux[] = {
1471 VI1_CLKENB_MARK,
1472 };
1473 static const unsigned int vin1_clk_pins[] = {
1474 RCAR_GP_PIN(5, 0),
1475 };
1476 static const unsigned int vin1_clk_mux[] = {
1477 VI1_CLK_MARK,
1478 };
1479 /* - VIN2 ------------------------------------------------------------------- */
1480 static const union vin_data vin2_data_pins = {
1481 .data16 = {
1482 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
1483 RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
1484 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1485 RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
1486 RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
1487 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
1488 RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),
1489 RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
1490 },
1491 };
1492 static const union vin_data vin2_data_mux = {
1493 .data16 = {
1494 VI2_D0_C0_MARK, VI2_D1_C1_MARK,
1495 VI2_D2_C2_MARK, VI2_D3_C3_MARK,
1496 VI2_D4_C4_MARK, VI2_D5_C5_MARK,
1497 VI2_D6_C6_MARK, VI2_D7_C7_MARK,
1498 VI2_D8_Y0_MARK, VI2_D9_Y1_MARK,
1499 VI2_D10_Y2_MARK, VI2_D11_Y3_MARK,
1500 VI2_D12_Y4_MARK, VI2_D13_Y5_MARK,
1501 VI2_D14_Y6_MARK, VI2_D15_Y7_MARK,
1502 },
1503 };
1504 static const unsigned int vin2_sync_pins[] = {
1505 /* HSYNC#, VSYNC# */
1506 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
1507 };
1508 static const unsigned int vin2_sync_mux[] = {
1509 VI2_HSYNC_N_MARK, VI2_VSYNC_N_MARK,
1510 };
1511 static const unsigned int vin2_field_pins[] = {
1512 RCAR_GP_PIN(6, 16),
1513 };
1514 static const unsigned int vin2_field_mux[] = {
1515 VI2_FIELD_MARK,
1516 };
1517 static const unsigned int vin2_clkenb_pins[] = {
1518 RCAR_GP_PIN(6, 1),
1519 };
1520 static const unsigned int vin2_clkenb_mux[] = {
1521 VI2_CLKENB_MARK,
1522 };
1523 static const unsigned int vin2_clk_pins[] = {
1524 RCAR_GP_PIN(6, 0),
1525 };
1526 static const unsigned int vin2_clk_mux[] = {
1527 VI2_CLK_MARK,
1528 };
1529 /* - VIN3 ------------------------------------------------------------------- */
1530 static const union vin_data vin3_data_pins = {
1531 .data16 = {
1532 RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 5),
1533 RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 7),
1534 RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
1535 RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 11),
1536 RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 13),
1537 RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
1538 RCAR_GP_PIN(8, 13), RCAR_GP_PIN(8, 14),
1539 RCAR_GP_PIN(8, 15), RCAR_GP_PIN(8, 16),
1540 },
1541 };
1542 static const union vin_data vin3_data_mux = {
1543 .data16 = {
1544 VI3_D0_C0_MARK, VI3_D1_C1_MARK,
1545 VI3_D2_C2_MARK, VI3_D3_C3_MARK,
1546 VI3_D4_C4_MARK, VI3_D5_C5_MARK,
1547 VI3_D6_C6_MARK, VI3_D7_C7_MARK,
1548 VI3_D8_Y0_MARK, VI3_D9_Y1_MARK,
1549 VI3_D10_Y2_MARK, VI3_D11_Y3_MARK,
1550 VI3_D12_Y4_MARK, VI3_D13_Y5_MARK,
1551 VI3_D14_Y6_MARK, VI3_D15_Y7_MARK,
1552 },
1553 };
1554 static const unsigned int vin3_sync_pins[] = {
1555 /* HSYNC#, VSYNC# */
1556 RCAR_GP_PIN(7, 2), RCAR_GP_PIN(7, 3),
1557 };
1558 static const unsigned int vin3_sync_mux[] = {
1559 VI3_HSYNC_N_MARK, VI3_VSYNC_N_MARK,
1560 };
1561 static const unsigned int vin3_field_pins[] = {
1562 RCAR_GP_PIN(7, 16),
1563 };
1564 static const unsigned int vin3_field_mux[] = {
1565 VI3_FIELD_MARK,
1566 };
1567 static const unsigned int vin3_clkenb_pins[] = {
1568 RCAR_GP_PIN(7, 1),
1569 };
1570 static const unsigned int vin3_clkenb_mux[] = {
1571 VI3_CLKENB_MARK,
1572 };
1573 static const unsigned int vin3_clk_pins[] = {
1574 RCAR_GP_PIN(7, 0),
1575 };
1576 static const unsigned int vin3_clk_mux[] = {
1577 VI3_CLK_MARK,
1578 };
1579 /* - VIN4 ------------------------------------------------------------------- */
1580 static const union vin_data vin4_data_pins = {
1581 .data12 = {
1582 RCAR_GP_PIN(8, 4), RCAR_GP_PIN(8, 5),
1583 RCAR_GP_PIN(8, 6), RCAR_GP_PIN(8, 7),
1584 RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9),
1585 RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 11),
1586 RCAR_GP_PIN(8, 12), RCAR_GP_PIN(8, 13),
1587 RCAR_GP_PIN(8, 14), RCAR_GP_PIN(8, 15),
1588 },
1589 };
1590 static const union vin_data vin4_data_mux = {
1591 .data12 = {
1592 VI4_D0_C0_MARK, VI4_D1_C1_MARK,
1593 VI4_D2_C2_MARK, VI4_D3_C3_MARK,
1594 VI4_D4_C4_MARK, VI4_D5_C5_MARK,
1595 VI4_D6_C6_MARK, VI4_D7_C7_MARK,
1596 VI4_D8_Y0_MARK, VI4_D9_Y1_MARK,
1597 VI4_D10_Y2_MARK, VI4_D11_Y3_MARK,
1598 },
1599 };
1600 static const unsigned int vin4_sync_pins[] = {
1601 /* HSYNC#, VSYNC# */
1602 RCAR_GP_PIN(8, 2), RCAR_GP_PIN(8, 3),
1603 };
1604 static const unsigned int vin4_sync_mux[] = {
1605 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
1606 };
1607 static const unsigned int vin4_field_pins[] = {
1608 RCAR_GP_PIN(8, 16),
1609 };
1610 static const unsigned int vin4_field_mux[] = {
1611 VI4_FIELD_MARK,
1612 };
1613 static const unsigned int vin4_clkenb_pins[] = {
1614 RCAR_GP_PIN(8, 1),
1615 };
1616 static const unsigned int vin4_clkenb_mux[] = {
1617 VI4_CLKENB_MARK,
1618 };
1619 static const unsigned int vin4_clk_pins[] = {
1620 RCAR_GP_PIN(8, 0),
1621 };
1622 static const unsigned int vin4_clk_mux[] = {
1623 VI4_CLK_MARK,
1624 };
1625 /* - VIN5 ------------------------------------------------------------------- */
1626 static const union vin_data vin5_data_pins = {
1627 .data12 = {
1628 RCAR_GP_PIN(9, 4), RCAR_GP_PIN(9, 5),
1629 RCAR_GP_PIN(9, 6), RCAR_GP_PIN(9, 7),
1630 RCAR_GP_PIN(9, 8), RCAR_GP_PIN(9, 9),
1631 RCAR_GP_PIN(9, 10), RCAR_GP_PIN(9, 11),
1632 RCAR_GP_PIN(9, 12), RCAR_GP_PIN(9, 13),
1633 RCAR_GP_PIN(9, 14), RCAR_GP_PIN(9, 15),
1634 },
1635 };
1636 static const union vin_data vin5_data_mux = {
1637 .data12 = {
1638 VI5_D0_C0_MARK, VI5_D1_C1_MARK,
1639 VI5_D2_C2_MARK, VI5_D3_C3_MARK,
1640 VI5_D4_C4_MARK, VI5_D5_C5_MARK,
1641 VI5_D6_C6_MARK, VI5_D7_C7_MARK,
1642 VI5_D8_Y0_MARK, VI5_D9_Y1_MARK,
1643 VI5_D10_Y2_MARK, VI5_D11_Y3_MARK,
1644 },
1645 };
1646 static const unsigned int vin5_sync_pins[] = {
1647 /* HSYNC#, VSYNC# */
1648 RCAR_GP_PIN(9, 2), RCAR_GP_PIN(9, 3),
1649 };
1650 static const unsigned int vin5_sync_mux[] = {
1651 VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
1652 };
1653 static const unsigned int vin5_field_pins[] = {
1654 RCAR_GP_PIN(9, 16),
1655 };
1656 static const unsigned int vin5_field_mux[] = {
1657 VI5_FIELD_MARK,
1658 };
1659 static const unsigned int vin5_clkenb_pins[] = {
1660 RCAR_GP_PIN(9, 1),
1661 };
1662 static const unsigned int vin5_clkenb_mux[] = {
1663 VI5_CLKENB_MARK,
1664 };
1665 static const unsigned int vin5_clk_pins[] = {
1666 RCAR_GP_PIN(9, 0),
1667 };
1668 static const unsigned int vin5_clk_mux[] = {
1669 VI5_CLK_MARK,
1670 };
1671
1672 static const struct sh_pfc_pin_group pinmux_groups[] = {
1673 SH_PFC_PIN_GROUP(avb_link),
1674 SH_PFC_PIN_GROUP(avb_magic),
1675 SH_PFC_PIN_GROUP(avb_phy_int),
1676 SH_PFC_PIN_GROUP(avb_mdio),
1677 SH_PFC_PIN_GROUP(avb_mii),
1678 SH_PFC_PIN_GROUP(avb_gmii),
1679 SH_PFC_PIN_GROUP(avb_avtp_match),
1680 SH_PFC_PIN_GROUP(can0_data),
1681 SH_PFC_PIN_GROUP(can1_data),
1682 SH_PFC_PIN_GROUP(can_clk),
1683 SH_PFC_PIN_GROUP(du0_rgb666),
1684 SH_PFC_PIN_GROUP(du0_rgb888),
1685 SH_PFC_PIN_GROUP(du0_sync),
1686 SH_PFC_PIN_GROUP(du0_oddf),
1687 SH_PFC_PIN_GROUP(du0_disp),
1688 SH_PFC_PIN_GROUP(du0_cde),
1689 SH_PFC_PIN_GROUP(du1_rgb666),
1690 SH_PFC_PIN_GROUP(du1_sync),
1691 SH_PFC_PIN_GROUP(du1_oddf),
1692 SH_PFC_PIN_GROUP(du1_disp),
1693 SH_PFC_PIN_GROUP(du1_cde),
1694 SH_PFC_PIN_GROUP(intc_irq0),
1695 SH_PFC_PIN_GROUP(intc_irq1),
1696 SH_PFC_PIN_GROUP(intc_irq2),
1697 SH_PFC_PIN_GROUP(intc_irq3),
1698 SH_PFC_PIN_GROUP(lbsc_cs0),
1699 SH_PFC_PIN_GROUP(lbsc_cs1),
1700 SH_PFC_PIN_GROUP(lbsc_ex_cs0),
1701 SH_PFC_PIN_GROUP(lbsc_ex_cs1),
1702 SH_PFC_PIN_GROUP(lbsc_ex_cs2),
1703 SH_PFC_PIN_GROUP(lbsc_ex_cs3),
1704 SH_PFC_PIN_GROUP(lbsc_ex_cs4),
1705 SH_PFC_PIN_GROUP(lbsc_ex_cs5),
1706 SH_PFC_PIN_GROUP(msiof0_clk),
1707 SH_PFC_PIN_GROUP(msiof0_sync),
1708 SH_PFC_PIN_GROUP(msiof0_rx),
1709 SH_PFC_PIN_GROUP(msiof0_tx),
1710 SH_PFC_PIN_GROUP(msiof1_clk),
1711 SH_PFC_PIN_GROUP(msiof1_sync),
1712 SH_PFC_PIN_GROUP(msiof1_rx),
1713 SH_PFC_PIN_GROUP(msiof1_tx),
1714 SH_PFC_PIN_GROUP(qspi_ctrl),
1715 SH_PFC_PIN_GROUP(qspi_data2),
1716 SH_PFC_PIN_GROUP(qspi_data4),
1717 SH_PFC_PIN_GROUP(scif0_data),
1718 SH_PFC_PIN_GROUP(scif0_clk),
1719 SH_PFC_PIN_GROUP(scif0_ctrl),
1720 SH_PFC_PIN_GROUP(scif1_data),
1721 SH_PFC_PIN_GROUP(scif1_clk),
1722 SH_PFC_PIN_GROUP(scif1_ctrl),
1723 SH_PFC_PIN_GROUP(scif2_data),
1724 SH_PFC_PIN_GROUP(scif2_clk),
1725 SH_PFC_PIN_GROUP(scif3_data),
1726 SH_PFC_PIN_GROUP(scif3_clk),
1727 SH_PFC_PIN_GROUP(sdhi0_data1),
1728 SH_PFC_PIN_GROUP(sdhi0_data4),
1729 SH_PFC_PIN_GROUP(sdhi0_ctrl),
1730 SH_PFC_PIN_GROUP(sdhi0_cd),
1731 SH_PFC_PIN_GROUP(sdhi0_wp),
1732 VIN_DATA_PIN_GROUP(vin0_data, 24),
1733 VIN_DATA_PIN_GROUP(vin0_data, 20),
1734 SH_PFC_PIN_GROUP(vin0_data18),
1735 VIN_DATA_PIN_GROUP(vin0_data, 16),
1736 VIN_DATA_PIN_GROUP(vin0_data, 12),
1737 VIN_DATA_PIN_GROUP(vin0_data, 10),
1738 VIN_DATA_PIN_GROUP(vin0_data, 8),
1739 SH_PFC_PIN_GROUP(vin0_sync),
1740 SH_PFC_PIN_GROUP(vin0_field),
1741 SH_PFC_PIN_GROUP(vin0_clkenb),
1742 SH_PFC_PIN_GROUP(vin0_clk),
1743 VIN_DATA_PIN_GROUP(vin1_data, 24),
1744 VIN_DATA_PIN_GROUP(vin1_data, 20),
1745 SH_PFC_PIN_GROUP(vin1_data18),
1746 VIN_DATA_PIN_GROUP(vin1_data, 16),
1747 VIN_DATA_PIN_GROUP(vin1_data, 12),
1748 VIN_DATA_PIN_GROUP(vin1_data, 10),
1749 VIN_DATA_PIN_GROUP(vin1_data, 8),
1750 VIN_DATA_PIN_GROUP(vin1_data_b, 24),
1751 VIN_DATA_PIN_GROUP(vin1_data_b, 20),
1752 SH_PFC_PIN_GROUP(vin1_data18_b),
1753 VIN_DATA_PIN_GROUP(vin1_data_b, 16),
1754 SH_PFC_PIN_GROUP(vin1_sync),
1755 SH_PFC_PIN_GROUP(vin1_field),
1756 SH_PFC_PIN_GROUP(vin1_clkenb),
1757 SH_PFC_PIN_GROUP(vin1_clk),
1758 VIN_DATA_PIN_GROUP(vin2_data, 16),
1759 VIN_DATA_PIN_GROUP(vin2_data, 12),
1760 VIN_DATA_PIN_GROUP(vin2_data, 10),
1761 VIN_DATA_PIN_GROUP(vin2_data, 8),
1762 SH_PFC_PIN_GROUP(vin2_sync),
1763 SH_PFC_PIN_GROUP(vin2_field),
1764 SH_PFC_PIN_GROUP(vin2_clkenb),
1765 SH_PFC_PIN_GROUP(vin2_clk),
1766 VIN_DATA_PIN_GROUP(vin3_data, 16),
1767 VIN_DATA_PIN_GROUP(vin3_data, 12),
1768 VIN_DATA_PIN_GROUP(vin3_data, 10),
1769 VIN_DATA_PIN_GROUP(vin3_data, 8),
1770 SH_PFC_PIN_GROUP(vin3_sync),
1771 SH_PFC_PIN_GROUP(vin3_field),
1772 SH_PFC_PIN_GROUP(vin3_clkenb),
1773 SH_PFC_PIN_GROUP(vin3_clk),
1774 VIN_DATA_PIN_GROUP(vin4_data, 12),
1775 VIN_DATA_PIN_GROUP(vin4_data, 10),
1776 VIN_DATA_PIN_GROUP(vin4_data, 8),
1777 SH_PFC_PIN_GROUP(vin4_sync),
1778 SH_PFC_PIN_GROUP(vin4_field),
1779 SH_PFC_PIN_GROUP(vin4_clkenb),
1780 SH_PFC_PIN_GROUP(vin4_clk),
1781 VIN_DATA_PIN_GROUP(vin5_data, 12),
1782 VIN_DATA_PIN_GROUP(vin5_data, 10),
1783 VIN_DATA_PIN_GROUP(vin5_data, 8),
1784 SH_PFC_PIN_GROUP(vin5_sync),
1785 SH_PFC_PIN_GROUP(vin5_field),
1786 SH_PFC_PIN_GROUP(vin5_clkenb),
1787 SH_PFC_PIN_GROUP(vin5_clk),
1788 };
1789
1790 static const char * const avb_groups[] = {
1791 "avb_link",
1792 "avb_magic",
1793 "avb_phy_int",
1794 "avb_mdio",
1795 "avb_mii",
1796 "avb_gmii",
1797 "avb_avtp_match",
1798 };
1799
1800 static const char * const can0_groups[] = {
1801 "can0_data",
1802 "can_clk",
1803 };
1804
1805 static const char * const can1_groups[] = {
1806 "can1_data",
1807 "can_clk",
1808 };
1809
1810 static const char * const du0_groups[] = {
1811 "du0_rgb666",
1812 "du0_rgb888",
1813 "du0_sync",
1814 "du0_oddf",
1815 "du0_disp",
1816 "du0_cde",
1817 };
1818
1819 static const char * const du1_groups[] = {
1820 "du1_rgb666",
1821 "du1_sync",
1822 "du1_oddf",
1823 "du1_disp",
1824 "du1_cde",
1825 };
1826
1827 static const char * const intc_groups[] = {
1828 "intc_irq0",
1829 "intc_irq1",
1830 "intc_irq2",
1831 "intc_irq3",
1832 };
1833
1834 static const char * const lbsc_groups[] = {
1835 "lbsc_cs0",
1836 "lbsc_cs1",
1837 "lbsc_ex_cs0",
1838 "lbsc_ex_cs1",
1839 "lbsc_ex_cs2",
1840 "lbsc_ex_cs3",
1841 "lbsc_ex_cs4",
1842 "lbsc_ex_cs5",
1843 };
1844
1845 static const char * const msiof0_groups[] = {
1846 "msiof0_clk",
1847 "msiof0_sync",
1848 "msiof0_rx",
1849 "msiof0_tx",
1850 };
1851
1852 static const char * const msiof1_groups[] = {
1853 "msiof1_clk",
1854 "msiof1_sync",
1855 "msiof1_rx",
1856 "msiof1_tx",
1857 };
1858
1859 static const char * const qspi_groups[] = {
1860 "qspi_ctrl",
1861 "qspi_data2",
1862 "qspi_data4",
1863 };
1864
1865 static const char * const scif0_groups[] = {
1866 "scif0_data",
1867 "scif0_clk",
1868 "scif0_ctrl",
1869 };
1870
1871 static const char * const scif1_groups[] = {
1872 "scif1_data",
1873 "scif1_clk",
1874 "scif1_ctrl",
1875 };
1876
1877 static const char * const scif2_groups[] = {
1878 "scif2_data",
1879 "scif2_clk",
1880 };
1881
1882 static const char * const scif3_groups[] = {
1883 "scif3_data",
1884 "scif3_clk",
1885 };
1886
1887 static const char * const sdhi0_groups[] = {
1888 "sdhi0_data1",
1889 "sdhi0_data4",
1890 "sdhi0_ctrl",
1891 "sdhi0_cd",
1892 "sdhi0_wp",
1893 };
1894
1895 static const char * const vin0_groups[] = {
1896 "vin0_data24",
1897 "vin0_data20",
1898 "vin0_data18",
1899 "vin0_data16",
1900 "vin0_data12",
1901 "vin0_data10",
1902 "vin0_data8",
1903 "vin0_sync",
1904 "vin0_field",
1905 "vin0_clkenb",
1906 "vin0_clk",
1907 };
1908
1909 static const char * const vin1_groups[] = {
1910 "vin1_data24",
1911 "vin1_data20",
1912 "vin1_data18",
1913 "vin1_data16",
1914 "vin1_data12",
1915 "vin1_data10",
1916 "vin1_data8",
1917 "vin1_data24_b",
1918 "vin1_data20_b",
1919 "vin1_data16_b",
1920 "vin1_sync",
1921 "vin1_field",
1922 "vin1_clkenb",
1923 "vin1_clk",
1924 };
1925
1926 static const char * const vin2_groups[] = {
1927 "vin2_data16",
1928 "vin2_data12",
1929 "vin2_data10",
1930 "vin2_data8",
1931 "vin2_sync",
1932 "vin2_field",
1933 "vin2_clkenb",
1934 "vin2_clk",
1935 };
1936
1937 static const char * const vin3_groups[] = {
1938 "vin3_data16",
1939 "vin3_data12",
1940 "vin3_data10",
1941 "vin3_data8",
1942 "vin3_sync",
1943 "vin3_field",
1944 "vin3_clkenb",
1945 "vin3_clk",
1946 };
1947
1948 static const char * const vin4_groups[] = {
1949 "vin4_data12",
1950 "vin4_data10",
1951 "vin4_data8",
1952 "vin4_sync",
1953 "vin4_field",
1954 "vin4_clkenb",
1955 "vin4_clk",
1956 };
1957
1958 static const char * const vin5_groups[] = {
1959 "vin5_data12",
1960 "vin5_data10",
1961 "vin5_data8",
1962 "vin5_sync",
1963 "vin5_field",
1964 "vin5_clkenb",
1965 "vin5_clk",
1966 };
1967
1968 static const struct sh_pfc_function pinmux_functions[] = {
1969 SH_PFC_FUNCTION(avb),
1970 SH_PFC_FUNCTION(can0),
1971 SH_PFC_FUNCTION(can1),
1972 SH_PFC_FUNCTION(du0),
1973 SH_PFC_FUNCTION(du1),
1974 SH_PFC_FUNCTION(intc),
1975 SH_PFC_FUNCTION(lbsc),
1976 SH_PFC_FUNCTION(msiof0),
1977 SH_PFC_FUNCTION(msiof1),
1978 SH_PFC_FUNCTION(qspi),
1979 SH_PFC_FUNCTION(scif0),
1980 SH_PFC_FUNCTION(scif1),
1981 SH_PFC_FUNCTION(scif2),
1982 SH_PFC_FUNCTION(scif3),
1983 SH_PFC_FUNCTION(sdhi0),
1984 SH_PFC_FUNCTION(vin0),
1985 SH_PFC_FUNCTION(vin1),
1986 SH_PFC_FUNCTION(vin2),
1987 SH_PFC_FUNCTION(vin3),
1988 SH_PFC_FUNCTION(vin4),
1989 SH_PFC_FUNCTION(vin5),
1990 };
1991
1992 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1993 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
1994 0, 0,
1995 0, 0,
1996 0, 0,
1997 GP_0_28_FN, FN_IP1_4,
1998 GP_0_27_FN, FN_IP1_3,
1999 GP_0_26_FN, FN_IP1_2,
2000 GP_0_25_FN, FN_IP1_1,
2001 GP_0_24_FN, FN_IP1_0,
2002 GP_0_23_FN, FN_IP0_23,
2003 GP_0_22_FN, FN_IP0_22,
2004 GP_0_21_FN, FN_IP0_21,
2005 GP_0_20_FN, FN_IP0_20,
2006 GP_0_19_FN, FN_IP0_19,
2007 GP_0_18_FN, FN_IP0_18,
2008 GP_0_17_FN, FN_IP0_17,
2009 GP_0_16_FN, FN_IP0_16,
2010 GP_0_15_FN, FN_IP0_15,
2011 GP_0_14_FN, FN_IP0_14,
2012 GP_0_13_FN, FN_IP0_13,
2013 GP_0_12_FN, FN_IP0_12,
2014 GP_0_11_FN, FN_IP0_11,
2015 GP_0_10_FN, FN_IP0_10,
2016 GP_0_9_FN, FN_IP0_9,
2017 GP_0_8_FN, FN_IP0_8,
2018 GP_0_7_FN, FN_IP0_7,
2019 GP_0_6_FN, FN_IP0_6,
2020 GP_0_5_FN, FN_IP0_5,
2021 GP_0_4_FN, FN_IP0_4,
2022 GP_0_3_FN, FN_IP0_3,
2023 GP_0_2_FN, FN_IP0_2,
2024 GP_0_1_FN, FN_IP0_1,
2025 GP_0_0_FN, FN_IP0_0 }
2026 },
2027 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
2028 0, 0,
2029 0, 0,
2030 0, 0,
2031 0, 0,
2032 0, 0,
2033 0, 0,
2034 0, 0,
2035 0, 0,
2036 0, 0,
2037 GP_1_22_FN, FN_DU1_CDE,
2038 GP_1_21_FN, FN_DU1_DISP,
2039 GP_1_20_FN, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
2040 GP_1_19_FN, FN_DU1_EXVSYNC_DU1_VSYNC,
2041 GP_1_18_FN, FN_DU1_EXHSYNC_DU1_HSYNC,
2042 GP_1_17_FN, FN_DU1_DB7_C5,
2043 GP_1_16_FN, FN_DU1_DB6_C4,
2044 GP_1_15_FN, FN_DU1_DB5_C3_DATA15,
2045 GP_1_14_FN, FN_DU1_DB4_C2_DATA14,
2046 GP_1_13_FN, FN_DU1_DB3_C1_DATA13,
2047 GP_1_12_FN, FN_DU1_DB2_C0_DATA12,
2048 GP_1_11_FN, FN_IP1_16,
2049 GP_1_10_FN, FN_IP1_15,
2050 GP_1_9_FN, FN_IP1_14,
2051 GP_1_8_FN, FN_IP1_13,
2052 GP_1_7_FN, FN_IP1_12,
2053 GP_1_6_FN, FN_IP1_11,
2054 GP_1_5_FN, FN_IP1_10,
2055 GP_1_4_FN, FN_IP1_9,
2056 GP_1_3_FN, FN_IP1_8,
2057 GP_1_2_FN, FN_IP1_7,
2058 GP_1_1_FN, FN_IP1_6,
2059 GP_1_0_FN, FN_IP1_5, }
2060 },
2061 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
2062 GP_2_31_FN, FN_A15,
2063 GP_2_30_FN, FN_A14,
2064 GP_2_29_FN, FN_A13,
2065 GP_2_28_FN, FN_A12,
2066 GP_2_27_FN, FN_A11,
2067 GP_2_26_FN, FN_A10,
2068 GP_2_25_FN, FN_A9,
2069 GP_2_24_FN, FN_A8,
2070 GP_2_23_FN, FN_A7,
2071 GP_2_22_FN, FN_A6,
2072 GP_2_21_FN, FN_A5,
2073 GP_2_20_FN, FN_A4,
2074 GP_2_19_FN, FN_A3,
2075 GP_2_18_FN, FN_A2,
2076 GP_2_17_FN, FN_A1,
2077 GP_2_16_FN, FN_A0,
2078 GP_2_15_FN, FN_D15,
2079 GP_2_14_FN, FN_D14,
2080 GP_2_13_FN, FN_D13,
2081 GP_2_12_FN, FN_D12,
2082 GP_2_11_FN, FN_D11,
2083 GP_2_10_FN, FN_D10,
2084 GP_2_9_FN, FN_D9,
2085 GP_2_8_FN, FN_D8,
2086 GP_2_7_FN, FN_D7,
2087 GP_2_6_FN, FN_D6,
2088 GP_2_5_FN, FN_D5,
2089 GP_2_4_FN, FN_D4,
2090 GP_2_3_FN, FN_D3,
2091 GP_2_2_FN, FN_D2,
2092 GP_2_1_FN, FN_D1,
2093 GP_2_0_FN, FN_D0 }
2094 },
2095 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
2096 0, 0,
2097 0, 0,
2098 0, 0,
2099 0, 0,
2100 GP_3_27_FN, FN_CS0_N,
2101 GP_3_26_FN, FN_IP1_22,
2102 GP_3_25_FN, FN_IP1_21,
2103 GP_3_24_FN, FN_IP1_20,
2104 GP_3_23_FN, FN_IP1_19,
2105 GP_3_22_FN, FN_IRQ3,
2106 GP_3_21_FN, FN_IRQ2,
2107 GP_3_20_FN, FN_IRQ1,
2108 GP_3_19_FN, FN_IRQ0,
2109 GP_3_18_FN, FN_EX_WAIT0,
2110 GP_3_17_FN, FN_WE1_N,
2111 GP_3_16_FN, FN_WE0_N,
2112 GP_3_15_FN, FN_RD_WR_N,
2113 GP_3_14_FN, FN_RD_N,
2114 GP_3_13_FN, FN_BS_N,
2115 GP_3_12_FN, FN_EX_CS5_N,
2116 GP_3_11_FN, FN_EX_CS4_N,
2117 GP_3_10_FN, FN_EX_CS3_N,
2118 GP_3_9_FN, FN_EX_CS2_N,
2119 GP_3_8_FN, FN_EX_CS1_N,
2120 GP_3_7_FN, FN_EX_CS0_N,
2121 GP_3_6_FN, FN_CS1_N_A26,
2122 GP_3_5_FN, FN_IP1_18,
2123 GP_3_4_FN, FN_IP1_17,
2124 GP_3_3_FN, FN_A19,
2125 GP_3_2_FN, FN_A18,
2126 GP_3_1_FN, FN_A17,
2127 GP_3_0_FN, FN_A16 }
2128 },
2129 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
2130 0, 0,
2131 0, 0,
2132 0, 0,
2133 0, 0,
2134 0, 0,
2135 0, 0,
2136 0, 0,
2137 0, 0,
2138 0, 0,
2139 0, 0,
2140 0, 0,
2141 0, 0,
2142 0, 0,
2143 0, 0,
2144 0, 0,
2145 GP_4_16_FN, FN_VI0_FIELD,
2146 GP_4_15_FN, FN_VI0_D11_G3_Y3,
2147 GP_4_14_FN, FN_VI0_D10_G2_Y2,
2148 GP_4_13_FN, FN_VI0_D9_G1_Y1,
2149 GP_4_12_FN, FN_VI0_D8_G0_Y0,
2150 GP_4_11_FN, FN_VI0_D7_B7_C7,
2151 GP_4_10_FN, FN_VI0_D6_B6_C6,
2152 GP_4_9_FN, FN_VI0_D5_B5_C5,
2153 GP_4_8_FN, FN_VI0_D4_B4_C4,
2154 GP_4_7_FN, FN_VI0_D3_B3_C3,
2155 GP_4_6_FN, FN_VI0_D2_B2_C2,
2156 GP_4_5_FN, FN_VI0_D1_B1_C1,
2157 GP_4_4_FN, FN_VI0_D0_B0_C0,
2158 GP_4_3_FN, FN_VI0_VSYNC_N,
2159 GP_4_2_FN, FN_VI0_HSYNC_N,
2160 GP_4_1_FN, FN_VI0_CLKENB,
2161 GP_4_0_FN, FN_VI0_CLK }
2162 },
2163 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
2164 0, 0,
2165 0, 0,
2166 0, 0,
2167 0, 0,
2168 0, 0,
2169 0, 0,
2170 0, 0,
2171 0, 0,
2172 0, 0,
2173 0, 0,
2174 0, 0,
2175 0, 0,
2176 0, 0,
2177 0, 0,
2178 0, 0,
2179 GP_5_16_FN, FN_VI1_FIELD,
2180 GP_5_15_FN, FN_VI1_D11_G3_Y3,
2181 GP_5_14_FN, FN_VI1_D10_G2_Y2,
2182 GP_5_13_FN, FN_VI1_D9_G1_Y1,
2183 GP_5_12_FN, FN_VI1_D8_G0_Y0,
2184 GP_5_11_FN, FN_VI1_D7_B7_C7,
2185 GP_5_10_FN, FN_VI1_D6_B6_C6,
2186 GP_5_9_FN, FN_VI1_D5_B5_C5,
2187 GP_5_8_FN, FN_VI1_D4_B4_C4,
2188 GP_5_7_FN, FN_VI1_D3_B3_C3,
2189 GP_5_6_FN, FN_VI1_D2_B2_C2,
2190 GP_5_5_FN, FN_VI1_D1_B1_C1,
2191 GP_5_4_FN, FN_VI1_D0_B0_C0,
2192 GP_5_3_FN, FN_VI1_VSYNC_N,
2193 GP_5_2_FN, FN_VI1_HSYNC_N,
2194 GP_5_1_FN, FN_VI1_CLKENB,
2195 GP_5_0_FN, FN_VI1_CLK }
2196 },
2197 { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
2198 0, 0,
2199 0, 0,
2200 0, 0,
2201 0, 0,
2202 0, 0,
2203 0, 0,
2204 0, 0,
2205 0, 0,
2206 0, 0,
2207 0, 0,
2208 0, 0,
2209 0, 0,
2210 0, 0,
2211 0, 0,
2212 0, 0,
2213 GP_6_16_FN, FN_IP2_16,
2214 GP_6_15_FN, FN_IP2_15,
2215 GP_6_14_FN, FN_IP2_14,
2216 GP_6_13_FN, FN_IP2_13,
2217 GP_6_12_FN, FN_IP2_12,
2218 GP_6_11_FN, FN_IP2_11,
2219 GP_6_10_FN, FN_IP2_10,
2220 GP_6_9_FN, FN_IP2_9,
2221 GP_6_8_FN, FN_IP2_8,
2222 GP_6_7_FN, FN_IP2_7,
2223 GP_6_6_FN, FN_IP2_6,
2224 GP_6_5_FN, FN_IP2_5,
2225 GP_6_4_FN, FN_IP2_4,
2226 GP_6_3_FN, FN_IP2_3,
2227 GP_6_2_FN, FN_IP2_2,
2228 GP_6_1_FN, FN_IP2_1,
2229 GP_6_0_FN, FN_IP2_0 }
2230 },
2231 { PINMUX_CFG_REG("GPSR7", 0xE6060020, 32, 1) {
2232 0, 0,
2233 0, 0,
2234 0, 0,
2235 0, 0,
2236 0, 0,
2237 0, 0,
2238 0, 0,
2239 0, 0,
2240 0, 0,
2241 0, 0,
2242 0, 0,
2243 0, 0,
2244 0, 0,
2245 0, 0,
2246 0, 0,
2247 GP_7_16_FN, FN_VI3_FIELD,
2248 GP_7_15_FN, FN_IP3_14,
2249 GP_7_14_FN, FN_VI3_D10_Y2,
2250 GP_7_13_FN, FN_IP3_13,
2251 GP_7_12_FN, FN_IP3_12,
2252 GP_7_11_FN, FN_IP3_11,
2253 GP_7_10_FN, FN_IP3_10,
2254 GP_7_9_FN, FN_IP3_9,
2255 GP_7_8_FN, FN_IP3_8,
2256 GP_7_7_FN, FN_IP3_7,
2257 GP_7_6_FN, FN_IP3_6,
2258 GP_7_5_FN, FN_IP3_5,
2259 GP_7_4_FN, FN_IP3_4,
2260 GP_7_3_FN, FN_IP3_3,
2261 GP_7_2_FN, FN_IP3_2,
2262 GP_7_1_FN, FN_IP3_1,
2263 GP_7_0_FN, FN_IP3_0 }
2264 },
2265 { PINMUX_CFG_REG("GPSR8", 0xE6060024, 32, 1) {
2266 0, 0,
2267 0, 0,
2268 0, 0,
2269 0, 0,
2270 0, 0,
2271 0, 0,
2272 0, 0,
2273 0, 0,
2274 0, 0,
2275 0, 0,
2276 0, 0,
2277 0, 0,
2278 0, 0,
2279 0, 0,
2280 0, 0,
2281 GP_8_16_FN, FN_IP4_24,
2282 GP_8_15_FN, FN_IP4_23,
2283 GP_8_14_FN, FN_IP4_22,
2284 GP_8_13_FN, FN_IP4_21,
2285 GP_8_12_FN, FN_IP4_20_19,
2286 GP_8_11_FN, FN_IP4_18_17,
2287 GP_8_10_FN, FN_IP4_16_15,
2288 GP_8_9_FN, FN_IP4_14_13,
2289 GP_8_8_FN, FN_IP4_12_11,
2290 GP_8_7_FN, FN_IP4_10_9,
2291 GP_8_6_FN, FN_IP4_8_7,
2292 GP_8_5_FN, FN_IP4_6_5,
2293 GP_8_4_FN, FN_IP4_4,
2294 GP_8_3_FN, FN_IP4_3_2,
2295 GP_8_2_FN, FN_IP4_1,
2296 GP_8_1_FN, FN_IP4_0,
2297 GP_8_0_FN, FN_VI4_CLK }
2298 },
2299 { PINMUX_CFG_REG("GPSR9", 0xE6060028, 32, 1) {
2300 0, 0,
2301 0, 0,
2302 0, 0,
2303 0, 0,
2304 0, 0,
2305 0, 0,
2306 0, 0,
2307 0, 0,
2308 0, 0,
2309 0, 0,
2310 0, 0,
2311 0, 0,
2312 0, 0,
2313 0, 0,
2314 0, 0,
2315 GP_9_16_FN, FN_VI5_FIELD,
2316 GP_9_15_FN, FN_VI5_D11_Y3,
2317 GP_9_14_FN, FN_VI5_D10_Y2,
2318 GP_9_13_FN, FN_VI5_D9_Y1,
2319 GP_9_12_FN, FN_IP5_11,
2320 GP_9_11_FN, FN_IP5_10,
2321 GP_9_10_FN, FN_IP5_9,
2322 GP_9_9_FN, FN_IP5_8,
2323 GP_9_8_FN, FN_IP5_7,
2324 GP_9_7_FN, FN_IP5_6,
2325 GP_9_6_FN, FN_IP5_5,
2326 GP_9_5_FN, FN_IP5_4,
2327 GP_9_4_FN, FN_IP5_3,
2328 GP_9_3_FN, FN_IP5_2,
2329 GP_9_2_FN, FN_IP5_1,
2330 GP_9_1_FN, FN_IP5_0,
2331 GP_9_0_FN, FN_VI5_CLK }
2332 },
2333 { PINMUX_CFG_REG("GPSR10", 0xE606002C, 32, 1) {
2334 GP_10_31_FN, FN_CAN1_RX,
2335 GP_10_30_FN, FN_CAN1_TX,
2336 GP_10_29_FN, FN_CAN_CLK,
2337 GP_10_28_FN, FN_CAN0_RX,
2338 GP_10_27_FN, FN_CAN0_TX,
2339 GP_10_26_FN, FN_SCIF_CLK,
2340 GP_10_25_FN, FN_IP6_18_17,
2341 GP_10_24_FN, FN_IP6_16,
2342 GP_10_23_FN, FN_IP6_15_14,
2343 GP_10_22_FN, FN_IP6_13_12,
2344 GP_10_21_FN, FN_IP6_11_10,
2345 GP_10_20_FN, FN_IP6_9_8,
2346 GP_10_19_FN, FN_RX1,
2347 GP_10_18_FN, FN_TX1,
2348 GP_10_17_FN, FN_RTS1_N,
2349 GP_10_16_FN, FN_CTS1_N,
2350 GP_10_15_FN, FN_SCK1,
2351 GP_10_14_FN, FN_RX0,
2352 GP_10_13_FN, FN_TX0,
2353 GP_10_12_FN, FN_RTS0_N,
2354 GP_10_11_FN, FN_CTS0_N,
2355 GP_10_10_FN, FN_SCK0,
2356 GP_10_9_FN, FN_IP6_7,
2357 GP_10_8_FN, FN_IP6_6,
2358 GP_10_7_FN, FN_HCTS1_N,
2359 GP_10_6_FN, FN_IP6_5,
2360 GP_10_5_FN, FN_IP6_4,
2361 GP_10_4_FN, FN_IP6_3,
2362 GP_10_3_FN, FN_IP6_2,
2363 GP_10_2_FN, FN_HRTS0_N,
2364 GP_10_1_FN, FN_IP6_1,
2365 GP_10_0_FN, FN_IP6_0 }
2366 },
2367 { PINMUX_CFG_REG("GPSR11", 0xE6060030, 32, 1) {
2368 0, 0,
2369 0, 0,
2370 GP_11_29_FN, FN_AVS2,
2371 GP_11_28_FN, FN_AVS1,
2372 GP_11_27_FN, FN_ADICHS2,
2373 GP_11_26_FN, FN_ADICHS1,
2374 GP_11_25_FN, FN_ADICHS0,
2375 GP_11_24_FN, FN_ADIDATA,
2376 GP_11_23_FN, FN_ADICS_SAMP,
2377 GP_11_22_FN, FN_ADICLK,
2378 GP_11_21_FN, FN_IP7_20,
2379 GP_11_20_FN, FN_IP7_19,
2380 GP_11_19_FN, FN_IP7_18,
2381 GP_11_18_FN, FN_IP7_17,
2382 GP_11_17_FN, FN_IP7_16,
2383 GP_11_16_FN, FN_IP7_15_14,
2384 GP_11_15_FN, FN_IP7_13_12,
2385 GP_11_14_FN, FN_IP7_11_10,
2386 GP_11_13_FN, FN_IP7_9_8,
2387 GP_11_12_FN, FN_SD0_WP,
2388 GP_11_11_FN, FN_SD0_CD,
2389 GP_11_10_FN, FN_SD0_DAT3,
2390 GP_11_9_FN, FN_SD0_DAT2,
2391 GP_11_8_FN, FN_SD0_DAT1,
2392 GP_11_7_FN, FN_SD0_DAT0,
2393 GP_11_6_FN, FN_SD0_CMD,
2394 GP_11_5_FN, FN_SD0_CLK,
2395 GP_11_4_FN, FN_IP7_7,
2396 GP_11_3_FN, FN_IP7_6,
2397 GP_11_2_FN, FN_IP7_5_4,
2398 GP_11_1_FN, FN_IP7_3_2,
2399 GP_11_0_FN, FN_IP7_1_0 }
2400 },
2401 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32,
2402 4, 4,
2403 1, 1, 1, 1, 1, 1, 1, 1,
2404 1, 1, 1, 1, 1, 1, 1, 1,
2405 1, 1, 1, 1, 1, 1, 1, 1) {
2406 /* IP0_31_28 [4] */
2407 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2408 /* IP0_27_24 [4] */
2409 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2410 /* IP0_23 [1] */
2411 FN_DU0_DB7_C5, 0,
2412 /* IP0_22 [1] */
2413 FN_DU0_DB6_C4, 0,
2414 /* IP0_21 [1] */
2415 FN_DU0_DB5_C3, 0,
2416 /* IP0_20 [1] */
2417 FN_DU0_DB4_C2, 0,
2418 /* IP0_19 [1] */
2419 FN_DU0_DB3_C1, 0,
2420 /* IP0_18 [1] */
2421 FN_DU0_DB2_C0, 0,
2422 /* IP0_17 [1] */
2423 FN_DU0_DB1, 0,
2424 /* IP0_16 [1] */
2425 FN_DU0_DB0, 0,
2426 /* IP0_15 [1] */
2427 FN_DU0_DG7_Y3_DATA15, 0,
2428 /* IP0_14 [1] */
2429 FN_DU0_DG6_Y2_DATA14, 0,
2430 /* IP0_13 [1] */
2431 FN_DU0_DG5_Y1_DATA13, 0,
2432 /* IP0_12 [1] */
2433 FN_DU0_DG4_Y0_DATA12, 0,
2434 /* IP0_11 [1] */
2435 FN_DU0_DG3_C7_DATA11, 0,
2436 /* IP0_10 [1] */
2437 FN_DU0_DG2_C6_DATA10, 0,
2438 /* IP0_9 [1] */
2439 FN_DU0_DG1_DATA9, 0,
2440 /* IP0_8 [1] */
2441 FN_DU0_DG0_DATA8, 0,
2442 /* IP0_7 [1] */
2443 FN_DU0_DR7_Y9_DATA7, 0,
2444 /* IP0_6 [1] */
2445 FN_DU0_DR6_Y8_DATA6, 0,
2446 /* IP0_5 [1] */
2447 FN_DU0_DR5_Y7_DATA5, 0,
2448 /* IP0_4 [1] */
2449 FN_DU0_DR4_Y6_DATA4, 0,
2450 /* IP0_3 [1] */
2451 FN_DU0_DR3_Y5_DATA3, 0,
2452 /* IP0_2 [1] */
2453 FN_DU0_DR2_Y4_DATA2, 0,
2454 /* IP0_1 [1] */
2455 FN_DU0_DR1_DATA1, 0,
2456 /* IP0_0 [1] */
2457 FN_DU0_DR0_DATA0, 0 }
2458 },
2459 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32,
2460 4, 4,
2461 1, 1, 1, 1, 1, 1, 1, 1,
2462 1, 1, 1, 1, 1, 1, 1, 1,
2463 1, 1, 1, 1, 1, 1, 1, 1) {
2464 /* IP1_31_28 [4] */
2465 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2466 /* IP1_27_24 [4] */
2467 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2468 /* IP1_23 [1] */
2469 0, 0,
2470 /* IP1_22 [1] */
2471 FN_A25, FN_SSL,
2472 /* IP1_21 [1] */
2473 FN_A24, FN_SPCLK,
2474 /* IP1_20 [1] */
2475 FN_A23, FN_IO3,
2476 /* IP1_19 [1] */
2477 FN_A22, FN_IO2,
2478 /* IP1_18 [1] */
2479 FN_A21, FN_MISO_IO1,
2480 /* IP1_17 [1] */
2481 FN_A20, FN_MOSI_IO0,
2482 /* IP1_16 [1] */
2483 FN_DU1_DG7_Y3_DATA11, 0,
2484 /* IP1_15 [1] */
2485 FN_DU1_DG6_Y2_DATA10, 0,
2486 /* IP1_14 [1] */
2487 FN_DU1_DG5_Y1_DATA9, 0,
2488 /* IP1_13 [1] */
2489 FN_DU1_DG4_Y0_DATA8, 0,
2490 /* IP1_12 [1] */
2491 FN_DU1_DG3_C7_DATA7, 0,
2492 /* IP1_11 [1] */
2493 FN_DU1_DG2_C6_DATA6, 0,
2494 /* IP1_10 [1] */
2495 FN_DU1_DR7_DATA5, 0,
2496 /* IP1_9 [1] */
2497 FN_DU1_DR6_DATA4, 0,
2498 /* IP1_8 [1] */
2499 FN_DU1_DR5_Y7_DATA3, 0,
2500 /* IP1_7 [1] */
2501 FN_DU1_DR4_Y6_DATA2, 0,
2502 /* IP1_6 [1] */
2503 FN_DU1_DR3_Y5_DATA1, 0,
2504 /* IP1_5 [1] */
2505 FN_DU1_DR2_Y4_DATA0, 0,
2506 /* IP1_4 [1] */
2507 FN_DU0_CDE, 0,
2508 /* IP1_3 [1] */
2509 FN_DU0_DISP, 0,
2510 /* IP1_2 [1] */
2511 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, 0,
2512 /* IP1_1 [1] */
2513 FN_DU0_EXVSYNC_DU0_VSYNC, 0,
2514 /* IP1_0 [1] */
2515 FN_DU0_EXHSYNC_DU0_HSYNC, 0 }
2516 },
2517 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32,
2518 4, 4,
2519 4, 3, 1,
2520 1, 1, 1, 1, 1, 1, 1, 1,
2521 1, 1, 1, 1, 1, 1, 1, 1) {
2522 /* IP2_31_28 [4] */
2523 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2524 /* IP2_27_24 [4] */
2525 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2526 /* IP2_23_20 [4] */
2527 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2528 /* IP2_19_17 [3] */
2529 0, 0, 0, 0, 0, 0, 0, 0,
2530 /* IP2_16 [1] */
2531 FN_VI2_FIELD, FN_AVB_TXD2,
2532 /* IP2_15 [1] */
2533 FN_VI2_D11_Y3, FN_AVB_TXD1,
2534 /* IP2_14 [1] */
2535 FN_VI2_D10_Y2, FN_AVB_TXD0,
2536 /* IP2_13 [1] */
2537 FN_VI2_D9_Y1, FN_AVB_TX_EN,
2538 /* IP2_12 [1] */
2539 FN_VI2_D8_Y0, FN_AVB_TXD3,
2540 /* IP2_11 [1] */
2541 FN_VI2_D7_C7, FN_AVB_COL,
2542 /* IP2_10 [1] */
2543 FN_VI2_D6_C6, FN_AVB_RX_ER,
2544 /* IP2_9 [1] */
2545 FN_VI2_D5_C5, FN_AVB_RXD7,
2546 /* IP2_8 [1] */
2547 FN_VI2_D4_C4, FN_AVB_RXD6,
2548 /* IP2_7 [1] */
2549 FN_VI2_D3_C3, FN_AVB_RXD5,
2550 /* IP2_6 [1] */
2551 FN_VI2_D2_C2, FN_AVB_RXD4,
2552 /* IP2_5 [1] */
2553 FN_VI2_D1_C1, FN_AVB_RXD3,
2554 /* IP2_4 [1] */
2555 FN_VI2_D0_C0, FN_AVB_RXD2,
2556 /* IP2_3 [1] */
2557 FN_VI2_VSYNC_N, FN_AVB_RXD1,
2558 /* IP2_2 [1] */
2559 FN_VI2_HSYNC_N, FN_AVB_RXD0,
2560 /* IP2_1 [1] */
2561 FN_VI2_CLKENB, FN_AVB_RX_DV,
2562 /* IP2_0 [1] */
2563 FN_VI2_CLK, FN_AVB_RX_CLK }
2564 },
2565 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32,
2566 4, 4,
2567 4, 4,
2568 1, 1, 1, 1, 1, 1, 1, 1,
2569 1, 1, 1, 1, 1, 1, 1, 1) {
2570 /* IP3_31_28 [4] */
2571 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2572 /* IP3_27_24 [4] */
2573 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2574 /* IP3_23_20 [4] */
2575 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2576 /* IP3_19_16 [4] */
2577 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2578 /* IP3_15 [1] */
2579 0, 0,
2580 /* IP3_14 [1] */
2581 FN_VI3_D11_Y3, FN_AVB_AVTP_MATCH,
2582 /* IP3_13 [1] */
2583 FN_VI3_D9_Y1, FN_AVB_GTXREFCLK,
2584 /* IP3_12 [1] */
2585 FN_VI3_D8_Y0, FN_AVB_CRS,
2586 /* IP3_11 [1] */
2587 FN_VI3_D7_C7, FN_AVB_PHY_INT,
2588 /* IP3_10 [1] */
2589 FN_VI3_D6_C6, FN_AVB_MAGIC,
2590 /* IP3_9 [1] */
2591 FN_VI3_D5_C5, FN_AVB_LINK,
2592 /* IP3_8 [1] */
2593 FN_VI3_D4_C4, FN_AVB_MDIO,
2594 /* IP3_7 [1] */
2595 FN_VI3_D3_C3, FN_AVB_MDC,
2596 /* IP3_6 [1] */
2597 FN_VI3_D2_C2, FN_AVB_GTX_CLK,
2598 /* IP3_5 [1] */
2599 FN_VI3_D1_C1, FN_AVB_TX_ER,
2600 /* IP3_4 [1] */
2601 FN_VI3_D0_C0, FN_AVB_TXD7,
2602 /* IP3_3 [1] */
2603 FN_VI3_VSYNC_N, FN_AVB_TXD6,
2604 /* IP3_2 [1] */
2605 FN_VI3_HSYNC_N, FN_AVB_TXD5,
2606 /* IP3_1 [1] */
2607 FN_VI3_CLKENB, FN_AVB_TXD4,
2608 /* IP3_0 [1] */
2609 FN_VI3_CLK, FN_AVB_TX_CLK }
2610 },
2611 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32,
2612 4, 3, 1,
2613 1, 1, 1, 2, 2, 2,
2614 2, 2, 2, 2, 2, 1, 2, 1, 1) {
2615 /* IP4_31_28 [4] */
2616 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2617 /* IP4_27_25 [3] */
2618 0, 0, 0, 0, 0, 0, 0, 0,
2619 /* IP4_24 [1] */
2620 FN_VI4_FIELD, FN_VI3_D15_Y7,
2621 /* IP4_23 [1] */
2622 FN_VI4_D11_Y3, FN_VI3_D14_Y6,
2623 /* IP4_22 [1] */
2624 FN_VI4_D10_Y2, FN_VI3_D13_Y5,
2625 /* IP4_21 [1] */
2626 FN_VI4_D9_Y1, FN_VI3_D12_Y4,
2627 /* IP4_20_19 [2] */
2628 FN_VI4_D8_Y0, FN_VI0_D23_R7, FN_VI2_D15_Y7, 0,
2629 /* IP4_18_17 [2] */
2630 FN_VI4_D7_C7, FN_VI0_D22_R6, FN_VI2_D14_Y6, 0,
2631 /* IP4_16_15 [2] */
2632 FN_VI4_D6_C6, FN_VI0_D21_R5, FN_VI2_D13_Y5, 0,
2633 /* IP4_14_13 [2] */
2634 FN_VI4_D5_C5, FN_VI0_D20_R4, FN_VI2_D12_Y4, 0,
2635 /* IP4_12_11 [2] */
2636 FN_VI4_D4_C4, FN_VI0_D19_R3, FN_VI1_D15_G7_Y7, 0,
2637 /* IP4_10_9 [2] */
2638 FN_VI4_D3_C3, FN_VI0_D18_R2, FN_VI1_D14_G6_Y6, 0,
2639 /* IP4_8_7 [2] */
2640 FN_VI4_D2_C2, 0, FN_VI0_D17_R1, FN_VI1_D13_G5_Y5,
2641 /* IP4_6_5 [2] */
2642 FN_VI4_D1_C1, FN_VI0_D16_R0, FN_VI1_D12_G4_Y4, 0,
2643 /* IP4_4 [1] */
2644 FN_VI4_D0_C0, FN_VI0_D15_G7_Y7,
2645 /* IP4_3_2 [2] */
2646 FN_VI4_VSYNC_N, FN_VI0_D14_G6_Y6, 0, 0,
2647 /* IP4_1 [1] */
2648 FN_VI4_HSYNC_N, FN_VI0_D13_G5_Y5,
2649 /* IP4_0 [1] */
2650 FN_VI4_CLKENB, FN_VI0_D12_G4_Y4 }
2651 },
2652 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32,
2653 4, 4,
2654 4, 4,
2655 4, 1, 1, 1, 1,
2656 1, 1, 1, 1, 1, 1, 1, 1) {
2657 /* IP5_31_28 [4] */
2658 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2659 /* IP5_27_24 [4] */
2660 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2661 /* IP5_23_20 [4] */
2662 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2663 /* IP5_19_16 [4] */
2664 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2665 /* IP5_15_12 [4] */
2666 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2667 /* IP5_11 [1] */
2668 FN_VI5_D8_Y0, FN_VI1_D23_R7,
2669 /* IP5_10 [1] */
2670 FN_VI5_D7_C7, FN_VI1_D22_R6,
2671 /* IP5_9 [1] */
2672 FN_VI5_D6_C6, FN_VI1_D21_R5,
2673 /* IP5_8 [1] */
2674 FN_VI5_D5_C5, FN_VI1_D20_R4,
2675 /* IP5_7 [1] */
2676 FN_VI5_D4_C4, FN_VI1_D19_R3,
2677 /* IP5_6 [1] */
2678 FN_VI5_D3_C3, FN_VI1_D18_R2,
2679 /* IP5_5 [1] */
2680 FN_VI5_D2_C2, FN_VI1_D17_R1,
2681 /* IP5_4 [1] */
2682 FN_VI5_D1_C1, FN_VI1_D16_R0,
2683 /* IP5_3 [1] */
2684 FN_VI5_D0_C0, FN_VI1_D15_G7_Y7_B,
2685 /* IP5_2 [1] */
2686 FN_VI5_VSYNC_N, FN_VI1_D14_G6_Y6_B,
2687 /* IP5_1 [1] */
2688 FN_VI5_HSYNC_N, FN_VI1_D13_G5_Y5_B,
2689 /* IP5_0 [1] */
2690 FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_B }
2691 },
2692 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32,
2693 4, 4,
2694 4, 1, 2, 1,
2695 2, 2, 2, 2,
2696 1, 1, 1, 1, 1, 1, 1, 1) {
2697 /* IP6_31_28 [4] */
2698 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2699 /* IP6_27_24 [4] */
2700 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2701 /* IP6_23_20 [4] */
2702 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2703 /* IP6_19 [1] */
2704 0, 0,
2705 /* IP6_18_17 [2] */
2706 FN_DREQ1_N, FN_RX3, 0, 0,
2707 /* IP6_16 [1] */
2708 FN_TX3, 0,
2709 /* IP6_15_14 [2] */
2710 FN_DACK1, FN_SCK3, 0, 0,
2711 /* IP6_13_12 [2] */
2712 FN_DREQ0_N, FN_RX2, 0, 0,
2713 /* IP6_11_10 [2] */
2714 FN_DACK0, FN_TX2, 0, 0,
2715 /* IP6_9_8 [2] */
2716 FN_DRACK0, FN_SCK2, 0, 0,
2717 /* IP6_7 [1] */
2718 FN_MSIOF1_RXD, FN_HRX1,
2719 /* IP6_6 [1] */
2720 FN_MSIOF1_TXD, FN_HTX1,
2721 /* IP6_5 [1] */
2722 FN_MSIOF1_SYNC, FN_HRTS1_N,
2723 /* IP6_4 [1] */
2724 FN_MSIOF1_SCK, FN_HSCK1,
2725 /* IP6_3 [1] */
2726 FN_MSIOF0_RXD, FN_HRX0,
2727 /* IP6_2 [1] */
2728 FN_MSIOF0_TXD, FN_HTX0,
2729 /* IP6_1 [1] */
2730 FN_MSIOF0_SYNC, FN_HCTS0_N,
2731 /* IP6_0 [1] */
2732 FN_MSIOF0_SCK, FN_HSCK0 }
2733 },
2734 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32,
2735 4, 4,
2736 3, 1, 1, 1, 1, 1,
2737 2, 2, 2, 2,
2738 1, 1, 2, 2, 2) {
2739 /* IP7_31_28 [4] */
2740 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2741 /* IP7_27_24 [4] */
2742 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2743 /* IP7_23_21 [3] */
2744 0, 0, 0, 0, 0, 0, 0, 0,
2745 /* IP7_20 [1] */
2746 FN_AUDIO_CLKB, 0,
2747 /* IP7_19 [1] */
2748 FN_AUDIO_CLKA, 0,
2749 /* IP7_18 [1] */
2750 FN_AUDIO_CLKOUT, 0,
2751 /* IP7_17 [1] */
2752 FN_SSI_SDATA4, 0,
2753 /* IP7_16 [1] */
2754 FN_SSI_WS4, 0,
2755 /* IP7_15_14 [2] */
2756 FN_SSI_SCK4, FN_TPU0TO3, 0, 0,
2757 /* IP7_13_12 [2] */
2758 FN_SSI_SDATA3, FN_TPU0TO2, 0, 0,
2759 /* IP7_11_10 [2] */
2760 FN_SSI_WS34, FN_TPU0TO1, 0, 0,
2761 /* IP7_9_8 [2] */
2762 FN_SSI_SCK34, FN_TPU0TO0, 0, 0,
2763 /* IP7_7 [1] */
2764 FN_PWM4, 0,
2765 /* IP7_6 [1] */
2766 FN_PWM3, 0,
2767 /* IP7_5_4 [2] */
2768 FN_PWM2, FN_TCLK3, FN_FSO_TOE, 0,
2769 /* IP7_3_2 [2] */
2770 FN_PWM1, FN_TCLK2, FN_FSO_CFE_1, 0,
2771 /* IP7_1_0 [2] */
2772 FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, 0 }
2773 },
2774 { },
2775 };
2776
2777 const struct sh_pfc_soc_info r8a7792_pinmux_info = {
2778 .name = "r8a77920_pfc",
2779 .unlock_reg = 0xe6060000, /* PMMR */
2780
2781 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2782
2783 .pins = pinmux_pins,
2784 .nr_pins = ARRAY_SIZE(pinmux_pins),
2785 .groups = pinmux_groups,
2786 .nr_groups = ARRAY_SIZE(pinmux_groups),
2787 .functions = pinmux_functions,
2788 .nr_functions = ARRAY_SIZE(pinmux_functions),
2789
2790 .cfg_regs = pinmux_config_regs,
2791
2792 .pinmux_data = pinmux_data,
2793 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
2794 };
Linux with added FPC-III support