drivers/hwmon/hwmon-vid.c

   1 /*
   2  * hwmon-vid.c - VID/VRM/VRD voltage conversions
   3  *
   4  * Copyright (c) 2004 Rudolf Marek <r.marek@assembler.cz>
   5  *
   6  * Partly imported from i2c-vid.h of the lm_sensors project
   7  * Copyright (c) 2002 Mark D. Studebaker <mdsxyz123@yahoo.com>
   8  * With assistance from Trent Piepho <xyzzy@speakeasy.org>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  23  */
  24
  25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  26
  27 #include <linux/module.h>
  28 #include <linux/kernel.h>
  29 #include <linux/hwmon-vid.h>
  30
  31 /*
  32  * Common code for decoding VID pins.
  33  *
  34  * References:
  35  *
  36  * For VRM 8.4 to 9.1, "VRM x.y DC-DC Converter Design Guidelines",
  37  * available at http://developer.intel.com/.
  38  *
  39  * For VRD 10.0 and up, "VRD x.y Design Guide",
  40  * available at http://developer.intel.com/.
  41  *
  42  * AMD Athlon 64 and AMD Opteron Processors, AMD Publication 26094,
  43  * http://support.amd.com/us/Processor_TechDocs/26094.PDF
  44  * Table 74. VID Code Voltages
  45  * This corresponds to an arbitrary VRM code of 24 in the functions below.
  46  * These CPU models (K8 revision <= E) have 5 VID pins. See also:
  47  * Revision Guide for AMD Athlon 64 and AMD Opteron Processors, AMD Publication 25759,
  48  * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf
  49  *
  50  * AMD NPT Family 0Fh Processors, AMD Publication 32559,
  51  * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/32559.pdf
  52  * Table 71. VID Code Voltages
  53  * This corresponds to an arbitrary VRM code of 25 in the functions below.
  54  * These CPU models (K8 revision >= F) have 6 VID pins. See also:
  55  * Revision Guide for AMD NPT Family 0Fh Processors, AMD Publication 33610,
  56  * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
  57  *
  58  * The 17 specification is in fact Intel Mobile Voltage Positioning -
  59  * (IMVP-II). You can find more information in the datasheet of Max1718
  60  * http://www.maxim-ic.com/quick_view2.cfm/qv_pk/2452
  61  *
  62  * The 13 specification corresponds to the Intel Pentium M series. There
  63  * doesn't seem to be any named specification for these. The conversion
  64  * tables are detailed directly in the various Pentium M datasheets:
  65  * http://www.intel.com/design/intarch/pentiumm/docs_pentiumm.htm
  66  *
  67  * The 14 specification corresponds to Intel Core series. There
  68  * doesn't seem to be any named specification for these. The conversion
  69  * tables are detailed directly in the various Pentium Core datasheets:
  70  * http://www.intel.com/design/mobile/datashts/309221.htm
  71  *
  72  * The 110 (VRM 11) specification corresponds to Intel Conroe based series.
  73  * http://www.intel.com/design/processor/applnots/313214.htm
  74  */
  75
  76 /*
  77  * vrm is the VRM/VRD document version multiplied by 10.
  78  * val is the 4-bit or more VID code.
  79  * Returned value is in mV to avoid floating point in the kernel.
  80  * Some VID have some bits in uV scale, this is rounded to mV.
  81  */
  82 int vid_from_reg(int val, u8 vrm)
  83 {
  84         int vid;
  85
  86         switch(vrm) {
  87
  88         case 100:               /* VRD 10.0 */
  89                 /* compute in uV, round to mV */
  90                 val &= 0x3f;
  91                 if((val & 0x1f) == 0x1f)
  92                         return 0;
  93                 if((val & 0x1f) <= 0x09 || val == 0x0a)
  94                         vid = 1087500 - (val & 0x1f) * 25000;
  95                 else
  96                         vid = 1862500 - (val & 0x1f) * 25000;
  97                 if(val & 0x20)
  98                         vid -= 12500;
  99                 return((vid + 500) / 1000);
 100
 101         case 110:               /* Intel Conroe */
 102                                 /* compute in uV, round to mV */
 103                 val &= 0xff;
 104                 if (val < 0x02 || val > 0xb2)
 105                         return 0;
 106                 return((1600000 - (val - 2) * 6250 + 500) / 1000);
 107
 108         case 24:                /* Athlon64 & Opteron */
 109                 val &= 0x1f;
 110                 if (val == 0x1f)
 111                         return 0;
 112                                 /* fall through */
 113         case 25:                /* AMD NPT 0Fh */
 114                 val &= 0x3f;
 115                 return (val < 32) ? 1550 - 25 * val
 116                         : 775 - (25 * (val - 31)) / 2;
 117
 118         case 91:                /* VRM 9.1 */
 119         case 90:                /* VRM 9.0 */
 120                 val &= 0x1f;
 121                 return(val == 0x1f ? 0 :
 122                                        1850 - val * 25);
 123
 124         case 85:                /* VRM 8.5 */
 125                 val &= 0x1f;
 126                 return((val & 0x10  ? 25 : 0) +
 127                        ((val & 0x0f) > 0x04 ? 2050 : 1250) -
 128                        ((val & 0x0f) * 50));
 129
 130         case 84:                /* VRM 8.4 */
 131                 val &= 0x0f;
 132                                 /* fall through */
 133         case 82:                /* VRM 8.2 */
 134                 val &= 0x1f;
 135                 return(val == 0x1f ? 0 :
 136                        val & 0x10  ? 5100 - (val) * 100 :
 137                                      2050 - (val) * 50);
 138         case 17:                /* Intel IMVP-II */
 139                 val &= 0x1f;
 140                 return(val & 0x10 ? 975 - (val & 0xF) * 25 :
 141                                     1750 - val * 50);
 142         case 13:
 143                 val &= 0x3f;
 144                 return(1708 - val * 16);
 145         case 14:                /* Intel Core */
 146                                 /* compute in uV, round to mV */
 147                 val &= 0x7f;
 148                 return(val > 0x77 ? 0 : (1500000 - (val * 12500) + 500) / 1000);
 149         default:                /* report 0 for unknown */
 150                 if (vrm)
 151                         pr_warn("Requested unsupported VRM version (%u)\n",
 152                                 (unsigned int)vrm);
 153                 return 0;
 154         }
 155 }
 156
 157
 158 /*
 159  * After this point is the code to automatically determine which
 160  * VRM/VRD specification should be used depending on the CPU.
 161  */
 162
 163 struct vrm_model {
 164         u8 vendor;
 165         u8 eff_family;
 166         u8 eff_model;
 167         u8 eff_stepping;
 168         u8 vrm_type;
 169 };
 170
 171 #define ANY 0xFF
 172
 173 #ifdef CONFIG_X86
 174
 175 /*
 176  * The stepping parameter is highest acceptable stepping for current line.
 177  * The model match must be exact for 4-bit values. For model values 0x10
 178  * and above (extended model), all models below the parameter will match.
 179  */
 180
 181 static struct vrm_model vrm_models[] = {
 182         {X86_VENDOR_AMD, 0x6, ANY, ANY, 90},            /* Athlon Duron etc */
 183         {X86_VENDOR_AMD, 0xF, 0x3F, ANY, 24},           /* Athlon 64, Opteron */
 184         /* In theory, all NPT family 0Fh processors have 6 VID pins and should
 185            thus use vrm 25, however in practice not all mainboards route the
 186            6th VID pin because it is never needed. So we use the 5 VID pin
 187            variant (vrm 24) for the models which exist today. */
 188         {X86_VENDOR_AMD, 0xF, 0x7F, ANY, 24},           /* NPT family 0Fh */
 189         {X86_VENDOR_AMD, 0xF, ANY, ANY, 25},            /* future fam. 0Fh */
 190         {X86_VENDOR_AMD, 0x10, ANY, ANY, 25},           /* NPT family 10h */
 191
 192         {X86_VENDOR_INTEL, 0x6, 0x9, ANY, 13},          /* Pentium M (130 nm) */
 193         {X86_VENDOR_INTEL, 0x6, 0xB, ANY, 85},          /* Tualatin */
 194         {X86_VENDOR_INTEL, 0x6, 0xD, ANY, 13},          /* Pentium M (90 nm) */
 195         {X86_VENDOR_INTEL, 0x6, 0xE, ANY, 14},          /* Intel Core (65 nm) */
 196         {X86_VENDOR_INTEL, 0x6, 0xF, ANY, 110},         /* Intel Conroe */
 197         {X86_VENDOR_INTEL, 0x6, ANY, ANY, 82},          /* any P6 */
 198         {X86_VENDOR_INTEL, 0xF, 0x0, ANY, 90},          /* P4 */
 199         {X86_VENDOR_INTEL, 0xF, 0x1, ANY, 90},          /* P4 Willamette */
 200         {X86_VENDOR_INTEL, 0xF, 0x2, ANY, 90},          /* P4 Northwood */
 201         {X86_VENDOR_INTEL, 0xF, ANY, ANY, 100},         /* Prescott and above assume VRD 10 */
 202
 203         {X86_VENDOR_CENTAUR, 0x6, 0x7, ANY, 85},        /* Eden ESP/Ezra */
 204         {X86_VENDOR_CENTAUR, 0x6, 0x8, 0x7, 85},        /* Ezra T */
 205         {X86_VENDOR_CENTAUR, 0x6, 0x9, 0x7, 85},        /* Nemiah */
 206         {X86_VENDOR_CENTAUR, 0x6, 0x9, ANY, 17},        /* C3-M, Eden-N */
 207         {X86_VENDOR_CENTAUR, 0x6, 0xA, 0x7, 0},         /* No information */
 208         {X86_VENDOR_CENTAUR, 0x6, 0xA, ANY, 13},        /* C7, Esther */
 209
 210         {X86_VENDOR_UNKNOWN, ANY, ANY, ANY, 0}          /* stop here */
 211 };
 212
 213 static u8 find_vrm(u8 eff_family, u8 eff_model, u8 eff_stepping, u8 vendor)
 214 {
 215         int i = 0;
 216
 217         while (vrm_models[i].vendor!=X86_VENDOR_UNKNOWN) {
 218                 if (vrm_models[i].vendor==vendor)
 219                         if ((vrm_models[i].eff_family==eff_family)
 220                          && ((vrm_models[i].eff_model==eff_model) ||
 221                              (vrm_models[i].eff_model >= 0x10 &&
 222                               eff_model <= vrm_models[i].eff_model) ||
 223                              (vrm_models[i].eff_model==ANY)) &&
 224                              (eff_stepping <= vrm_models[i].eff_stepping))
 225                                 return vrm_models[i].vrm_type;
 226                 i++;
 227         }
 228
 229         return 0;
 230 }
 231
 232 u8 vid_which_vrm(void)
 233 {
 234         struct cpuinfo_x86 *c = &cpu_data(0);
 235         u32 eax;
 236         u8 eff_family, eff_model, eff_stepping, vrm_ret;
 237
 238         if (c->x86 < 6)         /* Any CPU with family lower than 6 */
 239                 return 0;       /* doesn't have VID and/or CPUID */
 240
 241         eax = cpuid_eax(1);
 242         eff_family = ((eax & 0x00000F00)>>8);
 243         eff_model  = ((eax & 0x000000F0)>>4);
 244         eff_stepping = eax & 0xF;
 245         if (eff_family == 0xF) {        /* use extended model & family */
 246                 eff_family += ((eax & 0x00F00000)>>20);
 247                 eff_model += ((eax & 0x000F0000)>>16)<<4;
 248         }
 249         vrm_ret = find_vrm(eff_family, eff_model, eff_stepping, c->x86_vendor);
 250         if (vrm_ret == 0)
 251                 pr_info("Unknown VRM version of your x86 CPU\n");
 252         return vrm_ret;
 253 }
 254
 255 /* and now for something completely different for the non-x86 world */
 256 #else
 257 u8 vid_which_vrm(void)
 258 {
 259         pr_info("Unknown VRM version of your CPU\n");
 260         return 0;
 261 }
 262 #endif
 263
 264 EXPORT_SYMBOL(vid_from_reg);
 265 EXPORT_SYMBOL(vid_which_vrm);
 266
 267 MODULE_AUTHOR("Rudolf Marek <r.marek@assembler.cz>");
 268
 269 MODULE_DESCRIPTION("hwmon-vid driver");
 270 MODULE_LICENSE("GPL");