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thp: clear_copy_huge_page
[linux/fpc-iii.git] / drivers / net / arm / ep93xx_eth.c
blob5a77001b6d1053d4898b4635b0f1b9d1357e5868
1 /*
2 * EP93xx ethernet network device driver
3 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
4 * Dedicated to Marija Kulikova.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12 #define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__
13
14 #include <linux/dma-mapping.h>
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/netdevice.h>
18 #include <linux/mii.h>
19 #include <linux/etherdevice.h>
20 #include <linux/ethtool.h>
21 #include <linux/init.h>
22 #include <linux/moduleparam.h>
23 #include <linux/platform_device.h>
24 #include <linux/delay.h>
25 #include <linux/io.h>
26 #include <linux/slab.h>
27
28 #include <mach/hardware.h>
29
30 #define DRV_MODULE_NAME "ep93xx-eth"
31 #define DRV_MODULE_VERSION "0.1"
32
33 #define RX_QUEUE_ENTRIES 64
34 #define TX_QUEUE_ENTRIES 8
35
36 #define MAX_PKT_SIZE 2044
37 #define PKT_BUF_SIZE 2048
38
39 #define REG_RXCTL 0x0000
40 #define REG_RXCTL_DEFAULT 0x00073800
41 #define REG_TXCTL 0x0004
42 #define REG_TXCTL_ENABLE 0x00000001
43 #define REG_MIICMD 0x0010
44 #define REG_MIICMD_READ 0x00008000
45 #define REG_MIICMD_WRITE 0x00004000
46 #define REG_MIIDATA 0x0014
47 #define REG_MIISTS 0x0018
48 #define REG_MIISTS_BUSY 0x00000001
49 #define REG_SELFCTL 0x0020
50 #define REG_SELFCTL_RESET 0x00000001
51 #define REG_INTEN 0x0024
52 #define REG_INTEN_TX 0x00000008
53 #define REG_INTEN_RX 0x00000007
54 #define REG_INTSTSP 0x0028
55 #define REG_INTSTS_TX 0x00000008
56 #define REG_INTSTS_RX 0x00000004
57 #define REG_INTSTSC 0x002c
58 #define REG_AFP 0x004c
59 #define REG_INDAD0 0x0050
60 #define REG_INDAD1 0x0051
61 #define REG_INDAD2 0x0052
62 #define REG_INDAD3 0x0053
63 #define REG_INDAD4 0x0054
64 #define REG_INDAD5 0x0055
65 #define REG_GIINTMSK 0x0064
66 #define REG_GIINTMSK_ENABLE 0x00008000
67 #define REG_BMCTL 0x0080
68 #define REG_BMCTL_ENABLE_TX 0x00000100
69 #define REG_BMCTL_ENABLE_RX 0x00000001
70 #define REG_BMSTS 0x0084
71 #define REG_BMSTS_RX_ACTIVE 0x00000008
72 #define REG_RXDQBADD 0x0090
73 #define REG_RXDQBLEN 0x0094
74 #define REG_RXDCURADD 0x0098
75 #define REG_RXDENQ 0x009c
76 #define REG_RXSTSQBADD 0x00a0
77 #define REG_RXSTSQBLEN 0x00a4
78 #define REG_RXSTSQCURADD 0x00a8
79 #define REG_RXSTSENQ 0x00ac
80 #define REG_TXDQBADD 0x00b0
81 #define REG_TXDQBLEN 0x00b4
82 #define REG_TXDQCURADD 0x00b8
83 #define REG_TXDENQ 0x00bc
84 #define REG_TXSTSQBADD 0x00c0
85 #define REG_TXSTSQBLEN 0x00c4
86 #define REG_TXSTSQCURADD 0x00c8
87 #define REG_MAXFRMLEN 0x00e8
88
89 struct ep93xx_rdesc
90 {
91 u32 buf_addr;
92 u32 rdesc1;
93 };
94
95 #define RDESC1_NSOF 0x80000000
96 #define RDESC1_BUFFER_INDEX 0x7fff0000
97 #define RDESC1_BUFFER_LENGTH 0x0000ffff
98
99 struct ep93xx_rstat
100 {
101 u32 rstat0;
102 u32 rstat1;
103 };
104
105 #define RSTAT0_RFP 0x80000000
106 #define RSTAT0_RWE 0x40000000
107 #define RSTAT0_EOF 0x20000000
108 #define RSTAT0_EOB 0x10000000
109 #define RSTAT0_AM 0x00c00000
110 #define RSTAT0_RX_ERR 0x00200000
111 #define RSTAT0_OE 0x00100000
112 #define RSTAT0_FE 0x00080000
113 #define RSTAT0_RUNT 0x00040000
114 #define RSTAT0_EDATA 0x00020000
115 #define RSTAT0_CRCE 0x00010000
116 #define RSTAT0_CRCI 0x00008000
117 #define RSTAT0_HTI 0x00003f00
118 #define RSTAT1_RFP 0x80000000
119 #define RSTAT1_BUFFER_INDEX 0x7fff0000
120 #define RSTAT1_FRAME_LENGTH 0x0000ffff
121
122 struct ep93xx_tdesc
123 {
124 u32 buf_addr;
125 u32 tdesc1;
126 };
127
128 #define TDESC1_EOF 0x80000000
129 #define TDESC1_BUFFER_INDEX 0x7fff0000
130 #define TDESC1_BUFFER_ABORT 0x00008000
131 #define TDESC1_BUFFER_LENGTH 0x00000fff
132
133 struct ep93xx_tstat
134 {
135 u32 tstat0;
136 };
137
138 #define TSTAT0_TXFP 0x80000000
139 #define TSTAT0_TXWE 0x40000000
140 #define TSTAT0_FA 0x20000000
141 #define TSTAT0_LCRS 0x10000000
142 #define TSTAT0_OW 0x04000000
143 #define TSTAT0_TXU 0x02000000
144 #define TSTAT0_ECOLL 0x01000000
145 #define TSTAT0_NCOLL 0x001f0000
146 #define TSTAT0_BUFFER_INDEX 0x00007fff
147
148 struct ep93xx_descs
149 {
150 struct ep93xx_rdesc rdesc[RX_QUEUE_ENTRIES];
151 struct ep93xx_tdesc tdesc[TX_QUEUE_ENTRIES];
152 struct ep93xx_rstat rstat[RX_QUEUE_ENTRIES];
153 struct ep93xx_tstat tstat[TX_QUEUE_ENTRIES];
154 };
155
156 struct ep93xx_priv
157 {
158 struct resource *res;
159 void __iomem *base_addr;
160 int irq;
161
162 struct ep93xx_descs *descs;
163 dma_addr_t descs_dma_addr;
164
165 void *rx_buf[RX_QUEUE_ENTRIES];
166 void *tx_buf[TX_QUEUE_ENTRIES];
167
168 spinlock_t rx_lock;
169 unsigned int rx_pointer;
170 unsigned int tx_clean_pointer;
171 unsigned int tx_pointer;
172 spinlock_t tx_pending_lock;
173 unsigned int tx_pending;
174
175 struct net_device *dev;
176 struct napi_struct napi;
177
178 struct mii_if_info mii;
179 u8 mdc_divisor;
180 };
181
182 #define rdb(ep, off) __raw_readb((ep)->base_addr + (off))
183 #define rdw(ep, off) __raw_readw((ep)->base_addr + (off))
184 #define rdl(ep, off) __raw_readl((ep)->base_addr + (off))
185 #define wrb(ep, off, val) __raw_writeb((val), (ep)->base_addr + (off))
186 #define wrw(ep, off, val) __raw_writew((val), (ep)->base_addr + (off))
187 #define wrl(ep, off, val) __raw_writel((val), (ep)->base_addr + (off))
188
189 static int ep93xx_mdio_read(struct net_device *dev, int phy_id, int reg)
190 {
191 struct ep93xx_priv *ep = netdev_priv(dev);
192 int data;
193 int i;
194
195 wrl(ep, REG_MIICMD, REG_MIICMD_READ | (phy_id << 5) | reg);
196
197 for (i = 0; i < 10; i++) {
198 if ((rdl(ep, REG_MIISTS) & REG_MIISTS_BUSY) == 0)
199 break;
200 msleep(1);
201 }
202
203 if (i == 10) {
204 pr_info("mdio read timed out\n");
205 data = 0xffff;
206 } else {
207 data = rdl(ep, REG_MIIDATA);
208 }
209
210 return data;
211 }
212
213 static void ep93xx_mdio_write(struct net_device *dev, int phy_id, int reg, int data)
214 {
215 struct ep93xx_priv *ep = netdev_priv(dev);
216 int i;
217
218 wrl(ep, REG_MIIDATA, data);
219 wrl(ep, REG_MIICMD, REG_MIICMD_WRITE | (phy_id << 5) | reg);
220
221 for (i = 0; i < 10; i++) {
222 if ((rdl(ep, REG_MIISTS) & REG_MIISTS_BUSY) == 0)
223 break;
224 msleep(1);
225 }
226
227 if (i == 10)
228 pr_info("mdio write timed out\n");
229 }
230
231 static int ep93xx_rx(struct net_device *dev, int processed, int budget)
232 {
233 struct ep93xx_priv *ep = netdev_priv(dev);
234
235 while (processed < budget) {
236 int entry;
237 struct ep93xx_rstat *rstat;
238 u32 rstat0;
239 u32 rstat1;
240 int length;
241 struct sk_buff *skb;
242
243 entry = ep->rx_pointer;
244 rstat = ep->descs->rstat + entry;
245
246 rstat0 = rstat->rstat0;
247 rstat1 = rstat->rstat1;
248 if (!(rstat0 & RSTAT0_RFP) || !(rstat1 & RSTAT1_RFP))
249 break;
250
251 rstat->rstat0 = 0;
252 rstat->rstat1 = 0;
253
254 if (!(rstat0 & RSTAT0_EOF))
255 pr_crit("not end-of-frame %.8x %.8x\n", rstat0, rstat1);
256 if (!(rstat0 & RSTAT0_EOB))
257 pr_crit("not end-of-buffer %.8x %.8x\n", rstat0, rstat1);
258 if ((rstat1 & RSTAT1_BUFFER_INDEX) >> 16 != entry)
259 pr_crit("entry mismatch %.8x %.8x\n", rstat0, rstat1);
260
261 if (!(rstat0 & RSTAT0_RWE)) {
262 dev->stats.rx_errors++;
263 if (rstat0 & RSTAT0_OE)
264 dev->stats.rx_fifo_errors++;
265 if (rstat0 & RSTAT0_FE)
266 dev->stats.rx_frame_errors++;
267 if (rstat0 & (RSTAT0_RUNT | RSTAT0_EDATA))
268 dev->stats.rx_length_errors++;
269 if (rstat0 & RSTAT0_CRCE)
270 dev->stats.rx_crc_errors++;
271 goto err;
272 }
273
274 length = rstat1 & RSTAT1_FRAME_LENGTH;
275 if (length > MAX_PKT_SIZE) {
276 pr_notice("invalid length %.8x %.8x\n", rstat0, rstat1);
277 goto err;
278 }
279
280 /* Strip FCS. */
281 if (rstat0 & RSTAT0_CRCI)
282 length -= 4;
283
284 skb = dev_alloc_skb(length + 2);
285 if (likely(skb != NULL)) {
286 skb_reserve(skb, 2);
287 dma_sync_single_for_cpu(NULL, ep->descs->rdesc[entry].buf_addr,
288 length, DMA_FROM_DEVICE);
289 skb_copy_to_linear_data(skb, ep->rx_buf[entry], length);
290 skb_put(skb, length);
291 skb->protocol = eth_type_trans(skb, dev);
292
293 netif_receive_skb(skb);
294
295 dev->stats.rx_packets++;
296 dev->stats.rx_bytes += length;
297 } else {
298 dev->stats.rx_dropped++;
299 }
300
301 err:
302 ep->rx_pointer = (entry + 1) & (RX_QUEUE_ENTRIES - 1);
303 processed++;
304 }
305
306 return processed;
307 }
308
309 static int ep93xx_have_more_rx(struct ep93xx_priv *ep)
310 {
311 struct ep93xx_rstat *rstat = ep->descs->rstat + ep->rx_pointer;
312 return !!((rstat->rstat0 & RSTAT0_RFP) && (rstat->rstat1 & RSTAT1_RFP));
313 }
314
315 static int ep93xx_poll(struct napi_struct *napi, int budget)
316 {
317 struct ep93xx_priv *ep = container_of(napi, struct ep93xx_priv, napi);
318 struct net_device *dev = ep->dev;
319 int rx = 0;
320
321 poll_some_more:
322 rx = ep93xx_rx(dev, rx, budget);
323 if (rx < budget) {
324 int more = 0;
325
326 spin_lock_irq(&ep->rx_lock);
327 __napi_complete(napi);
328 wrl(ep, REG_INTEN, REG_INTEN_TX | REG_INTEN_RX);
329 if (ep93xx_have_more_rx(ep)) {
330 wrl(ep, REG_INTEN, REG_INTEN_TX);
331 wrl(ep, REG_INTSTSP, REG_INTSTS_RX);
332 more = 1;
333 }
334 spin_unlock_irq(&ep->rx_lock);
335
336 if (more && napi_reschedule(napi))
337 goto poll_some_more;
338 }
339
340 if (rx) {
341 wrw(ep, REG_RXDENQ, rx);
342 wrw(ep, REG_RXSTSENQ, rx);
343 }
344
345 return rx;
346 }
347
348 static int ep93xx_xmit(struct sk_buff *skb, struct net_device *dev)
349 {
350 struct ep93xx_priv *ep = netdev_priv(dev);
351 int entry;
352
353 if (unlikely(skb->len > MAX_PKT_SIZE)) {
354 dev->stats.tx_dropped++;
355 dev_kfree_skb(skb);
356 return NETDEV_TX_OK;
357 }
358
359 entry = ep->tx_pointer;
360 ep->tx_pointer = (ep->tx_pointer + 1) & (TX_QUEUE_ENTRIES - 1);
361
362 ep->descs->tdesc[entry].tdesc1 =
363 TDESC1_EOF | (entry << 16) | (skb->len & 0xfff);
364 skb_copy_and_csum_dev(skb, ep->tx_buf[entry]);
365 dma_sync_single_for_cpu(NULL, ep->descs->tdesc[entry].buf_addr,
366 skb->len, DMA_TO_DEVICE);
367 dev_kfree_skb(skb);
368
369 spin_lock_irq(&ep->tx_pending_lock);
370 ep->tx_pending++;
371 if (ep->tx_pending == TX_QUEUE_ENTRIES)
372 netif_stop_queue(dev);
373 spin_unlock_irq(&ep->tx_pending_lock);
374
375 wrl(ep, REG_TXDENQ, 1);
376
377 return NETDEV_TX_OK;
378 }
379
380 static void ep93xx_tx_complete(struct net_device *dev)
381 {
382 struct ep93xx_priv *ep = netdev_priv(dev);
383 int wake;
384
385 wake = 0;
386
387 spin_lock(&ep->tx_pending_lock);
388 while (1) {
389 int entry;
390 struct ep93xx_tstat *tstat;
391 u32 tstat0;
392
393 entry = ep->tx_clean_pointer;
394 tstat = ep->descs->tstat + entry;
395
396 tstat0 = tstat->tstat0;
397 if (!(tstat0 & TSTAT0_TXFP))
398 break;
399
400 tstat->tstat0 = 0;
401
402 if (tstat0 & TSTAT0_FA)
403 pr_crit("frame aborted %.8x\n", tstat0);
404 if ((tstat0 & TSTAT0_BUFFER_INDEX) != entry)
405 pr_crit("entry mismatch %.8x\n", tstat0);
406
407 if (tstat0 & TSTAT0_TXWE) {
408 int length = ep->descs->tdesc[entry].tdesc1 & 0xfff;
409
410 dev->stats.tx_packets++;
411 dev->stats.tx_bytes += length;
412 } else {
413 dev->stats.tx_errors++;
414 }
415
416 if (tstat0 & TSTAT0_OW)
417 dev->stats.tx_window_errors++;
418 if (tstat0 & TSTAT0_TXU)
419 dev->stats.tx_fifo_errors++;
420 dev->stats.collisions += (tstat0 >> 16) & 0x1f;
421
422 ep->tx_clean_pointer = (entry + 1) & (TX_QUEUE_ENTRIES - 1);
423 if (ep->tx_pending == TX_QUEUE_ENTRIES)
424 wake = 1;
425 ep->tx_pending--;
426 }
427 spin_unlock(&ep->tx_pending_lock);
428
429 if (wake)
430 netif_wake_queue(dev);
431 }
432
433 static irqreturn_t ep93xx_irq(int irq, void *dev_id)
434 {
435 struct net_device *dev = dev_id;
436 struct ep93xx_priv *ep = netdev_priv(dev);
437 u32 status;
438
439 status = rdl(ep, REG_INTSTSC);
440 if (status == 0)
441 return IRQ_NONE;
442
443 if (status & REG_INTSTS_RX) {
444 spin_lock(&ep->rx_lock);
445 if (likely(napi_schedule_prep(&ep->napi))) {
446 wrl(ep, REG_INTEN, REG_INTEN_TX);
447 __napi_schedule(&ep->napi);
448 }
449 spin_unlock(&ep->rx_lock);
450 }
451
452 if (status & REG_INTSTS_TX)
453 ep93xx_tx_complete(dev);
454
455 return IRQ_HANDLED;
456 }
457
458 static void ep93xx_free_buffers(struct ep93xx_priv *ep)
459 {
460 int i;
461
462 for (i = 0; i < RX_QUEUE_ENTRIES; i += 2) {
463 dma_addr_t d;
464
465 d = ep->descs->rdesc[i].buf_addr;
466 if (d)
467 dma_unmap_single(NULL, d, PAGE_SIZE, DMA_FROM_DEVICE);
468
469 if (ep->rx_buf[i] != NULL)
470 free_page((unsigned long)ep->rx_buf[i]);
471 }
472
473 for (i = 0; i < TX_QUEUE_ENTRIES; i += 2) {
474 dma_addr_t d;
475
476 d = ep->descs->tdesc[i].buf_addr;
477 if (d)
478 dma_unmap_single(NULL, d, PAGE_SIZE, DMA_TO_DEVICE);
479
480 if (ep->tx_buf[i] != NULL)
481 free_page((unsigned long)ep->tx_buf[i]);
482 }
483
484 dma_free_coherent(NULL, sizeof(struct ep93xx_descs), ep->descs,
485 ep->descs_dma_addr);
486 }
487
488 /*
489 * The hardware enforces a sub-2K maximum packet size, so we put
490 * two buffers on every hardware page.
491 */
492 static int ep93xx_alloc_buffers(struct ep93xx_priv *ep)
493 {
494 int i;
495
496 ep->descs = dma_alloc_coherent(NULL, sizeof(struct ep93xx_descs),
497 &ep->descs_dma_addr, GFP_KERNEL | GFP_DMA);
498 if (ep->descs == NULL)
499 return 1;
500
501 for (i = 0; i < RX_QUEUE_ENTRIES; i += 2) {
502 void *page;
503 dma_addr_t d;
504
505 page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
506 if (page == NULL)
507 goto err;
508
509 d = dma_map_single(NULL, page, PAGE_SIZE, DMA_FROM_DEVICE);
510 if (dma_mapping_error(NULL, d)) {
511 free_page((unsigned long)page);
512 goto err;
513 }
514
515 ep->rx_buf[i] = page;
516 ep->descs->rdesc[i].buf_addr = d;
517 ep->descs->rdesc[i].rdesc1 = (i << 16) | PKT_BUF_SIZE;
518
519 ep->rx_buf[i + 1] = page + PKT_BUF_SIZE;
520 ep->descs->rdesc[i + 1].buf_addr = d + PKT_BUF_SIZE;
521 ep->descs->rdesc[i + 1].rdesc1 = ((i + 1) << 16) | PKT_BUF_SIZE;
522 }
523
524 for (i = 0; i < TX_QUEUE_ENTRIES; i += 2) {
525 void *page;
526 dma_addr_t d;
527
528 page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
529 if (page == NULL)
530 goto err;
531
532 d = dma_map_single(NULL, page, PAGE_SIZE, DMA_TO_DEVICE);
533 if (dma_mapping_error(NULL, d)) {
534 free_page((unsigned long)page);
535 goto err;
536 }
537
538 ep->tx_buf[i] = page;
539 ep->descs->tdesc[i].buf_addr = d;
540
541 ep->tx_buf[i + 1] = page + PKT_BUF_SIZE;
542 ep->descs->tdesc[i + 1].buf_addr = d + PKT_BUF_SIZE;
543 }
544
545 return 0;
546
547 err:
548 ep93xx_free_buffers(ep);
549 return 1;
550 }
551
552 static int ep93xx_start_hw(struct net_device *dev)
553 {
554 struct ep93xx_priv *ep = netdev_priv(dev);
555 unsigned long addr;
556 int i;
557
558 wrl(ep, REG_SELFCTL, REG_SELFCTL_RESET);
559 for (i = 0; i < 10; i++) {
560 if ((rdl(ep, REG_SELFCTL) & REG_SELFCTL_RESET) == 0)
561 break;
562 msleep(1);
563 }
564
565 if (i == 10) {
566 pr_crit("hw failed to reset\n");
567 return 1;
568 }
569
570 wrl(ep, REG_SELFCTL, ((ep->mdc_divisor - 1) << 9));
571
572 /* Does the PHY support preamble suppress? */
573 if ((ep93xx_mdio_read(dev, ep->mii.phy_id, MII_BMSR) & 0x0040) != 0)
574 wrl(ep, REG_SELFCTL, ((ep->mdc_divisor - 1) << 9) | (1 << 8));
575
576 /* Receive descriptor ring. */
577 addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, rdesc);
578 wrl(ep, REG_RXDQBADD, addr);
579 wrl(ep, REG_RXDCURADD, addr);
580 wrw(ep, REG_RXDQBLEN, RX_QUEUE_ENTRIES * sizeof(struct ep93xx_rdesc));
581
582 /* Receive status ring. */
583 addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, rstat);
584 wrl(ep, REG_RXSTSQBADD, addr);
585 wrl(ep, REG_RXSTSQCURADD, addr);
586 wrw(ep, REG_RXSTSQBLEN, RX_QUEUE_ENTRIES * sizeof(struct ep93xx_rstat));
587
588 /* Transmit descriptor ring. */
589 addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, tdesc);
590 wrl(ep, REG_TXDQBADD, addr);
591 wrl(ep, REG_TXDQCURADD, addr);
592 wrw(ep, REG_TXDQBLEN, TX_QUEUE_ENTRIES * sizeof(struct ep93xx_tdesc));
593
594 /* Transmit status ring. */
595 addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, tstat);
596 wrl(ep, REG_TXSTSQBADD, addr);
597 wrl(ep, REG_TXSTSQCURADD, addr);
598 wrw(ep, REG_TXSTSQBLEN, TX_QUEUE_ENTRIES * sizeof(struct ep93xx_tstat));
599
600 wrl(ep, REG_BMCTL, REG_BMCTL_ENABLE_TX | REG_BMCTL_ENABLE_RX);
601 wrl(ep, REG_INTEN, REG_INTEN_TX | REG_INTEN_RX);
602 wrl(ep, REG_GIINTMSK, 0);
603
604 for (i = 0; i < 10; i++) {
605 if ((rdl(ep, REG_BMSTS) & REG_BMSTS_RX_ACTIVE) != 0)
606 break;
607 msleep(1);
608 }
609
610 if (i == 10) {
611 pr_crit("hw failed to start\n");
612 return 1;
613 }
614
615 wrl(ep, REG_RXDENQ, RX_QUEUE_ENTRIES);
616 wrl(ep, REG_RXSTSENQ, RX_QUEUE_ENTRIES);
617
618 wrb(ep, REG_INDAD0, dev->dev_addr[0]);
619 wrb(ep, REG_INDAD1, dev->dev_addr[1]);
620 wrb(ep, REG_INDAD2, dev->dev_addr[2]);
621 wrb(ep, REG_INDAD3, dev->dev_addr[3]);
622 wrb(ep, REG_INDAD4, dev->dev_addr[4]);
623 wrb(ep, REG_INDAD5, dev->dev_addr[5]);
624 wrl(ep, REG_AFP, 0);
625
626 wrl(ep, REG_MAXFRMLEN, (MAX_PKT_SIZE << 16) | MAX_PKT_SIZE);
627
628 wrl(ep, REG_RXCTL, REG_RXCTL_DEFAULT);
629 wrl(ep, REG_TXCTL, REG_TXCTL_ENABLE);
630
631 return 0;
632 }
633
634 static void ep93xx_stop_hw(struct net_device *dev)
635 {
636 struct ep93xx_priv *ep = netdev_priv(dev);
637 int i;
638
639 wrl(ep, REG_SELFCTL, REG_SELFCTL_RESET);
640 for (i = 0; i < 10; i++) {
641 if ((rdl(ep, REG_SELFCTL) & REG_SELFCTL_RESET) == 0)
642 break;
643 msleep(1);
644 }
645
646 if (i == 10)
647 pr_crit("hw failed to reset\n");
648 }
649
650 static int ep93xx_open(struct net_device *dev)
651 {
652 struct ep93xx_priv *ep = netdev_priv(dev);
653 int err;
654
655 if (ep93xx_alloc_buffers(ep))
656 return -ENOMEM;
657
658 napi_enable(&ep->napi);
659
660 if (ep93xx_start_hw(dev)) {
661 napi_disable(&ep->napi);
662 ep93xx_free_buffers(ep);
663 return -EIO;
664 }
665
666 spin_lock_init(&ep->rx_lock);
667 ep->rx_pointer = 0;
668 ep->tx_clean_pointer = 0;
669 ep->tx_pointer = 0;
670 spin_lock_init(&ep->tx_pending_lock);
671 ep->tx_pending = 0;
672
673 err = request_irq(ep->irq, ep93xx_irq, IRQF_SHARED, dev->name, dev);
674 if (err) {
675 napi_disable(&ep->napi);
676 ep93xx_stop_hw(dev);
677 ep93xx_free_buffers(ep);
678 return err;
679 }
680
681 wrl(ep, REG_GIINTMSK, REG_GIINTMSK_ENABLE);
682
683 netif_start_queue(dev);
684
685 return 0;
686 }
687
688 static int ep93xx_close(struct net_device *dev)
689 {
690 struct ep93xx_priv *ep = netdev_priv(dev);
691
692 napi_disable(&ep->napi);
693 netif_stop_queue(dev);
694
695 wrl(ep, REG_GIINTMSK, 0);
696 free_irq(ep->irq, dev);
697 ep93xx_stop_hw(dev);
698 ep93xx_free_buffers(ep);
699
700 return 0;
701 }
702
703 static int ep93xx_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
704 {
705 struct ep93xx_priv *ep = netdev_priv(dev);
706 struct mii_ioctl_data *data = if_mii(ifr);
707
708 return generic_mii_ioctl(&ep->mii, data, cmd, NULL);
709 }
710
711 static void ep93xx_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
712 {
713 strcpy(info->driver, DRV_MODULE_NAME);
714 strcpy(info->version, DRV_MODULE_VERSION);
715 }
716
717 static int ep93xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
718 {
719 struct ep93xx_priv *ep = netdev_priv(dev);
720 return mii_ethtool_gset(&ep->mii, cmd);
721 }
722
723 static int ep93xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
724 {
725 struct ep93xx_priv *ep = netdev_priv(dev);
726 return mii_ethtool_sset(&ep->mii, cmd);
727 }
728
729 static int ep93xx_nway_reset(struct net_device *dev)
730 {
731 struct ep93xx_priv *ep = netdev_priv(dev);
732 return mii_nway_restart(&ep->mii);
733 }
734
735 static u32 ep93xx_get_link(struct net_device *dev)
736 {
737 struct ep93xx_priv *ep = netdev_priv(dev);
738 return mii_link_ok(&ep->mii);
739 }
740
741 static const struct ethtool_ops ep93xx_ethtool_ops = {
742 .get_drvinfo = ep93xx_get_drvinfo,
743 .get_settings = ep93xx_get_settings,
744 .set_settings = ep93xx_set_settings,
745 .nway_reset = ep93xx_nway_reset,
746 .get_link = ep93xx_get_link,
747 };
748
749 static const struct net_device_ops ep93xx_netdev_ops = {
750 .ndo_open = ep93xx_open,
751 .ndo_stop = ep93xx_close,
752 .ndo_start_xmit = ep93xx_xmit,
753 .ndo_do_ioctl = ep93xx_ioctl,
754 .ndo_validate_addr = eth_validate_addr,
755 .ndo_change_mtu = eth_change_mtu,
756 .ndo_set_mac_address = eth_mac_addr,
757 };
758
759 static struct net_device *ep93xx_dev_alloc(struct ep93xx_eth_data *data)
760 {
761 struct net_device *dev;
762
763 dev = alloc_etherdev(sizeof(struct ep93xx_priv));
764 if (dev == NULL)
765 return NULL;
766
767 memcpy(dev->dev_addr, data->dev_addr, ETH_ALEN);
768
769 dev->ethtool_ops = &ep93xx_ethtool_ops;
770 dev->netdev_ops = &ep93xx_netdev_ops;
771
772 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM;
773
774 return dev;
775 }
776
777
778 static int ep93xx_eth_remove(struct platform_device *pdev)
779 {
780 struct net_device *dev;
781 struct ep93xx_priv *ep;
782
783 dev = platform_get_drvdata(pdev);
784 if (dev == NULL)
785 return 0;
786 platform_set_drvdata(pdev, NULL);
787
788 ep = netdev_priv(dev);
789
790 /* @@@ Force down. */
791 unregister_netdev(dev);
792 ep93xx_free_buffers(ep);
793
794 if (ep->base_addr != NULL)
795 iounmap(ep->base_addr);
796
797 if (ep->res != NULL) {
798 release_resource(ep->res);
799 kfree(ep->res);
800 }
801
802 free_netdev(dev);
803
804 return 0;
805 }
806
807 static int ep93xx_eth_probe(struct platform_device *pdev)
808 {
809 struct ep93xx_eth_data *data;
810 struct net_device *dev;
811 struct ep93xx_priv *ep;
812 struct resource *mem;
813 int irq;
814 int err;
815
816 if (pdev == NULL)
817 return -ENODEV;
818 data = pdev->dev.platform_data;
819
820 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
821 irq = platform_get_irq(pdev, 0);
822 if (!mem || irq < 0)
823 return -ENXIO;
824
825 dev = ep93xx_dev_alloc(data);
826 if (dev == NULL) {
827 err = -ENOMEM;
828 goto err_out;
829 }
830 ep = netdev_priv(dev);
831 ep->dev = dev;
832 netif_napi_add(dev, &ep->napi, ep93xx_poll, 64);
833
834 platform_set_drvdata(pdev, dev);
835
836 ep->res = request_mem_region(mem->start, resource_size(mem),
837 dev_name(&pdev->dev));
838 if (ep->res == NULL) {
839 dev_err(&pdev->dev, "Could not reserve memory region\n");
840 err = -ENOMEM;
841 goto err_out;
842 }
843
844 ep->base_addr = ioremap(mem->start, resource_size(mem));
845 if (ep->base_addr == NULL) {
846 dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n");
847 err = -EIO;
848 goto err_out;
849 }
850 ep->irq = irq;
851
852 ep->mii.phy_id = data->phy_id;
853 ep->mii.phy_id_mask = 0x1f;
854 ep->mii.reg_num_mask = 0x1f;
855 ep->mii.dev = dev;
856 ep->mii.mdio_read = ep93xx_mdio_read;
857 ep->mii.mdio_write = ep93xx_mdio_write;
858 ep->mdc_divisor = 40; /* Max HCLK 100 MHz, min MDIO clk 2.5 MHz. */
859
860 if (is_zero_ether_addr(dev->dev_addr))
861 random_ether_addr(dev->dev_addr);
862
863 err = register_netdev(dev);
864 if (err) {
865 dev_err(&pdev->dev, "Failed to register netdev\n");
866 goto err_out;
867 }
868
869 printk(KERN_INFO "%s: ep93xx on-chip ethernet, IRQ %d, %pM\n",
870 dev->name, ep->irq, dev->dev_addr);
871
872 return 0;
873
874 err_out:
875 ep93xx_eth_remove(pdev);
876 return err;
877 }
878
879
880 static struct platform_driver ep93xx_eth_driver = {
881 .probe = ep93xx_eth_probe,
882 .remove = ep93xx_eth_remove,
883 .driver = {
884 .name = "ep93xx-eth",
885 .owner = THIS_MODULE,
886 },
887 };
888
889 static int __init ep93xx_eth_init_module(void)
890 {
891 printk(KERN_INFO DRV_MODULE_NAME " version " DRV_MODULE_VERSION " loading\n");
892 return platform_driver_register(&ep93xx_eth_driver);
893 }
894
895 static void __exit ep93xx_eth_cleanup_module(void)
896 {
897 platform_driver_unregister(&ep93xx_eth_driver);
898 }
899
900 module_init(ep93xx_eth_init_module);
901 module_exit(ep93xx_eth_cleanup_module);
902 MODULE_LICENSE("GPL");
903 MODULE_ALIAS("platform:ep93xx-eth");
Linux with added FPC-III support