drivers/gpu/ipu-v3/ipu-dc.c

   1 /*
   2  * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
   3  * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2 of the License, or (at your
   8  * option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  12  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * for more details.
  14  */
  15
  16 #include <linux/export.h>
  17 #include <linux/module.h>
  18 #include <linux/types.h>
  19 #include <linux/errno.h>
  20 #include <linux/delay.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/io.h>
  23
  24 #include <video/imx-ipu-v3.h>
  25 #include "ipu-prv.h"
  26
  27 #define DC_MAP_CONF_PTR(n)      (0x108 + ((n) & ~0x1) * 2)
  28 #define DC_MAP_CONF_VAL(n)      (0x144 + ((n) & ~0x1) * 2)
  29
  30 #define DC_EVT_NF               0
  31 #define DC_EVT_NL               1
  32 #define DC_EVT_EOF              2
  33 #define DC_EVT_NFIELD           3
  34 #define DC_EVT_EOL              4
  35 #define DC_EVT_EOFIELD          5
  36 #define DC_EVT_NEW_ADDR         6
  37 #define DC_EVT_NEW_CHAN         7
  38 #define DC_EVT_NEW_DATA         8
  39
  40 #define DC_EVT_NEW_ADDR_W_0     0
  41 #define DC_EVT_NEW_ADDR_W_1     1
  42 #define DC_EVT_NEW_CHAN_W_0     2
  43 #define DC_EVT_NEW_CHAN_W_1     3
  44 #define DC_EVT_NEW_DATA_W_0     4
  45 #define DC_EVT_NEW_DATA_W_1     5
  46 #define DC_EVT_NEW_ADDR_R_0     6
  47 #define DC_EVT_NEW_ADDR_R_1     7
  48 #define DC_EVT_NEW_CHAN_R_0     8
  49 #define DC_EVT_NEW_CHAN_R_1     9
  50 #define DC_EVT_NEW_DATA_R_0     10
  51 #define DC_EVT_NEW_DATA_R_1     11
  52
  53 #define DC_WR_CH_CONF           0x0
  54 #define DC_WR_CH_ADDR           0x4
  55 #define DC_RL_CH(evt)           (8 + ((evt) & ~0x1) * 2)
  56
  57 #define DC_GEN                  0xd4
  58 #define DC_DISP_CONF1(disp)     (0xd8 + (disp) * 4)
  59 #define DC_DISP_CONF2(disp)     (0xe8 + (disp) * 4)
  60 #define DC_STAT                 0x1c8
  61
  62 #define WROD(lf)                (0x18 | ((lf) << 1))
  63 #define WRG                     0x01
  64 #define WCLK                    0xc9
  65
  66 #define SYNC_WAVE 0
  67 #define NULL_WAVE (-1)
  68
  69 #define DC_GEN_SYNC_1_6_SYNC    (2 << 1)
  70 #define DC_GEN_SYNC_PRIORITY_1  (1 << 7)
  71
  72 #define DC_WR_CH_CONF_WORD_SIZE_8               (0 << 0)
  73 #define DC_WR_CH_CONF_WORD_SIZE_16              (1 << 0)
  74 #define DC_WR_CH_CONF_WORD_SIZE_24              (2 << 0)
  75 #define DC_WR_CH_CONF_WORD_SIZE_32              (3 << 0)
  76 #define DC_WR_CH_CONF_DISP_ID_PARALLEL(i)       (((i) & 0x1) << 3)
  77 #define DC_WR_CH_CONF_DISP_ID_SERIAL            (2 << 3)
  78 #define DC_WR_CH_CONF_DISP_ID_ASYNC             (3 << 4)
  79 #define DC_WR_CH_CONF_FIELD_MODE                (1 << 9)
  80 #define DC_WR_CH_CONF_PROG_TYPE_NORMAL          (4 << 5)
  81 #define DC_WR_CH_CONF_PROG_TYPE_MASK            (7 << 5)
  82 #define DC_WR_CH_CONF_PROG_DI_ID                (1 << 2)
  83 #define DC_WR_CH_CONF_PROG_DISP_ID(i)           (((i) & 0x1) << 3)
  84
  85 #define IPU_DC_NUM_CHANNELS     10
  86
  87 struct ipu_dc_priv;
  88
  89 enum ipu_dc_map {
  90         IPU_DC_MAP_RGB24,
  91         IPU_DC_MAP_RGB565,
  92         IPU_DC_MAP_GBR24, /* TVEv2 */
  93         IPU_DC_MAP_BGR666,
  94         IPU_DC_MAP_LVDS666,
  95         IPU_DC_MAP_BGR24,
  96 };
  97
  98 struct ipu_dc {
  99         /* The display interface number assigned to this dc channel */
 100         unsigned int            di;
 101         void __iomem            *base;
 102         struct ipu_dc_priv      *priv;
 103         int                     chno;
 104         bool                    in_use;
 105 };
 106
 107 struct ipu_dc_priv {
 108         void __iomem            *dc_reg;
 109         void __iomem            *dc_tmpl_reg;
 110         struct ipu_soc          *ipu;
 111         struct device           *dev;
 112         struct ipu_dc           channels[IPU_DC_NUM_CHANNELS];
 113         struct mutex            mutex;
 114         struct completion       comp;
 115         int                     use_count;
 116 };
 117
 118 static void dc_link_event(struct ipu_dc *dc, int event, int addr, int priority)
 119 {
 120         u32 reg;
 121
 122         reg = readl(dc->base + DC_RL_CH(event));
 123         reg &= ~(0xffff << (16 * (event & 0x1)));
 124         reg |= ((addr << 8) | priority) << (16 * (event & 0x1));
 125         writel(reg, dc->base + DC_RL_CH(event));
 126 }
 127
 128 static void dc_write_tmpl(struct ipu_dc *dc, int word, u32 opcode, u32 operand,
 129                 int map, int wave, int glue, int sync, int stop)
 130 {
 131         struct ipu_dc_priv *priv = dc->priv;
 132         u32 reg1, reg2;
 133
 134         if (opcode == WCLK) {
 135                 reg1 = (operand << 20) & 0xfff00000;
 136                 reg2 = operand >> 12 | opcode << 1 | stop << 9;
 137         } else if (opcode == WRG) {
 138                 reg1 = sync | glue << 4 | ++wave << 11 | ((operand << 15) & 0xffff8000);
 139                 reg2 = operand >> 17 | opcode << 7 | stop << 9;
 140         } else {
 141                 reg1 = sync | glue << 4 | ++wave << 11 | ++map << 15 | ((operand << 20) & 0xfff00000);
 142                 reg2 = operand >> 12 | opcode << 4 | stop << 9;
 143         }
 144         writel(reg1, priv->dc_tmpl_reg + word * 8);
 145         writel(reg2, priv->dc_tmpl_reg + word * 8 + 4);
 146 }
 147
 148 static int ipu_bus_format_to_map(u32 fmt)
 149 {
 150         switch (fmt) {
 151         default:
 152                 WARN_ON(1);
 153                 /* fall-through */
 154         case MEDIA_BUS_FMT_RGB888_1X24:
 155                 return IPU_DC_MAP_RGB24;
 156         case MEDIA_BUS_FMT_RGB565_1X16:
 157                 return IPU_DC_MAP_RGB565;
 158         case MEDIA_BUS_FMT_GBR888_1X24:
 159                 return IPU_DC_MAP_GBR24;
 160         case MEDIA_BUS_FMT_RGB666_1X18:
 161                 return IPU_DC_MAP_BGR666;
 162         case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
 163                 return IPU_DC_MAP_LVDS666;
 164         case MEDIA_BUS_FMT_BGR888_1X24:
 165                 return IPU_DC_MAP_BGR24;
 166         }
 167 }
 168
 169 int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
 170                 u32 bus_format, u32 width)
 171 {
 172         struct ipu_dc_priv *priv = dc->priv;
 173         int addr, sync;
 174         u32 reg = 0;
 175         int map;
 176
 177         dc->di = ipu_di_get_num(di);
 178
 179         map = ipu_bus_format_to_map(bus_format);
 180
 181         /*
 182          * In interlaced mode we need more counters to create the asymmetric
 183          * per-field VSYNC signals. The pixel active signal synchronising DC
 184          * to DI moves to signal generator #6 (see ipu-di.c). In progressive
 185          * mode counter #5 is used.
 186          */
 187         sync = interlaced ? 6 : 5;
 188
 189         /* Reserve 5 microcode template words for each DI */
 190         if (dc->di)
 191                 addr = 5;
 192         else
 193                 addr = 0;
 194
 195         if (interlaced) {
 196                 dc_link_event(dc, DC_EVT_NL, addr, 3);
 197                 dc_link_event(dc, DC_EVT_EOL, addr, 2);
 198                 dc_link_event(dc, DC_EVT_NEW_DATA, addr, 1);
 199
 200                 /* Init template microcode */
 201                 dc_write_tmpl(dc, addr, WROD(0), 0, map, SYNC_WAVE, 0, sync, 1);
 202         } else {
 203                 dc_link_event(dc, DC_EVT_NL, addr + 2, 3);
 204                 dc_link_event(dc, DC_EVT_EOL, addr + 3, 2);
 205                 dc_link_event(dc, DC_EVT_NEW_DATA, addr + 1, 1);
 206
 207                 /* Init template microcode */
 208                 dc_write_tmpl(dc, addr + 2, WROD(0), 0, map, SYNC_WAVE, 8, sync, 1);
 209                 dc_write_tmpl(dc, addr + 3, WROD(0), 0, map, SYNC_WAVE, 4, sync, 0);
 210                 dc_write_tmpl(dc, addr + 4, WRG, 0, map, NULL_WAVE, 0, 0, 1);
 211                 dc_write_tmpl(dc, addr + 1, WROD(0), 0, map, SYNC_WAVE, 0, sync, 1);
 212         }
 213
 214         dc_link_event(dc, DC_EVT_NF, 0, 0);
 215         dc_link_event(dc, DC_EVT_NFIELD, 0, 0);
 216         dc_link_event(dc, DC_EVT_EOF, 0, 0);
 217         dc_link_event(dc, DC_EVT_EOFIELD, 0, 0);
 218         dc_link_event(dc, DC_EVT_NEW_CHAN, 0, 0);
 219         dc_link_event(dc, DC_EVT_NEW_ADDR, 0, 0);
 220
 221         reg = readl(dc->base + DC_WR_CH_CONF);
 222         if (interlaced)
 223                 reg |= DC_WR_CH_CONF_FIELD_MODE;
 224         else
 225                 reg &= ~DC_WR_CH_CONF_FIELD_MODE;
 226         writel(reg, dc->base + DC_WR_CH_CONF);
 227
 228         writel(0x0, dc->base + DC_WR_CH_ADDR);
 229         writel(width, priv->dc_reg + DC_DISP_CONF2(dc->di));
 230
 231         return 0;
 232 }
 233 EXPORT_SYMBOL_GPL(ipu_dc_init_sync);
 234
 235 void ipu_dc_enable(struct ipu_soc *ipu)
 236 {
 237         struct ipu_dc_priv *priv = ipu->dc_priv;
 238
 239         mutex_lock(&priv->mutex);
 240
 241         if (!priv->use_count)
 242                 ipu_module_enable(priv->ipu, IPU_CONF_DC_EN);
 243
 244         priv->use_count++;
 245
 246         mutex_unlock(&priv->mutex);
 247 }
 248 EXPORT_SYMBOL_GPL(ipu_dc_enable);
 249
 250 void ipu_dc_enable_channel(struct ipu_dc *dc)
 251 {
 252         u32 reg;
 253
 254         reg = readl(dc->base + DC_WR_CH_CONF);
 255         reg |= DC_WR_CH_CONF_PROG_TYPE_NORMAL;
 256         writel(reg, dc->base + DC_WR_CH_CONF);
 257 }
 258 EXPORT_SYMBOL_GPL(ipu_dc_enable_channel);
 259
 260 void ipu_dc_disable_channel(struct ipu_dc *dc)
 261 {
 262         u32 val;
 263
 264         val = readl(dc->base + DC_WR_CH_CONF);
 265         val &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
 266         writel(val, dc->base + DC_WR_CH_CONF);
 267 }
 268 EXPORT_SYMBOL_GPL(ipu_dc_disable_channel);
 269
 270 void ipu_dc_disable(struct ipu_soc *ipu)
 271 {
 272         struct ipu_dc_priv *priv = ipu->dc_priv;
 273
 274         mutex_lock(&priv->mutex);
 275
 276         priv->use_count--;
 277         if (!priv->use_count)
 278                 ipu_module_disable(priv->ipu, IPU_CONF_DC_EN);
 279
 280         if (priv->use_count < 0)
 281                 priv->use_count = 0;
 282
 283         mutex_unlock(&priv->mutex);
 284 }
 285 EXPORT_SYMBOL_GPL(ipu_dc_disable);
 286
 287 static void ipu_dc_map_config(struct ipu_dc_priv *priv, enum ipu_dc_map map,
 288                 int byte_num, int offset, int mask)
 289 {
 290         int ptr = map * 3 + byte_num;
 291         u32 reg;
 292
 293         reg = readl(priv->dc_reg + DC_MAP_CONF_VAL(ptr));
 294         reg &= ~(0xffff << (16 * (ptr & 0x1)));
 295         reg |= ((offset << 8) | mask) << (16 * (ptr & 0x1));
 296         writel(reg, priv->dc_reg + DC_MAP_CONF_VAL(ptr));
 297
 298         reg = readl(priv->dc_reg + DC_MAP_CONF_PTR(map));
 299         reg &= ~(0x1f << ((16 * (map & 0x1)) + (5 * byte_num)));
 300         reg |= ptr << ((16 * (map & 0x1)) + (5 * byte_num));
 301         writel(reg, priv->dc_reg + DC_MAP_CONF_PTR(map));
 302 }
 303
 304 static void ipu_dc_map_clear(struct ipu_dc_priv *priv, int map)
 305 {
 306         u32 reg = readl(priv->dc_reg + DC_MAP_CONF_PTR(map));
 307
 308         writel(reg & ~(0xffff << (16 * (map & 0x1))),
 309                      priv->dc_reg + DC_MAP_CONF_PTR(map));
 310 }
 311
 312 struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel)
 313 {
 314         struct ipu_dc_priv *priv = ipu->dc_priv;
 315         struct ipu_dc *dc;
 316
 317         if (channel >= IPU_DC_NUM_CHANNELS)
 318                 return ERR_PTR(-ENODEV);
 319
 320         dc = &priv->channels[channel];
 321
 322         mutex_lock(&priv->mutex);
 323
 324         if (dc->in_use) {
 325                 mutex_unlock(&priv->mutex);
 326                 return ERR_PTR(-EBUSY);
 327         }
 328
 329         dc->in_use = true;
 330
 331         mutex_unlock(&priv->mutex);
 332
 333         return dc;
 334 }
 335 EXPORT_SYMBOL_GPL(ipu_dc_get);
 336
 337 void ipu_dc_put(struct ipu_dc *dc)
 338 {
 339         struct ipu_dc_priv *priv = dc->priv;
 340
 341         mutex_lock(&priv->mutex);
 342         dc->in_use = false;
 343         mutex_unlock(&priv->mutex);
 344 }
 345 EXPORT_SYMBOL_GPL(ipu_dc_put);
 346
 347 int ipu_dc_init(struct ipu_soc *ipu, struct device *dev,
 348                 unsigned long base, unsigned long template_base)
 349 {
 350         struct ipu_dc_priv *priv;
 351         static int channel_offsets[] = { 0, 0x1c, 0x38, 0x54, 0x58, 0x5c,
 352                 0x78, 0, 0x94, 0xb4};
 353         int i;
 354
 355         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 356         if (!priv)
 357                 return -ENOMEM;
 358
 359         mutex_init(&priv->mutex);
 360
 361         priv->dev = dev;
 362         priv->ipu = ipu;
 363         priv->dc_reg = devm_ioremap(dev, base, PAGE_SIZE);
 364         priv->dc_tmpl_reg = devm_ioremap(dev, template_base, PAGE_SIZE);
 365         if (!priv->dc_reg || !priv->dc_tmpl_reg)
 366                 return -ENOMEM;
 367
 368         for (i = 0; i < IPU_DC_NUM_CHANNELS; i++) {
 369                 priv->channels[i].chno = i;
 370                 priv->channels[i].priv = priv;
 371                 priv->channels[i].base = priv->dc_reg + channel_offsets[i];
 372         }
 373
 374         writel(DC_WR_CH_CONF_WORD_SIZE_24 | DC_WR_CH_CONF_DISP_ID_PARALLEL(1) |
 375                         DC_WR_CH_CONF_PROG_DI_ID,
 376                         priv->channels[1].base + DC_WR_CH_CONF);
 377         writel(DC_WR_CH_CONF_WORD_SIZE_24 | DC_WR_CH_CONF_DISP_ID_PARALLEL(0),
 378                         priv->channels[5].base + DC_WR_CH_CONF);
 379
 380         writel(DC_GEN_SYNC_1_6_SYNC | DC_GEN_SYNC_PRIORITY_1,
 381                 priv->dc_reg + DC_GEN);
 382
 383         ipu->dc_priv = priv;
 384
 385         dev_dbg(dev, "DC base: 0x%08lx template base: 0x%08lx\n",
 386                         base, template_base);
 387
 388         /* rgb24 */
 389         ipu_dc_map_clear(priv, IPU_DC_MAP_RGB24);
 390         ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 0, 7, 0xff); /* blue */
 391         ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 1, 15, 0xff); /* green */
 392         ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 2, 23, 0xff); /* red */
 393
 394         /* rgb565 */
 395         ipu_dc_map_clear(priv, IPU_DC_MAP_RGB565);
 396         ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 0, 4, 0xf8); /* blue */
 397         ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 1, 10, 0xfc); /* green */
 398         ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 2, 15, 0xf8); /* red */
 399
 400         /* gbr24 */
 401         ipu_dc_map_clear(priv, IPU_DC_MAP_GBR24);
 402         ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 2, 15, 0xff); /* green */
 403         ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 1, 7, 0xff); /* blue */
 404         ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 0, 23, 0xff); /* red */
 405
 406         /* bgr666 */
 407         ipu_dc_map_clear(priv, IPU_DC_MAP_BGR666);
 408         ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 0, 5, 0xfc); /* blue */
 409         ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 1, 11, 0xfc); /* green */
 410         ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 2, 17, 0xfc); /* red */
 411
 412         /* lvds666 */
 413         ipu_dc_map_clear(priv, IPU_DC_MAP_LVDS666);
 414         ipu_dc_map_config(priv, IPU_DC_MAP_LVDS666, 0, 5, 0xfc); /* blue */
 415         ipu_dc_map_config(priv, IPU_DC_MAP_LVDS666, 1, 13, 0xfc); /* green */
 416         ipu_dc_map_config(priv, IPU_DC_MAP_LVDS666, 2, 21, 0xfc); /* red */
 417
 418         /* bgr24 */
 419         ipu_dc_map_clear(priv, IPU_DC_MAP_BGR24);
 420         ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 2, 7, 0xff); /* red */
 421         ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 1, 15, 0xff); /* green */
 422         ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 0, 23, 0xff); /* blue */
 423
 424         return 0;
 425 }
 426
 427 void ipu_dc_exit(struct ipu_soc *ipu)
 428 {
 429 }