drivers/iommu/intel-svm.c

   1 /*
   2  * Copyright © 2015 Intel Corporation.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * Authors: David Woodhouse <dwmw2@infradead.org>
  14  */
  15
  16 #include <linux/intel-iommu.h>
  17 #include <linux/mmu_notifier.h>
  18 #include <linux/sched.h>
  19 #include <linux/sched/mm.h>
  20 #include <linux/slab.h>
  21 #include <linux/intel-svm.h>
  22 #include <linux/rculist.h>
  23 #include <linux/pci.h>
  24 #include <linux/pci-ats.h>
  25 #include <linux/dmar.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/mm_types.h>
  28 #include <asm/page.h>
  29
  30 #define PASID_ENTRY_P           BIT_ULL(0)
  31 #define PASID_ENTRY_FLPM_5LP    BIT_ULL(9)
  32 #define PASID_ENTRY_SRE         BIT_ULL(11)
  33
  34 static irqreturn_t prq_event_thread(int irq, void *d);
  35
  36 struct pasid_entry {
  37         u64 val;
  38 };
  39
  40 struct pasid_state_entry {
  41         u64 val;
  42 };
  43
  44 int intel_svm_alloc_pasid_tables(struct intel_iommu *iommu)
  45 {
  46         struct page *pages;
  47         int order;
  48
  49         if (cpu_feature_enabled(X86_FEATURE_GBPAGES) &&
  50                         !cap_fl1gp_support(iommu->cap))
  51                 return -EINVAL;
  52
  53         if (cpu_feature_enabled(X86_FEATURE_LA57) &&
  54                         !cap_5lp_support(iommu->cap))
  55                 return -EINVAL;
  56
  57         /* Start at 2 because it's defined as 2^(1+PSS) */
  58         iommu->pasid_max = 2 << ecap_pss(iommu->ecap);
  59
  60         /* Eventually I'm promised we will get a multi-level PASID table
  61          * and it won't have to be physically contiguous. Until then,
  62          * limit the size because 8MiB contiguous allocations can be hard
  63          * to come by. The limit of 0x20000, which is 1MiB for each of
  64          * the PASID and PASID-state tables, is somewhat arbitrary. */
  65         if (iommu->pasid_max > 0x20000)
  66                 iommu->pasid_max = 0x20000;
  67
  68         order = get_order(sizeof(struct pasid_entry) * iommu->pasid_max);
  69         pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, order);
  70         if (!pages) {
  71                 pr_warn("IOMMU: %s: Failed to allocate PASID table\n",
  72                         iommu->name);
  73                 return -ENOMEM;
  74         }
  75         iommu->pasid_table = page_address(pages);
  76         pr_info("%s: Allocated order %d PASID table.\n", iommu->name, order);
  77
  78         if (ecap_dis(iommu->ecap)) {
  79                 /* Just making it explicit... */
  80                 BUILD_BUG_ON(sizeof(struct pasid_entry) != sizeof(struct pasid_state_entry));
  81                 pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, order);
  82                 if (pages)
  83                         iommu->pasid_state_table = page_address(pages);
  84                 else
  85                         pr_warn("IOMMU: %s: Failed to allocate PASID state table\n",
  86                                 iommu->name);
  87         }
  88
  89         idr_init(&iommu->pasid_idr);
  90
  91         return 0;
  92 }
  93
  94 int intel_svm_free_pasid_tables(struct intel_iommu *iommu)
  95 {
  96         int order = get_order(sizeof(struct pasid_entry) * iommu->pasid_max);
  97
  98         if (iommu->pasid_table) {
  99                 free_pages((unsigned long)iommu->pasid_table, order);
 100                 iommu->pasid_table = NULL;
 101         }
 102         if (iommu->pasid_state_table) {
 103                 free_pages((unsigned long)iommu->pasid_state_table, order);
 104                 iommu->pasid_state_table = NULL;
 105         }
 106         idr_destroy(&iommu->pasid_idr);
 107         return 0;
 108 }
 109
 110 #define PRQ_ORDER 0
 111
 112 int intel_svm_enable_prq(struct intel_iommu *iommu)
 113 {
 114         struct page *pages;
 115         int irq, ret;
 116
 117         pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, PRQ_ORDER);
 118         if (!pages) {
 119                 pr_warn("IOMMU: %s: Failed to allocate page request queue\n",
 120                         iommu->name);
 121                 return -ENOMEM;
 122         }
 123         iommu->prq = page_address(pages);
 124
 125         irq = dmar_alloc_hwirq(DMAR_UNITS_SUPPORTED + iommu->seq_id, iommu->node, iommu);
 126         if (irq <= 0) {
 127                 pr_err("IOMMU: %s: Failed to create IRQ vector for page request queue\n",
 128                        iommu->name);
 129                 ret = -EINVAL;
 130         err:
 131                 free_pages((unsigned long)iommu->prq, PRQ_ORDER);
 132                 iommu->prq = NULL;
 133                 return ret;
 134         }
 135         iommu->pr_irq = irq;
 136
 137         snprintf(iommu->prq_name, sizeof(iommu->prq_name), "dmar%d-prq", iommu->seq_id);
 138
 139         ret = request_threaded_irq(irq, NULL, prq_event_thread, IRQF_ONESHOT,
 140                                    iommu->prq_name, iommu);
 141         if (ret) {
 142                 pr_err("IOMMU: %s: Failed to request IRQ for page request queue\n",
 143                        iommu->name);
 144                 dmar_free_hwirq(irq);
 145                 iommu->pr_irq = 0;
 146                 goto err;
 147         }
 148         dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL);
 149         dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL);
 150         dmar_writeq(iommu->reg + DMAR_PQA_REG, virt_to_phys(iommu->prq) | PRQ_ORDER);
 151
 152         return 0;
 153 }
 154
 155 int intel_svm_finish_prq(struct intel_iommu *iommu)
 156 {
 157         dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL);
 158         dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL);
 159         dmar_writeq(iommu->reg + DMAR_PQA_REG, 0ULL);
 160
 161         if (iommu->pr_irq) {
 162                 free_irq(iommu->pr_irq, iommu);
 163                 dmar_free_hwirq(iommu->pr_irq);
 164                 iommu->pr_irq = 0;
 165         }
 166
 167         free_pages((unsigned long)iommu->prq, PRQ_ORDER);
 168         iommu->prq = NULL;
 169
 170         return 0;
 171 }
 172
 173 static void intel_flush_svm_range_dev (struct intel_svm *svm, struct intel_svm_dev *sdev,
 174                                        unsigned long address, unsigned long pages, int ih, int gl)
 175 {
 176         struct qi_desc desc;
 177
 178         if (pages == -1) {
 179                 /* For global kernel pages we have to flush them in *all* PASIDs
 180                  * because that's the only option the hardware gives us. Despite
 181                  * the fact that they are actually only accessible through one. */
 182                 if (gl)
 183                         desc.low = QI_EIOTLB_PASID(svm->pasid) | QI_EIOTLB_DID(sdev->did) |
 184                                 QI_EIOTLB_GRAN(QI_GRAN_ALL_ALL) | QI_EIOTLB_TYPE;
 185                 else
 186                         desc.low = QI_EIOTLB_PASID(svm->pasid) | QI_EIOTLB_DID(sdev->did) |
 187                                 QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) | QI_EIOTLB_TYPE;
 188                 desc.high = 0;
 189         } else {
 190                 int mask = ilog2(__roundup_pow_of_two(pages));
 191
 192                 desc.low = QI_EIOTLB_PASID(svm->pasid) | QI_EIOTLB_DID(sdev->did) |
 193                         QI_EIOTLB_GRAN(QI_GRAN_PSI_PASID) | QI_EIOTLB_TYPE;
 194                 desc.high = QI_EIOTLB_ADDR(address) | QI_EIOTLB_GL(gl) |
 195                         QI_EIOTLB_IH(ih) | QI_EIOTLB_AM(mask);
 196         }
 197         qi_submit_sync(&desc, svm->iommu);
 198
 199         if (sdev->dev_iotlb) {
 200                 desc.low = QI_DEV_EIOTLB_PASID(svm->pasid) | QI_DEV_EIOTLB_SID(sdev->sid) |
 201                         QI_DEV_EIOTLB_QDEP(sdev->qdep) | QI_DEIOTLB_TYPE;
 202                 if (pages == -1) {
 203                         desc.high = QI_DEV_EIOTLB_ADDR(-1ULL >> 1) | QI_DEV_EIOTLB_SIZE;
 204                 } else if (pages > 1) {
 205                         /* The least significant zero bit indicates the size. So,
 206                          * for example, an "address" value of 0x12345f000 will
 207                          * flush from 0x123440000 to 0x12347ffff (256KiB). */
 208                         unsigned long last = address + ((unsigned long)(pages - 1) << VTD_PAGE_SHIFT);
 209                         unsigned long mask = __rounddown_pow_of_two(address ^ last);
 210
 211                         desc.high = QI_DEV_EIOTLB_ADDR((address & ~mask) | (mask - 1)) | QI_DEV_EIOTLB_SIZE;
 212                 } else {
 213                         desc.high = QI_DEV_EIOTLB_ADDR(address);
 214                 }
 215                 qi_submit_sync(&desc, svm->iommu);
 216         }
 217 }
 218
 219 static void intel_flush_svm_range(struct intel_svm *svm, unsigned long address,
 220                                   unsigned long pages, int ih, int gl)
 221 {
 222         struct intel_svm_dev *sdev;
 223
 224         /* Try deferred invalidate if available */
 225         if (svm->iommu->pasid_state_table &&
 226             !cmpxchg64(&svm->iommu->pasid_state_table[svm->pasid].val, 0, 1ULL << 63))
 227                 return;
 228
 229         rcu_read_lock();
 230         list_for_each_entry_rcu(sdev, &svm->devs, list)
 231                 intel_flush_svm_range_dev(svm, sdev, address, pages, ih, gl);
 232         rcu_read_unlock();
 233 }
 234
 235 static void intel_change_pte(struct mmu_notifier *mn, struct mm_struct *mm,
 236                              unsigned long address, pte_t pte)
 237 {
 238         struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
 239
 240         intel_flush_svm_range(svm, address, 1, 1, 0);
 241 }
 242
 243 /* Pages have been freed at this point */
 244 static void intel_invalidate_range(struct mmu_notifier *mn,
 245                                    struct mm_struct *mm,
 246                                    unsigned long start, unsigned long end)
 247 {
 248         struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
 249
 250         intel_flush_svm_range(svm, start,
 251                               (end - start + PAGE_SIZE - 1) >> VTD_PAGE_SHIFT, 0, 0);
 252 }
 253
 254
 255 static void intel_flush_pasid_dev(struct intel_svm *svm, struct intel_svm_dev *sdev, int pasid)
 256 {
 257         struct qi_desc desc;
 258
 259         desc.high = 0;
 260         desc.low = QI_PC_TYPE | QI_PC_DID(sdev->did) | QI_PC_PASID_SEL | QI_PC_PASID(pasid);
 261
 262         qi_submit_sync(&desc, svm->iommu);
 263 }
 264
 265 static void intel_mm_release(struct mmu_notifier *mn, struct mm_struct *mm)
 266 {
 267         struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
 268         struct intel_svm_dev *sdev;
 269
 270         /* This might end up being called from exit_mmap(), *before* the page
 271          * tables are cleared. And __mmu_notifier_release() will delete us from
 272          * the list of notifiers so that our invalidate_range() callback doesn't
 273          * get called when the page tables are cleared. So we need to protect
 274          * against hardware accessing those page tables.
 275          *
 276          * We do it by clearing the entry in the PASID table and then flushing
 277          * the IOTLB and the PASID table caches. This might upset hardware;
 278          * perhaps we'll want to point the PASID to a dummy PGD (like the zero
 279          * page) so that we end up taking a fault that the hardware really
 280          * *has* to handle gracefully without affecting other processes.
 281          */
 282         svm->iommu->pasid_table[svm->pasid].val = 0;
 283         wmb();
 284
 285         rcu_read_lock();
 286         list_for_each_entry_rcu(sdev, &svm->devs, list) {
 287                 intel_flush_pasid_dev(svm, sdev, svm->pasid);
 288                 intel_flush_svm_range_dev(svm, sdev, 0, -1, 0, !svm->mm);
 289         }
 290         rcu_read_unlock();
 291
 292 }
 293
 294 static const struct mmu_notifier_ops intel_mmuops = {
 295         .flags = MMU_INVALIDATE_DOES_NOT_BLOCK,
 296         .release = intel_mm_release,
 297         .change_pte = intel_change_pte,
 298         .invalidate_range = intel_invalidate_range,
 299 };
 300
 301 static DEFINE_MUTEX(pasid_mutex);
 302
 303 int intel_svm_bind_mm(struct device *dev, int *pasid, int flags, struct svm_dev_ops *ops)
 304 {
 305         struct intel_iommu *iommu = intel_svm_device_to_iommu(dev);
 306         struct intel_svm_dev *sdev;
 307         struct intel_svm *svm = NULL;
 308         struct mm_struct *mm = NULL;
 309         u64 pasid_entry_val;
 310         int pasid_max;
 311         int ret;
 312
 313         if (WARN_ON(!iommu || !iommu->pasid_table))
 314                 return -EINVAL;
 315
 316         if (dev_is_pci(dev)) {
 317                 pasid_max = pci_max_pasids(to_pci_dev(dev));
 318                 if (pasid_max < 0)
 319                         return -EINVAL;
 320         } else
 321                 pasid_max = 1 << 20;
 322
 323         if (flags & SVM_FLAG_SUPERVISOR_MODE) {
 324                 if (!ecap_srs(iommu->ecap))
 325                         return -EINVAL;
 326         } else if (pasid) {
 327                 mm = get_task_mm(current);
 328                 BUG_ON(!mm);
 329         }
 330
 331         mutex_lock(&pasid_mutex);
 332         if (pasid && !(flags & SVM_FLAG_PRIVATE_PASID)) {
 333                 int i;
 334
 335                 idr_for_each_entry(&iommu->pasid_idr, svm, i) {
 336                         if (svm->mm != mm ||
 337                             (svm->flags & SVM_FLAG_PRIVATE_PASID))
 338                                 continue;
 339
 340                         if (svm->pasid >= pasid_max) {
 341                                 dev_warn(dev,
 342                                          "Limited PASID width. Cannot use existing PASID %d\n",
 343                                          svm->pasid);
 344                                 ret = -ENOSPC;
 345                                 goto out;
 346                         }
 347
 348                         list_for_each_entry(sdev, &svm->devs, list) {
 349                                 if (dev == sdev->dev) {
 350                                         if (sdev->ops != ops) {
 351                                                 ret = -EBUSY;
 352                                                 goto out;
 353                                         }
 354                                         sdev->users++;
 355                                         goto success;
 356                                 }
 357                         }
 358
 359                         break;
 360                 }
 361         }
 362
 363         sdev = kzalloc(sizeof(*sdev), GFP_KERNEL);
 364         if (!sdev) {
 365                 ret = -ENOMEM;
 366                 goto out;
 367         }
 368         sdev->dev = dev;
 369
 370         ret = intel_iommu_enable_pasid(iommu, sdev);
 371         if (ret || !pasid) {
 372                 /* If they don't actually want to assign a PASID, this is
 373                  * just an enabling check/preparation. */
 374                 kfree(sdev);
 375                 goto out;
 376         }
 377         /* Finish the setup now we know we're keeping it */
 378         sdev->users = 1;
 379         sdev->ops = ops;
 380         init_rcu_head(&sdev->rcu);
 381
 382         if (!svm) {
 383                 svm = kzalloc(sizeof(*svm), GFP_KERNEL);
 384                 if (!svm) {
 385                         ret = -ENOMEM;
 386                         kfree(sdev);
 387                         goto out;
 388                 }
 389                 svm->iommu = iommu;
 390
 391                 if (pasid_max > iommu->pasid_max)
 392                         pasid_max = iommu->pasid_max;
 393
 394                 /* Do not use PASID 0 in caching mode (virtualised IOMMU) */
 395                 ret = idr_alloc(&iommu->pasid_idr, svm,
 396                                 !!cap_caching_mode(iommu->cap),
 397                                 pasid_max - 1, GFP_KERNEL);
 398                 if (ret < 0) {
 399                         kfree(svm);
 400                         kfree(sdev);
 401                         goto out;
 402                 }
 403                 svm->pasid = ret;
 404                 svm->notifier.ops = &intel_mmuops;
 405                 svm->mm = mm;
 406                 svm->flags = flags;
 407                 INIT_LIST_HEAD_RCU(&svm->devs);
 408                 ret = -ENOMEM;
 409                 if (mm) {
 410                         ret = mmu_notifier_register(&svm->notifier, mm);
 411                         if (ret) {
 412                                 idr_remove(&svm->iommu->pasid_idr, svm->pasid);
 413                                 kfree(svm);
 414                                 kfree(sdev);
 415                                 goto out;
 416                         }
 417                         pasid_entry_val = (u64)__pa(mm->pgd) | PASID_ENTRY_P;
 418                 } else
 419                         pasid_entry_val = (u64)__pa(init_mm.pgd) |
 420                                           PASID_ENTRY_P | PASID_ENTRY_SRE;
 421                 if (cpu_feature_enabled(X86_FEATURE_LA57))
 422                         pasid_entry_val |= PASID_ENTRY_FLPM_5LP;
 423
 424                 iommu->pasid_table[svm->pasid].val = pasid_entry_val;
 425
 426                 wmb();
 427
 428                 /*
 429                  * Flush PASID cache when a PASID table entry becomes
 430                  * present.
 431                  */
 432                 if (cap_caching_mode(iommu->cap))
 433                         intel_flush_pasid_dev(svm, sdev, svm->pasid);
 434         }
 435         list_add_rcu(&sdev->list, &svm->devs);
 436
 437  success:
 438         *pasid = svm->pasid;
 439         ret = 0;
 440  out:
 441         mutex_unlock(&pasid_mutex);
 442         if (mm)
 443                 mmput(mm);
 444         return ret;
 445 }
 446 EXPORT_SYMBOL_GPL(intel_svm_bind_mm);
 447
 448 int intel_svm_unbind_mm(struct device *dev, int pasid)
 449 {
 450         struct intel_svm_dev *sdev;
 451         struct intel_iommu *iommu;
 452         struct intel_svm *svm;
 453         int ret = -EINVAL;
 454
 455         mutex_lock(&pasid_mutex);
 456         iommu = intel_svm_device_to_iommu(dev);
 457         if (!iommu || !iommu->pasid_table)
 458                 goto out;
 459
 460         svm = idr_find(&iommu->pasid_idr, pasid);
 461         if (!svm)
 462                 goto out;
 463
 464         list_for_each_entry(sdev, &svm->devs, list) {
 465                 if (dev == sdev->dev) {
 466                         ret = 0;
 467                         sdev->users--;
 468                         if (!sdev->users) {
 469                                 list_del_rcu(&sdev->list);
 470                                 /* Flush the PASID cache and IOTLB for this device.
 471                                  * Note that we do depend on the hardware *not* using
 472                                  * the PASID any more. Just as we depend on other
 473                                  * devices never using PASIDs that they have no right
 474                                  * to use. We have a *shared* PASID table, because it's
 475                                  * large and has to be physically contiguous. So it's
 476                                  * hard to be as defensive as we might like. */
 477                                 intel_flush_pasid_dev(svm, sdev, svm->pasid);
 478                                 intel_flush_svm_range_dev(svm, sdev, 0, -1, 0, !svm->mm);
 479                                 kfree_rcu(sdev, rcu);
 480
 481                                 if (list_empty(&svm->devs)) {
 482                                         svm->iommu->pasid_table[svm->pasid].val = 0;
 483                                         wmb();
 484
 485                                         idr_remove(&svm->iommu->pasid_idr, svm->pasid);
 486                                         if (svm->mm)
 487                                                 mmu_notifier_unregister(&svm->notifier, svm->mm);
 488
 489                                         /* We mandate that no page faults may be outstanding
 490                                          * for the PASID when intel_svm_unbind_mm() is called.
 491                                          * If that is not obeyed, subtle errors will happen.
 492                                          * Let's make them less subtle... */
 493                                         memset(svm, 0x6b, sizeof(*svm));
 494                                         kfree(svm);
 495                                 }
 496                         }
 497                         break;
 498                 }
 499         }
 500  out:
 501         mutex_unlock(&pasid_mutex);
 502
 503         return ret;
 504 }
 505 EXPORT_SYMBOL_GPL(intel_svm_unbind_mm);
 506
 507 int intel_svm_is_pasid_valid(struct device *dev, int pasid)
 508 {
 509         struct intel_iommu *iommu;
 510         struct intel_svm *svm;
 511         int ret = -EINVAL;
 512
 513         mutex_lock(&pasid_mutex);
 514         iommu = intel_svm_device_to_iommu(dev);
 515         if (!iommu || !iommu->pasid_table)
 516                 goto out;
 517
 518         svm = idr_find(&iommu->pasid_idr, pasid);
 519         if (!svm)
 520                 goto out;
 521
 522         /* init_mm is used in this case */
 523         if (!svm->mm)
 524                 ret = 1;
 525         else if (atomic_read(&svm->mm->mm_users) > 0)
 526                 ret = 1;
 527         else
 528                 ret = 0;
 529
 530  out:
 531         mutex_unlock(&pasid_mutex);
 532
 533         return ret;
 534 }
 535 EXPORT_SYMBOL_GPL(intel_svm_is_pasid_valid);
 536
 537 /* Page request queue descriptor */
 538 struct page_req_dsc {
 539         u64 srr:1;
 540         u64 bof:1;
 541         u64 pasid_present:1;
 542         u64 lpig:1;
 543         u64 pasid:20;
 544         u64 bus:8;
 545         u64 private:23;
 546         u64 prg_index:9;
 547         u64 rd_req:1;
 548         u64 wr_req:1;
 549         u64 exe_req:1;
 550         u64 priv_req:1;
 551         u64 devfn:8;
 552         u64 addr:52;
 553 };
 554
 555 #define PRQ_RING_MASK ((0x1000 << PRQ_ORDER) - 0x10)
 556
 557 static bool access_error(struct vm_area_struct *vma, struct page_req_dsc *req)
 558 {
 559         unsigned long requested = 0;
 560
 561         if (req->exe_req)
 562                 requested |= VM_EXEC;
 563
 564         if (req->rd_req)
 565                 requested |= VM_READ;
 566
 567         if (req->wr_req)
 568                 requested |= VM_WRITE;
 569
 570         return (requested & ~vma->vm_flags) != 0;
 571 }
 572
 573 static bool is_canonical_address(u64 addr)
 574 {
 575         int shift = 64 - (__VIRTUAL_MASK_SHIFT + 1);
 576         long saddr = (long) addr;
 577
 578         return (((saddr << shift) >> shift) == saddr);
 579 }
 580
 581 static irqreturn_t prq_event_thread(int irq, void *d)
 582 {
 583         struct intel_iommu *iommu = d;
 584         struct intel_svm *svm = NULL;
 585         int head, tail, handled = 0;
 586
 587         /* Clear PPR bit before reading head/tail registers, to
 588          * ensure that we get a new interrupt if needed. */
 589         writel(DMA_PRS_PPR, iommu->reg + DMAR_PRS_REG);
 590
 591         tail = dmar_readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK;
 592         head = dmar_readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK;
 593         while (head != tail) {
 594                 struct intel_svm_dev *sdev;
 595                 struct vm_area_struct *vma;
 596                 struct page_req_dsc *req;
 597                 struct qi_desc resp;
 598                 int result;
 599                 vm_fault_t ret;
 600                 u64 address;
 601
 602                 handled = 1;
 603
 604                 req = &iommu->prq[head / sizeof(*req)];
 605
 606                 result = QI_RESP_FAILURE;
 607                 address = (u64)req->addr << VTD_PAGE_SHIFT;
 608                 if (!req->pasid_present) {
 609                         pr_err("%s: Page request without PASID: %08llx %08llx\n",
 610                                iommu->name, ((unsigned long long *)req)[0],
 611                                ((unsigned long long *)req)[1]);
 612                         goto bad_req;
 613                 }
 614
 615                 if (!svm || svm->pasid != req->pasid) {
 616                         rcu_read_lock();
 617                         svm = idr_find(&iommu->pasid_idr, req->pasid);
 618                         /* It *can't* go away, because the driver is not permitted
 619                          * to unbind the mm while any page faults are outstanding.
 620                          * So we only need RCU to protect the internal idr code. */
 621                         rcu_read_unlock();
 622
 623                         if (!svm) {
 624                                 pr_err("%s: Page request for invalid PASID %d: %08llx %08llx\n",
 625                                        iommu->name, req->pasid, ((unsigned long long *)req)[0],
 626                                        ((unsigned long long *)req)[1]);
 627                                 goto no_pasid;
 628                         }
 629                 }
 630
 631                 result = QI_RESP_INVALID;
 632                 /* Since we're using init_mm.pgd directly, we should never take
 633                  * any faults on kernel addresses. */
 634                 if (!svm->mm)
 635                         goto bad_req;
 636                 /* If the mm is already defunct, don't handle faults. */
 637                 if (!mmget_not_zero(svm->mm))
 638                         goto bad_req;
 639
 640                 /* If address is not canonical, return invalid response */
 641                 if (!is_canonical_address(address))
 642                         goto bad_req;
 643
 644                 down_read(&svm->mm->mmap_sem);
 645                 vma = find_extend_vma(svm->mm, address);
 646                 if (!vma || address < vma->vm_start)
 647                         goto invalid;
 648
 649                 if (access_error(vma, req))
 650                         goto invalid;
 651
 652                 ret = handle_mm_fault(vma, address,
 653                                       req->wr_req ? FAULT_FLAG_WRITE : 0);
 654                 if (ret & VM_FAULT_ERROR)
 655                         goto invalid;
 656
 657                 result = QI_RESP_SUCCESS;
 658         invalid:
 659                 up_read(&svm->mm->mmap_sem);
 660                 mmput(svm->mm);
 661         bad_req:
 662                 /* Accounting for major/minor faults? */
 663                 rcu_read_lock();
 664                 list_for_each_entry_rcu(sdev, &svm->devs, list) {
 665                         if (sdev->sid == PCI_DEVID(req->bus, req->devfn))
 666                                 break;
 667                 }
 668                 /* Other devices can go away, but the drivers are not permitted
 669                  * to unbind while any page faults might be in flight. So it's
 670                  * OK to drop the 'lock' here now we have it. */
 671                 rcu_read_unlock();
 672
 673                 if (WARN_ON(&sdev->list == &svm->devs))
 674                         sdev = NULL;
 675
 676                 if (sdev && sdev->ops && sdev->ops->fault_cb) {
 677                         int rwxp = (req->rd_req << 3) | (req->wr_req << 2) |
 678                                 (req->exe_req << 1) | (req->priv_req);
 679                         sdev->ops->fault_cb(sdev->dev, req->pasid, req->addr, req->private, rwxp, result);
 680                 }
 681                 /* We get here in the error case where the PASID lookup failed,
 682                    and these can be NULL. Do not use them below this point! */
 683                 sdev = NULL;
 684                 svm = NULL;
 685         no_pasid:
 686                 if (req->lpig) {
 687                         /* Page Group Response */
 688                         resp.low = QI_PGRP_PASID(req->pasid) |
 689                                 QI_PGRP_DID((req->bus << 8) | req->devfn) |
 690                                 QI_PGRP_PASID_P(req->pasid_present) |
 691                                 QI_PGRP_RESP_TYPE;
 692                         resp.high = QI_PGRP_IDX(req->prg_index) |
 693                                 QI_PGRP_PRIV(req->private) | QI_PGRP_RESP_CODE(result);
 694
 695                         qi_submit_sync(&resp, iommu);
 696                 } else if (req->srr) {
 697                         /* Page Stream Response */
 698                         resp.low = QI_PSTRM_IDX(req->prg_index) |
 699                                 QI_PSTRM_PRIV(req->private) | QI_PSTRM_BUS(req->bus) |
 700                                 QI_PSTRM_PASID(req->pasid) | QI_PSTRM_RESP_TYPE;
 701                         resp.high = QI_PSTRM_ADDR(address) | QI_PSTRM_DEVFN(req->devfn) |
 702                                 QI_PSTRM_RESP_CODE(result);
 703
 704                         qi_submit_sync(&resp, iommu);
 705                 }
 706
 707                 head = (head + sizeof(*req)) & PRQ_RING_MASK;
 708         }
 709
 710         dmar_writeq(iommu->reg + DMAR_PQH_REG, tail);
 711
 712         return IRQ_RETVAL(handled);
 713 }