drivers/media/platform/s5p-mfc/s5p_mfc_common.h

   1 /*
   2  * Samsung S5P Multi Format Codec v 5.0
   3  *
   4  * This file contains definitions of enums and structs used by the codec
   5  * driver.
   6  *
   7  * Copyright (C) 2011 Samsung Electronics Co., Ltd.
   8  * Kamil Debski, <k.debski@samsung.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by the
  12  * Free Software Foundation; either version 2 of the
  13  * License, or (at your option) any later version
  14  */
  15
  16 #ifndef S5P_MFC_COMMON_H_
  17 #define S5P_MFC_COMMON_H_
  18
  19 #include <linux/platform_device.h>
  20 #include <linux/videodev2.h>
  21 #include <media/v4l2-ctrls.h>
  22 #include <media/v4l2-device.h>
  23 #include <media/v4l2-ioctl.h>
  24 #include <media/videobuf2-v4l2.h>
  25 #include "regs-mfc.h"
  26 #include "regs-mfc-v8.h"
  27
  28 #define S5P_MFC_NAME            "s5p-mfc"
  29
  30 /* Definitions related to MFC memory */
  31
  32 /* Offset base used to differentiate between CAPTURE and OUTPUT
  33 *  while mmaping */
  34 #define DST_QUEUE_OFF_BASE      (1 << 30)
  35
  36 #define MFC_BANK1_ALLOC_CTX     0
  37 #define MFC_BANK2_ALLOC_CTX     1
  38
  39 #define MFC_BANK1_ALIGN_ORDER   13
  40 #define MFC_BANK2_ALIGN_ORDER   13
  41 #define MFC_BASE_ALIGN_ORDER    17
  42
  43 #define MFC_FW_MAX_VERSIONS     2
  44
  45 #include <media/videobuf2-dma-contig.h>
  46
  47 static inline dma_addr_t s5p_mfc_mem_cookie(void *a, void *b)
  48 {
  49         /* Same functionality as the vb2_dma_contig_plane_paddr */
  50         dma_addr_t *paddr = vb2_dma_contig_memops.cookie(b);
  51
  52         return *paddr;
  53 }
  54
  55 /* MFC definitions */
  56 #define MFC_MAX_EXTRA_DPB       5
  57 #define MFC_MAX_BUFFERS         32
  58 #define MFC_NUM_CONTEXTS        4
  59 /* Interrupt timeout */
  60 #define MFC_INT_TIMEOUT         2000
  61 /* Busy wait timeout */
  62 #define MFC_BW_TIMEOUT          500
  63 /* Watchdog interval */
  64 #define MFC_WATCHDOG_INTERVAL   1000
  65 /* After how many executions watchdog should assume lock up */
  66 #define MFC_WATCHDOG_CNT        10
  67 #define MFC_NO_INSTANCE_SET     -1
  68 #define MFC_ENC_CAP_PLANE_COUNT 1
  69 #define MFC_ENC_OUT_PLANE_COUNT 2
  70 #define STUFF_BYTE              4
  71 #define MFC_MAX_CTRLS           77
  72
  73 #define S5P_MFC_CODEC_NONE              -1
  74 #define S5P_MFC_CODEC_H264_DEC          0
  75 #define S5P_MFC_CODEC_H264_MVC_DEC      1
  76 #define S5P_MFC_CODEC_VC1_DEC           2
  77 #define S5P_MFC_CODEC_MPEG4_DEC         3
  78 #define S5P_MFC_CODEC_MPEG2_DEC         4
  79 #define S5P_MFC_CODEC_H263_DEC          5
  80 #define S5P_MFC_CODEC_VC1RCV_DEC        6
  81 #define S5P_MFC_CODEC_VP8_DEC           7
  82
  83 #define S5P_MFC_CODEC_H264_ENC          20
  84 #define S5P_MFC_CODEC_H264_MVC_ENC      21
  85 #define S5P_MFC_CODEC_MPEG4_ENC         22
  86 #define S5P_MFC_CODEC_H263_ENC          23
  87 #define S5P_MFC_CODEC_VP8_ENC           24
  88
  89 #define S5P_MFC_R2H_CMD_EMPTY                   0
  90 #define S5P_MFC_R2H_CMD_SYS_INIT_RET            1
  91 #define S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET       2
  92 #define S5P_MFC_R2H_CMD_SEQ_DONE_RET            3
  93 #define S5P_MFC_R2H_CMD_INIT_BUFFERS_RET        4
  94 #define S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET      6
  95 #define S5P_MFC_R2H_CMD_SLEEP_RET               7
  96 #define S5P_MFC_R2H_CMD_WAKEUP_RET              8
  97 #define S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET        9
  98 #define S5P_MFC_R2H_CMD_DPB_FLUSH_RET           10
  99 #define S5P_MFC_R2H_CMD_NAL_ABORT_RET           11
 100 #define S5P_MFC_R2H_CMD_FW_STATUS_RET           12
 101 #define S5P_MFC_R2H_CMD_FRAME_DONE_RET          13
 102 #define S5P_MFC_R2H_CMD_FIELD_DONE_RET          14
 103 #define S5P_MFC_R2H_CMD_SLICE_DONE_RET          15
 104 #define S5P_MFC_R2H_CMD_ENC_BUFFER_FUL_RET      16
 105 #define S5P_MFC_R2H_CMD_ERR_RET                 32
 106
 107 #define MFC_MAX_CLOCKS          4
 108
 109 #define mfc_read(dev, offset)           readl(dev->regs_base + (offset))
 110 #define mfc_write(dev, data, offset)    writel((data), dev->regs_base + \
 111                                                                 (offset))
 112
 113 /**
 114  * enum s5p_mfc_fmt_type - type of the pixelformat
 115  */
 116 enum s5p_mfc_fmt_type {
 117         MFC_FMT_DEC,
 118         MFC_FMT_ENC,
 119         MFC_FMT_RAW,
 120 };
 121
 122 /**
 123  * enum s5p_mfc_inst_type - The type of an MFC instance.
 124  */
 125 enum s5p_mfc_inst_type {
 126         MFCINST_INVALID,
 127         MFCINST_DECODER,
 128         MFCINST_ENCODER,
 129 };
 130
 131 /**
 132  * enum s5p_mfc_inst_state - The state of an MFC instance.
 133  */
 134 enum s5p_mfc_inst_state {
 135         MFCINST_FREE = 0,
 136         MFCINST_INIT = 100,
 137         MFCINST_GOT_INST,
 138         MFCINST_HEAD_PARSED,
 139         MFCINST_HEAD_PRODUCED,
 140         MFCINST_BUFS_SET,
 141         MFCINST_RUNNING,
 142         MFCINST_FINISHING,
 143         MFCINST_FINISHED,
 144         MFCINST_RETURN_INST,
 145         MFCINST_ERROR,
 146         MFCINST_ABORT,
 147         MFCINST_FLUSH,
 148         MFCINST_RES_CHANGE_INIT,
 149         MFCINST_RES_CHANGE_FLUSH,
 150         MFCINST_RES_CHANGE_END,
 151 };
 152
 153 /**
 154  * enum s5p_mfc_queue_state - The state of buffer queue.
 155  */
 156 enum s5p_mfc_queue_state {
 157         QUEUE_FREE,
 158         QUEUE_BUFS_REQUESTED,
 159         QUEUE_BUFS_QUERIED,
 160         QUEUE_BUFS_MMAPED,
 161 };
 162
 163 /**
 164  * enum s5p_mfc_decode_arg - type of frame decoding
 165  */
 166 enum s5p_mfc_decode_arg {
 167         MFC_DEC_FRAME,
 168         MFC_DEC_LAST_FRAME,
 169         MFC_DEC_RES_CHANGE,
 170 };
 171
 172 enum s5p_mfc_fw_ver {
 173         MFC_FW_V1,
 174         MFC_FW_V2,
 175 };
 176
 177 #define MFC_BUF_FLAG_USED       (1 << 0)
 178 #define MFC_BUF_FLAG_EOS        (1 << 1)
 179
 180 struct s5p_mfc_ctx;
 181
 182 /**
 183  * struct s5p_mfc_buf - MFC buffer
 184  */
 185 struct s5p_mfc_buf {
 186         struct vb2_v4l2_buffer *b;
 187         struct list_head list;
 188         union {
 189                 struct {
 190                         size_t luma;
 191                         size_t chroma;
 192                 } raw;
 193                 size_t stream;
 194         } cookie;
 195         int flags;
 196 };
 197
 198 /**
 199  * struct s5p_mfc_pm - power management data structure
 200  */
 201 struct s5p_mfc_pm {
 202         struct clk      *clock_gate;
 203         const char      **clk_names;
 204         struct clk      *clocks[MFC_MAX_CLOCKS];
 205         int             num_clocks;
 206         bool            use_clock_gating;
 207
 208         struct device   *device;
 209 };
 210
 211 struct s5p_mfc_buf_size_v5 {
 212         unsigned int h264_ctx;
 213         unsigned int non_h264_ctx;
 214         unsigned int dsc;
 215         unsigned int shm;
 216 };
 217
 218 struct s5p_mfc_buf_size_v6 {
 219         unsigned int dev_ctx;
 220         unsigned int h264_dec_ctx;
 221         unsigned int other_dec_ctx;
 222         unsigned int h264_enc_ctx;
 223         unsigned int other_enc_ctx;
 224 };
 225
 226 struct s5p_mfc_buf_size {
 227         unsigned int fw;
 228         unsigned int cpb;
 229         void *priv;
 230 };
 231
 232 struct s5p_mfc_buf_align {
 233         unsigned int base;
 234 };
 235
 236 struct s5p_mfc_variant {
 237         unsigned int version;
 238         unsigned int port_num;
 239         u32 version_bit;
 240         struct s5p_mfc_buf_size *buf_size;
 241         struct s5p_mfc_buf_align *buf_align;
 242         char    *fw_name[MFC_FW_MAX_VERSIONS];
 243         const char      *clk_names[MFC_MAX_CLOCKS];
 244         int             num_clocks;
 245         bool            use_clock_gating;
 246 };
 247
 248 /**
 249  * struct s5p_mfc_priv_buf - represents internal used buffer
 250  * @ofs:                offset of each buffer, will be used for MFC
 251  * @virt:               kernel virtual address, only valid when the
 252  *                      buffer accessed by driver
 253  * @dma:                DMA address, only valid when kernel DMA API used
 254  * @size:               size of the buffer
 255  */
 256 struct s5p_mfc_priv_buf {
 257         unsigned long   ofs;
 258         void            *virt;
 259         dma_addr_t      dma;
 260         size_t          size;
 261 };
 262
 263 /**
 264  * struct s5p_mfc_dev - The struct containing driver internal parameters.
 265  *
 266  * @v4l2_dev:           v4l2_device
 267  * @vfd_dec:            video device for decoding
 268  * @vfd_enc:            video device for encoding
 269  * @plat_dev:           platform device
 270  * @mem_dev_l:          child device of the left memory bank (0)
 271  * @mem_dev_r:          child device of the right memory bank (1)
 272  * @regs_base:          base address of the MFC hw registers
 273  * @irq:                irq resource
 274  * @dec_ctrl_handler:   control framework handler for decoding
 275  * @enc_ctrl_handler:   control framework handler for encoding
 276  * @pm:                 power management control
 277  * @variant:            MFC hardware variant information
 278  * @num_inst:           couter of active MFC instances
 279  * @irqlock:            lock for operations on videobuf2 queues
 280  * @condlock:           lock for changing/checking if a context is ready to be
 281  *                      processed
 282  * @mfc_mutex:          lock for video_device
 283  * @int_cond:           variable used by the waitqueue
 284  * @int_type:           type of last interrupt
 285  * @int_err:            error number for last interrupt
 286  * @queue:              waitqueue for waiting for completion of device commands
 287  * @fw_size:            size of firmware
 288  * @fw_virt_addr:       virtual firmware address
 289  * @bank1:              address of the beginning of bank 1 memory
 290  * @bank2:              address of the beginning of bank 2 memory
 291  * @hw_lock:            used for hardware locking
 292  * @ctx:                array of driver contexts
 293  * @curr_ctx:           number of the currently running context
 294  * @ctx_work_bits:      used to mark which contexts are waiting for hardware
 295  * @watchdog_cnt:       counter for the watchdog
 296  * @watchdog_workqueue: workqueue for the watchdog
 297  * @watchdog_work:      worker for the watchdog
 298  * @enter_suspend:      flag set when entering suspend
 299  * @ctx_buf:            common context memory (MFCv6)
 300  * @warn_start:         hardware error code from which warnings start
 301  * @mfc_ops:            ops structure holding HW operation function pointers
 302  * @mfc_cmds:           cmd structure holding HW commands function pointers
 303  * @mfc_regs:           structure holding MFC registers
 304  * @fw_ver:             loaded firmware sub-version
 305  * risc_on:             flag indicates RISC is on or off
 306  *
 307  */
 308 struct s5p_mfc_dev {
 309         struct v4l2_device      v4l2_dev;
 310         struct video_device     *vfd_dec;
 311         struct video_device     *vfd_enc;
 312         struct platform_device  *plat_dev;
 313         struct device           *mem_dev_l;
 314         struct device           *mem_dev_r;
 315         void __iomem            *regs_base;
 316         int                     irq;
 317         struct v4l2_ctrl_handler dec_ctrl_handler;
 318         struct v4l2_ctrl_handler enc_ctrl_handler;
 319         struct s5p_mfc_pm       pm;
 320         struct s5p_mfc_variant  *variant;
 321         int num_inst;
 322         spinlock_t irqlock;     /* lock when operating on context */
 323         spinlock_t condlock;    /* lock when changing/checking if a context is
 324                                         ready to be processed */
 325         struct mutex mfc_mutex; /* video_device lock */
 326         int int_cond;
 327         int int_type;
 328         unsigned int int_err;
 329         wait_queue_head_t queue;
 330         size_t fw_size;
 331         void *fw_virt_addr;
 332         dma_addr_t bank1;
 333         dma_addr_t bank2;
 334         unsigned long hw_lock;
 335         struct s5p_mfc_ctx *ctx[MFC_NUM_CONTEXTS];
 336         int curr_ctx;
 337         unsigned long ctx_work_bits;
 338         atomic_t watchdog_cnt;
 339         struct timer_list watchdog_timer;
 340         struct workqueue_struct *watchdog_workqueue;
 341         struct work_struct watchdog_work;
 342         unsigned long enter_suspend;
 343
 344         struct s5p_mfc_priv_buf ctx_buf;
 345         int warn_start;
 346         struct s5p_mfc_hw_ops *mfc_ops;
 347         struct s5p_mfc_hw_cmds *mfc_cmds;
 348         const struct s5p_mfc_regs *mfc_regs;
 349         enum s5p_mfc_fw_ver fw_ver;
 350         bool risc_on; /* indicates if RISC is on or off */
 351 };
 352
 353 /**
 354  * struct s5p_mfc_h264_enc_params - encoding parameters for h264
 355  */
 356 struct s5p_mfc_h264_enc_params {
 357         enum v4l2_mpeg_video_h264_profile profile;
 358         enum v4l2_mpeg_video_h264_loop_filter_mode loop_filter_mode;
 359         s8 loop_filter_alpha;
 360         s8 loop_filter_beta;
 361         enum v4l2_mpeg_video_h264_entropy_mode entropy_mode;
 362         u8 max_ref_pic;
 363         u8 num_ref_pic_4p;
 364         int _8x8_transform;
 365         int rc_mb_dark;
 366         int rc_mb_smooth;
 367         int rc_mb_static;
 368         int rc_mb_activity;
 369         int vui_sar;
 370         u8 vui_sar_idc;
 371         u16 vui_ext_sar_width;
 372         u16 vui_ext_sar_height;
 373         int open_gop;
 374         u16 open_gop_size;
 375         u8 rc_frame_qp;
 376         u8 rc_min_qp;
 377         u8 rc_max_qp;
 378         u8 rc_p_frame_qp;
 379         u8 rc_b_frame_qp;
 380         enum v4l2_mpeg_video_h264_level level_v4l2;
 381         int level;
 382         u16 cpb_size;
 383         int interlace;
 384         u8 hier_qp;
 385         u8 hier_qp_type;
 386         u8 hier_qp_layer;
 387         u8 hier_qp_layer_qp[7];
 388         u8 sei_frame_packing;
 389         u8 sei_fp_curr_frame_0;
 390         u8 sei_fp_arrangement_type;
 391
 392         u8 fmo;
 393         u8 fmo_map_type;
 394         u8 fmo_slice_grp;
 395         u8 fmo_chg_dir;
 396         u32 fmo_chg_rate;
 397         u32 fmo_run_len[4];
 398         u8 aso;
 399         u32 aso_slice_order[8];
 400 };
 401
 402 /**
 403  * struct s5p_mfc_mpeg4_enc_params - encoding parameters for h263 and mpeg4
 404  */
 405 struct s5p_mfc_mpeg4_enc_params {
 406         /* MPEG4 Only */
 407         enum v4l2_mpeg_video_mpeg4_profile profile;
 408         int quarter_pixel;
 409         /* Common for MPEG4, H263 */
 410         u16 vop_time_res;
 411         u16 vop_frm_delta;
 412         u8 rc_frame_qp;
 413         u8 rc_min_qp;
 414         u8 rc_max_qp;
 415         u8 rc_p_frame_qp;
 416         u8 rc_b_frame_qp;
 417         enum v4l2_mpeg_video_mpeg4_level level_v4l2;
 418         int level;
 419 };
 420
 421 /**
 422  * struct s5p_mfc_vp8_enc_params - encoding parameters for vp8
 423  */
 424 struct s5p_mfc_vp8_enc_params {
 425         u8 imd_4x4;
 426         enum v4l2_vp8_num_partitions num_partitions;
 427         enum v4l2_vp8_num_ref_frames num_ref;
 428         u8 filter_level;
 429         u8 filter_sharpness;
 430         u32 golden_frame_ref_period;
 431         enum v4l2_vp8_golden_frame_sel golden_frame_sel;
 432         u8 hier_layer;
 433         u8 hier_layer_qp[3];
 434         u8 rc_min_qp;
 435         u8 rc_max_qp;
 436         u8 rc_frame_qp;
 437         u8 rc_p_frame_qp;
 438         u8 profile;
 439 };
 440
 441 /**
 442  * struct s5p_mfc_enc_params - general encoding parameters
 443  */
 444 struct s5p_mfc_enc_params {
 445         u16 width;
 446         u16 height;
 447         u32 mv_h_range;
 448         u32 mv_v_range;
 449
 450         u16 gop_size;
 451         enum v4l2_mpeg_video_multi_slice_mode slice_mode;
 452         u16 slice_mb;
 453         u32 slice_bit;
 454         u16 intra_refresh_mb;
 455         int pad;
 456         u8 pad_luma;
 457         u8 pad_cb;
 458         u8 pad_cr;
 459         int rc_frame;
 460         int rc_mb;
 461         u32 rc_bitrate;
 462         u16 rc_reaction_coeff;
 463         u16 vbv_size;
 464         u32 vbv_delay;
 465
 466         enum v4l2_mpeg_video_header_mode seq_hdr_mode;
 467         enum v4l2_mpeg_mfc51_video_frame_skip_mode frame_skip_mode;
 468         int fixed_target_bit;
 469
 470         u8 num_b_frame;
 471         u32 rc_framerate_num;
 472         u32 rc_framerate_denom;
 473
 474         struct {
 475                 struct s5p_mfc_h264_enc_params h264;
 476                 struct s5p_mfc_mpeg4_enc_params mpeg4;
 477                 struct s5p_mfc_vp8_enc_params vp8;
 478         } codec;
 479
 480 };
 481
 482 /**
 483  * struct s5p_mfc_codec_ops - codec ops, used by encoding
 484  */
 485 struct s5p_mfc_codec_ops {
 486         /* initialization routines */
 487         int (*pre_seq_start) (struct s5p_mfc_ctx *ctx);
 488         int (*post_seq_start) (struct s5p_mfc_ctx *ctx);
 489         /* execution routines */
 490         int (*pre_frame_start) (struct s5p_mfc_ctx *ctx);
 491         int (*post_frame_start) (struct s5p_mfc_ctx *ctx);
 492 };
 493
 494 #define call_cop(c, op, args...)                                \
 495         (((c)->c_ops->op) ?                                     \
 496                 ((c)->c_ops->op(args)) : 0)
 497
 498 /**
 499  * struct s5p_mfc_ctx - This struct contains the instance context
 500  *
 501  * @dev:                pointer to the s5p_mfc_dev of the device
 502  * @fh:                 struct v4l2_fh
 503  * @num:                number of the context that this structure describes
 504  * @int_cond:           variable used by the waitqueue
 505  * @int_type:           type of the last interrupt
 506  * @int_err:            error number received from MFC hw in the interrupt
 507  * @queue:              waitqueue that can be used to wait for this context to
 508  *                      finish
 509  * @src_fmt:            source pixelformat information
 510  * @dst_fmt:            destination pixelformat information
 511  * @vq_src:             vb2 queue for source buffers
 512  * @vq_dst:             vb2 queue for destination buffers
 513  * @src_queue:          driver internal queue for source buffers
 514  * @dst_queue:          driver internal queue for destination buffers
 515  * @src_queue_cnt:      number of buffers queued on the source internal queue
 516  * @dst_queue_cnt:      number of buffers queued on the dest internal queue
 517  * @type:               type of the instance - decoder or encoder
 518  * @state:              state of the context
 519  * @inst_no:            number of hw instance associated with the context
 520  * @img_width:          width of the image that is decoded or encoded
 521  * @img_height:         height of the image that is decoded or encoded
 522  * @buf_width:          width of the buffer for processed image
 523  * @buf_height:         height of the buffer for processed image
 524  * @luma_size:          size of a luma plane
 525  * @chroma_size:        size of a chroma plane
 526  * @mv_size:            size of a motion vectors buffer
 527  * @consumed_stream:    number of bytes that have been used so far from the
 528  *                      decoding buffer
 529  * @dpb_flush_flag:     flag used to indicate that a DPB buffers are being
 530  *                      flushed
 531  * @head_processed:     flag mentioning whether the header data is processed
 532  *                      completely or not
 533  * @bank1:              handle to memory allocated for temporary buffers from
 534  *                      memory bank 1
 535  * @bank2:              handle to memory allocated for temporary buffers from
 536  *                      memory bank 2
 537  * @capture_state:      state of the capture buffers queue
 538  * @output_state:       state of the output buffers queue
 539  * @src_bufs:           information on allocated source buffers
 540  * @dst_bufs:           information on allocated destination buffers
 541  * @sequence:           counter for the sequence number for v4l2
 542  * @dec_dst_flag:       flags for buffers queued in the hardware
 543  * @dec_src_buf_size:   size of the buffer for source buffers in decoding
 544  * @codec_mode:         number of codec mode used by MFC hw
 545  * @slice_interface:    slice interface flag
 546  * @loop_filter_mpeg4:  loop filter for MPEG4 flag
 547  * @display_delay:      value of the display delay for H264
 548  * @display_delay_enable:       display delay for H264 enable flag
 549  * @after_packed_pb:    flag used to track buffer when stream is in
 550  *                      Packed PB format
 551  * @sei_fp_parse:       enable/disable parsing of frame packing SEI information
 552  * @dpb_count:          count of the DPB buffers required by MFC hw
 553  * @total_dpb_count:    count of DPB buffers with additional buffers
 554  *                      requested by the application
 555  * @ctx:                context buffer information
 556  * @dsc:                descriptor buffer information
 557  * @shm:                shared memory buffer information
 558  * @mv_count:           number of MV buffers allocated for decoding
 559  * @enc_params:         encoding parameters for MFC
 560  * @enc_dst_buf_size:   size of the buffers for encoder output
 561  * @luma_dpb_size:      dpb buffer size for luma
 562  * @chroma_dpb_size:    dpb buffer size for chroma
 563  * @me_buffer_size:     size of the motion estimation buffer
 564  * @tmv_buffer_size:    size of temporal predictor motion vector buffer
 565  * @frame_type:         used to force the type of the next encoded frame
 566  * @ref_queue:          list of the reference buffers for encoding
 567  * @ref_queue_cnt:      number of the buffers in the reference list
 568  * @c_ops:              ops for encoding
 569  * @ctrls:              array of controls, used when adding controls to the
 570  *                      v4l2 control framework
 571  * @ctrl_handler:       handler for v4l2 framework
 572  */
 573 struct s5p_mfc_ctx {
 574         struct s5p_mfc_dev *dev;
 575         struct v4l2_fh fh;
 576
 577         int num;
 578
 579         int int_cond;
 580         int int_type;
 581         unsigned int int_err;
 582         wait_queue_head_t queue;
 583
 584         struct s5p_mfc_fmt *src_fmt;
 585         struct s5p_mfc_fmt *dst_fmt;
 586
 587         struct vb2_queue vq_src;
 588         struct vb2_queue vq_dst;
 589
 590         struct list_head src_queue;
 591         struct list_head dst_queue;
 592
 593         unsigned int src_queue_cnt;
 594         unsigned int dst_queue_cnt;
 595
 596         enum s5p_mfc_inst_type type;
 597         enum s5p_mfc_inst_state state;
 598         int inst_no;
 599
 600         /* Image parameters */
 601         int img_width;
 602         int img_height;
 603         int buf_width;
 604         int buf_height;
 605
 606         int luma_size;
 607         int chroma_size;
 608         int mv_size;
 609
 610         unsigned long consumed_stream;
 611
 612         unsigned int dpb_flush_flag;
 613         unsigned int head_processed;
 614
 615         struct s5p_mfc_priv_buf bank1;
 616         struct s5p_mfc_priv_buf bank2;
 617
 618         enum s5p_mfc_queue_state capture_state;
 619         enum s5p_mfc_queue_state output_state;
 620
 621         struct s5p_mfc_buf src_bufs[MFC_MAX_BUFFERS];
 622         int src_bufs_cnt;
 623         struct s5p_mfc_buf dst_bufs[MFC_MAX_BUFFERS];
 624         int dst_bufs_cnt;
 625
 626         unsigned int sequence;
 627         unsigned long dec_dst_flag;
 628         size_t dec_src_buf_size;
 629
 630         /* Control values */
 631         int codec_mode;
 632         int slice_interface;
 633         int loop_filter_mpeg4;
 634         int display_delay;
 635         int display_delay_enable;
 636         int after_packed_pb;
 637         int sei_fp_parse;
 638
 639         int pb_count;
 640         int total_dpb_count;
 641         int mv_count;
 642         /* Buffers */
 643         struct s5p_mfc_priv_buf ctx;
 644         struct s5p_mfc_priv_buf dsc;
 645         struct s5p_mfc_priv_buf shm;
 646
 647         struct s5p_mfc_enc_params enc_params;
 648
 649         size_t enc_dst_buf_size;
 650         size_t luma_dpb_size;
 651         size_t chroma_dpb_size;
 652         size_t me_buffer_size;
 653         size_t tmv_buffer_size;
 654
 655         enum v4l2_mpeg_mfc51_video_force_frame_type force_frame_type;
 656
 657         struct list_head ref_queue;
 658         unsigned int ref_queue_cnt;
 659
 660         enum v4l2_mpeg_video_multi_slice_mode slice_mode;
 661         union {
 662                 unsigned int mb;
 663                 unsigned int bits;
 664         } slice_size;
 665
 666         const struct s5p_mfc_codec_ops *c_ops;
 667
 668         struct v4l2_ctrl *ctrls[MFC_MAX_CTRLS];
 669         struct v4l2_ctrl_handler ctrl_handler;
 670         unsigned int frame_tag;
 671         size_t scratch_buf_size;
 672 };
 673
 674 /*
 675  * struct s5p_mfc_fmt - structure used to store information about pixelformats
 676  *                      used by the MFC
 677  */
 678 struct s5p_mfc_fmt {
 679         char *name;
 680         u32 fourcc;
 681         u32 codec_mode;
 682         enum s5p_mfc_fmt_type type;
 683         u32 num_planes;
 684         u32 versions;
 685 };
 686
 687 /**
 688  * struct mfc_control - structure used to store information about MFC controls
 689  *                      it is used to initialize the control framework.
 690  */
 691 struct mfc_control {
 692         __u32                   id;
 693         enum v4l2_ctrl_type     type;
 694         __u8                    name[32];  /* Whatever */
 695         __s32                   minimum;   /* Note signedness */
 696         __s32                   maximum;
 697         __s32                   step;
 698         __u32                   menu_skip_mask;
 699         __s32                   default_value;
 700         __u32                   flags;
 701         __u32                   reserved[2];
 702         __u8                    is_volatile;
 703 };
 704
 705 /* Macro for making hardware specific calls */
 706 #define s5p_mfc_hw_call(f, op, args...) \
 707         ((f && f->op) ? f->op(args) : (typeof(f->op(args)))(-ENODEV))
 708
 709 #define fh_to_ctx(__fh) container_of(__fh, struct s5p_mfc_ctx, fh)
 710 #define ctrl_to_ctx(__ctrl) \
 711         container_of((__ctrl)->handler, struct s5p_mfc_ctx, ctrl_handler)
 712
 713 void clear_work_bit(struct s5p_mfc_ctx *ctx);
 714 void set_work_bit(struct s5p_mfc_ctx *ctx);
 715 void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx);
 716 void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx);
 717 int s5p_mfc_get_new_ctx(struct s5p_mfc_dev *dev);
 718 void s5p_mfc_cleanup_queue(struct list_head *lh, struct vb2_queue *vq);
 719
 720 #define HAS_PORTNUM(dev)        (dev ? (dev->variant ? \
 721                                 (dev->variant->port_num ? 1 : 0) : 0) : 0)
 722 #define IS_TWOPORT(dev)         (dev->variant->port_num == 2 ? 1 : 0)
 723 #define IS_MFCV6_PLUS(dev)      (dev->variant->version >= 0x60 ? 1 : 0)
 724 #define IS_MFCV7_PLUS(dev)      (dev->variant->version >= 0x70 ? 1 : 0)
 725 #define IS_MFCV8(dev)           (dev->variant->version >= 0x80 ? 1 : 0)
 726
 727 #define MFC_V5_BIT      BIT(0)
 728 #define MFC_V6_BIT      BIT(1)
 729 #define MFC_V7_BIT      BIT(2)
 730 #define MFC_V8_BIT      BIT(3)
 731
 732
 733 #endif /* S5P_MFC_COMMON_H_ */