drivers/spi/spi-fsl-spi.h

   1 /*
   2  * Freescale SPI controller driver.
   3  *
   4  * Maintainer: Kumar Gala
   5  *
   6  * Copyright (C) 2006 Polycom, Inc.
   7  * Copyright 2010 Freescale Semiconductor, Inc.
   8  *
   9  * CPM SPI and QE buffer descriptors mode support:
  10  * Copyright (c) 2009  MontaVista Software, Inc.
  11  * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
  12  *
  13  * GRLIB support:
  14  * Copyright (c) 2012 Aeroflex Gaisler AB.
  15  * Author: Andreas Larsson <andreas@gaisler.com>
  16  *
  17  * This program is free software; you can redistribute  it and/or modify it
  18  * under  the terms of  the GNU General  Public License as published by the
  19  * Free Software Foundation;  either version 2 of the  License, or (at your
  20  * option) any later version.
  21  */
  22
  23 #ifndef __SPI_FSL_SPI_H__
  24 #define __SPI_FSL_SPI_H__
  25
  26 /* SPI Controller registers */
  27 struct fsl_spi_reg {
  28         __be32 cap; /* TYPE_GRLIB specific */
  29         u8 res1[0x1C];
  30         __be32 mode;
  31         __be32 event;
  32         __be32 mask;
  33         __be32 command;
  34         __be32 transmit;
  35         __be32 receive;
  36         __be32 slvsel; /* TYPE_GRLIB specific */
  37 };
  38
  39 /* SPI Controller mode register definitions */
  40 #define SPMODE_LOOP             (1 << 30)
  41 #define SPMODE_CI_INACTIVEHIGH  (1 << 29)
  42 #define SPMODE_CP_BEGIN_EDGECLK (1 << 28)
  43 #define SPMODE_DIV16            (1 << 27)
  44 #define SPMODE_REV              (1 << 26)
  45 #define SPMODE_MS               (1 << 25)
  46 #define SPMODE_ENABLE           (1 << 24)
  47 #define SPMODE_LEN(x)           ((x) << 20)
  48 #define SPMODE_PM(x)            ((x) << 16)
  49 #define SPMODE_OP               (1 << 14)
  50 #define SPMODE_CG(x)            ((x) << 7)
  51
  52 /* TYPE_GRLIB SPI Controller capability register definitions */
  53 #define SPCAP_SSEN(x)           (((x) >> 16) & 0x1)
  54 #define SPCAP_SSSZ(x)           (((x) >> 24) & 0xff)
  55 #define SPCAP_MAXWLEN(x)        (((x) >> 20) & 0xf)
  56
  57 /*
  58  * Default for SPI Mode:
  59  *      SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk
  60  */
  61 #define SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \
  62                          SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf))
  63
  64 /* SPIE register values */
  65 #define SPIE_NE         0x00000200      /* Not empty */
  66 #define SPIE_NF         0x00000100      /* Not full */
  67
  68 /* SPIM register values */
  69 #define SPIM_NE         0x00000200      /* Not empty */
  70 #define SPIM_NF         0x00000100      /* Not full */
  71
  72 #endif /* __SPI_FSL_SPI_H__ */