drivers/spi/spi-mpc512x-psc.c

   1 /*
   2  * MPC512x PSC in SPI mode driver.
   3  *
   4  * Copyright (C) 2007,2008 Freescale Semiconductor Inc.
   5  * Original port from 52xx driver:
   6  *      Hongjun Chen <hong-jun.chen@freescale.com>
   7  *
   8  * Fork of mpc52xx_psc_spi.c:
   9  *      Copyright (C) 2006 TOPTICA Photonics AG., Dragos Carp
  10  *
  11  * This program is free software; you can redistribute  it and/or modify it
  12  * under  the terms of  the GNU General  Public License as published by the
  13  * Free Software Foundation;  either version 2 of the  License, or (at your
  14  * option) any later version.
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/kernel.h>
  19 #include <linux/errno.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/of_address.h>
  22 #include <linux/of_irq.h>
  23 #include <linux/of_platform.h>
  24 #include <linux/completion.h>
  25 #include <linux/io.h>
  26 #include <linux/delay.h>
  27 #include <linux/clk.h>
  28 #include <linux/spi/spi.h>
  29 #include <linux/fsl_devices.h>
  30 #include <linux/gpio.h>
  31 #include <asm/mpc52xx_psc.h>
  32
  33 enum {
  34         TYPE_MPC5121,
  35         TYPE_MPC5125,
  36 };
  37
  38 /*
  39  * This macro abstracts the differences in the PSC register layout between
  40  * MPC5121 (which uses a struct mpc52xx_psc) and MPC5125 (using mpc5125_psc).
  41  */
  42 #define psc_addr(mps, regname) ({                                       \
  43         void *__ret = NULL;                                             \
  44         switch (mps->type) {                                            \
  45         case TYPE_MPC5121: {                                            \
  46                         struct mpc52xx_psc __iomem *psc = mps->psc;     \
  47                         __ret = &psc->regname;                          \
  48                 };                                                      \
  49                 break;                                                  \
  50         case TYPE_MPC5125: {                                            \
  51                         struct mpc5125_psc __iomem *psc = mps->psc;     \
  52                         __ret = &psc->regname;                          \
  53                 };                                                      \
  54                 break;                                                  \
  55         }                                                               \
  56         __ret; })
  57
  58 struct mpc512x_psc_spi {
  59         void (*cs_control)(struct spi_device *spi, bool on);
  60
  61         /* driver internal data */
  62         int type;
  63         void __iomem *psc;
  64         struct mpc512x_psc_fifo __iomem *fifo;
  65         unsigned int irq;
  66         u8 bits_per_word;
  67         struct clk *clk_mclk;
  68         struct clk *clk_ipg;
  69         u32 mclk_rate;
  70
  71         struct completion txisrdone;
  72 };
  73
  74 /* controller state */
  75 struct mpc512x_psc_spi_cs {
  76         int bits_per_word;
  77         int speed_hz;
  78 };
  79
  80 /* set clock freq, clock ramp, bits per work
  81  * if t is NULL then reset the values to the default values
  82  */
  83 static int mpc512x_psc_spi_transfer_setup(struct spi_device *spi,
  84                                           struct spi_transfer *t)
  85 {
  86         struct mpc512x_psc_spi_cs *cs = spi->controller_state;
  87
  88         cs->speed_hz = (t && t->speed_hz)
  89             ? t->speed_hz : spi->max_speed_hz;
  90         cs->bits_per_word = (t && t->bits_per_word)
  91             ? t->bits_per_word : spi->bits_per_word;
  92         cs->bits_per_word = ((cs->bits_per_word + 7) / 8) * 8;
  93         return 0;
  94 }
  95
  96 static void mpc512x_psc_spi_activate_cs(struct spi_device *spi)
  97 {
  98         struct mpc512x_psc_spi_cs *cs = spi->controller_state;
  99         struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master);
 100         u32 sicr;
 101         u32 ccr;
 102         int speed;
 103         u16 bclkdiv;
 104
 105         sicr = in_be32(psc_addr(mps, sicr));
 106
 107         /* Set clock phase and polarity */
 108         if (spi->mode & SPI_CPHA)
 109                 sicr |= 0x00001000;
 110         else
 111                 sicr &= ~0x00001000;
 112
 113         if (spi->mode & SPI_CPOL)
 114                 sicr |= 0x00002000;
 115         else
 116                 sicr &= ~0x00002000;
 117
 118         if (spi->mode & SPI_LSB_FIRST)
 119                 sicr |= 0x10000000;
 120         else
 121                 sicr &= ~0x10000000;
 122         out_be32(psc_addr(mps, sicr), sicr);
 123
 124         ccr = in_be32(psc_addr(mps, ccr));
 125         ccr &= 0xFF000000;
 126         speed = cs->speed_hz;
 127         if (!speed)
 128                 speed = 1000000;        /* default 1MHz */
 129         bclkdiv = (mps->mclk_rate / speed) - 1;
 130
 131         ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8));
 132         out_be32(psc_addr(mps, ccr), ccr);
 133         mps->bits_per_word = cs->bits_per_word;
 134
 135         if (mps->cs_control && gpio_is_valid(spi->cs_gpio))
 136                 mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 1 : 0);
 137 }
 138
 139 static void mpc512x_psc_spi_deactivate_cs(struct spi_device *spi)
 140 {
 141         struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master);
 142
 143         if (mps->cs_control && gpio_is_valid(spi->cs_gpio))
 144                 mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 0 : 1);
 145
 146 }
 147
 148 /* extract and scale size field in txsz or rxsz */
 149 #define MPC512x_PSC_FIFO_SZ(sz) ((sz & 0x7ff) << 2);
 150
 151 #define EOFBYTE 1
 152
 153 static int mpc512x_psc_spi_transfer_rxtx(struct spi_device *spi,
 154                                          struct spi_transfer *t)
 155 {
 156         struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master);
 157         struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
 158         size_t tx_len = t->len;
 159         size_t rx_len = t->len;
 160         u8 *tx_buf = (u8 *)t->tx_buf;
 161         u8 *rx_buf = (u8 *)t->rx_buf;
 162
 163         if (!tx_buf && !rx_buf && t->len)
 164                 return -EINVAL;
 165
 166         while (rx_len || tx_len) {
 167                 size_t txcount;
 168                 u8 data;
 169                 size_t fifosz;
 170                 size_t rxcount;
 171                 int rxtries;
 172
 173                 /*
 174                  * send the TX bytes in as large a chunk as possible
 175                  * but neither exceed the TX nor the RX FIFOs
 176                  */
 177                 fifosz = MPC512x_PSC_FIFO_SZ(in_be32(&fifo->txsz));
 178                 txcount = min(fifosz, tx_len);
 179                 fifosz = MPC512x_PSC_FIFO_SZ(in_be32(&fifo->rxsz));
 180                 fifosz -= in_be32(&fifo->rxcnt) + 1;
 181                 txcount = min(fifosz, txcount);
 182                 if (txcount) {
 183
 184                         /* fill the TX FIFO */
 185                         while (txcount-- > 0) {
 186                                 data = tx_buf ? *tx_buf++ : 0;
 187                                 if (tx_len == EOFBYTE && t->cs_change)
 188                                         setbits32(&fifo->txcmd,
 189                                                   MPC512x_PSC_FIFO_EOF);
 190                                 out_8(&fifo->txdata_8, data);
 191                                 tx_len--;
 192                         }
 193
 194                         /* have the ISR trigger when the TX FIFO is empty */
 195                         reinit_completion(&mps->txisrdone);
 196                         out_be32(&fifo->txisr, MPC512x_PSC_FIFO_EMPTY);
 197                         out_be32(&fifo->tximr, MPC512x_PSC_FIFO_EMPTY);
 198                         wait_for_completion(&mps->txisrdone);
 199                 }
 200
 201                 /*
 202                  * consume as much RX data as the FIFO holds, while we
 203                  * iterate over the transfer's TX data length
 204                  *
 205                  * only insist in draining all the remaining RX bytes
 206                  * when the TX bytes were exhausted (that's at the very
 207                  * end of this transfer, not when still iterating over
 208                  * the transfer's chunks)
 209                  */
 210                 rxtries = 50;
 211                 do {
 212
 213                         /*
 214                          * grab whatever was in the FIFO when we started
 215                          * looking, don't bother fetching what was added to
 216                          * the FIFO while we read from it -- we'll return
 217                          * here eventually and prefer sending out remaining
 218                          * TX data
 219                          */
 220                         fifosz = in_be32(&fifo->rxcnt);
 221                         rxcount = min(fifosz, rx_len);
 222                         while (rxcount-- > 0) {
 223                                 data = in_8(&fifo->rxdata_8);
 224                                 if (rx_buf)
 225                                         *rx_buf++ = data;
 226                                 rx_len--;
 227                         }
 228
 229                         /*
 230                          * come back later if there still is TX data to send,
 231                          * bail out of the RX drain loop if all of the TX data
 232                          * was sent and all of the RX data was received (i.e.
 233                          * when the transmission has completed)
 234                          */
 235                         if (tx_len)
 236                                 break;
 237                         if (!rx_len)
 238                                 break;
 239
 240                         /*
 241                          * TX data transmission has completed while RX data
 242                          * is still pending -- that's a transient situation
 243                          * which depends on wire speed and specific
 244                          * hardware implementation details (buffering) yet
 245                          * should resolve very quickly
 246                          *
 247                          * just yield for a moment to not hog the CPU for
 248                          * too long when running SPI at low speed
 249                          *
 250                          * the timeout range is rather arbitrary and tries
 251                          * to balance throughput against system load; the
 252                          * chosen values result in a minimal timeout of 50
 253                          * times 10us and thus work at speeds as low as
 254                          * some 20kbps, while the maximum timeout at the
 255                          * transfer's end could be 5ms _if_ nothing else
 256                          * ticks in the system _and_ RX data still wasn't
 257                          * received, which only occurs in situations that
 258                          * are exceptional; removing the unpredictability
 259                          * of the timeout either decreases throughput
 260                          * (longer timeouts), or puts more load on the
 261                          * system (fixed short timeouts) or requires the
 262                          * use of a timeout API instead of a counter and an
 263                          * unknown inner delay
 264                          */
 265                         usleep_range(10, 100);
 266
 267                 } while (--rxtries > 0);
 268                 if (!tx_len && rx_len && !rxtries) {
 269                         /*
 270                          * not enough RX bytes even after several retries
 271                          * and the resulting rather long timeout?
 272                          */
 273                         rxcount = in_be32(&fifo->rxcnt);
 274                         dev_warn(&spi->dev,
 275                                  "short xfer, missing %zd RX bytes, FIFO level %zd\n",
 276                                  rx_len, rxcount);
 277                 }
 278
 279                 /*
 280                  * drain and drop RX data which "should not be there" in
 281                  * the first place, for undisturbed transmission this turns
 282                  * into a NOP (except for the FIFO level fetch)
 283                  */
 284                 if (!tx_len && !rx_len) {
 285                         while (in_be32(&fifo->rxcnt))
 286                                 in_8(&fifo->rxdata_8);
 287                 }
 288
 289         }
 290         return 0;
 291 }
 292
 293 static int mpc512x_psc_spi_msg_xfer(struct spi_master *master,
 294                                     struct spi_message *m)
 295 {
 296         struct spi_device *spi;
 297         unsigned cs_change;
 298         int status;
 299         struct spi_transfer *t;
 300
 301         spi = m->spi;
 302         cs_change = 1;
 303         status = 0;
 304         list_for_each_entry(t, &m->transfers, transfer_list) {
 305                 status = mpc512x_psc_spi_transfer_setup(spi, t);
 306                 if (status < 0)
 307                         break;
 308
 309                 if (cs_change)
 310                         mpc512x_psc_spi_activate_cs(spi);
 311                 cs_change = t->cs_change;
 312
 313                 status = mpc512x_psc_spi_transfer_rxtx(spi, t);
 314                 if (status)
 315                         break;
 316                 m->actual_length += t->len;
 317
 318                 if (t->delay_usecs)
 319                         udelay(t->delay_usecs);
 320
 321                 if (cs_change)
 322                         mpc512x_psc_spi_deactivate_cs(spi);
 323         }
 324
 325         m->status = status;
 326         if (m->complete)
 327                 m->complete(m->context);
 328
 329         if (status || !cs_change)
 330                 mpc512x_psc_spi_deactivate_cs(spi);
 331
 332         mpc512x_psc_spi_transfer_setup(spi, NULL);
 333
 334         spi_finalize_current_message(master);
 335         return status;
 336 }
 337
 338 static int mpc512x_psc_spi_prep_xfer_hw(struct spi_master *master)
 339 {
 340         struct mpc512x_psc_spi *mps = spi_master_get_devdata(master);
 341
 342         dev_dbg(&master->dev, "%s()\n", __func__);
 343
 344         /* Zero MR2 */
 345         in_8(psc_addr(mps, mr2));
 346         out_8(psc_addr(mps, mr2), 0x0);
 347
 348         /* enable transmitter/receiver */
 349         out_8(psc_addr(mps, command), MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE);
 350
 351         return 0;
 352 }
 353
 354 static int mpc512x_psc_spi_unprep_xfer_hw(struct spi_master *master)
 355 {
 356         struct mpc512x_psc_spi *mps = spi_master_get_devdata(master);
 357         struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
 358
 359         dev_dbg(&master->dev, "%s()\n", __func__);
 360
 361         /* disable transmitter/receiver and fifo interrupt */
 362         out_8(psc_addr(mps, command), MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
 363         out_be32(&fifo->tximr, 0);
 364
 365         return 0;
 366 }
 367
 368 static int mpc512x_psc_spi_setup(struct spi_device *spi)
 369 {
 370         struct mpc512x_psc_spi_cs *cs = spi->controller_state;
 371         int ret;
 372
 373         if (spi->bits_per_word % 8)
 374                 return -EINVAL;
 375
 376         if (!cs) {
 377                 cs = kzalloc(sizeof *cs, GFP_KERNEL);
 378                 if (!cs)
 379                         return -ENOMEM;
 380
 381                 if (gpio_is_valid(spi->cs_gpio)) {
 382                         ret = gpio_request(spi->cs_gpio, dev_name(&spi->dev));
 383                         if (ret) {
 384                                 dev_err(&spi->dev, "can't get CS gpio: %d\n",
 385                                         ret);
 386                                 kfree(cs);
 387                                 return ret;
 388                         }
 389                         gpio_direction_output(spi->cs_gpio,
 390                                         spi->mode & SPI_CS_HIGH ? 0 : 1);
 391                 }
 392
 393                 spi->controller_state = cs;
 394         }
 395
 396         cs->bits_per_word = spi->bits_per_word;
 397         cs->speed_hz = spi->max_speed_hz;
 398
 399         return 0;
 400 }
 401
 402 static void mpc512x_psc_spi_cleanup(struct spi_device *spi)
 403 {
 404         if (gpio_is_valid(spi->cs_gpio))
 405                 gpio_free(spi->cs_gpio);
 406         kfree(spi->controller_state);
 407 }
 408
 409 static int mpc512x_psc_spi_port_config(struct spi_master *master,
 410                                        struct mpc512x_psc_spi *mps)
 411 {
 412         struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
 413         u32 sicr;
 414         u32 ccr;
 415         int speed;
 416         u16 bclkdiv;
 417
 418         /* Reset the PSC into a known state */
 419         out_8(psc_addr(mps, command), MPC52xx_PSC_RST_RX);
 420         out_8(psc_addr(mps, command), MPC52xx_PSC_RST_TX);
 421         out_8(psc_addr(mps, command), MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
 422
 423         /* Disable psc interrupts all useful interrupts are in fifo */
 424         out_be16(psc_addr(mps, isr_imr.imr), 0);
 425
 426         /* Disable fifo interrupts, will be enabled later */
 427         out_be32(&fifo->tximr, 0);
 428         out_be32(&fifo->rximr, 0);
 429
 430         /* Setup fifo slice address and size */
 431         /*out_be32(&fifo->txsz, 0x0fe00004);*/
 432         /*out_be32(&fifo->rxsz, 0x0ff00004);*/
 433
 434         sicr =  0x01000000 |    /* SIM = 0001 -- 8 bit */
 435                 0x00800000 |    /* GenClk = 1 -- internal clk */
 436                 0x00008000 |    /* SPI = 1 */
 437                 0x00004000 |    /* MSTR = 1   -- SPI master */
 438                 0x00000800;     /* UseEOF = 1 -- SS low until EOF */
 439
 440         out_be32(psc_addr(mps, sicr), sicr);
 441
 442         ccr = in_be32(psc_addr(mps, ccr));
 443         ccr &= 0xFF000000;
 444         speed = 1000000;        /* default 1MHz */
 445         bclkdiv = (mps->mclk_rate / speed) - 1;
 446         ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8));
 447         out_be32(psc_addr(mps, ccr), ccr);
 448
 449         /* Set 2ms DTL delay */
 450         out_8(psc_addr(mps, ctur), 0x00);
 451         out_8(psc_addr(mps, ctlr), 0x82);
 452
 453         /* we don't use the alarms */
 454         out_be32(&fifo->rxalarm, 0xfff);
 455         out_be32(&fifo->txalarm, 0);
 456
 457         /* Enable FIFO slices for Rx/Tx */
 458         out_be32(&fifo->rxcmd,
 459                  MPC512x_PSC_FIFO_ENABLE_SLICE | MPC512x_PSC_FIFO_ENABLE_DMA);
 460         out_be32(&fifo->txcmd,
 461                  MPC512x_PSC_FIFO_ENABLE_SLICE | MPC512x_PSC_FIFO_ENABLE_DMA);
 462
 463         mps->bits_per_word = 8;
 464
 465         return 0;
 466 }
 467
 468 static irqreturn_t mpc512x_psc_spi_isr(int irq, void *dev_id)
 469 {
 470         struct mpc512x_psc_spi *mps = (struct mpc512x_psc_spi *)dev_id;
 471         struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
 472
 473         /* clear interrupt and wake up the rx/tx routine */
 474         if (in_be32(&fifo->txisr) &
 475             in_be32(&fifo->tximr) & MPC512x_PSC_FIFO_EMPTY) {
 476                 out_be32(&fifo->txisr, MPC512x_PSC_FIFO_EMPTY);
 477                 out_be32(&fifo->tximr, 0);
 478                 complete(&mps->txisrdone);
 479                 return IRQ_HANDLED;
 480         }
 481         return IRQ_NONE;
 482 }
 483
 484 static void mpc512x_spi_cs_control(struct spi_device *spi, bool onoff)
 485 {
 486         gpio_set_value(spi->cs_gpio, onoff);
 487 }
 488
 489 static int mpc512x_psc_spi_do_probe(struct device *dev, u32 regaddr,
 490                                               u32 size, unsigned int irq)
 491 {
 492         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
 493         struct mpc512x_psc_spi *mps;
 494         struct spi_master *master;
 495         int ret;
 496         void *tempp;
 497         struct clk *clk;
 498
 499         master = spi_alloc_master(dev, sizeof *mps);
 500         if (master == NULL)
 501                 return -ENOMEM;
 502
 503         dev_set_drvdata(dev, master);
 504         mps = spi_master_get_devdata(master);
 505         mps->type = (int)of_device_get_match_data(dev);
 506         mps->irq = irq;
 507
 508         if (pdata == NULL) {
 509                 mps->cs_control = mpc512x_spi_cs_control;
 510         } else {
 511                 mps->cs_control = pdata->cs_control;
 512                 master->bus_num = pdata->bus_num;
 513                 master->num_chipselect = pdata->max_chipselect;
 514         }
 515
 516         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
 517         master->setup = mpc512x_psc_spi_setup;
 518         master->prepare_transfer_hardware = mpc512x_psc_spi_prep_xfer_hw;
 519         master->transfer_one_message = mpc512x_psc_spi_msg_xfer;
 520         master->unprepare_transfer_hardware = mpc512x_psc_spi_unprep_xfer_hw;
 521         master->cleanup = mpc512x_psc_spi_cleanup;
 522         master->dev.of_node = dev->of_node;
 523
 524         tempp = devm_ioremap(dev, regaddr, size);
 525         if (!tempp) {
 526                 dev_err(dev, "could not ioremap I/O port range\n");
 527                 ret = -EFAULT;
 528                 goto free_master;
 529         }
 530         mps->psc = tempp;
 531         mps->fifo =
 532                 (struct mpc512x_psc_fifo *)(tempp + sizeof(struct mpc52xx_psc));
 533         ret = devm_request_irq(dev, mps->irq, mpc512x_psc_spi_isr, IRQF_SHARED,
 534                                 "mpc512x-psc-spi", mps);
 535         if (ret)
 536                 goto free_master;
 537         init_completion(&mps->txisrdone);
 538
 539         clk = devm_clk_get(dev, "mclk");
 540         if (IS_ERR(clk)) {
 541                 ret = PTR_ERR(clk);
 542                 goto free_master;
 543         }
 544         ret = clk_prepare_enable(clk);
 545         if (ret)
 546                 goto free_master;
 547         mps->clk_mclk = clk;
 548         mps->mclk_rate = clk_get_rate(clk);
 549
 550         clk = devm_clk_get(dev, "ipg");
 551         if (IS_ERR(clk)) {
 552                 ret = PTR_ERR(clk);
 553                 goto free_mclk_clock;
 554         }
 555         ret = clk_prepare_enable(clk);
 556         if (ret)
 557                 goto free_mclk_clock;
 558         mps->clk_ipg = clk;
 559
 560         ret = mpc512x_psc_spi_port_config(master, mps);
 561         if (ret < 0)
 562                 goto free_ipg_clock;
 563
 564         ret = devm_spi_register_master(dev, master);
 565         if (ret < 0)
 566                 goto free_ipg_clock;
 567
 568         return ret;
 569
 570 free_ipg_clock:
 571         clk_disable_unprepare(mps->clk_ipg);
 572 free_mclk_clock:
 573         clk_disable_unprepare(mps->clk_mclk);
 574 free_master:
 575         spi_master_put(master);
 576
 577         return ret;
 578 }
 579
 580 static int mpc512x_psc_spi_do_remove(struct device *dev)
 581 {
 582         struct spi_master *master = dev_get_drvdata(dev);
 583         struct mpc512x_psc_spi *mps = spi_master_get_devdata(master);
 584
 585         clk_disable_unprepare(mps->clk_mclk);
 586         clk_disable_unprepare(mps->clk_ipg);
 587
 588         return 0;
 589 }
 590
 591 static int mpc512x_psc_spi_of_probe(struct platform_device *op)
 592 {
 593         const u32 *regaddr_p;
 594         u64 regaddr64, size64;
 595
 596         regaddr_p = of_get_address(op->dev.of_node, 0, &size64, NULL);
 597         if (!regaddr_p) {
 598                 dev_err(&op->dev, "Invalid PSC address\n");
 599                 return -EINVAL;
 600         }
 601         regaddr64 = of_translate_address(op->dev.of_node, regaddr_p);
 602
 603         return mpc512x_psc_spi_do_probe(&op->dev, (u32) regaddr64, (u32) size64,
 604                                 irq_of_parse_and_map(op->dev.of_node, 0));
 605 }
 606
 607 static int mpc512x_psc_spi_of_remove(struct platform_device *op)
 608 {
 609         return mpc512x_psc_spi_do_remove(&op->dev);
 610 }
 611
 612 static const struct of_device_id mpc512x_psc_spi_of_match[] = {
 613         { .compatible = "fsl,mpc5121-psc-spi", .data = (void *)TYPE_MPC5121 },
 614         { .compatible = "fsl,mpc5125-psc-spi", .data = (void *)TYPE_MPC5125 },
 615         {},
 616 };
 617
 618 MODULE_DEVICE_TABLE(of, mpc512x_psc_spi_of_match);
 619
 620 static struct platform_driver mpc512x_psc_spi_of_driver = {
 621         .probe = mpc512x_psc_spi_of_probe,
 622         .remove = mpc512x_psc_spi_of_remove,
 623         .driver = {
 624                 .name = "mpc512x-psc-spi",
 625                 .of_match_table = mpc512x_psc_spi_of_match,
 626         },
 627 };
 628 module_platform_driver(mpc512x_psc_spi_of_driver);
 629
 630 MODULE_AUTHOR("John Rigby");
 631 MODULE_DESCRIPTION("MPC512x PSC SPI Driver");
 632 MODULE_LICENSE("GPL");