2 * Copyright (C) 2008 Sascha Hauer, Pengutronix
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 #include <linux/types.h>
20 #include <linux/init.h>
22 #include <linux/platform_device.h>
23 #include <linux/mtd/physmap.h>
24 #include <linux/mtd/plat-ram.h>
25 #include <linux/memory.h>
26 #include <linux/gpio.h>
27 #include <linux/smsc911x.h>
28 #include <linux/interrupt.h>
29 #include <linux/i2c.h>
30 #include <linux/i2c/at24.h>
31 #include <linux/delay.h>
32 #include <linux/spi/spi.h>
33 #include <linux/irq.h>
34 #include <linux/fsl_devices.h>
36 #include <mach/hardware.h>
37 #include <asm/mach-types.h>
38 #include <asm/mach/arch.h>
39 #include <asm/mach/time.h>
40 #include <asm/mach/map.h>
41 #include <mach/common.h>
42 #include <mach/imx-uart.h>
43 #include <mach/iomux-mx3.h>
45 #include <mach/board-pcm037.h>
46 #include <mach/mx3fb.h>
47 #include <mach/mxc_nand.h>
55 static unsigned int pcm037_pins
[] = {
57 MX31_PIN_CSPI2_MOSI__SCL
,
58 MX31_PIN_CSPI2_MISO__SDA
,
60 MX31_PIN_SD1_DATA3__SD1_DATA3
,
61 MX31_PIN_SD1_DATA2__SD1_DATA2
,
62 MX31_PIN_SD1_DATA1__SD1_DATA1
,
63 MX31_PIN_SD1_DATA0__SD1_DATA0
,
64 MX31_PIN_SD1_CLK__SD1_CLK
,
65 MX31_PIN_SD1_CMD__SD1_CMD
,
66 IOMUX_MODE(MX31_PIN_SCK6
, IOMUX_CONFIG_GPIO
), /* card detect */
67 IOMUX_MODE(MX31_PIN_SFS6
, IOMUX_CONFIG_GPIO
), /* write protect */
69 MX31_PIN_CSPI1_MOSI__MOSI
,
70 MX31_PIN_CSPI1_MISO__MISO
,
71 MX31_PIN_CSPI1_SCLK__SCLK
,
72 MX31_PIN_CSPI1_SPI_RDY__SPI_RDY
,
73 MX31_PIN_CSPI1_SS0__SS0
,
74 MX31_PIN_CSPI1_SS1__SS1
,
75 MX31_PIN_CSPI1_SS2__SS2
,
87 MX31_PIN_CSPI3_MOSI__RXD3
,
88 MX31_PIN_CSPI3_MISO__TXD3
,
89 MX31_PIN_CSPI3_SCLK__RTS3
,
90 MX31_PIN_CSPI3_SPI_RDY__CTS3
,
92 IOMUX_MODE(MX31_PIN_GPIO3_1
, IOMUX_CONFIG_GPIO
),
94 MX31_PIN_BATT_LINE__OWIRE
,
114 MX31_PIN_VSYNC3__VSYNC3
,
115 MX31_PIN_HSYNC__HSYNC
,
116 MX31_PIN_FPSHIFT__FPSHIFT
,
117 MX31_PIN_DRDY0__DRDY0
,
118 MX31_PIN_D3_REV__D3_REV
,
119 MX31_PIN_CONTRAST__CONTRAST
,
120 MX31_PIN_D3_SPL__D3_SPL
,
121 MX31_PIN_D3_CLS__D3_CLS
,
122 MX31_PIN_LCS0__GPI03_23
,
125 static struct physmap_flash_data pcm037_flash_data
= {
129 static struct resource pcm037_flash_resource
= {
132 .flags
= IORESOURCE_MEM
,
135 static int usbotg_pins
[] = {
136 MX31_PIN_USBOTG_DATA0__USBOTG_DATA0
,
137 MX31_PIN_USBOTG_DATA1__USBOTG_DATA1
,
138 MX31_PIN_USBOTG_DATA2__USBOTG_DATA2
,
139 MX31_PIN_USBOTG_DATA3__USBOTG_DATA3
,
140 MX31_PIN_USBOTG_DATA4__USBOTG_DATA4
,
141 MX31_PIN_USBOTG_DATA5__USBOTG_DATA5
,
142 MX31_PIN_USBOTG_DATA6__USBOTG_DATA6
,
143 MX31_PIN_USBOTG_DATA7__USBOTG_DATA7
,
144 MX31_PIN_USBOTG_CLK__USBOTG_CLK
,
145 MX31_PIN_USBOTG_DIR__USBOTG_DIR
,
146 MX31_PIN_USBOTG_NXT__USBOTG_NXT
,
147 MX31_PIN_USBOTG_STP__USBOTG_STP
,
150 /* USB OTG HS port */
151 static int __init
gpio_usbotg_hs_activate(void)
153 int ret
= mxc_iomux_setup_multiple_pins(usbotg_pins
,
154 ARRAY_SIZE(usbotg_pins
), "usbotg");
157 printk(KERN_ERR
"Cannot set up OTG pins\n");
161 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0
, PAD_CTL_DRV_MAX
| PAD_CTL_SRE_FAST
);
162 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1
, PAD_CTL_DRV_MAX
| PAD_CTL_SRE_FAST
);
163 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2
, PAD_CTL_DRV_MAX
| PAD_CTL_SRE_FAST
);
164 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3
, PAD_CTL_DRV_MAX
| PAD_CTL_SRE_FAST
);
165 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4
, PAD_CTL_DRV_MAX
| PAD_CTL_SRE_FAST
);
166 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5
, PAD_CTL_DRV_MAX
| PAD_CTL_SRE_FAST
);
167 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6
, PAD_CTL_DRV_MAX
| PAD_CTL_SRE_FAST
);
168 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7
, PAD_CTL_DRV_MAX
| PAD_CTL_SRE_FAST
);
169 mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK
, PAD_CTL_DRV_MAX
| PAD_CTL_SRE_FAST
);
170 mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR
, PAD_CTL_DRV_MAX
| PAD_CTL_SRE_FAST
);
171 mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT
, PAD_CTL_DRV_MAX
| PAD_CTL_SRE_FAST
);
172 mxc_iomux_set_pad(MX31_PIN_USBOTG_STP
, PAD_CTL_DRV_MAX
| PAD_CTL_SRE_FAST
);
178 static struct fsl_usb2_platform_data usb_pdata
= {
179 .operating_mode
= FSL_USB2_DR_DEVICE
,
180 .phy_mode
= FSL_USB2_PHY_ULPI
,
183 static struct platform_device pcm037_flash
= {
184 .name
= "physmap-flash",
187 .platform_data
= &pcm037_flash_data
,
189 .resource
= &pcm037_flash_resource
,
193 static struct imxuart_platform_data uart_pdata
= {
194 .flags
= IMXUART_HAVE_RTSCTS
,
197 static struct resource smsc911x_resources
[] = {
199 .start
= CS1_BASE_ADDR
+ 0x300,
200 .end
= CS1_BASE_ADDR
+ 0x300 + SZ_64K
- 1,
201 .flags
= IORESOURCE_MEM
,
204 .start
= IOMUX_TO_IRQ(MX31_PIN_GPIO3_1
),
205 .end
= IOMUX_TO_IRQ(MX31_PIN_GPIO3_1
),
206 .flags
= IORESOURCE_IRQ
| IORESOURCE_IRQ_LOWLEVEL
,
210 static struct smsc911x_platform_config smsc911x_info
= {
211 .flags
= SMSC911X_USE_32BIT
| SMSC911X_FORCE_INTERNAL_PHY
|
212 SMSC911X_SAVE_MAC_ADDRESS
,
213 .irq_polarity
= SMSC911X_IRQ_POLARITY_ACTIVE_LOW
,
214 .irq_type
= SMSC911X_IRQ_TYPE_OPEN_DRAIN
,
215 .phy_interface
= PHY_INTERFACE_MODE_MII
,
218 static struct platform_device pcm037_eth
= {
221 .num_resources
= ARRAY_SIZE(smsc911x_resources
),
222 .resource
= smsc911x_resources
,
224 .platform_data
= &smsc911x_info
,
228 static struct platdata_mtd_ram pcm038_sram_data
= {
232 static struct resource pcm038_sram_resource
= {
233 .start
= CS4_BASE_ADDR
,
234 .end
= CS4_BASE_ADDR
+ 512 * 1024 - 1,
235 .flags
= IORESOURCE_MEM
,
238 static struct platform_device pcm037_sram_device
= {
242 .platform_data
= &pcm038_sram_data
,
245 .resource
= &pcm038_sram_resource
,
248 static struct mxc_nand_platform_data pcm037_nand_board_info
= {
253 #ifdef CONFIG_I2C_IMX
254 static struct imxi2c_platform_data pcm037_i2c_1_data
= {
258 static struct at24_platform_data board_eeprom
= {
261 .flags
= AT24_FLAG_ADDR16
,
264 static struct i2c_board_info pcm037_i2c_devices
[] = {
266 I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
267 .platform_data
= &board_eeprom
,
269 I2C_BOARD_INFO("rtc-pcf8563", 0x51),
275 /* Not connected by default */
276 #ifdef PCM970_SDHC_RW_SWITCH
277 static int pcm970_sdhc1_get_ro(struct device
*dev
)
279 return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_SFS6
));
283 #define SDHC1_GPIO_WP IOMUX_TO_GPIO(MX31_PIN_SFS6)
284 #define SDHC1_GPIO_DET IOMUX_TO_GPIO(MX31_PIN_SCK6)
286 static int pcm970_sdhc1_init(struct device
*dev
, irq_handler_t detect_irq
,
291 ret
= gpio_request(SDHC1_GPIO_DET
, "sdhc-detect");
295 gpio_direction_input(SDHC1_GPIO_DET
);
297 #ifdef PCM970_SDHC_RW_SWITCH
298 ret
= gpio_request(SDHC1_GPIO_WP
, "sdhc-wp");
301 gpio_direction_input(SDHC1_GPIO_WP
);
304 ret
= request_irq(IOMUX_TO_IRQ(MX31_PIN_SCK6
), detect_irq
,
305 IRQF_DISABLED
| IRQF_TRIGGER_FALLING
,
306 "sdhc-detect", data
);
308 goto err_gpio_free_2
;
313 #ifdef PCM970_SDHC_RW_SWITCH
314 gpio_free(SDHC1_GPIO_WP
);
317 gpio_free(SDHC1_GPIO_DET
);
322 static void pcm970_sdhc1_exit(struct device
*dev
, void *data
)
324 free_irq(IOMUX_TO_IRQ(MX31_PIN_SCK6
), data
);
325 gpio_free(SDHC1_GPIO_DET
);
326 gpio_free(SDHC1_GPIO_WP
);
329 static struct imxmmc_platform_data sdhc_pdata
= {
330 #ifdef PCM970_SDHC_RW_SWITCH
331 .get_ro
= pcm970_sdhc1_get_ro
,
333 .init
= pcm970_sdhc1_init
,
334 .exit
= pcm970_sdhc1_exit
,
337 static struct platform_device
*devices
[] __initdata
= {
342 static struct ipu_platform_data mx3_ipu_data
= {
343 .irq_base
= MXC_IPU_IRQ_START
,
346 static const struct fb_videomode fb_modedb
[] = {
348 /* 240x320 @ 60 Hz Sharp */
349 .name
= "Sharp-LQ035Q7DH06-QVGA",
360 .sync
= FB_SYNC_HOR_HIGH_ACT
| FB_SYNC_SHARP_MODE
|
361 FB_SYNC_CLK_INVERT
| FB_SYNC_CLK_IDLE_EN
,
362 .vmode
= FB_VMODE_NONINTERLACED
,
365 /* 240x320 @ 60 Hz */
377 .sync
= FB_SYNC_VERT_HIGH_ACT
| FB_SYNC_OE_ACT_HIGH
,
378 .vmode
= FB_VMODE_NONINTERLACED
,
383 static struct mx3fb_platform_data mx3fb_pdata
= {
384 .dma_dev
= &mx3_ipu
.dev
,
385 .name
= "Sharp-LQ035Q7DH06-QVGA",
387 .num_modes
= ARRAY_SIZE(fb_modedb
),
391 * Board specific initialization.
393 static void __init
mxc_board_init(void)
397 mxc_iomux_setup_multiple_pins(pcm037_pins
, ARRAY_SIZE(pcm037_pins
),
400 platform_add_devices(devices
, ARRAY_SIZE(devices
));
402 mxc_register_device(&mxc_uart_device0
, &uart_pdata
);
403 mxc_register_device(&mxc_uart_device1
, &uart_pdata
);
404 mxc_register_device(&mxc_uart_device2
, &uart_pdata
);
406 mxc_register_device(&mxc_w1_master_device
, NULL
);
408 /* LAN9217 IRQ pin */
409 ret
= gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1
), "lan9217-irq");
411 pr_warning("could not get LAN irq gpio\n");
413 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1
));
414 platform_device_register(&pcm037_eth
);
418 #ifdef CONFIG_I2C_IMX
419 i2c_register_board_info(1, pcm037_i2c_devices
,
420 ARRAY_SIZE(pcm037_i2c_devices
));
422 mxc_register_device(&mxc_i2c_device1
, &pcm037_i2c_1_data
);
424 mxc_register_device(&mxc_nand_device
, &pcm037_nand_board_info
);
425 mxc_register_device(&mxcsdhc_device0
, &sdhc_pdata
);
426 mxc_register_device(&mx3_ipu
, &mx3_ipu_data
);
427 mxc_register_device(&mx3_fb
, &mx3fb_pdata
);
428 if (!gpio_usbotg_hs_activate())
429 mxc_register_device(&mxc_otg_udc_device
, &usb_pdata
);
432 static void __init
pcm037_timer_init(void)
434 mx31_clocks_init(26000000);
437 struct sys_timer pcm037_timer
= {
438 .init
= pcm037_timer_init
,
441 MACHINE_START(PCM037
, "Phytec Phycore pcm037")
442 /* Maintainer: Pengutronix */
443 .phys_io
= AIPS1_BASE_ADDR
,
444 .io_pg_offst
= ((AIPS1_BASE_ADDR_VIRT
) >> 18) & 0xfffc,
445 .boot_params
= PHYS_OFFSET
+ 0x100,
446 .map_io
= mx31_map_io
,
447 .init_irq
= mxc_init_irq
,
448 .init_machine
= mxc_board_init
,
449 .timer
= &pcm037_timer
,