arch/arm/plat-omap/sram.c

   1 /*
   2  * linux/arch/arm/plat-omap/sram.c
   3  *
   4  * OMAP SRAM detection and management
   5  *
   6  * Copyright (C) 2005 Nokia Corporation
   7  * Written by Tony Lindgren <tony@atomide.com>
   8  *
   9  * Copyright (C) 2009 Texas Instruments
  10  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16 #undef DEBUG
  17
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/init.h>
  21 #include <linux/io.h>
  22
  23 #include <asm/tlb.h>
  24 #include <asm/cacheflush.h>
  25
  26 #include <asm/mach/map.h>
  27
  28 #include <mach/sram.h>
  29 #include <mach/board.h>
  30 #include <mach/cpu.h>
  31
  32 #include <mach/control.h>
  33
  34 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
  35 # include "../mach-omap2/prm.h"
  36 # include "../mach-omap2/cm.h"
  37 # include "../mach-omap2/sdrc.h"
  38 #endif
  39
  40 #define OMAP1_SRAM_PA           0x20000000
  41 #define OMAP1_SRAM_VA           VMALLOC_END
  42 #define OMAP2_SRAM_PA           0x40200000
  43 #define OMAP2_SRAM_PUB_PA       0x4020f800
  44 #define OMAP2_SRAM_VA           0xe3000000
  45 #define OMAP2_SRAM_PUB_VA       (OMAP2_SRAM_VA + 0x800)
  46 #define OMAP3_SRAM_PA           0x40200000
  47 #define OMAP3_SRAM_VA           0xd7000000
  48 #define OMAP3_SRAM_PUB_PA       0x40208000
  49 #define OMAP3_SRAM_PUB_VA       0xd7008000
  50 #define OMAP4_SRAM_PA           0x40200000              /*0x402f0000*/
  51 #define OMAP4_SRAM_VA           0xd7000000              /*0xd70f0000*/
  52
  53 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
  54 #define SRAM_BOOTLOADER_SZ      0x00
  55 #else
  56 #define SRAM_BOOTLOADER_SZ      0x80
  57 #endif
  58
  59 #define OMAP24XX_VA_REQINFOPERM0        IO_ADDRESS(0x68005048)
  60 #define OMAP24XX_VA_READPERM0           IO_ADDRESS(0x68005050)
  61 #define OMAP24XX_VA_WRITEPERM0          IO_ADDRESS(0x68005058)
  62
  63 #define OMAP34XX_VA_REQINFOPERM0        IO_ADDRESS(0x68012848)
  64 #define OMAP34XX_VA_READPERM0           IO_ADDRESS(0x68012850)
  65 #define OMAP34XX_VA_WRITEPERM0          IO_ADDRESS(0x68012858)
  66 #define OMAP34XX_VA_ADDR_MATCH2         IO_ADDRESS(0x68012880)
  67 #define OMAP34XX_VA_SMS_RG_ATT0         IO_ADDRESS(0x6C000048)
  68 #define OMAP34XX_VA_CONTROL_STAT        IO_ADDRESS(0x480022F0)
  69
  70 #define GP_DEVICE               0x300
  71
  72 #define ROUND_DOWN(value,boundary)      ((value) & (~((boundary)-1)))
  73
  74 static unsigned long omap_sram_start;
  75 static unsigned long omap_sram_base;
  76 static unsigned long omap_sram_size;
  77 static unsigned long omap_sram_ceil;
  78
  79 extern unsigned long omapfb_reserve_sram(unsigned long sram_pstart,
  80                                          unsigned long sram_vstart,
  81                                          unsigned long sram_size,
  82                                          unsigned long pstart_avail,
  83                                          unsigned long size_avail);
  84
  85 /*
  86  * Depending on the target RAMFS firewall setup, the public usable amount of
  87  * SRAM varies.  The default accessible size for all device types is 2k. A GP
  88  * device allows ARM11 but not other initiators for full size. This
  89  * functionality seems ok until some nice security API happens.
  90  */
  91 static int is_sram_locked(void)
  92 {
  93         int type = 0;
  94
  95         if (cpu_is_omap44xx())
  96                 /* Not yet supported */
  97                 return 0;
  98
  99         if (cpu_is_omap242x())
 100                 type = omap_rev() & OMAP2_DEVICETYPE_MASK;
 101
 102         if (type == GP_DEVICE) {
 103                 /* RAMFW: R/W access to all initiators for all qualifier sets */
 104                 if (cpu_is_omap242x()) {
 105                         __raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
 106                         __raw_writel(0xCFDE, OMAP24XX_VA_READPERM0);  /* all i-read */
 107                         __raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
 108                 }
 109                 if (cpu_is_omap34xx()) {
 110                         __raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
 111                         __raw_writel(0xFFFF, OMAP34XX_VA_READPERM0);  /* all i-read */
 112                         __raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
 113                         __raw_writel(0x0, OMAP34XX_VA_ADDR_MATCH2);
 114                         __raw_writel(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
 115                 }
 116                 return 0;
 117         } else
 118                 return 1; /* assume locked with no PPA or security driver */
 119 }
 120
 121 /*
 122  * The amount of SRAM depends on the core type.
 123  * Note that we cannot try to test for SRAM here because writes
 124  * to secure SRAM will hang the system. Also the SRAM is not
 125  * yet mapped at this point.
 126  */
 127 void __init omap_detect_sram(void)
 128 {
 129         unsigned long reserved;
 130
 131         if (cpu_class_is_omap2()) {
 132                 if (is_sram_locked()) {
 133                         if (cpu_is_omap34xx()) {
 134                                 omap_sram_base = OMAP3_SRAM_PUB_VA;
 135                                 omap_sram_start = OMAP3_SRAM_PUB_PA;
 136                                 omap_sram_size = 0x8000; /* 32K */
 137                         } else {
 138                                 omap_sram_base = OMAP2_SRAM_PUB_VA;
 139                                 omap_sram_start = OMAP2_SRAM_PUB_PA;
 140                                 omap_sram_size = 0x800; /* 2K */
 141                         }
 142                 } else {
 143                         if (cpu_is_omap34xx()) {
 144                                 omap_sram_base = OMAP3_SRAM_VA;
 145                                 omap_sram_start = OMAP3_SRAM_PA;
 146                                 omap_sram_size = 0x10000; /* 64K */
 147                         } else if (cpu_is_omap44xx()) {
 148                                 omap_sram_base = OMAP4_SRAM_VA;
 149                                 omap_sram_start = OMAP4_SRAM_PA;
 150                                 omap_sram_size = 0x8000; /* 32K */
 151                         } else {
 152                                 omap_sram_base = OMAP2_SRAM_VA;
 153                                 omap_sram_start = OMAP2_SRAM_PA;
 154                                 if (cpu_is_omap242x())
 155                                         omap_sram_size = 0xa0000; /* 640K */
 156                                 else if (cpu_is_omap243x())
 157                                         omap_sram_size = 0x10000; /* 64K */
 158                         }
 159                 }
 160         } else {
 161                 omap_sram_base = OMAP1_SRAM_VA;
 162                 omap_sram_start = OMAP1_SRAM_PA;
 163
 164                 if (cpu_is_omap7xx())
 165                         omap_sram_size = 0x32000;       /* 200K */
 166                 else if (cpu_is_omap15xx())
 167                         omap_sram_size = 0x30000;       /* 192K */
 168                 else if (cpu_is_omap1610() || cpu_is_omap1621() ||
 169                      cpu_is_omap1710())
 170                         omap_sram_size = 0x4000;        /* 16K */
 171                 else if (cpu_is_omap1611())
 172                         omap_sram_size = 0x3e800;       /* 250K */
 173                 else {
 174                         printk(KERN_ERR "Could not detect SRAM size\n");
 175                         omap_sram_size = 0x4000;
 176                 }
 177         }
 178         reserved = omapfb_reserve_sram(omap_sram_start, omap_sram_base,
 179                                        omap_sram_size,
 180                                        omap_sram_start + SRAM_BOOTLOADER_SZ,
 181                                        omap_sram_size - SRAM_BOOTLOADER_SZ);
 182         omap_sram_size -= reserved;
 183         omap_sram_ceil = omap_sram_base + omap_sram_size;
 184 }
 185
 186 static struct map_desc omap_sram_io_desc[] __initdata = {
 187         {       /* .length gets filled in at runtime */
 188                 .virtual        = OMAP1_SRAM_VA,
 189                 .pfn            = __phys_to_pfn(OMAP1_SRAM_PA),
 190                 .type           = MT_MEMORY
 191         }
 192 };
 193
 194 /*
 195  * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
 196  */
 197 void __init omap_map_sram(void)
 198 {
 199         unsigned long base;
 200
 201         if (omap_sram_size == 0)
 202                 return;
 203
 204         if (cpu_is_omap24xx()) {
 205                 omap_sram_io_desc[0].virtual = OMAP2_SRAM_VA;
 206
 207                 base = OMAP2_SRAM_PA;
 208                 base = ROUND_DOWN(base, PAGE_SIZE);
 209                 omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
 210         }
 211
 212         if (cpu_is_omap34xx()) {
 213                 omap_sram_io_desc[0].virtual = OMAP3_SRAM_VA;
 214                 base = OMAP3_SRAM_PA;
 215                 base = ROUND_DOWN(base, PAGE_SIZE);
 216                 omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
 217
 218                 /*
 219                  * SRAM must be marked as non-cached on OMAP3 since the
 220                  * CORE DPLL M2 divider change code (in SRAM) runs with the
 221                  * SDRAM controller disabled, and if it is marked cached,
 222                  * the ARM may attempt to write cache lines back to SDRAM
 223                  * which will cause the system to hang.
 224                  */
 225                 omap_sram_io_desc[0].type = MT_MEMORY_NONCACHED;
 226         }
 227
 228         if (cpu_is_omap44xx()) {
 229                 omap_sram_io_desc[0].virtual = OMAP4_SRAM_VA;
 230                 base = OMAP4_SRAM_PA;
 231                 base = ROUND_DOWN(base, PAGE_SIZE);
 232                 omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
 233         }
 234         omap_sram_io_desc[0].length = 1024 * 1024;      /* Use section desc */
 235         iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc));
 236
 237         printk(KERN_INFO "SRAM: Mapped pa 0x%08lx to va 0x%08lx size: 0x%lx\n",
 238         __pfn_to_phys(omap_sram_io_desc[0].pfn),
 239         omap_sram_io_desc[0].virtual,
 240                omap_sram_io_desc[0].length);
 241
 242         /*
 243          * Normally devicemaps_init() would flush caches and tlb after
 244          * mdesc->map_io(), but since we're called from map_io(), we
 245          * must do it here.
 246          */
 247         local_flush_tlb_all();
 248         flush_cache_all();
 249
 250         /*
 251          * Looks like we need to preserve some bootloader code at the
 252          * beginning of SRAM for jumping to flash for reboot to work...
 253          */
 254         memset((void *)omap_sram_base + SRAM_BOOTLOADER_SZ, 0,
 255                omap_sram_size - SRAM_BOOTLOADER_SZ);
 256 }
 257
 258 void * omap_sram_push(void * start, unsigned long size)
 259 {
 260         if (size > (omap_sram_ceil - (omap_sram_base + SRAM_BOOTLOADER_SZ))) {
 261                 printk(KERN_ERR "Not enough space in SRAM\n");
 262                 return NULL;
 263         }
 264
 265         omap_sram_ceil -= size;
 266         omap_sram_ceil = ROUND_DOWN(omap_sram_ceil, sizeof(void *));
 267         memcpy((void *)omap_sram_ceil, start, size);
 268         flush_icache_range((unsigned long)start, (unsigned long)(start + size));
 269
 270         return (void *)omap_sram_ceil;
 271 }
 272
 273 #ifdef CONFIG_ARCH_OMAP1
 274
 275 static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl);
 276
 277 void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)
 278 {
 279         BUG_ON(!_omap_sram_reprogram_clock);
 280         _omap_sram_reprogram_clock(dpllctl, ckctl);
 281 }
 282
 283 int __init omap1_sram_init(void)
 284 {
 285         _omap_sram_reprogram_clock =
 286                         omap_sram_push(omap1_sram_reprogram_clock,
 287                                         omap1_sram_reprogram_clock_sz);
 288
 289         return 0;
 290 }
 291
 292 #else
 293 #define omap1_sram_init()       do {} while (0)
 294 #endif
 295
 296 #if defined(CONFIG_ARCH_OMAP2)
 297
 298 static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
 299                               u32 base_cs, u32 force_unlock);
 300
 301 void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
 302                    u32 base_cs, u32 force_unlock)
 303 {
 304         BUG_ON(!_omap2_sram_ddr_init);
 305         _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
 306                              base_cs, force_unlock);
 307 }
 308
 309 static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val,
 310                                           u32 mem_type);
 311
 312 void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type)
 313 {
 314         BUG_ON(!_omap2_sram_reprogram_sdrc);
 315         _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
 316 }
 317
 318 static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
 319
 320 u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
 321 {
 322         BUG_ON(!_omap2_set_prcm);
 323         return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
 324 }
 325 #endif
 326
 327 #ifdef CONFIG_ARCH_OMAP2420
 328 int __init omap242x_sram_init(void)
 329 {
 330         _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
 331                                         omap242x_sram_ddr_init_sz);
 332
 333         _omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc,
 334                                             omap242x_sram_reprogram_sdrc_sz);
 335
 336         _omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm,
 337                                          omap242x_sram_set_prcm_sz);
 338
 339         return 0;
 340 }
 341 #else
 342 static inline int omap242x_sram_init(void)
 343 {
 344         return 0;
 345 }
 346 #endif
 347
 348 #ifdef CONFIG_ARCH_OMAP2430
 349 int __init omap243x_sram_init(void)
 350 {
 351         _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
 352                                         omap243x_sram_ddr_init_sz);
 353
 354         _omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc,
 355                                             omap243x_sram_reprogram_sdrc_sz);
 356
 357         _omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm,
 358                                          omap243x_sram_set_prcm_sz);
 359
 360         return 0;
 361 }
 362 #else
 363 static inline int omap243x_sram_init(void)
 364 {
 365         return 0;
 366 }
 367 #endif
 368
 369 #ifdef CONFIG_ARCH_OMAP3
 370
 371 static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl,
 372                                               u32 sdrc_actim_ctrla,
 373                                               u32 sdrc_actim_ctrlb,
 374                                               u32 m2, u32 unlock_dll);
 375 u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla,
 376                               u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll)
 377 {
 378         BUG_ON(!_omap3_sram_configure_core_dpll);
 379         return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl,
 380                                                sdrc_actim_ctrla,
 381                                                sdrc_actim_ctrlb, m2,
 382                                                unlock_dll);
 383 }
 384
 385 /* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */
 386 void restore_sram_functions(void)
 387 {
 388         omap_sram_ceil = omap_sram_base + omap_sram_size;
 389
 390         _omap3_sram_configure_core_dpll =
 391                 omap_sram_push(omap3_sram_configure_core_dpll,
 392                                omap3_sram_configure_core_dpll_sz);
 393 }
 394
 395 int __init omap34xx_sram_init(void)
 396 {
 397         _omap3_sram_configure_core_dpll =
 398                 omap_sram_push(omap3_sram_configure_core_dpll,
 399                                omap3_sram_configure_core_dpll_sz);
 400
 401         return 0;
 402 }
 403 #else
 404 static inline int omap34xx_sram_init(void)
 405 {
 406         return 0;
 407 }
 408 #endif
 409
 410 int __init omap_sram_init(void)
 411 {
 412         omap_detect_sram();
 413         omap_map_sram();
 414
 415         if (!(cpu_class_is_omap2()))
 416                 omap1_sram_init();
 417         else if (cpu_is_omap242x())
 418                 omap242x_sram_init();
 419         else if (cpu_is_omap2430())
 420                 omap243x_sram_init();
 421         else if (cpu_is_omap34xx())
 422                 omap34xx_sram_init();
 423         else if (cpu_is_omap44xx())
 424                 omap34xx_sram_init(); /* FIXME: */
 425
 426         return 0;
 427 }