1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018 MediaTek Inc.
5 * Author: Sean Wang <sean.wang@mediatek.com>
9 #include <dt-bindings/pinctrl/mt65xx.h>
10 #include <linux/device.h>
11 #include <linux/err.h>
12 #include <linux/gpio/driver.h>
13 #include <linux/platform_device.h>
15 #include <linux/module.h>
16 #include <linux/of_irq.h>
19 #include "pinctrl-mtk-common-v2.h"
22 * struct mtk_drive_desc - the structure that holds the information
23 * of the driving current
24 * @min: the minimum current of this group
25 * @max: the maximum current of this group
26 * @step: the step current of this group
27 * @scal: the weight factor
29 * formula: output = ((input) / step - 1) * scal
31 struct mtk_drive_desc
{
38 /* The groups of drive strength */
39 static const struct mtk_drive_desc mtk_drive
[] = {
40 [DRV_GRP0
] = { 4, 16, 4, 1 },
41 [DRV_GRP1
] = { 4, 16, 4, 2 },
42 [DRV_GRP2
] = { 2, 8, 2, 1 },
43 [DRV_GRP3
] = { 2, 8, 2, 2 },
44 [DRV_GRP4
] = { 2, 16, 2, 1 },
47 static void mtk_w32(struct mtk_pinctrl
*pctl
, u8 i
, u32 reg
, u32 val
)
49 writel_relaxed(val
, pctl
->base
[i
] + reg
);
52 static u32
mtk_r32(struct mtk_pinctrl
*pctl
, u8 i
, u32 reg
)
54 return readl_relaxed(pctl
->base
[i
] + reg
);
57 void mtk_rmw(struct mtk_pinctrl
*pctl
, u8 i
, u32 reg
, u32 mask
, u32 set
)
61 val
= mtk_r32(pctl
, i
, reg
);
64 mtk_w32(pctl
, i
, reg
, val
);
67 static int mtk_hw_pin_field_lookup(struct mtk_pinctrl
*hw
,
68 const struct mtk_pin_desc
*desc
,
69 int field
, struct mtk_pin_field
*pfd
)
71 const struct mtk_pin_field_calc
*c
;
72 const struct mtk_pin_reg_calc
*rc
;
73 int start
= 0, end
, check
;
77 if (hw
->soc
->reg_cal
&& hw
->soc
->reg_cal
[field
].range
) {
78 rc
= &hw
->soc
->reg_cal
[field
];
81 "Not support field %d for this soc\n", field
);
85 end
= rc
->nranges
- 1;
87 while (start
<= end
) {
88 check
= (start
+ end
) >> 1;
89 if (desc
->number
>= rc
->range
[check
].s_pin
90 && desc
->number
<= rc
->range
[check
].e_pin
) {
93 } else if (start
== end
)
95 else if (desc
->number
< rc
->range
[check
].s_pin
)
102 dev_dbg(hw
->dev
, "Not support field %d for pin = %d (%s)\n",
103 field
, desc
->number
, desc
->name
);
107 c
= rc
->range
+ check
;
109 if (c
->i_base
> hw
->nbase
- 1) {
111 "Invalid base for field %d for pin = %d (%s)\n",
112 field
, desc
->number
, desc
->name
);
116 /* Calculated bits as the overall offset the pin is located at,
117 * if c->fixed is held, that determines the all the pins in the
118 * range use the same field with the s_pin.
120 bits
= c
->fixed
? c
->s_bit
: c
->s_bit
+
121 (desc
->number
- c
->s_pin
) * (c
->x_bits
);
123 /* Fill pfd from bits. For example 32-bit register applied is assumed
124 * when c->sz_reg is equal to 32.
126 pfd
->index
= c
->i_base
;
127 pfd
->offset
= c
->s_addr
+ c
->x_addrs
* (bits
/ c
->sz_reg
);
128 pfd
->bitpos
= bits
% c
->sz_reg
;
129 pfd
->mask
= (1 << c
->x_bits
) - 1;
131 /* pfd->next is used for indicating that bit wrapping-around happens
132 * which requires the manipulation for bit 0 starting in the next
133 * register to form the complete field read/write.
135 pfd
->next
= pfd
->bitpos
+ c
->x_bits
> c
->sz_reg
? c
->x_addrs
: 0;
140 static int mtk_hw_pin_field_get(struct mtk_pinctrl
*hw
,
141 const struct mtk_pin_desc
*desc
,
142 int field
, struct mtk_pin_field
*pfd
)
144 if (field
< 0 || field
>= PINCTRL_PIN_REG_MAX
) {
145 dev_err(hw
->dev
, "Invalid Field %d\n", field
);
149 return mtk_hw_pin_field_lookup(hw
, desc
, field
, pfd
);
152 static void mtk_hw_bits_part(struct mtk_pin_field
*pf
, int *h
, int *l
)
154 *l
= 32 - pf
->bitpos
;
155 *h
= get_count_order(pf
->mask
) - *l
;
158 static void mtk_hw_write_cross_field(struct mtk_pinctrl
*hw
,
159 struct mtk_pin_field
*pf
, int value
)
161 int nbits_l
, nbits_h
;
163 mtk_hw_bits_part(pf
, &nbits_h
, &nbits_l
);
165 mtk_rmw(hw
, pf
->index
, pf
->offset
, pf
->mask
<< pf
->bitpos
,
166 (value
& pf
->mask
) << pf
->bitpos
);
168 mtk_rmw(hw
, pf
->index
, pf
->offset
+ pf
->next
, BIT(nbits_h
) - 1,
169 (value
& pf
->mask
) >> nbits_l
);
172 static void mtk_hw_read_cross_field(struct mtk_pinctrl
*hw
,
173 struct mtk_pin_field
*pf
, int *value
)
175 int nbits_l
, nbits_h
, h
, l
;
177 mtk_hw_bits_part(pf
, &nbits_h
, &nbits_l
);
179 l
= (mtk_r32(hw
, pf
->index
, pf
->offset
)
180 >> pf
->bitpos
) & (BIT(nbits_l
) - 1);
181 h
= (mtk_r32(hw
, pf
->index
, pf
->offset
+ pf
->next
))
182 & (BIT(nbits_h
) - 1);
184 *value
= (h
<< nbits_l
) | l
;
187 int mtk_hw_set_value(struct mtk_pinctrl
*hw
, const struct mtk_pin_desc
*desc
,
188 int field
, int value
)
190 struct mtk_pin_field pf
;
193 err
= mtk_hw_pin_field_get(hw
, desc
, field
, &pf
);
197 if (value
< 0 || value
> pf
.mask
)
201 mtk_rmw(hw
, pf
.index
, pf
.offset
, pf
.mask
<< pf
.bitpos
,
202 (value
& pf
.mask
) << pf
.bitpos
);
204 mtk_hw_write_cross_field(hw
, &pf
, value
);
208 EXPORT_SYMBOL_GPL(mtk_hw_set_value
);
210 int mtk_hw_get_value(struct mtk_pinctrl
*hw
, const struct mtk_pin_desc
*desc
,
211 int field
, int *value
)
213 struct mtk_pin_field pf
;
216 err
= mtk_hw_pin_field_get(hw
, desc
, field
, &pf
);
221 *value
= (mtk_r32(hw
, pf
.index
, pf
.offset
)
222 >> pf
.bitpos
) & pf
.mask
;
224 mtk_hw_read_cross_field(hw
, &pf
, value
);
228 EXPORT_SYMBOL_GPL(mtk_hw_get_value
);
230 static int mtk_xt_find_eint_num(struct mtk_pinctrl
*hw
, unsigned long eint_n
)
232 const struct mtk_pin_desc
*desc
;
235 desc
= (const struct mtk_pin_desc
*)hw
->soc
->pins
;
237 while (i
< hw
->soc
->npins
) {
238 if (desc
[i
].eint
.eint_n
== eint_n
)
239 return desc
[i
].number
;
247 * Virtual GPIO only used inside SOC and not being exported to outside SOC.
248 * Some modules use virtual GPIO as eint (e.g. pmif or usb).
249 * In MTK platform, external interrupt (EINT) and GPIO is 1-1 mapping
250 * and we can set GPIO as eint.
251 * But some modules use specific eint which doesn't have real GPIO pin.
252 * So we use virtual GPIO to map it.
255 bool mtk_is_virt_gpio(struct mtk_pinctrl
*hw
, unsigned int gpio_n
)
257 const struct mtk_pin_desc
*desc
;
258 bool virt_gpio
= false;
260 desc
= (const struct mtk_pin_desc
*)&hw
->soc
->pins
[gpio_n
];
262 if (desc
->funcs
&& !desc
->funcs
[desc
->eint
.eint_m
].name
)
267 EXPORT_SYMBOL_GPL(mtk_is_virt_gpio
);
269 static int mtk_xt_get_gpio_n(void *data
, unsigned long eint_n
,
270 unsigned int *gpio_n
,
271 struct gpio_chip
**gpio_chip
)
273 struct mtk_pinctrl
*hw
= (struct mtk_pinctrl
*)data
;
274 const struct mtk_pin_desc
*desc
;
276 desc
= (const struct mtk_pin_desc
*)hw
->soc
->pins
;
277 *gpio_chip
= &hw
->chip
;
279 /* Be greedy to guess first gpio_n is equal to eint_n */
280 if (desc
[eint_n
].eint
.eint_n
== eint_n
)
283 *gpio_n
= mtk_xt_find_eint_num(hw
, eint_n
);
285 return *gpio_n
== EINT_NA
? -EINVAL
: 0;
288 static int mtk_xt_get_gpio_state(void *data
, unsigned long eint_n
)
290 struct mtk_pinctrl
*hw
= (struct mtk_pinctrl
*)data
;
291 const struct mtk_pin_desc
*desc
;
292 struct gpio_chip
*gpio_chip
;
296 err
= mtk_xt_get_gpio_n(hw
, eint_n
, &gpio_n
, &gpio_chip
);
300 desc
= (const struct mtk_pin_desc
*)&hw
->soc
->pins
[gpio_n
];
302 err
= mtk_hw_get_value(hw
, desc
, PINCTRL_PIN_REG_DI
, &value
);
309 static int mtk_xt_set_gpio_as_eint(void *data
, unsigned long eint_n
)
311 struct mtk_pinctrl
*hw
= (struct mtk_pinctrl
*)data
;
312 const struct mtk_pin_desc
*desc
;
313 struct gpio_chip
*gpio_chip
;
317 err
= mtk_xt_get_gpio_n(hw
, eint_n
, &gpio_n
, &gpio_chip
);
321 if (mtk_is_virt_gpio(hw
, gpio_n
))
324 desc
= (const struct mtk_pin_desc
*)&hw
->soc
->pins
[gpio_n
];
326 err
= mtk_hw_set_value(hw
, desc
, PINCTRL_PIN_REG_MODE
,
331 err
= mtk_hw_set_value(hw
, desc
, PINCTRL_PIN_REG_DIR
, MTK_INPUT
);
335 err
= mtk_hw_set_value(hw
, desc
, PINCTRL_PIN_REG_SMT
, MTK_ENABLE
);
336 /* SMT is supposed to be supported by every real GPIO and doesn't
337 * support virtual GPIOs, so the extra condition err != -ENOTSUPP
338 * is just for adding EINT support to these virtual GPIOs. It should
339 * add an extra flag in the pin descriptor when more pins with
340 * distinctive characteristic come out.
342 if (err
&& err
!= -ENOTSUPP
)
348 static const struct mtk_eint_xt mtk_eint_xt
= {
349 .get_gpio_n
= mtk_xt_get_gpio_n
,
350 .get_gpio_state
= mtk_xt_get_gpio_state
,
351 .set_gpio_as_eint
= mtk_xt_set_gpio_as_eint
,
354 int mtk_build_eint(struct mtk_pinctrl
*hw
, struct platform_device
*pdev
)
356 struct device_node
*np
= pdev
->dev
.of_node
;
357 struct resource
*res
;
359 if (!IS_ENABLED(CONFIG_EINT_MTK
))
362 if (!of_property_read_bool(np
, "interrupt-controller"))
365 hw
->eint
= devm_kzalloc(hw
->dev
, sizeof(*hw
->eint
), GFP_KERNEL
);
369 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "eint");
371 dev_err(&pdev
->dev
, "Unable to get eint resource\n");
375 hw
->eint
->base
= devm_ioremap_resource(&pdev
->dev
, res
);
376 if (IS_ERR(hw
->eint
->base
))
377 return PTR_ERR(hw
->eint
->base
);
379 hw
->eint
->irq
= irq_of_parse_and_map(np
, 0);
383 if (!hw
->soc
->eint_hw
)
386 hw
->eint
->dev
= &pdev
->dev
;
387 hw
->eint
->hw
= hw
->soc
->eint_hw
;
389 hw
->eint
->gpio_xlate
= &mtk_eint_xt
;
391 return mtk_eint_do_init(hw
->eint
);
393 EXPORT_SYMBOL_GPL(mtk_build_eint
);
396 int mtk_pinconf_bias_disable_set(struct mtk_pinctrl
*hw
,
397 const struct mtk_pin_desc
*desc
)
401 err
= mtk_hw_set_value(hw
, desc
, PINCTRL_PIN_REG_PU
,
406 err
= mtk_hw_set_value(hw
, desc
, PINCTRL_PIN_REG_PD
,
413 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_disable_set
);
415 int mtk_pinconf_bias_disable_get(struct mtk_pinctrl
*hw
,
416 const struct mtk_pin_desc
*desc
, int *res
)
421 err
= mtk_hw_get_value(hw
, desc
, PINCTRL_PIN_REG_PU
, &v
);
425 err
= mtk_hw_get_value(hw
, desc
, PINCTRL_PIN_REG_PD
, &v2
);
429 if (v
== MTK_ENABLE
|| v2
== MTK_ENABLE
)
436 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_disable_get
);
438 int mtk_pinconf_bias_set(struct mtk_pinctrl
*hw
,
439 const struct mtk_pin_desc
*desc
, bool pullup
)
443 arg
= pullup
? 1 : 2;
445 err
= mtk_hw_set_value(hw
, desc
, PINCTRL_PIN_REG_PU
, arg
& 1);
449 err
= mtk_hw_set_value(hw
, desc
, PINCTRL_PIN_REG_PD
,
456 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_set
);
458 int mtk_pinconf_bias_get(struct mtk_pinctrl
*hw
,
459 const struct mtk_pin_desc
*desc
, bool pullup
, int *res
)
463 reg
= pullup
? PINCTRL_PIN_REG_PU
: PINCTRL_PIN_REG_PD
;
465 err
= mtk_hw_get_value(hw
, desc
, reg
, &v
);
476 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_get
);
479 int mtk_pinconf_bias_disable_set_rev1(struct mtk_pinctrl
*hw
,
480 const struct mtk_pin_desc
*desc
)
484 err
= mtk_hw_set_value(hw
, desc
, PINCTRL_PIN_REG_PULLEN
,
491 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_disable_set_rev1
);
493 int mtk_pinconf_bias_disable_get_rev1(struct mtk_pinctrl
*hw
,
494 const struct mtk_pin_desc
*desc
, int *res
)
498 err
= mtk_hw_get_value(hw
, desc
, PINCTRL_PIN_REG_PULLEN
, &v
);
509 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_disable_get_rev1
);
511 int mtk_pinconf_bias_set_rev1(struct mtk_pinctrl
*hw
,
512 const struct mtk_pin_desc
*desc
, bool pullup
)
516 arg
= pullup
? MTK_PULLUP
: MTK_PULLDOWN
;
518 err
= mtk_hw_set_value(hw
, desc
, PINCTRL_PIN_REG_PULLEN
,
523 err
= mtk_hw_set_value(hw
, desc
, PINCTRL_PIN_REG_PULLSEL
, arg
);
529 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_set_rev1
);
531 int mtk_pinconf_bias_get_rev1(struct mtk_pinctrl
*hw
,
532 const struct mtk_pin_desc
*desc
, bool pullup
,
537 err
= mtk_hw_get_value(hw
, desc
, PINCTRL_PIN_REG_PULLEN
, &v
);
541 if (v
== MTK_DISABLE
)
544 err
= mtk_hw_get_value(hw
, desc
, PINCTRL_PIN_REG_PULLSEL
, &v
);
548 if (pullup
^ (v
== MTK_PULLUP
))
555 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_get_rev1
);
557 /* Combo for the following pull register type:
559 * 2. PULLSEL + PULLEN
562 static int mtk_pinconf_bias_set_pu_pd(struct mtk_pinctrl
*hw
,
563 const struct mtk_pin_desc
*desc
,
568 if (arg
== MTK_DISABLE
) {
571 } else if ((arg
== MTK_ENABLE
) && pullup
) {
574 } else if ((arg
== MTK_ENABLE
) && !pullup
) {
582 err
= mtk_hw_set_value(hw
, desc
, PINCTRL_PIN_REG_PU
, pu
);
586 err
= mtk_hw_set_value(hw
, desc
, PINCTRL_PIN_REG_PD
, pd
);
592 static int mtk_pinconf_bias_set_pullsel_pullen(struct mtk_pinctrl
*hw
,
593 const struct mtk_pin_desc
*desc
,
598 if (arg
== MTK_DISABLE
)
600 else if (arg
== MTK_ENABLE
)
607 err
= mtk_hw_set_value(hw
, desc
, PINCTRL_PIN_REG_PULLEN
, enable
);
611 err
= mtk_hw_set_value(hw
, desc
, PINCTRL_PIN_REG_PULLSEL
, pullup
);
617 static int mtk_pinconf_bias_set_pupd_r1_r0(struct mtk_pinctrl
*hw
,
618 const struct mtk_pin_desc
*desc
,
623 if ((arg
== MTK_DISABLE
) || (arg
== MTK_PUPD_SET_R1R0_00
)) {
627 } else if (arg
== MTK_PUPD_SET_R1R0_01
) {
630 } else if (arg
== MTK_PUPD_SET_R1R0_10
) {
633 } else if (arg
== MTK_PUPD_SET_R1R0_11
) {
641 /* MTK HW PUPD bit: 1 for pull-down, 0 for pull-up */
642 err
= mtk_hw_set_value(hw
, desc
, PINCTRL_PIN_REG_PUPD
, !pullup
);
646 err
= mtk_hw_set_value(hw
, desc
, PINCTRL_PIN_REG_R0
, r0
);
650 err
= mtk_hw_set_value(hw
, desc
, PINCTRL_PIN_REG_R1
, r1
);
656 static int mtk_pinconf_bias_get_pu_pd(struct mtk_pinctrl
*hw
,
657 const struct mtk_pin_desc
*desc
,
658 u32
*pullup
, u32
*enable
)
662 err
= mtk_hw_get_value(hw
, desc
, PINCTRL_PIN_REG_PU
, &pu
);
666 err
= mtk_hw_get_value(hw
, desc
, PINCTRL_PIN_REG_PD
, &pd
);
670 if (pu
== 0 && pd
== 0) {
672 *enable
= MTK_DISABLE
;
673 } else if (pu
== 1 && pd
== 0) {
675 *enable
= MTK_ENABLE
;
676 } else if (pu
== 0 && pd
== 1) {
678 *enable
= MTK_ENABLE
;
686 static int mtk_pinconf_bias_get_pullsel_pullen(struct mtk_pinctrl
*hw
,
687 const struct mtk_pin_desc
*desc
,
688 u32
*pullup
, u32
*enable
)
692 err
= mtk_hw_get_value(hw
, desc
, PINCTRL_PIN_REG_PULLSEL
, pullup
);
696 err
= mtk_hw_get_value(hw
, desc
, PINCTRL_PIN_REG_PULLEN
, enable
);
702 static int mtk_pinconf_bias_get_pupd_r1_r0(struct mtk_pinctrl
*hw
,
703 const struct mtk_pin_desc
*desc
,
704 u32
*pullup
, u32
*enable
)
708 err
= mtk_hw_get_value(hw
, desc
, PINCTRL_PIN_REG_PUPD
, pullup
);
711 /* MTK HW PUPD bit: 1 for pull-down, 0 for pull-up */
712 *pullup
= !(*pullup
);
714 err
= mtk_hw_get_value(hw
, desc
, PINCTRL_PIN_REG_R0
, &r0
);
718 err
= mtk_hw_get_value(hw
, desc
, PINCTRL_PIN_REG_R1
, &r1
);
722 if ((r1
== 0) && (r0
== 0))
723 *enable
= MTK_PUPD_SET_R1R0_00
;
724 else if ((r1
== 0) && (r0
== 1))
725 *enable
= MTK_PUPD_SET_R1R0_01
;
726 else if ((r1
== 1) && (r0
== 0))
727 *enable
= MTK_PUPD_SET_R1R0_10
;
728 else if ((r1
== 1) && (r0
== 1))
729 *enable
= MTK_PUPD_SET_R1R0_11
;
737 int mtk_pinconf_bias_set_combo(struct mtk_pinctrl
*hw
,
738 const struct mtk_pin_desc
*desc
,
743 err
= mtk_pinconf_bias_set_pu_pd(hw
, desc
, pullup
, arg
);
747 err
= mtk_pinconf_bias_set_pullsel_pullen(hw
, desc
, pullup
, arg
);
751 err
= mtk_pinconf_bias_set_pupd_r1_r0(hw
, desc
, pullup
, arg
);
756 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_set_combo
);
758 int mtk_pinconf_bias_get_combo(struct mtk_pinctrl
*hw
,
759 const struct mtk_pin_desc
*desc
,
760 u32
*pullup
, u32
*enable
)
764 err
= mtk_pinconf_bias_get_pu_pd(hw
, desc
, pullup
, enable
);
768 err
= mtk_pinconf_bias_get_pullsel_pullen(hw
, desc
, pullup
, enable
);
772 err
= mtk_pinconf_bias_get_pupd_r1_r0(hw
, desc
, pullup
, enable
);
777 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_get_combo
);
780 int mtk_pinconf_drive_set(struct mtk_pinctrl
*hw
,
781 const struct mtk_pin_desc
*desc
, u32 arg
)
783 const struct mtk_drive_desc
*tb
;
786 tb
= &mtk_drive
[desc
->drv_n
];
787 /* 4mA when (e8, e4) = (0, 0)
788 * 8mA when (e8, e4) = (0, 1)
789 * 12mA when (e8, e4) = (1, 0)
790 * 16mA when (e8, e4) = (1, 1)
792 if ((arg
>= tb
->min
&& arg
<= tb
->max
) && !(arg
% tb
->step
)) {
793 arg
= (arg
/ tb
->step
- 1) * tb
->scal
;
794 err
= mtk_hw_set_value(hw
, desc
, PINCTRL_PIN_REG_E4
,
799 err
= mtk_hw_set_value(hw
, desc
, PINCTRL_PIN_REG_E8
,
807 EXPORT_SYMBOL_GPL(mtk_pinconf_drive_set
);
809 int mtk_pinconf_drive_get(struct mtk_pinctrl
*hw
,
810 const struct mtk_pin_desc
*desc
, int *val
)
812 const struct mtk_drive_desc
*tb
;
815 tb
= &mtk_drive
[desc
->drv_n
];
817 err
= mtk_hw_get_value(hw
, desc
, PINCTRL_PIN_REG_E4
, &val1
);
821 err
= mtk_hw_get_value(hw
, desc
, PINCTRL_PIN_REG_E8
, &val2
);
825 /* 4mA when (e8, e4) = (0, 0); 8mA when (e8, e4) = (0, 1)
826 * 12mA when (e8, e4) = (1, 0); 16mA when (e8, e4) = (1, 1)
828 *val
= (((val2
<< 1) + val1
) / tb
->scal
+ 1) * tb
->step
;
832 EXPORT_SYMBOL_GPL(mtk_pinconf_drive_get
);
835 int mtk_pinconf_drive_set_rev1(struct mtk_pinctrl
*hw
,
836 const struct mtk_pin_desc
*desc
, u32 arg
)
838 const struct mtk_drive_desc
*tb
;
841 tb
= &mtk_drive
[desc
->drv_n
];
843 if ((arg
>= tb
->min
&& arg
<= tb
->max
) && !(arg
% tb
->step
)) {
844 arg
= (arg
/ tb
->step
- 1) * tb
->scal
;
846 err
= mtk_hw_set_value(hw
, desc
, PINCTRL_PIN_REG_DRV
,
854 EXPORT_SYMBOL_GPL(mtk_pinconf_drive_set_rev1
);
856 int mtk_pinconf_drive_get_rev1(struct mtk_pinctrl
*hw
,
857 const struct mtk_pin_desc
*desc
, int *val
)
859 const struct mtk_drive_desc
*tb
;
862 tb
= &mtk_drive
[desc
->drv_n
];
864 err
= mtk_hw_get_value(hw
, desc
, PINCTRL_PIN_REG_DRV
, &val1
);
868 *val
= ((val1
& 0x7) / tb
->scal
+ 1) * tb
->step
;
872 EXPORT_SYMBOL_GPL(mtk_pinconf_drive_get_rev1
);
874 int mtk_pinconf_drive_set_raw(struct mtk_pinctrl
*hw
,
875 const struct mtk_pin_desc
*desc
, u32 arg
)
877 return mtk_hw_set_value(hw
, desc
, PINCTRL_PIN_REG_DRV
, arg
);
879 EXPORT_SYMBOL_GPL(mtk_pinconf_drive_set_raw
);
881 int mtk_pinconf_drive_get_raw(struct mtk_pinctrl
*hw
,
882 const struct mtk_pin_desc
*desc
, int *val
)
884 return mtk_hw_get_value(hw
, desc
, PINCTRL_PIN_REG_DRV
, val
);
886 EXPORT_SYMBOL_GPL(mtk_pinconf_drive_get_raw
);
888 int mtk_pinconf_adv_pull_set(struct mtk_pinctrl
*hw
,
889 const struct mtk_pin_desc
*desc
, bool pullup
,
894 /* 10K off & 50K (75K) off, when (R0, R1) = (0, 0);
895 * 10K off & 50K (75K) on, when (R0, R1) = (0, 1);
896 * 10K on & 50K (75K) off, when (R0, R1) = (1, 0);
897 * 10K on & 50K (75K) on, when (R0, R1) = (1, 1)
899 err
= mtk_hw_set_value(hw
, desc
, PINCTRL_PIN_REG_R0
, arg
& 1);
903 err
= mtk_hw_set_value(hw
, desc
, PINCTRL_PIN_REG_R1
,
908 arg
= pullup
? 0 : 1;
910 err
= mtk_hw_set_value(hw
, desc
, PINCTRL_PIN_REG_PUPD
, arg
);
912 /* If PUPD register is not supported for that pin, let's fallback to
913 * general bias control.
915 if (err
== -ENOTSUPP
) {
916 if (hw
->soc
->bias_set
) {
917 err
= hw
->soc
->bias_set(hw
, desc
, pullup
);
927 EXPORT_SYMBOL_GPL(mtk_pinconf_adv_pull_set
);
929 int mtk_pinconf_adv_pull_get(struct mtk_pinctrl
*hw
,
930 const struct mtk_pin_desc
*desc
, bool pullup
,
936 err
= mtk_hw_get_value(hw
, desc
, PINCTRL_PIN_REG_PUPD
, &t
);
938 /* If PUPD register is not supported for that pin, let's fallback to
939 * general bias control.
941 if (err
== -ENOTSUPP
) {
942 if (hw
->soc
->bias_get
) {
943 err
= hw
->soc
->bias_get(hw
, desc
, pullup
, val
);
950 /* t == 0 supposes PULLUP for the customized PULL setup */
958 err
= mtk_hw_get_value(hw
, desc
, PINCTRL_PIN_REG_R0
, &t
);
962 err
= mtk_hw_get_value(hw
, desc
, PINCTRL_PIN_REG_R1
, &t2
);
966 *val
= (t
| t2
<< 1) & 0x7;
970 EXPORT_SYMBOL_GPL(mtk_pinconf_adv_pull_get
);
972 int mtk_pinconf_adv_drive_set(struct mtk_pinctrl
*hw
,
973 const struct mtk_pin_desc
*desc
, u32 arg
)
977 int e0
= !!(arg
& 2);
978 int e1
= !!(arg
& 4);
980 err
= mtk_hw_set_value(hw
, desc
, PINCTRL_PIN_REG_DRV_EN
, en
);
987 err
= mtk_hw_set_value(hw
, desc
, PINCTRL_PIN_REG_DRV_E0
, e0
);
991 err
= mtk_hw_set_value(hw
, desc
, PINCTRL_PIN_REG_DRV_E1
, e1
);
997 EXPORT_SYMBOL_GPL(mtk_pinconf_adv_drive_set
);
999 int mtk_pinconf_adv_drive_get(struct mtk_pinctrl
*hw
,
1000 const struct mtk_pin_desc
*desc
, u32
*val
)
1005 err
= mtk_hw_get_value(hw
, desc
, PINCTRL_PIN_REG_DRV_EN
, &en
);
1009 err
= mtk_hw_get_value(hw
, desc
, PINCTRL_PIN_REG_DRV_E0
, &e0
);
1013 err
= mtk_hw_get_value(hw
, desc
, PINCTRL_PIN_REG_DRV_E1
, &e1
);
1017 *val
= (en
| e0
<< 1 | e1
<< 2) & 0x7;
1021 EXPORT_SYMBOL_GPL(mtk_pinconf_adv_drive_get
);
1023 MODULE_LICENSE("GPL v2");
1024 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
1025 MODULE_DESCRIPTION("Pin configuration library module for mediatek SoCs");