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Merge tag 'block-5.9-2020-08-14' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / pinctrl / pinctrl-amd.c
blob9a760f5cd7ed53c89bf5165733a0c2910036ecd9
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * GPIO driver for AMD
4 *
5 * Copyright (c) 2014,2015 AMD Corporation.
6 * Authors: Ken Xue <Ken.Xue@amd.com>
7 * Wu, Jeff <Jeff.Wu@amd.com>
8 *
9 * Contact Information: Nehal Shah <Nehal-bakulchandra.Shah@amd.com>
10 * Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
11 */
12
13 #include <linux/err.h>
14 #include <linux/bug.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/compiler.h>
19 #include <linux/types.h>
20 #include <linux/errno.h>
21 #include <linux/log2.h>
22 #include <linux/io.h>
23 #include <linux/gpio/driver.h>
24 #include <linux/slab.h>
25 #include <linux/platform_device.h>
26 #include <linux/mutex.h>
27 #include <linux/acpi.h>
28 #include <linux/seq_file.h>
29 #include <linux/interrupt.h>
30 #include <linux/list.h>
31 #include <linux/bitops.h>
32 #include <linux/pinctrl/pinconf.h>
33 #include <linux/pinctrl/pinconf-generic.h>
34
35 #include "core.h"
36 #include "pinctrl-utils.h"
37 #include "pinctrl-amd.h"
38
39 static int amd_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
40 {
41 unsigned long flags;
42 u32 pin_reg;
43 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
44
45 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
46 pin_reg = readl(gpio_dev->base + offset * 4);
47 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
48
49 if (pin_reg & BIT(OUTPUT_ENABLE_OFF))
50 return GPIO_LINE_DIRECTION_OUT;
51
52 return GPIO_LINE_DIRECTION_IN;
53 }
54
55 static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
56 {
57 unsigned long flags;
58 u32 pin_reg;
59 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
60
61 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
62 pin_reg = readl(gpio_dev->base + offset * 4);
63 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF);
64 writel(pin_reg, gpio_dev->base + offset * 4);
65 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
66
67 return 0;
68 }
69
70 static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
71 int value)
72 {
73 u32 pin_reg;
74 unsigned long flags;
75 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
76
77 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
78 pin_reg = readl(gpio_dev->base + offset * 4);
79 pin_reg |= BIT(OUTPUT_ENABLE_OFF);
80 if (value)
81 pin_reg |= BIT(OUTPUT_VALUE_OFF);
82 else
83 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
84 writel(pin_reg, gpio_dev->base + offset * 4);
85 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
86
87 return 0;
88 }
89
90 static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset)
91 {
92 u32 pin_reg;
93 unsigned long flags;
94 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
95
96 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
97 pin_reg = readl(gpio_dev->base + offset * 4);
98 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
99
100 return !!(pin_reg & BIT(PIN_STS_OFF));
101 }
102
103 static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value)
104 {
105 u32 pin_reg;
106 unsigned long flags;
107 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
108
109 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
110 pin_reg = readl(gpio_dev->base + offset * 4);
111 if (value)
112 pin_reg |= BIT(OUTPUT_VALUE_OFF);
113 else
114 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
115 writel(pin_reg, gpio_dev->base + offset * 4);
116 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
117 }
118
119 static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
120 unsigned debounce)
121 {
122 u32 time;
123 u32 pin_reg;
124 int ret = 0;
125 unsigned long flags;
126 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
127
128 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
129 pin_reg = readl(gpio_dev->base + offset * 4);
130
131 if (debounce) {
132 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
133 pin_reg &= ~DB_TMR_OUT_MASK;
134 /*
135 Debounce Debounce Timer Max
136 TmrLarge TmrOutUnit Unit Debounce
137 Time
138 0 0 61 usec (2 RtcClk) 976 usec
139 0 1 244 usec (8 RtcClk) 3.9 msec
140 1 0 15.6 msec (512 RtcClk) 250 msec
141 1 1 62.5 msec (2048 RtcClk) 1 sec
142 */
143
144 if (debounce < 61) {
145 pin_reg |= 1;
146 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
147 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
148 } else if (debounce < 976) {
149 time = debounce / 61;
150 pin_reg |= time & DB_TMR_OUT_MASK;
151 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
152 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
153 } else if (debounce < 3900) {
154 time = debounce / 244;
155 pin_reg |= time & DB_TMR_OUT_MASK;
156 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
157 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
158 } else if (debounce < 250000) {
159 time = debounce / 15600;
160 pin_reg |= time & DB_TMR_OUT_MASK;
161 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
162 pin_reg |= BIT(DB_TMR_LARGE_OFF);
163 } else if (debounce < 1000000) {
164 time = debounce / 62500;
165 pin_reg |= time & DB_TMR_OUT_MASK;
166 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
167 pin_reg |= BIT(DB_TMR_LARGE_OFF);
168 } else {
169 pin_reg &= ~DB_CNTRl_MASK;
170 ret = -EINVAL;
171 }
172 } else {
173 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
174 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
175 pin_reg &= ~DB_TMR_OUT_MASK;
176 pin_reg &= ~DB_CNTRl_MASK;
177 }
178 writel(pin_reg, gpio_dev->base + offset * 4);
179 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
180
181 return ret;
182 }
183
184 static int amd_gpio_set_config(struct gpio_chip *gc, unsigned offset,
185 unsigned long config)
186 {
187 u32 debounce;
188
189 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
190 return -ENOTSUPP;
191
192 debounce = pinconf_to_config_argument(config);
193 return amd_gpio_set_debounce(gc, offset, debounce);
194 }
195
196 #ifdef CONFIG_DEBUG_FS
197 static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
198 {
199 u32 pin_reg;
200 unsigned long flags;
201 unsigned int bank, i, pin_num;
202 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
203
204 char *level_trig;
205 char *active_level;
206 char *interrupt_enable;
207 char *interrupt_mask;
208 char *wake_cntrl0;
209 char *wake_cntrl1;
210 char *wake_cntrl2;
211 char *pin_sts;
212 char *pull_up_sel;
213 char *pull_up_enable;
214 char *pull_down_enable;
215 char *output_value;
216 char *output_enable;
217
218 for (bank = 0; bank < gpio_dev->hwbank_num; bank++) {
219 seq_printf(s, "GPIO bank%d\t", bank);
220
221 switch (bank) {
222 case 0:
223 i = 0;
224 pin_num = AMD_GPIO_PINS_BANK0;
225 break;
226 case 1:
227 i = 64;
228 pin_num = AMD_GPIO_PINS_BANK1 + i;
229 break;
230 case 2:
231 i = 128;
232 pin_num = AMD_GPIO_PINS_BANK2 + i;
233 break;
234 case 3:
235 i = 192;
236 pin_num = AMD_GPIO_PINS_BANK3 + i;
237 break;
238 default:
239 /* Illegal bank number, ignore */
240 continue;
241 }
242 for (; i < pin_num; i++) {
243 seq_printf(s, "pin%d\t", i);
244 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
245 pin_reg = readl(gpio_dev->base + i * 4);
246 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
247
248 if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) {
249 u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) &
250 ACTIVE_LEVEL_MASK;
251 interrupt_enable = "interrupt is enabled|";
252
253 if (level == ACTIVE_LEVEL_HIGH)
254 active_level = "Active high|";
255 else if (level == ACTIVE_LEVEL_LOW)
256 active_level = "Active low|";
257 else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) &&
258 level == ACTIVE_LEVEL_BOTH)
259 active_level = "Active on both|";
260 else
261 active_level = "Unknown Active level|";
262
263 if (pin_reg & BIT(LEVEL_TRIG_OFF))
264 level_trig = "Level trigger|";
265 else
266 level_trig = "Edge trigger|";
267
268 } else {
269 interrupt_enable =
270 "interrupt is disabled|";
271 active_level = " ";
272 level_trig = " ";
273 }
274
275 if (pin_reg & BIT(INTERRUPT_MASK_OFF))
276 interrupt_mask =
277 "interrupt is unmasked|";
278 else
279 interrupt_mask =
280 "interrupt is masked|";
281
282 if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3))
283 wake_cntrl0 = "enable wakeup in S0i3 state|";
284 else
285 wake_cntrl0 = "disable wakeup in S0i3 state|";
286
287 if (pin_reg & BIT(WAKE_CNTRL_OFF_S3))
288 wake_cntrl1 = "enable wakeup in S3 state|";
289 else
290 wake_cntrl1 = "disable wakeup in S3 state|";
291
292 if (pin_reg & BIT(WAKE_CNTRL_OFF_S4))
293 wake_cntrl2 = "enable wakeup in S4/S5 state|";
294 else
295 wake_cntrl2 = "disable wakeup in S4/S5 state|";
296
297 if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) {
298 pull_up_enable = "pull-up is enabled|";
299 if (pin_reg & BIT(PULL_UP_SEL_OFF))
300 pull_up_sel = "8k pull-up|";
301 else
302 pull_up_sel = "4k pull-up|";
303 } else {
304 pull_up_enable = "pull-up is disabled|";
305 pull_up_sel = " ";
306 }
307
308 if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF))
309 pull_down_enable = "pull-down is enabled|";
310 else
311 pull_down_enable = "Pull-down is disabled|";
312
313 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) {
314 pin_sts = " ";
315 output_enable = "output is enabled|";
316 if (pin_reg & BIT(OUTPUT_VALUE_OFF))
317 output_value = "output is high|";
318 else
319 output_value = "output is low|";
320 } else {
321 output_enable = "output is disabled|";
322 output_value = " ";
323
324 if (pin_reg & BIT(PIN_STS_OFF))
325 pin_sts = "input is high|";
326 else
327 pin_sts = "input is low|";
328 }
329
330 seq_printf(s, "%s %s %s %s %s %s\n"
331 " %s %s %s %s %s %s %s 0x%x\n",
332 level_trig, active_level, interrupt_enable,
333 interrupt_mask, wake_cntrl0, wake_cntrl1,
334 wake_cntrl2, pin_sts, pull_up_sel,
335 pull_up_enable, pull_down_enable,
336 output_value, output_enable, pin_reg);
337 }
338 }
339 }
340 #else
341 #define amd_gpio_dbg_show NULL
342 #endif
343
344 static void amd_gpio_irq_enable(struct irq_data *d)
345 {
346 u32 pin_reg;
347 unsigned long flags;
348 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
349 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
350
351 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
352 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
353 pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
354 pin_reg |= BIT(INTERRUPT_MASK_OFF);
355 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
356 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
357 }
358
359 static void amd_gpio_irq_disable(struct irq_data *d)
360 {
361 u32 pin_reg;
362 unsigned long flags;
363 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
364 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
365
366 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
367 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
368 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF);
369 pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
370 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
371 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
372 }
373
374 static void amd_gpio_irq_mask(struct irq_data *d)
375 {
376 u32 pin_reg;
377 unsigned long flags;
378 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
379 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
380
381 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
382 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
383 pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
384 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
385 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
386 }
387
388 static void amd_gpio_irq_unmask(struct irq_data *d)
389 {
390 u32 pin_reg;
391 unsigned long flags;
392 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
393 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
394
395 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
396 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
397 pin_reg |= BIT(INTERRUPT_MASK_OFF);
398 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
399 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
400 }
401
402 static void amd_gpio_irq_eoi(struct irq_data *d)
403 {
404 u32 reg;
405 unsigned long flags;
406 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
407 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
408
409 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
410 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
411 reg |= EOI_MASK;
412 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
413 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
414 }
415
416 static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
417 {
418 int ret = 0;
419 u32 pin_reg, pin_reg_irq_en, mask;
420 unsigned long flags;
421 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
422 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
423
424 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
425 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
426
427 switch (type & IRQ_TYPE_SENSE_MASK) {
428 case IRQ_TYPE_EDGE_RISING:
429 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
430 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
431 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
432 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
433 irq_set_handler_locked(d, handle_edge_irq);
434 break;
435
436 case IRQ_TYPE_EDGE_FALLING:
437 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
438 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
439 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
440 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
441 irq_set_handler_locked(d, handle_edge_irq);
442 break;
443
444 case IRQ_TYPE_EDGE_BOTH:
445 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
446 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
447 pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF;
448 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
449 irq_set_handler_locked(d, handle_edge_irq);
450 break;
451
452 case IRQ_TYPE_LEVEL_HIGH:
453 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
454 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
455 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
456 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
457 pin_reg |= DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF;
458 irq_set_handler_locked(d, handle_level_irq);
459 break;
460
461 case IRQ_TYPE_LEVEL_LOW:
462 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
463 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
464 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
465 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
466 pin_reg |= DB_TYPE_PRESERVE_HIGH_GLITCH << DB_CNTRL_OFF;
467 irq_set_handler_locked(d, handle_level_irq);
468 break;
469
470 case IRQ_TYPE_NONE:
471 break;
472
473 default:
474 dev_err(&gpio_dev->pdev->dev, "Invalid type value\n");
475 ret = -EINVAL;
476 }
477
478 pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF;
479 /*
480 * If WAKE_INT_MASTER_REG.MaskStsEn is set, a software write to the
481 * debounce registers of any GPIO will block wake/interrupt status
482 * generation for *all* GPIOs for a length of time that depends on
483 * WAKE_INT_MASTER_REG.MaskStsLength[11:0]. During this period the
484 * INTERRUPT_ENABLE bit will read as 0.
485 *
486 * We temporarily enable irq for the GPIO whose configuration is
487 * changing, and then wait for it to read back as 1 to know when
488 * debounce has settled and then disable the irq again.
489 * We do this polling with the spinlock held to ensure other GPIO
490 * access routines do not read an incorrect value for the irq enable
491 * bit of other GPIOs. We keep the GPIO masked while polling to avoid
492 * spurious irqs, and disable the irq again after polling.
493 */
494 mask = BIT(INTERRUPT_ENABLE_OFF);
495 pin_reg_irq_en = pin_reg;
496 pin_reg_irq_en |= mask;
497 pin_reg_irq_en &= ~BIT(INTERRUPT_MASK_OFF);
498 writel(pin_reg_irq_en, gpio_dev->base + (d->hwirq)*4);
499 while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask)
500 continue;
501 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
502 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
503
504 return ret;
505 }
506
507 static void amd_irq_ack(struct irq_data *d)
508 {
509 /*
510 * based on HW design,there is no need to ack HW
511 * before handle current irq. But this routine is
512 * necessary for handle_edge_irq
513 */
514 }
515
516 static struct irq_chip amd_gpio_irqchip = {
517 .name = "amd_gpio",
518 .irq_ack = amd_irq_ack,
519 .irq_enable = amd_gpio_irq_enable,
520 .irq_disable = amd_gpio_irq_disable,
521 .irq_mask = amd_gpio_irq_mask,
522 .irq_unmask = amd_gpio_irq_unmask,
523 .irq_eoi = amd_gpio_irq_eoi,
524 .irq_set_type = amd_gpio_irq_set_type,
525 .flags = IRQCHIP_SKIP_SET_WAKE,
526 };
527
528 #define PIN_IRQ_PENDING (BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF))
529
530 static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id)
531 {
532 struct amd_gpio *gpio_dev = dev_id;
533 struct gpio_chip *gc = &gpio_dev->gc;
534 irqreturn_t ret = IRQ_NONE;
535 unsigned int i, irqnr;
536 unsigned long flags;
537 u32 __iomem *regs;
538 u32 regval;
539 u64 status, mask;
540
541 /* Read the wake status */
542 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
543 status = readl(gpio_dev->base + WAKE_INT_STATUS_REG1);
544 status <<= 32;
545 status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0);
546 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
547
548 /* Bit 0-45 contain the relevant status bits */
549 status &= (1ULL << 46) - 1;
550 regs = gpio_dev->base;
551 for (mask = 1, irqnr = 0; status; mask <<= 1, regs += 4, irqnr += 4) {
552 if (!(status & mask))
553 continue;
554 status &= ~mask;
555
556 /* Each status bit covers four pins */
557 for (i = 0; i < 4; i++) {
558 regval = readl(regs + i);
559 if (!(regval & PIN_IRQ_PENDING) ||
560 !(regval & BIT(INTERRUPT_MASK_OFF)))
561 continue;
562 irq = irq_find_mapping(gc->irq.domain, irqnr + i);
563 if (irq != 0)
564 generic_handle_irq(irq);
565
566 /* Clear interrupt.
567 * We must read the pin register again, in case the
568 * value was changed while executing
569 * generic_handle_irq() above.
570 * If we didn't find a mapping for the interrupt,
571 * disable it in order to avoid a system hang caused
572 * by an interrupt storm.
573 */
574 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
575 regval = readl(regs + i);
576 if (irq == 0) {
577 regval &= ~BIT(INTERRUPT_ENABLE_OFF);
578 dev_dbg(&gpio_dev->pdev->dev,
579 "Disabling spurious GPIO IRQ %d\n",
580 irqnr + i);
581 }
582 writel(regval, regs + i);
583 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
584 ret = IRQ_HANDLED;
585 }
586 }
587
588 /* Signal EOI to the GPIO unit */
589 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
590 regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
591 regval |= EOI_MASK;
592 writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG);
593 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
594
595 return ret;
596 }
597
598 static int amd_get_groups_count(struct pinctrl_dev *pctldev)
599 {
600 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
601
602 return gpio_dev->ngroups;
603 }
604
605 static const char *amd_get_group_name(struct pinctrl_dev *pctldev,
606 unsigned group)
607 {
608 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
609
610 return gpio_dev->groups[group].name;
611 }
612
613 static int amd_get_group_pins(struct pinctrl_dev *pctldev,
614 unsigned group,
615 const unsigned **pins,
616 unsigned *num_pins)
617 {
618 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
619
620 *pins = gpio_dev->groups[group].pins;
621 *num_pins = gpio_dev->groups[group].npins;
622 return 0;
623 }
624
625 static const struct pinctrl_ops amd_pinctrl_ops = {
626 .get_groups_count = amd_get_groups_count,
627 .get_group_name = amd_get_group_name,
628 .get_group_pins = amd_get_group_pins,
629 #ifdef CONFIG_OF
630 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
631 .dt_free_map = pinctrl_utils_free_map,
632 #endif
633 };
634
635 static int amd_pinconf_get(struct pinctrl_dev *pctldev,
636 unsigned int pin,
637 unsigned long *config)
638 {
639 u32 pin_reg;
640 unsigned arg;
641 unsigned long flags;
642 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
643 enum pin_config_param param = pinconf_to_config_param(*config);
644
645 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
646 pin_reg = readl(gpio_dev->base + pin*4);
647 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
648 switch (param) {
649 case PIN_CONFIG_INPUT_DEBOUNCE:
650 arg = pin_reg & DB_TMR_OUT_MASK;
651 break;
652
653 case PIN_CONFIG_BIAS_PULL_DOWN:
654 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0);
655 break;
656
657 case PIN_CONFIG_BIAS_PULL_UP:
658 arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1));
659 break;
660
661 case PIN_CONFIG_DRIVE_STRENGTH:
662 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK;
663 break;
664
665 default:
666 dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n",
667 param);
668 return -ENOTSUPP;
669 }
670
671 *config = pinconf_to_config_packed(param, arg);
672
673 return 0;
674 }
675
676 static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
677 unsigned long *configs, unsigned num_configs)
678 {
679 int i;
680 u32 arg;
681 int ret = 0;
682 u32 pin_reg;
683 unsigned long flags;
684 enum pin_config_param param;
685 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
686
687 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
688 for (i = 0; i < num_configs; i++) {
689 param = pinconf_to_config_param(configs[i]);
690 arg = pinconf_to_config_argument(configs[i]);
691 pin_reg = readl(gpio_dev->base + pin*4);
692
693 switch (param) {
694 case PIN_CONFIG_INPUT_DEBOUNCE:
695 pin_reg &= ~DB_TMR_OUT_MASK;
696 pin_reg |= arg & DB_TMR_OUT_MASK;
697 break;
698
699 case PIN_CONFIG_BIAS_PULL_DOWN:
700 pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF);
701 pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF;
702 break;
703
704 case PIN_CONFIG_BIAS_PULL_UP:
705 pin_reg &= ~BIT(PULL_UP_SEL_OFF);
706 pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF;
707 pin_reg &= ~BIT(PULL_UP_ENABLE_OFF);
708 pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF;
709 break;
710
711 case PIN_CONFIG_DRIVE_STRENGTH:
712 pin_reg &= ~(DRV_STRENGTH_SEL_MASK
713 << DRV_STRENGTH_SEL_OFF);
714 pin_reg |= (arg & DRV_STRENGTH_SEL_MASK)
715 << DRV_STRENGTH_SEL_OFF;
716 break;
717
718 default:
719 dev_err(&gpio_dev->pdev->dev,
720 "Invalid config param %04x\n", param);
721 ret = -ENOTSUPP;
722 }
723
724 writel(pin_reg, gpio_dev->base + pin*4);
725 }
726 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
727
728 return ret;
729 }
730
731 static int amd_pinconf_group_get(struct pinctrl_dev *pctldev,
732 unsigned int group,
733 unsigned long *config)
734 {
735 const unsigned *pins;
736 unsigned npins;
737 int ret;
738
739 ret = amd_get_group_pins(pctldev, group, &pins, &npins);
740 if (ret)
741 return ret;
742
743 if (amd_pinconf_get(pctldev, pins[0], config))
744 return -ENOTSUPP;
745
746 return 0;
747 }
748
749 static int amd_pinconf_group_set(struct pinctrl_dev *pctldev,
750 unsigned group, unsigned long *configs,
751 unsigned num_configs)
752 {
753 const unsigned *pins;
754 unsigned npins;
755 int i, ret;
756
757 ret = amd_get_group_pins(pctldev, group, &pins, &npins);
758 if (ret)
759 return ret;
760 for (i = 0; i < npins; i++) {
761 if (amd_pinconf_set(pctldev, pins[i], configs, num_configs))
762 return -ENOTSUPP;
763 }
764 return 0;
765 }
766
767 static const struct pinconf_ops amd_pinconf_ops = {
768 .pin_config_get = amd_pinconf_get,
769 .pin_config_set = amd_pinconf_set,
770 .pin_config_group_get = amd_pinconf_group_get,
771 .pin_config_group_set = amd_pinconf_group_set,
772 };
773
774 #ifdef CONFIG_PM_SLEEP
775 static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin)
776 {
777 const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin);
778
779 if (!pd)
780 return false;
781
782 /*
783 * Only restore the pin if it is actually in use by the kernel (or
784 * by userspace).
785 */
786 if (pd->mux_owner || pd->gpio_owner ||
787 gpiochip_line_is_irq(&gpio_dev->gc, pin))
788 return true;
789
790 return false;
791 }
792
793 static int amd_gpio_suspend(struct device *dev)
794 {
795 struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
796 struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
797 int i;
798
799 for (i = 0; i < desc->npins; i++) {
800 int pin = desc->pins[i].number;
801
802 if (!amd_gpio_should_save(gpio_dev, pin))
803 continue;
804
805 gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin*4);
806 }
807
808 return 0;
809 }
810
811 static int amd_gpio_resume(struct device *dev)
812 {
813 struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
814 struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
815 int i;
816
817 for (i = 0; i < desc->npins; i++) {
818 int pin = desc->pins[i].number;
819
820 if (!amd_gpio_should_save(gpio_dev, pin))
821 continue;
822
823 writel(gpio_dev->saved_regs[i], gpio_dev->base + pin*4);
824 }
825
826 return 0;
827 }
828
829 static const struct dev_pm_ops amd_gpio_pm_ops = {
830 SET_LATE_SYSTEM_SLEEP_PM_OPS(amd_gpio_suspend,
831 amd_gpio_resume)
832 };
833 #endif
834
835 static struct pinctrl_desc amd_pinctrl_desc = {
836 .pins = kerncz_pins,
837 .npins = ARRAY_SIZE(kerncz_pins),
838 .pctlops = &amd_pinctrl_ops,
839 .confops = &amd_pinconf_ops,
840 .owner = THIS_MODULE,
841 };
842
843 static int amd_gpio_probe(struct platform_device *pdev)
844 {
845 int ret = 0;
846 int irq_base;
847 struct resource *res;
848 struct amd_gpio *gpio_dev;
849 struct gpio_irq_chip *girq;
850
851 gpio_dev = devm_kzalloc(&pdev->dev,
852 sizeof(struct amd_gpio), GFP_KERNEL);
853 if (!gpio_dev)
854 return -ENOMEM;
855
856 raw_spin_lock_init(&gpio_dev->lock);
857
858 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
859 if (!res) {
860 dev_err(&pdev->dev, "Failed to get gpio io resource.\n");
861 return -EINVAL;
862 }
863
864 gpio_dev->base = devm_ioremap(&pdev->dev, res->start,
865 resource_size(res));
866 if (!gpio_dev->base)
867 return -ENOMEM;
868
869 irq_base = platform_get_irq(pdev, 0);
870 if (irq_base < 0)
871 return irq_base;
872
873 #ifdef CONFIG_PM_SLEEP
874 gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins,
875 sizeof(*gpio_dev->saved_regs),
876 GFP_KERNEL);
877 if (!gpio_dev->saved_regs)
878 return -ENOMEM;
879 #endif
880
881 gpio_dev->pdev = pdev;
882 gpio_dev->gc.get_direction = amd_gpio_get_direction;
883 gpio_dev->gc.direction_input = amd_gpio_direction_input;
884 gpio_dev->gc.direction_output = amd_gpio_direction_output;
885 gpio_dev->gc.get = amd_gpio_get_value;
886 gpio_dev->gc.set = amd_gpio_set_value;
887 gpio_dev->gc.set_config = amd_gpio_set_config;
888 gpio_dev->gc.dbg_show = amd_gpio_dbg_show;
889
890 gpio_dev->gc.base = -1;
891 gpio_dev->gc.label = pdev->name;
892 gpio_dev->gc.owner = THIS_MODULE;
893 gpio_dev->gc.parent = &pdev->dev;
894 gpio_dev->gc.ngpio = resource_size(res) / 4;
895 #if defined(CONFIG_OF_GPIO)
896 gpio_dev->gc.of_node = pdev->dev.of_node;
897 #endif
898
899 gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64;
900 gpio_dev->groups = kerncz_groups;
901 gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups);
902
903 amd_pinctrl_desc.name = dev_name(&pdev->dev);
904 gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc,
905 gpio_dev);
906 if (IS_ERR(gpio_dev->pctrl)) {
907 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
908 return PTR_ERR(gpio_dev->pctrl);
909 }
910
911 girq = &gpio_dev->gc.irq;
912 girq->chip = &amd_gpio_irqchip;
913 /* This will let us handle the parent IRQ in the driver */
914 girq->parent_handler = NULL;
915 girq->num_parents = 0;
916 girq->parents = NULL;
917 girq->default_type = IRQ_TYPE_NONE;
918 girq->handler = handle_simple_irq;
919
920 ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev);
921 if (ret)
922 return ret;
923
924 ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev),
925 0, 0, gpio_dev->gc.ngpio);
926 if (ret) {
927 dev_err(&pdev->dev, "Failed to add pin range\n");
928 goto out2;
929 }
930
931 ret = devm_request_irq(&pdev->dev, irq_base, amd_gpio_irq_handler,
932 IRQF_SHARED, KBUILD_MODNAME, gpio_dev);
933 if (ret)
934 goto out2;
935
936 platform_set_drvdata(pdev, gpio_dev);
937
938 dev_dbg(&pdev->dev, "amd gpio driver loaded\n");
939 return ret;
940
941 out2:
942 gpiochip_remove(&gpio_dev->gc);
943
944 return ret;
945 }
946
947 static int amd_gpio_remove(struct platform_device *pdev)
948 {
949 struct amd_gpio *gpio_dev;
950
951 gpio_dev = platform_get_drvdata(pdev);
952
953 gpiochip_remove(&gpio_dev->gc);
954
955 return 0;
956 }
957
958 #ifdef CONFIG_ACPI
959 static const struct acpi_device_id amd_gpio_acpi_match[] = {
960 { "AMD0030", 0 },
961 { "AMDI0030", 0},
962 { },
963 };
964 MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match);
965 #endif
966
967 static struct platform_driver amd_gpio_driver = {
968 .driver = {
969 .name = "amd_gpio",
970 .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match),
971 #ifdef CONFIG_PM_SLEEP
972 .pm = &amd_gpio_pm_ops,
973 #endif
974 },
975 .probe = amd_gpio_probe,
976 .remove = amd_gpio_remove,
977 };
978
979 module_platform_driver(amd_gpio_driver);
980
981 MODULE_LICENSE("GPL v2");
982 MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>");
983 MODULE_DESCRIPTION("AMD GPIO pinctrl driver");
Linux with added FPC-III support