drivers/gpio/gpio-msm-v1.c

   1 /*
   2  * Copyright (C) 2007 Google, Inc.
   3  * Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  */
  15
  16 #include <linux/bitops.h>
  17 #include <linux/gpio.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/io.h>
  20 #include <linux/irq.h>
  21 #include <linux/module.h>
  22 #include <linux/device.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/err.h>
  25
  26 #include <mach/msm_gpiomux.h>
  27
  28 /* see 80-VA736-2 Rev C pp 695-751
  29 **
  30 ** These are actually the *shadow* gpio registers, since the
  31 ** real ones (which allow full access) are only available to the
  32 ** ARM9 side of the world.
  33 **
  34 ** Since the _BASE need to be page-aligned when we're mapping them
  35 ** to virtual addresses, adjust for the additional offset in these
  36 ** macros.
  37 */
  38
  39 #define MSM_GPIO1_REG(off) (off)
  40 #define MSM_GPIO2_REG(off) (off)
  41 #define MSM_GPIO1_SHADOW_REG(off) (off)
  42 #define MSM_GPIO2_SHADOW_REG(off) (off)
  43
  44 /*
  45  * MSM7X00 registers
  46  */
  47 /* output value */
  48 #define MSM7X00_GPIO_OUT_0      MSM_GPIO1_SHADOW_REG(0x00)  /* gpio  15-0  */
  49 #define MSM7X00_GPIO_OUT_1      MSM_GPIO2_SHADOW_REG(0x00)  /* gpio  42-16 */
  50 #define MSM7X00_GPIO_OUT_2      MSM_GPIO1_SHADOW_REG(0x04)  /* gpio  67-43 */
  51 #define MSM7X00_GPIO_OUT_3      MSM_GPIO1_SHADOW_REG(0x08)  /* gpio  94-68 */
  52 #define MSM7X00_GPIO_OUT_4      MSM_GPIO1_SHADOW_REG(0x0C)  /* gpio 106-95 */
  53 #define MSM7X00_GPIO_OUT_5      MSM_GPIO1_SHADOW_REG(0x50)  /* gpio 107-121 */
  54
  55 /* same pin map as above, output enable */
  56 #define MSM7X00_GPIO_OE_0       MSM_GPIO1_SHADOW_REG(0x10)
  57 #define MSM7X00_GPIO_OE_1       MSM_GPIO2_SHADOW_REG(0x08)
  58 #define MSM7X00_GPIO_OE_2       MSM_GPIO1_SHADOW_REG(0x14)
  59 #define MSM7X00_GPIO_OE_3       MSM_GPIO1_SHADOW_REG(0x18)
  60 #define MSM7X00_GPIO_OE_4       MSM_GPIO1_SHADOW_REG(0x1C)
  61 #define MSM7X00_GPIO_OE_5       MSM_GPIO1_SHADOW_REG(0x54)
  62
  63 /* same pin map as above, input read */
  64 #define MSM7X00_GPIO_IN_0       MSM_GPIO1_SHADOW_REG(0x34)
  65 #define MSM7X00_GPIO_IN_1       MSM_GPIO2_SHADOW_REG(0x20)
  66 #define MSM7X00_GPIO_IN_2       MSM_GPIO1_SHADOW_REG(0x38)
  67 #define MSM7X00_GPIO_IN_3       MSM_GPIO1_SHADOW_REG(0x3C)
  68 #define MSM7X00_GPIO_IN_4       MSM_GPIO1_SHADOW_REG(0x40)
  69 #define MSM7X00_GPIO_IN_5       MSM_GPIO1_SHADOW_REG(0x44)
  70
  71 /* same pin map as above, 1=edge 0=level interrup */
  72 #define MSM7X00_GPIO_INT_EDGE_0 MSM_GPIO1_SHADOW_REG(0x60)
  73 #define MSM7X00_GPIO_INT_EDGE_1 MSM_GPIO2_SHADOW_REG(0x50)
  74 #define MSM7X00_GPIO_INT_EDGE_2 MSM_GPIO1_SHADOW_REG(0x64)
  75 #define MSM7X00_GPIO_INT_EDGE_3 MSM_GPIO1_SHADOW_REG(0x68)
  76 #define MSM7X00_GPIO_INT_EDGE_4 MSM_GPIO1_SHADOW_REG(0x6C)
  77 #define MSM7X00_GPIO_INT_EDGE_5 MSM_GPIO1_SHADOW_REG(0xC0)
  78
  79 /* same pin map as above, 1=positive 0=negative */
  80 #define MSM7X00_GPIO_INT_POS_0  MSM_GPIO1_SHADOW_REG(0x70)
  81 #define MSM7X00_GPIO_INT_POS_1  MSM_GPIO2_SHADOW_REG(0x58)
  82 #define MSM7X00_GPIO_INT_POS_2  MSM_GPIO1_SHADOW_REG(0x74)
  83 #define MSM7X00_GPIO_INT_POS_3  MSM_GPIO1_SHADOW_REG(0x78)
  84 #define MSM7X00_GPIO_INT_POS_4  MSM_GPIO1_SHADOW_REG(0x7C)
  85 #define MSM7X00_GPIO_INT_POS_5  MSM_GPIO1_SHADOW_REG(0xBC)
  86
  87 /* same pin map as above, interrupt enable */
  88 #define MSM7X00_GPIO_INT_EN_0   MSM_GPIO1_SHADOW_REG(0x80)
  89 #define MSM7X00_GPIO_INT_EN_1   MSM_GPIO2_SHADOW_REG(0x60)
  90 #define MSM7X00_GPIO_INT_EN_2   MSM_GPIO1_SHADOW_REG(0x84)
  91 #define MSM7X00_GPIO_INT_EN_3   MSM_GPIO1_SHADOW_REG(0x88)
  92 #define MSM7X00_GPIO_INT_EN_4   MSM_GPIO1_SHADOW_REG(0x8C)
  93 #define MSM7X00_GPIO_INT_EN_5   MSM_GPIO1_SHADOW_REG(0xB8)
  94
  95 /* same pin map as above, write 1 to clear interrupt */
  96 #define MSM7X00_GPIO_INT_CLEAR_0        MSM_GPIO1_SHADOW_REG(0x90)
  97 #define MSM7X00_GPIO_INT_CLEAR_1        MSM_GPIO2_SHADOW_REG(0x68)
  98 #define MSM7X00_GPIO_INT_CLEAR_2        MSM_GPIO1_SHADOW_REG(0x94)
  99 #define MSM7X00_GPIO_INT_CLEAR_3        MSM_GPIO1_SHADOW_REG(0x98)
 100 #define MSM7X00_GPIO_INT_CLEAR_4        MSM_GPIO1_SHADOW_REG(0x9C)
 101 #define MSM7X00_GPIO_INT_CLEAR_5        MSM_GPIO1_SHADOW_REG(0xB4)
 102
 103 /* same pin map as above, 1=interrupt pending */
 104 #define MSM7X00_GPIO_INT_STATUS_0       MSM_GPIO1_SHADOW_REG(0xA0)
 105 #define MSM7X00_GPIO_INT_STATUS_1       MSM_GPIO2_SHADOW_REG(0x70)
 106 #define MSM7X00_GPIO_INT_STATUS_2       MSM_GPIO1_SHADOW_REG(0xA4)
 107 #define MSM7X00_GPIO_INT_STATUS_3       MSM_GPIO1_SHADOW_REG(0xA8)
 108 #define MSM7X00_GPIO_INT_STATUS_4       MSM_GPIO1_SHADOW_REG(0xAC)
 109 #define MSM7X00_GPIO_INT_STATUS_5       MSM_GPIO1_SHADOW_REG(0xB0)
 110
 111 /*
 112  * QSD8X50 registers
 113  */
 114 /* output value */
 115 #define QSD8X50_GPIO_OUT_0      MSM_GPIO1_SHADOW_REG(0x00)  /* gpio  15-0   */
 116 #define QSD8X50_GPIO_OUT_1      MSM_GPIO2_SHADOW_REG(0x00)  /* gpio  42-16  */
 117 #define QSD8X50_GPIO_OUT_2      MSM_GPIO1_SHADOW_REG(0x04)  /* gpio  67-43  */
 118 #define QSD8X50_GPIO_OUT_3      MSM_GPIO1_SHADOW_REG(0x08)  /* gpio  94-68  */
 119 #define QSD8X50_GPIO_OUT_4      MSM_GPIO1_SHADOW_REG(0x0C)  /* gpio 103-95  */
 120 #define QSD8X50_GPIO_OUT_5      MSM_GPIO1_SHADOW_REG(0x10)  /* gpio 121-104 */
 121 #define QSD8X50_GPIO_OUT_6      MSM_GPIO1_SHADOW_REG(0x14)  /* gpio 152-122 */
 122 #define QSD8X50_GPIO_OUT_7      MSM_GPIO1_SHADOW_REG(0x18)  /* gpio 164-153 */
 123
 124 /* same pin map as above, output enable */
 125 #define QSD8X50_GPIO_OE_0       MSM_GPIO1_SHADOW_REG(0x20)
 126 #define QSD8X50_GPIO_OE_1       MSM_GPIO2_SHADOW_REG(0x08)
 127 #define QSD8X50_GPIO_OE_2       MSM_GPIO1_SHADOW_REG(0x24)
 128 #define QSD8X50_GPIO_OE_3       MSM_GPIO1_SHADOW_REG(0x28)
 129 #define QSD8X50_GPIO_OE_4       MSM_GPIO1_SHADOW_REG(0x2C)
 130 #define QSD8X50_GPIO_OE_5       MSM_GPIO1_SHADOW_REG(0x30)
 131 #define QSD8X50_GPIO_OE_6       MSM_GPIO1_SHADOW_REG(0x34)
 132 #define QSD8X50_GPIO_OE_7       MSM_GPIO1_SHADOW_REG(0x38)
 133
 134 /* same pin map as above, input read */
 135 #define QSD8X50_GPIO_IN_0       MSM_GPIO1_SHADOW_REG(0x50)
 136 #define QSD8X50_GPIO_IN_1       MSM_GPIO2_SHADOW_REG(0x20)
 137 #define QSD8X50_GPIO_IN_2       MSM_GPIO1_SHADOW_REG(0x54)
 138 #define QSD8X50_GPIO_IN_3       MSM_GPIO1_SHADOW_REG(0x58)
 139 #define QSD8X50_GPIO_IN_4       MSM_GPIO1_SHADOW_REG(0x5C)
 140 #define QSD8X50_GPIO_IN_5       MSM_GPIO1_SHADOW_REG(0x60)
 141 #define QSD8X50_GPIO_IN_6       MSM_GPIO1_SHADOW_REG(0x64)
 142 #define QSD8X50_GPIO_IN_7       MSM_GPIO1_SHADOW_REG(0x68)
 143
 144 /* same pin map as above, 1=edge 0=level interrup */
 145 #define QSD8X50_GPIO_INT_EDGE_0 MSM_GPIO1_SHADOW_REG(0x70)
 146 #define QSD8X50_GPIO_INT_EDGE_1 MSM_GPIO2_SHADOW_REG(0x50)
 147 #define QSD8X50_GPIO_INT_EDGE_2 MSM_GPIO1_SHADOW_REG(0x74)
 148 #define QSD8X50_GPIO_INT_EDGE_3 MSM_GPIO1_SHADOW_REG(0x78)
 149 #define QSD8X50_GPIO_INT_EDGE_4 MSM_GPIO1_SHADOW_REG(0x7C)
 150 #define QSD8X50_GPIO_INT_EDGE_5 MSM_GPIO1_SHADOW_REG(0x80)
 151 #define QSD8X50_GPIO_INT_EDGE_6 MSM_GPIO1_SHADOW_REG(0x84)
 152 #define QSD8X50_GPIO_INT_EDGE_7 MSM_GPIO1_SHADOW_REG(0x88)
 153
 154 /* same pin map as above, 1=positive 0=negative */
 155 #define QSD8X50_GPIO_INT_POS_0  MSM_GPIO1_SHADOW_REG(0x90)
 156 #define QSD8X50_GPIO_INT_POS_1  MSM_GPIO2_SHADOW_REG(0x58)
 157 #define QSD8X50_GPIO_INT_POS_2  MSM_GPIO1_SHADOW_REG(0x94)
 158 #define QSD8X50_GPIO_INT_POS_3  MSM_GPIO1_SHADOW_REG(0x98)
 159 #define QSD8X50_GPIO_INT_POS_4  MSM_GPIO1_SHADOW_REG(0x9C)
 160 #define QSD8X50_GPIO_INT_POS_5  MSM_GPIO1_SHADOW_REG(0xA0)
 161 #define QSD8X50_GPIO_INT_POS_6  MSM_GPIO1_SHADOW_REG(0xA4)
 162 #define QSD8X50_GPIO_INT_POS_7  MSM_GPIO1_SHADOW_REG(0xA8)
 163
 164 /* same pin map as above, interrupt enable */
 165 #define QSD8X50_GPIO_INT_EN_0   MSM_GPIO1_SHADOW_REG(0xB0)
 166 #define QSD8X50_GPIO_INT_EN_1   MSM_GPIO2_SHADOW_REG(0x60)
 167 #define QSD8X50_GPIO_INT_EN_2   MSM_GPIO1_SHADOW_REG(0xB4)
 168 #define QSD8X50_GPIO_INT_EN_3   MSM_GPIO1_SHADOW_REG(0xB8)
 169 #define QSD8X50_GPIO_INT_EN_4   MSM_GPIO1_SHADOW_REG(0xBC)
 170 #define QSD8X50_GPIO_INT_EN_5   MSM_GPIO1_SHADOW_REG(0xC0)
 171 #define QSD8X50_GPIO_INT_EN_6   MSM_GPIO1_SHADOW_REG(0xC4)
 172 #define QSD8X50_GPIO_INT_EN_7   MSM_GPIO1_SHADOW_REG(0xC8)
 173
 174 /* same pin map as above, write 1 to clear interrupt */
 175 #define QSD8X50_GPIO_INT_CLEAR_0        MSM_GPIO1_SHADOW_REG(0xD0)
 176 #define QSD8X50_GPIO_INT_CLEAR_1        MSM_GPIO2_SHADOW_REG(0x68)
 177 #define QSD8X50_GPIO_INT_CLEAR_2        MSM_GPIO1_SHADOW_REG(0xD4)
 178 #define QSD8X50_GPIO_INT_CLEAR_3        MSM_GPIO1_SHADOW_REG(0xD8)
 179 #define QSD8X50_GPIO_INT_CLEAR_4        MSM_GPIO1_SHADOW_REG(0xDC)
 180 #define QSD8X50_GPIO_INT_CLEAR_5        MSM_GPIO1_SHADOW_REG(0xE0)
 181 #define QSD8X50_GPIO_INT_CLEAR_6        MSM_GPIO1_SHADOW_REG(0xE4)
 182 #define QSD8X50_GPIO_INT_CLEAR_7        MSM_GPIO1_SHADOW_REG(0xE8)
 183
 184 /* same pin map as above, 1=interrupt pending */
 185 #define QSD8X50_GPIO_INT_STATUS_0       MSM_GPIO1_SHADOW_REG(0xF0)
 186 #define QSD8X50_GPIO_INT_STATUS_1       MSM_GPIO2_SHADOW_REG(0x70)
 187 #define QSD8X50_GPIO_INT_STATUS_2       MSM_GPIO1_SHADOW_REG(0xF4)
 188 #define QSD8X50_GPIO_INT_STATUS_3       MSM_GPIO1_SHADOW_REG(0xF8)
 189 #define QSD8X50_GPIO_INT_STATUS_4       MSM_GPIO1_SHADOW_REG(0xFC)
 190 #define QSD8X50_GPIO_INT_STATUS_5       MSM_GPIO1_SHADOW_REG(0x100)
 191 #define QSD8X50_GPIO_INT_STATUS_6       MSM_GPIO1_SHADOW_REG(0x104)
 192 #define QSD8X50_GPIO_INT_STATUS_7       MSM_GPIO1_SHADOW_REG(0x108)
 193
 194 /*
 195  * MSM7X30 registers
 196  */
 197 /* output value */
 198 #define MSM7X30_GPIO_OUT_0      MSM_GPIO1_REG(0x00)   /* gpio  15-0   */
 199 #define MSM7X30_GPIO_OUT_1      MSM_GPIO2_REG(0x00)   /* gpio  43-16  */
 200 #define MSM7X30_GPIO_OUT_2      MSM_GPIO1_REG(0x04)   /* gpio  67-44  */
 201 #define MSM7X30_GPIO_OUT_3      MSM_GPIO1_REG(0x08)   /* gpio  94-68  */
 202 #define MSM7X30_GPIO_OUT_4      MSM_GPIO1_REG(0x0C)   /* gpio 106-95  */
 203 #define MSM7X30_GPIO_OUT_5      MSM_GPIO1_REG(0x50)   /* gpio 133-107 */
 204 #define MSM7X30_GPIO_OUT_6      MSM_GPIO1_REG(0xC4)   /* gpio 150-134 */
 205 #define MSM7X30_GPIO_OUT_7      MSM_GPIO1_REG(0x214)  /* gpio 181-151 */
 206
 207 /* same pin map as above, output enable */
 208 #define MSM7X30_GPIO_OE_0       MSM_GPIO1_REG(0x10)
 209 #define MSM7X30_GPIO_OE_1       MSM_GPIO2_REG(0x08)
 210 #define MSM7X30_GPIO_OE_2       MSM_GPIO1_REG(0x14)
 211 #define MSM7X30_GPIO_OE_3       MSM_GPIO1_REG(0x18)
 212 #define MSM7X30_GPIO_OE_4       MSM_GPIO1_REG(0x1C)
 213 #define MSM7X30_GPIO_OE_5       MSM_GPIO1_REG(0x54)
 214 #define MSM7X30_GPIO_OE_6       MSM_GPIO1_REG(0xC8)
 215 #define MSM7X30_GPIO_OE_7       MSM_GPIO1_REG(0x218)
 216
 217 /* same pin map as above, input read */
 218 #define MSM7X30_GPIO_IN_0       MSM_GPIO1_REG(0x34)
 219 #define MSM7X30_GPIO_IN_1       MSM_GPIO2_REG(0x20)
 220 #define MSM7X30_GPIO_IN_2       MSM_GPIO1_REG(0x38)
 221 #define MSM7X30_GPIO_IN_3       MSM_GPIO1_REG(0x3C)
 222 #define MSM7X30_GPIO_IN_4       MSM_GPIO1_REG(0x40)
 223 #define MSM7X30_GPIO_IN_5       MSM_GPIO1_REG(0x44)
 224 #define MSM7X30_GPIO_IN_6       MSM_GPIO1_REG(0xCC)
 225 #define MSM7X30_GPIO_IN_7       MSM_GPIO1_REG(0x21C)
 226
 227 /* same pin map as above, 1=edge 0=level interrup */
 228 #define MSM7X30_GPIO_INT_EDGE_0 MSM_GPIO1_REG(0x60)
 229 #define MSM7X30_GPIO_INT_EDGE_1 MSM_GPIO2_REG(0x50)
 230 #define MSM7X30_GPIO_INT_EDGE_2 MSM_GPIO1_REG(0x64)
 231 #define MSM7X30_GPIO_INT_EDGE_3 MSM_GPIO1_REG(0x68)
 232 #define MSM7X30_GPIO_INT_EDGE_4 MSM_GPIO1_REG(0x6C)
 233 #define MSM7X30_GPIO_INT_EDGE_5 MSM_GPIO1_REG(0xC0)
 234 #define MSM7X30_GPIO_INT_EDGE_6 MSM_GPIO1_REG(0xD0)
 235 #define MSM7X30_GPIO_INT_EDGE_7 MSM_GPIO1_REG(0x240)
 236
 237 /* same pin map as above, 1=positive 0=negative */
 238 #define MSM7X30_GPIO_INT_POS_0  MSM_GPIO1_REG(0x70)
 239 #define MSM7X30_GPIO_INT_POS_1  MSM_GPIO2_REG(0x58)
 240 #define MSM7X30_GPIO_INT_POS_2  MSM_GPIO1_REG(0x74)
 241 #define MSM7X30_GPIO_INT_POS_3  MSM_GPIO1_REG(0x78)
 242 #define MSM7X30_GPIO_INT_POS_4  MSM_GPIO1_REG(0x7C)
 243 #define MSM7X30_GPIO_INT_POS_5  MSM_GPIO1_REG(0xBC)
 244 #define MSM7X30_GPIO_INT_POS_6  MSM_GPIO1_REG(0xD4)
 245 #define MSM7X30_GPIO_INT_POS_7  MSM_GPIO1_REG(0x228)
 246
 247 /* same pin map as above, interrupt enable */
 248 #define MSM7X30_GPIO_INT_EN_0   MSM_GPIO1_REG(0x80)
 249 #define MSM7X30_GPIO_INT_EN_1   MSM_GPIO2_REG(0x60)
 250 #define MSM7X30_GPIO_INT_EN_2   MSM_GPIO1_REG(0x84)
 251 #define MSM7X30_GPIO_INT_EN_3   MSM_GPIO1_REG(0x88)
 252 #define MSM7X30_GPIO_INT_EN_4   MSM_GPIO1_REG(0x8C)
 253 #define MSM7X30_GPIO_INT_EN_5   MSM_GPIO1_REG(0xB8)
 254 #define MSM7X30_GPIO_INT_EN_6   MSM_GPIO1_REG(0xD8)
 255 #define MSM7X30_GPIO_INT_EN_7   MSM_GPIO1_REG(0x22C)
 256
 257 /* same pin map as above, write 1 to clear interrupt */
 258 #define MSM7X30_GPIO_INT_CLEAR_0        MSM_GPIO1_REG(0x90)
 259 #define MSM7X30_GPIO_INT_CLEAR_1        MSM_GPIO2_REG(0x68)
 260 #define MSM7X30_GPIO_INT_CLEAR_2        MSM_GPIO1_REG(0x94)
 261 #define MSM7X30_GPIO_INT_CLEAR_3        MSM_GPIO1_REG(0x98)
 262 #define MSM7X30_GPIO_INT_CLEAR_4        MSM_GPIO1_REG(0x9C)
 263 #define MSM7X30_GPIO_INT_CLEAR_5        MSM_GPIO1_REG(0xB4)
 264 #define MSM7X30_GPIO_INT_CLEAR_6        MSM_GPIO1_REG(0xDC)
 265 #define MSM7X30_GPIO_INT_CLEAR_7        MSM_GPIO1_REG(0x230)
 266
 267 /* same pin map as above, 1=interrupt pending */
 268 #define MSM7X30_GPIO_INT_STATUS_0       MSM_GPIO1_REG(0xA0)
 269 #define MSM7X30_GPIO_INT_STATUS_1       MSM_GPIO2_REG(0x70)
 270 #define MSM7X30_GPIO_INT_STATUS_2       MSM_GPIO1_REG(0xA4)
 271 #define MSM7X30_GPIO_INT_STATUS_3       MSM_GPIO1_REG(0xA8)
 272 #define MSM7X30_GPIO_INT_STATUS_4       MSM_GPIO1_REG(0xAC)
 273 #define MSM7X30_GPIO_INT_STATUS_5       MSM_GPIO1_REG(0xB0)
 274 #define MSM7X30_GPIO_INT_STATUS_6       MSM_GPIO1_REG(0xE0)
 275 #define MSM7X30_GPIO_INT_STATUS_7       MSM_GPIO1_REG(0x234)
 276
 277 #define FIRST_GPIO_IRQ MSM_GPIO_TO_INT(0)
 278
 279 #define MSM_GPIO_BANK(soc, bank, first, last)                           \
 280         {                                                               \
 281                 .regs[MSM_GPIO_OUT] =         soc##_GPIO_OUT_##bank,    \
 282                 .regs[MSM_GPIO_IN] =          soc##_GPIO_IN_##bank,     \
 283                 .regs[MSM_GPIO_INT_STATUS] =  soc##_GPIO_INT_STATUS_##bank, \
 284                 .regs[MSM_GPIO_INT_CLEAR] =   soc##_GPIO_INT_CLEAR_##bank, \
 285                 .regs[MSM_GPIO_INT_EN] =      soc##_GPIO_INT_EN_##bank, \
 286                 .regs[MSM_GPIO_INT_EDGE] =    soc##_GPIO_INT_EDGE_##bank, \
 287                 .regs[MSM_GPIO_INT_POS] =     soc##_GPIO_INT_POS_##bank, \
 288                 .regs[MSM_GPIO_OE] =          soc##_GPIO_OE_##bank,     \
 289                 .chip = {                                               \
 290                         .base = (first),                                \
 291                         .ngpio = (last) - (first) + 1,                  \
 292                         .get = msm_gpio_get,                            \
 293                         .set = msm_gpio_set,                            \
 294                         .direction_input = msm_gpio_direction_input,    \
 295                         .direction_output = msm_gpio_direction_output,  \
 296                         .to_irq = msm_gpio_to_irq,                      \
 297                         .request = msm_gpio_request,                    \
 298                         .free = msm_gpio_free,                          \
 299                 }                                                       \
 300         }
 301
 302 #define MSM_GPIO_BROKEN_INT_CLEAR 1
 303
 304 enum msm_gpio_reg {
 305         MSM_GPIO_IN,
 306         MSM_GPIO_OUT,
 307         MSM_GPIO_INT_STATUS,
 308         MSM_GPIO_INT_CLEAR,
 309         MSM_GPIO_INT_EN,
 310         MSM_GPIO_INT_EDGE,
 311         MSM_GPIO_INT_POS,
 312         MSM_GPIO_OE,
 313         MSM_GPIO_REG_NR
 314 };
 315
 316 struct msm_gpio_chip {
 317         spinlock_t              lock;
 318         struct gpio_chip        chip;
 319         unsigned long           regs[MSM_GPIO_REG_NR];
 320 #if MSM_GPIO_BROKEN_INT_CLEAR
 321         unsigned                int_status_copy;
 322 #endif
 323         unsigned int            both_edge_detect;
 324         unsigned int            int_enable[2]; /* 0: awake, 1: sleep */
 325         void __iomem            *base;
 326 };
 327
 328 struct msm_gpio_initdata {
 329         struct msm_gpio_chip *chips;
 330         int count;
 331 };
 332
 333 static void msm_gpio_writel(struct msm_gpio_chip *chip, u32 val,
 334                             enum msm_gpio_reg reg)
 335 {
 336         writel(val, chip->base + chip->regs[reg]);
 337 }
 338
 339 static u32 msm_gpio_readl(struct msm_gpio_chip *chip, enum msm_gpio_reg reg)
 340 {
 341         return readl(chip->base + chip->regs[reg]);
 342 }
 343
 344 static int msm_gpio_write(struct msm_gpio_chip *msm_chip,
 345                           unsigned offset, unsigned on)
 346 {
 347         unsigned mask = BIT(offset);
 348         unsigned val;
 349
 350         val = msm_gpio_readl(msm_chip, MSM_GPIO_OUT);
 351         if (on)
 352                 msm_gpio_writel(msm_chip, val | mask, MSM_GPIO_OUT);
 353         else
 354                 msm_gpio_writel(msm_chip, val & ~mask, MSM_GPIO_OUT);
 355         return 0;
 356 }
 357
 358 static void msm_gpio_update_both_edge_detect(struct msm_gpio_chip *msm_chip)
 359 {
 360         int loop_limit = 100;
 361         unsigned pol, val, val2, intstat;
 362         do {
 363                 val = msm_gpio_readl(msm_chip, MSM_GPIO_IN);
 364                 pol = msm_gpio_readl(msm_chip, MSM_GPIO_INT_POS);
 365                 pol = (pol & ~msm_chip->both_edge_detect) |
 366                       (~val & msm_chip->both_edge_detect);
 367                 msm_gpio_writel(msm_chip, pol, MSM_GPIO_INT_POS);
 368                 intstat = msm_gpio_readl(msm_chip, MSM_GPIO_INT_STATUS);
 369                 val2 = msm_gpio_readl(msm_chip, MSM_GPIO_IN);
 370                 if (((val ^ val2) & msm_chip->both_edge_detect & ~intstat) == 0)
 371                         return;
 372         } while (loop_limit-- > 0);
 373         printk(KERN_ERR "msm_gpio_update_both_edge_detect, "
 374                "failed to reach stable state %x != %x\n", val, val2);
 375 }
 376
 377 static int msm_gpio_clear_detect_status(struct msm_gpio_chip *msm_chip,
 378                                         unsigned offset)
 379 {
 380         unsigned bit = BIT(offset);
 381
 382 #if MSM_GPIO_BROKEN_INT_CLEAR
 383         /* Save interrupts that already triggered before we loose them. */
 384         /* Any interrupt that triggers between the read of int_status */
 385         /* and the write to int_clear will still be lost though. */
 386         msm_chip->int_status_copy |=
 387                 msm_gpio_readl(msm_chip, MSM_GPIO_INT_STATUS);
 388         msm_chip->int_status_copy &= ~bit;
 389 #endif
 390         msm_gpio_writel(msm_chip, bit, MSM_GPIO_INT_CLEAR);
 391         msm_gpio_update_both_edge_detect(msm_chip);
 392         return 0;
 393 }
 394
 395 static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 396 {
 397         struct msm_gpio_chip *msm_chip;
 398         unsigned long irq_flags;
 399         u32 val;
 400
 401         msm_chip = container_of(chip, struct msm_gpio_chip, chip);
 402         spin_lock_irqsave(&msm_chip->lock, irq_flags);
 403         val = msm_gpio_readl(msm_chip, MSM_GPIO_OE) & ~BIT(offset);
 404         msm_gpio_writel(msm_chip, val, MSM_GPIO_OE);
 405         spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
 406         return 0;
 407 }
 408
 409 static int
 410 msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)
 411 {
 412         struct msm_gpio_chip *msm_chip;
 413         unsigned long irq_flags;
 414         u32 val;
 415
 416         msm_chip = container_of(chip, struct msm_gpio_chip, chip);
 417         spin_lock_irqsave(&msm_chip->lock, irq_flags);
 418         msm_gpio_write(msm_chip, offset, value);
 419         val = msm_gpio_readl(msm_chip, MSM_GPIO_OE) | BIT(offset);
 420         msm_gpio_writel(msm_chip, val, MSM_GPIO_OE);
 421         spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
 422         return 0;
 423 }
 424
 425 static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
 426 {
 427         struct msm_gpio_chip *msm_chip;
 428
 429         msm_chip = container_of(chip, struct msm_gpio_chip, chip);
 430         return (msm_gpio_readl(msm_chip, MSM_GPIO_IN) & (1U << offset)) ? 1 : 0;
 431 }
 432
 433 static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 434 {
 435         struct msm_gpio_chip *msm_chip;
 436         unsigned long irq_flags;
 437
 438         msm_chip = container_of(chip, struct msm_gpio_chip, chip);
 439         spin_lock_irqsave(&msm_chip->lock, irq_flags);
 440         msm_gpio_write(msm_chip, offset, value);
 441         spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
 442 }
 443
 444 static int msm_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 445 {
 446         return MSM_GPIO_TO_INT(chip->base + offset);
 447 }
 448
 449 #ifdef CONFIG_MSM_GPIOMUX
 450 static int msm_gpio_request(struct gpio_chip *chip, unsigned offset)
 451 {
 452         return msm_gpiomux_get(chip->base + offset);
 453 }
 454
 455 static void msm_gpio_free(struct gpio_chip *chip, unsigned offset)
 456 {
 457         msm_gpiomux_put(chip->base + offset);
 458 }
 459 #else
 460 #define msm_gpio_request NULL
 461 #define msm_gpio_free NULL
 462 #endif
 463
 464 static struct msm_gpio_chip *msm_gpio_chips;
 465 static int msm_gpio_count;
 466
 467 static struct msm_gpio_chip msm_gpio_chips_msm7x01[] = {
 468         MSM_GPIO_BANK(MSM7X00, 0,   0,  15),
 469         MSM_GPIO_BANK(MSM7X00, 1,  16,  42),
 470         MSM_GPIO_BANK(MSM7X00, 2,  43,  67),
 471         MSM_GPIO_BANK(MSM7X00, 3,  68,  94),
 472         MSM_GPIO_BANK(MSM7X00, 4,  95, 106),
 473         MSM_GPIO_BANK(MSM7X00, 5, 107, 121),
 474 };
 475
 476 static struct msm_gpio_initdata msm_gpio_7x01_init = {
 477         .chips = msm_gpio_chips_msm7x01,
 478         .count = ARRAY_SIZE(msm_gpio_chips_msm7x01),
 479 };
 480
 481 static struct msm_gpio_chip msm_gpio_chips_msm7x30[] = {
 482         MSM_GPIO_BANK(MSM7X30, 0,   0,  15),
 483         MSM_GPIO_BANK(MSM7X30, 1,  16,  43),
 484         MSM_GPIO_BANK(MSM7X30, 2,  44,  67),
 485         MSM_GPIO_BANK(MSM7X30, 3,  68,  94),
 486         MSM_GPIO_BANK(MSM7X30, 4,  95, 106),
 487         MSM_GPIO_BANK(MSM7X30, 5, 107, 133),
 488         MSM_GPIO_BANK(MSM7X30, 6, 134, 150),
 489         MSM_GPIO_BANK(MSM7X30, 7, 151, 181),
 490 };
 491
 492 static struct msm_gpio_initdata msm_gpio_7x30_init = {
 493         .chips = msm_gpio_chips_msm7x30,
 494         .count = ARRAY_SIZE(msm_gpio_chips_msm7x30),
 495 };
 496
 497 static struct msm_gpio_chip msm_gpio_chips_qsd8x50[] = {
 498         MSM_GPIO_BANK(QSD8X50, 0,   0,  15),
 499         MSM_GPIO_BANK(QSD8X50, 1,  16,  42),
 500         MSM_GPIO_BANK(QSD8X50, 2,  43,  67),
 501         MSM_GPIO_BANK(QSD8X50, 3,  68,  94),
 502         MSM_GPIO_BANK(QSD8X50, 4,  95, 103),
 503         MSM_GPIO_BANK(QSD8X50, 5, 104, 121),
 504         MSM_GPIO_BANK(QSD8X50, 6, 122, 152),
 505         MSM_GPIO_BANK(QSD8X50, 7, 153, 164),
 506 };
 507
 508 static struct msm_gpio_initdata msm_gpio_8x50_init = {
 509         .chips = msm_gpio_chips_qsd8x50,
 510         .count = ARRAY_SIZE(msm_gpio_chips_qsd8x50),
 511 };
 512
 513 static void msm_gpio_irq_ack(struct irq_data *d)
 514 {
 515         unsigned long irq_flags;
 516         struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d);
 517         spin_lock_irqsave(&msm_chip->lock, irq_flags);
 518         msm_gpio_clear_detect_status(msm_chip,
 519                                      d->irq - gpio_to_irq(msm_chip->chip.base));
 520         spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
 521 }
 522
 523 static void msm_gpio_irq_mask(struct irq_data *d)
 524 {
 525         unsigned long irq_flags;
 526         struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d);
 527         unsigned offset = d->irq - gpio_to_irq(msm_chip->chip.base);
 528
 529         spin_lock_irqsave(&msm_chip->lock, irq_flags);
 530         /* level triggered interrupts are also latched */
 531         if (!(msm_gpio_readl(msm_chip, MSM_GPIO_INT_EDGE) & BIT(offset)))
 532                 msm_gpio_clear_detect_status(msm_chip, offset);
 533         msm_chip->int_enable[0] &= ~BIT(offset);
 534         msm_gpio_writel(msm_chip, msm_chip->int_enable[0], MSM_GPIO_INT_EN);
 535         spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
 536 }
 537
 538 static void msm_gpio_irq_unmask(struct irq_data *d)
 539 {
 540         unsigned long irq_flags;
 541         struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d);
 542         unsigned offset = d->irq - gpio_to_irq(msm_chip->chip.base);
 543
 544         spin_lock_irqsave(&msm_chip->lock, irq_flags);
 545         /* level triggered interrupts are also latched */
 546         if (!(msm_gpio_readl(msm_chip, MSM_GPIO_INT_EDGE) & BIT(offset)))
 547                 msm_gpio_clear_detect_status(msm_chip, offset);
 548         msm_chip->int_enable[0] |= BIT(offset);
 549         msm_gpio_writel(msm_chip, msm_chip->int_enable[0], MSM_GPIO_INT_EN);
 550         spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
 551 }
 552
 553 static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
 554 {
 555         unsigned long irq_flags;
 556         struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d);
 557         unsigned offset = d->irq - gpio_to_irq(msm_chip->chip.base);
 558
 559         spin_lock_irqsave(&msm_chip->lock, irq_flags);
 560
 561         if (on)
 562                 msm_chip->int_enable[1] |= BIT(offset);
 563         else
 564                 msm_chip->int_enable[1] &= ~BIT(offset);
 565
 566         spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
 567         return 0;
 568 }
 569
 570 static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type)
 571 {
 572         unsigned long irq_flags;
 573         struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d);
 574         unsigned offset = d->irq - gpio_to_irq(msm_chip->chip.base);
 575         unsigned val, mask = BIT(offset);
 576
 577         spin_lock_irqsave(&msm_chip->lock, irq_flags);
 578         val = msm_gpio_readl(msm_chip, MSM_GPIO_INT_EDGE);
 579         if (flow_type & IRQ_TYPE_EDGE_BOTH) {
 580                 msm_gpio_writel(msm_chip, val | mask, MSM_GPIO_INT_EDGE);
 581                 __irq_set_handler_locked(d->irq, handle_edge_irq);
 582         } else {
 583                 msm_gpio_writel(msm_chip, val & ~mask, MSM_GPIO_INT_EDGE);
 584                 __irq_set_handler_locked(d->irq, handle_level_irq);
 585         }
 586         if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
 587                 msm_chip->both_edge_detect |= mask;
 588                 msm_gpio_update_both_edge_detect(msm_chip);
 589         } else {
 590                 msm_chip->both_edge_detect &= ~mask;
 591                 val = msm_gpio_readl(msm_chip, MSM_GPIO_INT_POS);
 592                 if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_HIGH))
 593                         val |= mask;
 594                 else
 595                         val &= ~mask;
 596                 msm_gpio_writel(msm_chip, val, MSM_GPIO_INT_POS);
 597         }
 598         spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
 599         return 0;
 600 }
 601
 602 static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 603 {
 604         int i, j, mask;
 605         unsigned val;
 606
 607         for (i = 0; i < msm_gpio_count; i++) {
 608                 struct msm_gpio_chip *msm_chip = &msm_gpio_chips[i];
 609                 val = msm_gpio_readl(msm_chip, MSM_GPIO_INT_STATUS);
 610                 val &= msm_chip->int_enable[0];
 611                 while (val) {
 612                         mask = val & -val;
 613                         j = fls(mask) - 1;
 614                         /* printk("%s %08x %08x bit %d gpio %d irq %d\n",
 615                                 __func__, v, m, j, msm_chip->chip.start + j,
 616                                 FIRST_GPIO_IRQ + msm_chip->chip.start + j); */
 617                         val &= ~mask;
 618                         generic_handle_irq(FIRST_GPIO_IRQ +
 619                                            msm_chip->chip.base + j);
 620                 }
 621         }
 622         desc->irq_data.chip->irq_ack(&desc->irq_data);
 623 }
 624
 625 static struct irq_chip msm_gpio_irq_chip = {
 626         .name          = "msmgpio",
 627         .irq_ack       = msm_gpio_irq_ack,
 628         .irq_mask      = msm_gpio_irq_mask,
 629         .irq_unmask    = msm_gpio_irq_unmask,
 630         .irq_set_wake  = msm_gpio_irq_set_wake,
 631         .irq_set_type  = msm_gpio_irq_set_type,
 632 };
 633
 634 static int gpio_msm_v1_probe(struct platform_device *pdev)
 635 {
 636         int i, j = 0;
 637         const struct platform_device_id *dev_id = platform_get_device_id(pdev);
 638         struct msm_gpio_initdata *data;
 639         int irq1, irq2;
 640         struct resource *res;
 641         void __iomem *base1, __iomem *base2;
 642
 643         data = (struct msm_gpio_initdata *)dev_id->driver_data;
 644         msm_gpio_chips = data->chips;
 645         msm_gpio_count = data->count;
 646
 647         irq1 = platform_get_irq(pdev, 0);
 648         if (irq1 < 0)
 649                 return irq1;
 650
 651         irq2 = platform_get_irq(pdev, 1);
 652         if (irq2 < 0)
 653                 return irq2;
 654
 655         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 656         base1 = devm_ioremap_resource(&pdev->dev, res);
 657         if (IS_ERR(base1))
 658                 return PTR_ERR(base1);
 659
 660         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 661         base2 = devm_ioremap_resource(&pdev->dev, res);
 662         if (IS_ERR(base2))
 663                 return PTR_ERR(base2);
 664
 665         for (i = FIRST_GPIO_IRQ; i < FIRST_GPIO_IRQ + NR_GPIO_IRQS; i++) {
 666                 if (i - FIRST_GPIO_IRQ >=
 667                         msm_gpio_chips[j].chip.base +
 668                         msm_gpio_chips[j].chip.ngpio)
 669                         j++;
 670                 irq_set_chip_data(i, &msm_gpio_chips[j]);
 671                 irq_set_chip_and_handler(i, &msm_gpio_irq_chip,
 672                                          handle_edge_irq);
 673                 set_irq_flags(i, IRQF_VALID);
 674         }
 675
 676         for (i = 0; i < msm_gpio_count; i++) {
 677                 if (i == 1)
 678                         msm_gpio_chips[i].base = base2;
 679                 else
 680                         msm_gpio_chips[i].base = base1;
 681                 spin_lock_init(&msm_gpio_chips[i].lock);
 682                 msm_gpio_writel(&msm_gpio_chips[i], 0, MSM_GPIO_INT_EN);
 683                 gpiochip_add(&msm_gpio_chips[i].chip);
 684         }
 685
 686         irq_set_chained_handler(irq1, msm_gpio_irq_handler);
 687         irq_set_chained_handler(irq2, msm_gpio_irq_handler);
 688         irq_set_irq_wake(irq1, 1);
 689         irq_set_irq_wake(irq2, 2);
 690         return 0;
 691 }
 692
 693 static struct platform_device_id gpio_msm_v1_device_ids[] = {
 694         { "gpio-msm-7201", (unsigned long)&msm_gpio_7x01_init },
 695         { "gpio-msm-7x30", (unsigned long)&msm_gpio_7x30_init },
 696         { "gpio-msm-8x50", (unsigned long)&msm_gpio_8x50_init },
 697         { }
 698 };
 699 MODULE_DEVICE_TABLE(platform, gpio_msm_v1_device_ids);
 700
 701 static struct platform_driver gpio_msm_v1_driver = {
 702         .driver = {
 703                 .name = "gpio-msm-v1",
 704                 .owner = THIS_MODULE,
 705         },
 706         .probe = gpio_msm_v1_probe,
 707         .id_table = gpio_msm_v1_device_ids,
 708 };
 709
 710 static int __init gpio_msm_v1_init(void)
 711 {
 712         return platform_driver_register(&gpio_msm_v1_driver);
 713 }
 714 postcore_initcall(gpio_msm_v1_init);
 715 MODULE_LICENSE("GPL v2");