1 #include <linux/interrupt.h>
2 #include <linux/dmar.h>
3 #include <linux/spinlock.h>
4 #include <linux/slab.h>
5 #include <linux/jiffies.h>
6 #include <linux/hpet.h>
9 #include <linux/intel-iommu.h>
10 #include <linux/acpi.h>
11 #include <asm/io_apic.h>
14 #include <asm/irq_remapping.h>
15 #include <asm/pci-direct.h>
16 #include <asm/msidef.h>
18 #include "irq_remapping.h"
21 struct intel_iommu
*iommu
;
23 unsigned int bus
; /* PCI bus number */
24 unsigned int devfn
; /* PCI devfn number */
28 struct intel_iommu
*iommu
;
34 #define IR_X2APIC_MODE(mode) (mode ? (1 << 11) : 0)
35 #define IRTE_DEST(dest) ((x2apic_mode) ? dest : dest << 8)
37 static struct ioapic_scope ir_ioapic
[MAX_IO_APICS
];
38 static struct hpet_scope ir_hpet
[MAX_HPET_TBS
];
39 static int ir_ioapic_num
, ir_hpet_num
;
46 * ->iommu->register_lock
48 * intel_irq_remap_ops.{supported,prepare,enable,disable,reenable} are called
49 * in single-threaded environment with interrupt disabled, so no need to tabke
50 * the dmar_global_lock.
52 static DEFINE_RAW_SPINLOCK(irq_2_ir_lock
);
54 static int __init
parse_ioapics_under_ir(void);
56 static struct irq_2_iommu
*irq_2_iommu(unsigned int irq
)
58 struct irq_cfg
*cfg
= irq_get_chip_data(irq
);
59 return cfg
? &cfg
->irq_2_iommu
: NULL
;
62 static int get_irte(int irq
, struct irte
*entry
)
64 struct irq_2_iommu
*irq_iommu
= irq_2_iommu(irq
);
68 if (!entry
|| !irq_iommu
)
71 raw_spin_lock_irqsave(&irq_2_ir_lock
, flags
);
73 index
= irq_iommu
->irte_index
+ irq_iommu
->sub_handle
;
74 *entry
= *(irq_iommu
->iommu
->ir_table
->base
+ index
);
76 raw_spin_unlock_irqrestore(&irq_2_ir_lock
, flags
);
80 static int alloc_irte(struct intel_iommu
*iommu
, int irq
, u16 count
)
82 struct ir_table
*table
= iommu
->ir_table
;
83 struct irq_2_iommu
*irq_iommu
= irq_2_iommu(irq
);
84 struct irq_cfg
*cfg
= irq_get_chip_data(irq
);
85 unsigned int mask
= 0;
89 if (!count
|| !irq_iommu
)
93 count
= __roundup_pow_of_two(count
);
97 if (mask
> ecap_max_handle_mask(iommu
->ecap
)) {
99 "Requested mask %x exceeds the max invalidation handle"
100 " mask value %Lx\n", mask
,
101 ecap_max_handle_mask(iommu
->ecap
));
105 raw_spin_lock_irqsave(&irq_2_ir_lock
, flags
);
106 index
= bitmap_find_free_region(table
->bitmap
,
107 INTR_REMAP_TABLE_ENTRIES
, mask
);
109 pr_warn("IR%d: can't allocate an IRTE\n", iommu
->seq_id
);
112 irq_iommu
->iommu
= iommu
;
113 irq_iommu
->irte_index
= index
;
114 irq_iommu
->sub_handle
= 0;
115 irq_iommu
->irte_mask
= mask
;
117 raw_spin_unlock_irqrestore(&irq_2_ir_lock
, flags
);
122 static int qi_flush_iec(struct intel_iommu
*iommu
, int index
, int mask
)
126 desc
.low
= QI_IEC_IIDEX(index
) | QI_IEC_TYPE
| QI_IEC_IM(mask
)
130 return qi_submit_sync(&desc
, iommu
);
133 static int map_irq_to_irte_handle(int irq
, u16
*sub_handle
)
135 struct irq_2_iommu
*irq_iommu
= irq_2_iommu(irq
);
142 raw_spin_lock_irqsave(&irq_2_ir_lock
, flags
);
143 *sub_handle
= irq_iommu
->sub_handle
;
144 index
= irq_iommu
->irte_index
;
145 raw_spin_unlock_irqrestore(&irq_2_ir_lock
, flags
);
149 static int set_irte_irq(int irq
, struct intel_iommu
*iommu
, u16 index
, u16 subhandle
)
151 struct irq_2_iommu
*irq_iommu
= irq_2_iommu(irq
);
152 struct irq_cfg
*cfg
= irq_get_chip_data(irq
);
158 raw_spin_lock_irqsave(&irq_2_ir_lock
, flags
);
161 irq_iommu
->iommu
= iommu
;
162 irq_iommu
->irte_index
= index
;
163 irq_iommu
->sub_handle
= subhandle
;
164 irq_iommu
->irte_mask
= 0;
166 raw_spin_unlock_irqrestore(&irq_2_ir_lock
, flags
);
171 static int modify_irte(int irq
, struct irte
*irte_modified
)
173 struct irq_2_iommu
*irq_iommu
= irq_2_iommu(irq
);
174 struct intel_iommu
*iommu
;
182 raw_spin_lock_irqsave(&irq_2_ir_lock
, flags
);
184 iommu
= irq_iommu
->iommu
;
186 index
= irq_iommu
->irte_index
+ irq_iommu
->sub_handle
;
187 irte
= &iommu
->ir_table
->base
[index
];
189 set_64bit(&irte
->low
, irte_modified
->low
);
190 set_64bit(&irte
->high
, irte_modified
->high
);
191 __iommu_flush_cache(iommu
, irte
, sizeof(*irte
));
193 rc
= qi_flush_iec(iommu
, index
, 0);
194 raw_spin_unlock_irqrestore(&irq_2_ir_lock
, flags
);
199 static struct intel_iommu
*map_hpet_to_ir(u8 hpet_id
)
203 for (i
= 0; i
< MAX_HPET_TBS
; i
++)
204 if (ir_hpet
[i
].id
== hpet_id
)
205 return ir_hpet
[i
].iommu
;
209 static struct intel_iommu
*map_ioapic_to_ir(int apic
)
213 for (i
= 0; i
< MAX_IO_APICS
; i
++)
214 if (ir_ioapic
[i
].id
== apic
)
215 return ir_ioapic
[i
].iommu
;
219 static struct intel_iommu
*map_dev_to_ir(struct pci_dev
*dev
)
221 struct dmar_drhd_unit
*drhd
;
223 drhd
= dmar_find_matched_drhd_unit(dev
);
230 static int clear_entries(struct irq_2_iommu
*irq_iommu
)
232 struct irte
*start
, *entry
, *end
;
233 struct intel_iommu
*iommu
;
236 if (irq_iommu
->sub_handle
)
239 iommu
= irq_iommu
->iommu
;
240 index
= irq_iommu
->irte_index
+ irq_iommu
->sub_handle
;
242 start
= iommu
->ir_table
->base
+ index
;
243 end
= start
+ (1 << irq_iommu
->irte_mask
);
245 for (entry
= start
; entry
< end
; entry
++) {
246 set_64bit(&entry
->low
, 0);
247 set_64bit(&entry
->high
, 0);
249 bitmap_release_region(iommu
->ir_table
->bitmap
, index
,
250 irq_iommu
->irte_mask
);
252 return qi_flush_iec(iommu
, index
, irq_iommu
->irte_mask
);
255 static int free_irte(int irq
)
257 struct irq_2_iommu
*irq_iommu
= irq_2_iommu(irq
);
264 raw_spin_lock_irqsave(&irq_2_ir_lock
, flags
);
266 rc
= clear_entries(irq_iommu
);
268 irq_iommu
->iommu
= NULL
;
269 irq_iommu
->irte_index
= 0;
270 irq_iommu
->sub_handle
= 0;
271 irq_iommu
->irte_mask
= 0;
273 raw_spin_unlock_irqrestore(&irq_2_ir_lock
, flags
);
279 * source validation type
281 #define SVT_NO_VERIFY 0x0 /* no verification is required */
282 #define SVT_VERIFY_SID_SQ 0x1 /* verify using SID and SQ fields */
283 #define SVT_VERIFY_BUS 0x2 /* verify bus of request-id */
286 * source-id qualifier
288 #define SQ_ALL_16 0x0 /* verify all 16 bits of request-id */
289 #define SQ_13_IGNORE_1 0x1 /* verify most significant 13 bits, ignore
290 * the third least significant bit
292 #define SQ_13_IGNORE_2 0x2 /* verify most significant 13 bits, ignore
293 * the second and third least significant bits
295 #define SQ_13_IGNORE_3 0x3 /* verify most significant 13 bits, ignore
296 * the least three significant bits
300 * set SVT, SQ and SID fields of irte to verify
301 * source ids of interrupt requests
303 static void set_irte_sid(struct irte
*irte
, unsigned int svt
,
304 unsigned int sq
, unsigned int sid
)
306 if (disable_sourceid_checking
)
313 static int set_ioapic_sid(struct irte
*irte
, int apic
)
321 down_read(&dmar_global_lock
);
322 for (i
= 0; i
< MAX_IO_APICS
; i
++) {
323 if (ir_ioapic
[i
].id
== apic
) {
324 sid
= (ir_ioapic
[i
].bus
<< 8) | ir_ioapic
[i
].devfn
;
328 up_read(&dmar_global_lock
);
331 pr_warning("Failed to set source-id of IOAPIC (%d)\n", apic
);
335 set_irte_sid(irte
, SVT_VERIFY_SID_SQ
, SQ_ALL_16
, sid
);
340 static int set_hpet_sid(struct irte
*irte
, u8 id
)
348 down_read(&dmar_global_lock
);
349 for (i
= 0; i
< MAX_HPET_TBS
; i
++) {
350 if (ir_hpet
[i
].id
== id
) {
351 sid
= (ir_hpet
[i
].bus
<< 8) | ir_hpet
[i
].devfn
;
355 up_read(&dmar_global_lock
);
358 pr_warning("Failed to set source-id of HPET block (%d)\n", id
);
363 * Should really use SQ_ALL_16. Some platforms are broken.
364 * While we figure out the right quirks for these broken platforms, use
365 * SQ_13_IGNORE_3 for now.
367 set_irte_sid(irte
, SVT_VERIFY_SID_SQ
, SQ_13_IGNORE_3
, sid
);
372 static int set_msi_sid(struct irte
*irte
, struct pci_dev
*dev
)
374 struct pci_dev
*bridge
;
379 /* PCIe device or Root Complex integrated PCI device */
380 if (pci_is_pcie(dev
) || !dev
->bus
->parent
) {
381 set_irte_sid(irte
, SVT_VERIFY_SID_SQ
, SQ_ALL_16
,
382 (dev
->bus
->number
<< 8) | dev
->devfn
);
386 bridge
= pci_find_upstream_pcie_bridge(dev
);
388 if (pci_is_pcie(bridge
))/* this is a PCIe-to-PCI/PCIX bridge */
389 set_irte_sid(irte
, SVT_VERIFY_BUS
, SQ_ALL_16
,
390 (bridge
->bus
->number
<< 8) | dev
->bus
->number
);
391 else /* this is a legacy PCI bridge */
392 set_irte_sid(irte
, SVT_VERIFY_SID_SQ
, SQ_ALL_16
,
393 (bridge
->bus
->number
<< 8) | bridge
->devfn
);
399 static void iommu_set_irq_remapping(struct intel_iommu
*iommu
, int mode
)
405 addr
= virt_to_phys((void *)iommu
->ir_table
->base
);
407 raw_spin_lock_irqsave(&iommu
->register_lock
, flags
);
409 dmar_writeq(iommu
->reg
+ DMAR_IRTA_REG
,
410 (addr
) | IR_X2APIC_MODE(mode
) | INTR_REMAP_TABLE_REG_SIZE
);
412 /* Set interrupt-remapping table pointer */
413 iommu
->gcmd
|= DMA_GCMD_SIRTP
;
414 writel(iommu
->gcmd
, iommu
->reg
+ DMAR_GCMD_REG
);
416 IOMMU_WAIT_OP(iommu
, DMAR_GSTS_REG
,
417 readl
, (sts
& DMA_GSTS_IRTPS
), sts
);
418 raw_spin_unlock_irqrestore(&iommu
->register_lock
, flags
);
421 * global invalidation of interrupt entry cache before enabling
422 * interrupt-remapping.
424 qi_global_iec(iommu
);
426 raw_spin_lock_irqsave(&iommu
->register_lock
, flags
);
428 /* Enable interrupt-remapping */
429 iommu
->gcmd
|= DMA_GCMD_IRE
;
430 iommu
->gcmd
&= ~DMA_GCMD_CFI
; /* Block compatibility-format MSIs */
431 writel(iommu
->gcmd
, iommu
->reg
+ DMAR_GCMD_REG
);
433 IOMMU_WAIT_OP(iommu
, DMAR_GSTS_REG
,
434 readl
, (sts
& DMA_GSTS_IRES
), sts
);
437 * With CFI clear in the Global Command register, we should be
438 * protected from dangerous (i.e. compatibility) interrupts
439 * regardless of x2apic status. Check just to be sure.
441 if (sts
& DMA_GSTS_CFIS
)
443 "Compatibility-format IRQs enabled despite intr remapping;\n"
444 "you are vulnerable to IRQ injection.\n");
446 raw_spin_unlock_irqrestore(&iommu
->register_lock
, flags
);
450 static int intel_setup_irq_remapping(struct intel_iommu
*iommu
, int mode
)
452 struct ir_table
*ir_table
;
454 unsigned long *bitmap
;
456 ir_table
= iommu
->ir_table
= kzalloc(sizeof(struct ir_table
),
459 if (!iommu
->ir_table
)
462 pages
= alloc_pages_node(iommu
->node
, GFP_ATOMIC
| __GFP_ZERO
,
463 INTR_REMAP_PAGE_ORDER
);
466 pr_err("IR%d: failed to allocate pages of order %d\n",
467 iommu
->seq_id
, INTR_REMAP_PAGE_ORDER
);
468 kfree(iommu
->ir_table
);
472 bitmap
= kcalloc(BITS_TO_LONGS(INTR_REMAP_TABLE_ENTRIES
),
473 sizeof(long), GFP_ATOMIC
);
474 if (bitmap
== NULL
) {
475 pr_err("IR%d: failed to allocate bitmap\n", iommu
->seq_id
);
476 __free_pages(pages
, INTR_REMAP_PAGE_ORDER
);
481 ir_table
->base
= page_address(pages
);
482 ir_table
->bitmap
= bitmap
;
484 iommu_set_irq_remapping(iommu
, mode
);
489 * Disable Interrupt Remapping.
491 static void iommu_disable_irq_remapping(struct intel_iommu
*iommu
)
496 if (!ecap_ir_support(iommu
->ecap
))
500 * global invalidation of interrupt entry cache before disabling
501 * interrupt-remapping.
503 qi_global_iec(iommu
);
505 raw_spin_lock_irqsave(&iommu
->register_lock
, flags
);
507 sts
= dmar_readq(iommu
->reg
+ DMAR_GSTS_REG
);
508 if (!(sts
& DMA_GSTS_IRES
))
511 iommu
->gcmd
&= ~DMA_GCMD_IRE
;
512 writel(iommu
->gcmd
, iommu
->reg
+ DMAR_GCMD_REG
);
514 IOMMU_WAIT_OP(iommu
, DMAR_GSTS_REG
,
515 readl
, !(sts
& DMA_GSTS_IRES
), sts
);
518 raw_spin_unlock_irqrestore(&iommu
->register_lock
, flags
);
521 static int __init
dmar_x2apic_optout(void)
523 struct acpi_table_dmar
*dmar
;
524 dmar
= (struct acpi_table_dmar
*)dmar_tbl
;
525 if (!dmar
|| no_x2apic_optout
)
527 return dmar
->flags
& DMAR_X2APIC_OPT_OUT
;
530 static int __init
intel_irq_remapping_supported(void)
532 struct dmar_drhd_unit
*drhd
;
533 struct intel_iommu
*iommu
;
535 if (disable_irq_remap
)
537 if (irq_remap_broken
) {
539 "This system BIOS has enabled interrupt remapping\n"
540 "on a chipset that contains an erratum making that\n"
541 "feature unstable. To maintain system stability\n"
542 "interrupt remapping is being disabled. Please\n"
543 "contact your BIOS vendor for an update\n");
544 add_taint(TAINT_FIRMWARE_WORKAROUND
, LOCKDEP_STILL_OK
);
545 disable_irq_remap
= 1;
549 if (!dmar_ir_support())
552 for_each_iommu(iommu
, drhd
)
553 if (!ecap_ir_support(iommu
->ecap
))
559 static int __init
intel_enable_irq_remapping(void)
561 struct dmar_drhd_unit
*drhd
;
562 struct intel_iommu
*iommu
;
567 x2apic_present
= x2apic_supported();
569 if (parse_ioapics_under_ir() != 1) {
570 printk(KERN_INFO
"Not enable interrupt remapping\n");
574 if (x2apic_present
) {
575 pr_info("Queued invalidation will be enabled to support x2apic and Intr-remapping.\n");
577 eim
= !dmar_x2apic_optout();
580 "Your BIOS is broken and requested that x2apic be disabled.\n"
581 "This will slightly decrease performance.\n"
582 "Use 'intremap=no_x2apic_optout' to override BIOS request.\n");
585 for_each_iommu(iommu
, drhd
) {
587 * If the queued invalidation is already initialized,
588 * shouldn't disable it.
594 * Clear previous faults.
596 dmar_fault(-1, iommu
);
599 * Disable intr remapping and queued invalidation, if already
600 * enabled prior to OS handover.
602 iommu_disable_irq_remapping(iommu
);
604 dmar_disable_qi(iommu
);
608 * check for the Interrupt-remapping support
610 for_each_iommu(iommu
, drhd
) {
611 if (!ecap_ir_support(iommu
->ecap
))
614 if (eim
&& !ecap_eim_support(iommu
->ecap
)) {
615 printk(KERN_INFO
"DRHD %Lx: EIM not supported by DRHD, "
616 " ecap %Lx\n", drhd
->reg_base_addr
, iommu
->ecap
);
622 * Enable queued invalidation for all the DRHD's.
624 for_each_iommu(iommu
, drhd
) {
625 int ret
= dmar_enable_qi(iommu
);
628 printk(KERN_ERR
"DRHD %Lx: failed to enable queued, "
629 " invalidation, ecap %Lx, ret %d\n",
630 drhd
->reg_base_addr
, iommu
->ecap
, ret
);
636 * Setup Interrupt-remapping for all the DRHD's now.
638 for_each_iommu(iommu
, drhd
) {
639 if (!ecap_ir_support(iommu
->ecap
))
642 if (intel_setup_irq_remapping(iommu
, eim
))
651 irq_remapping_enabled
= 1;
654 * VT-d has a different layout for IO-APIC entries when
655 * interrupt remapping is enabled. So it needs a special routine
656 * to print IO-APIC entries for debugging purposes too.
658 x86_io_apic_ops
.print_entries
= intel_ir_io_apic_print_entries
;
660 pr_info("Enabled IRQ remapping in %s mode\n", eim
? "x2apic" : "xapic");
662 return eim
? IRQ_REMAP_X2APIC_MODE
: IRQ_REMAP_XAPIC_MODE
;
666 * handle error condition gracefully here!
670 pr_warn("Failed to enable irq remapping. You are vulnerable to irq-injection attacks.\n");
675 static void ir_parse_one_hpet_scope(struct acpi_dmar_device_scope
*scope
,
676 struct intel_iommu
*iommu
)
678 struct acpi_dmar_pci_path
*path
;
683 path
= (struct acpi_dmar_pci_path
*)(scope
+ 1);
684 count
= (scope
->length
- sizeof(struct acpi_dmar_device_scope
))
685 / sizeof(struct acpi_dmar_pci_path
);
687 while (--count
> 0) {
689 * Access PCI directly due to the PCI
690 * subsystem isn't initialized yet.
692 bus
= read_pci_config_byte(bus
, path
->device
, path
->function
,
696 ir_hpet
[ir_hpet_num
].bus
= bus
;
697 ir_hpet
[ir_hpet_num
].devfn
= PCI_DEVFN(path
->device
, path
->function
);
698 ir_hpet
[ir_hpet_num
].iommu
= iommu
;
699 ir_hpet
[ir_hpet_num
].id
= scope
->enumeration_id
;
703 static void ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope
*scope
,
704 struct intel_iommu
*iommu
)
706 struct acpi_dmar_pci_path
*path
;
711 path
= (struct acpi_dmar_pci_path
*)(scope
+ 1);
712 count
= (scope
->length
- sizeof(struct acpi_dmar_device_scope
))
713 / sizeof(struct acpi_dmar_pci_path
);
715 while (--count
> 0) {
717 * Access PCI directly due to the PCI
718 * subsystem isn't initialized yet.
720 bus
= read_pci_config_byte(bus
, path
->device
, path
->function
,
725 ir_ioapic
[ir_ioapic_num
].bus
= bus
;
726 ir_ioapic
[ir_ioapic_num
].devfn
= PCI_DEVFN(path
->device
, path
->function
);
727 ir_ioapic
[ir_ioapic_num
].iommu
= iommu
;
728 ir_ioapic
[ir_ioapic_num
].id
= scope
->enumeration_id
;
732 static int ir_parse_ioapic_hpet_scope(struct acpi_dmar_header
*header
,
733 struct intel_iommu
*iommu
)
735 struct acpi_dmar_hardware_unit
*drhd
;
736 struct acpi_dmar_device_scope
*scope
;
739 drhd
= (struct acpi_dmar_hardware_unit
*)header
;
741 start
= (void *)(drhd
+ 1);
742 end
= ((void *)drhd
) + header
->length
;
744 while (start
< end
) {
746 if (scope
->entry_type
== ACPI_DMAR_SCOPE_TYPE_IOAPIC
) {
747 if (ir_ioapic_num
== MAX_IO_APICS
) {
748 printk(KERN_WARNING
"Exceeded Max IO APICS\n");
752 printk(KERN_INFO
"IOAPIC id %d under DRHD base "
753 " 0x%Lx IOMMU %d\n", scope
->enumeration_id
,
754 drhd
->address
, iommu
->seq_id
);
756 ir_parse_one_ioapic_scope(scope
, iommu
);
757 } else if (scope
->entry_type
== ACPI_DMAR_SCOPE_TYPE_HPET
) {
758 if (ir_hpet_num
== MAX_HPET_TBS
) {
759 printk(KERN_WARNING
"Exceeded Max HPET blocks\n");
763 printk(KERN_INFO
"HPET id %d under DRHD base"
764 " 0x%Lx\n", scope
->enumeration_id
,
767 ir_parse_one_hpet_scope(scope
, iommu
);
769 start
+= scope
->length
;
776 * Finds the assocaition between IOAPIC's and its Interrupt-remapping
779 static int __init
parse_ioapics_under_ir(void)
781 struct dmar_drhd_unit
*drhd
;
782 struct intel_iommu
*iommu
;
783 int ir_supported
= 0;
786 for_each_iommu(iommu
, drhd
)
787 if (ecap_ir_support(iommu
->ecap
)) {
788 if (ir_parse_ioapic_hpet_scope(drhd
->hdr
, iommu
))
797 for (ioapic_idx
= 0; ioapic_idx
< nr_ioapics
; ioapic_idx
++) {
798 int ioapic_id
= mpc_ioapic_id(ioapic_idx
);
799 if (!map_ioapic_to_ir(ioapic_id
)) {
800 pr_err(FW_BUG
"ioapic %d has no mapping iommu, "
801 "interrupt remapping will be disabled\n",
810 static int __init
ir_dev_scope_init(void)
814 if (!irq_remapping_enabled
)
817 down_write(&dmar_global_lock
);
818 ret
= dmar_dev_scope_init();
819 up_write(&dmar_global_lock
);
823 rootfs_initcall(ir_dev_scope_init
);
825 static void disable_irq_remapping(void)
827 struct dmar_drhd_unit
*drhd
;
828 struct intel_iommu
*iommu
= NULL
;
831 * Disable Interrupt-remapping for all the DRHD's now.
833 for_each_iommu(iommu
, drhd
) {
834 if (!ecap_ir_support(iommu
->ecap
))
837 iommu_disable_irq_remapping(iommu
);
841 static int reenable_irq_remapping(int eim
)
843 struct dmar_drhd_unit
*drhd
;
845 struct intel_iommu
*iommu
= NULL
;
847 for_each_iommu(iommu
, drhd
)
849 dmar_reenable_qi(iommu
);
852 * Setup Interrupt-remapping for all the DRHD's now.
854 for_each_iommu(iommu
, drhd
) {
855 if (!ecap_ir_support(iommu
->ecap
))
858 /* Set up interrupt remapping for iommu.*/
859 iommu_set_irq_remapping(iommu
, eim
);
870 * handle error condition gracefully here!
875 static void prepare_irte(struct irte
*irte
, int vector
,
878 memset(irte
, 0, sizeof(*irte
));
881 irte
->dst_mode
= apic
->irq_dest_mode
;
883 * Trigger mode in the IRTE will always be edge, and for IO-APIC, the
884 * actual level or edge trigger will be setup in the IO-APIC
885 * RTE. This will help simplify level triggered irq migration.
886 * For more details, see the comments (in io_apic.c) explainig IO-APIC
887 * irq migration in the presence of interrupt-remapping.
889 irte
->trigger_mode
= 0;
890 irte
->dlvry_mode
= apic
->irq_delivery_mode
;
891 irte
->vector
= vector
;
892 irte
->dest_id
= IRTE_DEST(dest
);
893 irte
->redir_hint
= 1;
896 static int intel_setup_ioapic_entry(int irq
,
897 struct IO_APIC_route_entry
*route_entry
,
898 unsigned int destination
, int vector
,
899 struct io_apic_irq_attr
*attr
)
901 int ioapic_id
= mpc_ioapic_id(attr
->ioapic
);
902 struct intel_iommu
*iommu
;
903 struct IR_IO_APIC_route_entry
*entry
;
907 down_read(&dmar_global_lock
);
908 iommu
= map_ioapic_to_ir(ioapic_id
);
910 pr_warn("No mapping iommu for ioapic %d\n", ioapic_id
);
913 index
= alloc_irte(iommu
, irq
, 1);
915 pr_warn("Failed to allocate IRTE for ioapic %d\n",
920 up_read(&dmar_global_lock
);
924 prepare_irte(&irte
, vector
, destination
);
926 /* Set source-id of interrupt request */
927 set_ioapic_sid(&irte
, ioapic_id
);
929 modify_irte(irq
, &irte
);
931 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"IOAPIC[%d]: "
932 "Set IRTE entry (P:%d FPD:%d Dst_Mode:%d "
933 "Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X "
934 "Avail:%X Vector:%02X Dest:%08X "
935 "SID:%04X SQ:%X SVT:%X)\n",
936 attr
->ioapic
, irte
.present
, irte
.fpd
, irte
.dst_mode
,
937 irte
.redir_hint
, irte
.trigger_mode
, irte
.dlvry_mode
,
938 irte
.avail
, irte
.vector
, irte
.dest_id
,
939 irte
.sid
, irte
.sq
, irte
.svt
);
941 entry
= (struct IR_IO_APIC_route_entry
*)route_entry
;
942 memset(entry
, 0, sizeof(*entry
));
944 entry
->index2
= (index
>> 15) & 0x1;
947 entry
->index
= (index
& 0x7fff);
949 * IO-APIC RTE will be configured with virtual vector.
950 * irq handler will do the explicit EOI to the io-apic.
952 entry
->vector
= attr
->ioapic_pin
;
953 entry
->mask
= 0; /* enable IRQ */
954 entry
->trigger
= attr
->trigger
;
955 entry
->polarity
= attr
->polarity
;
957 /* Mask level triggered irqs.
958 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
967 * Migrate the IO-APIC irq in the presence of intr-remapping.
969 * For both level and edge triggered, irq migration is a simple atomic
970 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
972 * For level triggered, we eliminate the io-apic RTE modification (with the
973 * updated vector information), by using a virtual vector (io-apic pin number).
974 * Real vector that is used for interrupting cpu will be coming from
975 * the interrupt-remapping table entry.
977 * As the migration is a simple atomic update of IRTE, the same mechanism
978 * is used to migrate MSI irq's in the presence of interrupt-remapping.
981 intel_ioapic_set_affinity(struct irq_data
*data
, const struct cpumask
*mask
,
984 struct irq_cfg
*cfg
= data
->chip_data
;
985 unsigned int dest
, irq
= data
->irq
;
989 if (!config_enabled(CONFIG_SMP
))
992 if (!cpumask_intersects(mask
, cpu_online_mask
))
995 if (get_irte(irq
, &irte
))
998 err
= assign_irq_vector(irq
, cfg
, mask
);
1002 err
= apic
->cpu_mask_to_apicid_and(cfg
->domain
, mask
, &dest
);
1004 if (assign_irq_vector(irq
, cfg
, data
->affinity
))
1005 pr_err("Failed to recover vector for irq %d\n", irq
);
1009 irte
.vector
= cfg
->vector
;
1010 irte
.dest_id
= IRTE_DEST(dest
);
1013 * Atomically updates the IRTE with the new destination, vector
1014 * and flushes the interrupt entry cache.
1016 modify_irte(irq
, &irte
);
1019 * After this point, all the interrupts will start arriving
1020 * at the new destination. So, time to cleanup the previous
1021 * vector allocation.
1023 if (cfg
->move_in_progress
)
1024 send_cleanup_vector(cfg
);
1026 cpumask_copy(data
->affinity
, mask
);
1030 static void intel_compose_msi_msg(struct pci_dev
*pdev
,
1031 unsigned int irq
, unsigned int dest
,
1032 struct msi_msg
*msg
, u8 hpet_id
)
1034 struct irq_cfg
*cfg
;
1039 cfg
= irq_get_chip_data(irq
);
1041 ir_index
= map_irq_to_irte_handle(irq
, &sub_handle
);
1042 BUG_ON(ir_index
== -1);
1044 prepare_irte(&irte
, cfg
->vector
, dest
);
1046 /* Set source-id of interrupt request */
1048 set_msi_sid(&irte
, pdev
);
1050 set_hpet_sid(&irte
, hpet_id
);
1052 modify_irte(irq
, &irte
);
1054 msg
->address_hi
= MSI_ADDR_BASE_HI
;
1055 msg
->data
= sub_handle
;
1056 msg
->address_lo
= MSI_ADDR_BASE_LO
| MSI_ADDR_IR_EXT_INT
|
1058 MSI_ADDR_IR_INDEX1(ir_index
) |
1059 MSI_ADDR_IR_INDEX2(ir_index
);
1063 * Map the PCI dev to the corresponding remapping hardware unit
1064 * and allocate 'nvec' consecutive interrupt-remapping table entries
1067 static int intel_msi_alloc_irq(struct pci_dev
*dev
, int irq
, int nvec
)
1069 struct intel_iommu
*iommu
;
1072 down_read(&dmar_global_lock
);
1073 iommu
= map_dev_to_ir(dev
);
1076 "Unable to map PCI %s to iommu\n", pci_name(dev
));
1079 index
= alloc_irte(iommu
, irq
, nvec
);
1082 "Unable to allocate %d IRTE for PCI %s\n",
1083 nvec
, pci_name(dev
));
1087 up_read(&dmar_global_lock
);
1092 static int intel_msi_setup_irq(struct pci_dev
*pdev
, unsigned int irq
,
1093 int index
, int sub_handle
)
1095 struct intel_iommu
*iommu
;
1098 down_read(&dmar_global_lock
);
1099 iommu
= map_dev_to_ir(pdev
);
1102 * setup the mapping between the irq and the IRTE
1103 * base index, the sub_handle pointing to the
1104 * appropriate interrupt remap table entry.
1106 set_irte_irq(irq
, iommu
, index
, sub_handle
);
1109 up_read(&dmar_global_lock
);
1114 static int intel_setup_hpet_msi(unsigned int irq
, unsigned int id
)
1117 struct intel_iommu
*iommu
;
1120 down_read(&dmar_global_lock
);
1121 iommu
= map_hpet_to_ir(id
);
1123 index
= alloc_irte(iommu
, irq
, 1);
1127 up_read(&dmar_global_lock
);
1132 struct irq_remap_ops intel_irq_remap_ops
= {
1133 .supported
= intel_irq_remapping_supported
,
1134 .prepare
= dmar_table_init
,
1135 .enable
= intel_enable_irq_remapping
,
1136 .disable
= disable_irq_remapping
,
1137 .reenable
= reenable_irq_remapping
,
1138 .enable_faulting
= enable_drhd_fault_handling
,
1139 .setup_ioapic_entry
= intel_setup_ioapic_entry
,
1140 .set_affinity
= intel_ioapic_set_affinity
,
1141 .free_irq
= free_irte
,
1142 .compose_msi_msg
= intel_compose_msi_msg
,
1143 .msi_alloc_irq
= intel_msi_alloc_irq
,
1144 .msi_setup_irq
= intel_msi_setup_irq
,
1145 .setup_hpet_msi
= intel_setup_hpet_msi
,