?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
hyperv: Remove recv_pkt_list and lock
[linux/fpc-iii.git] / drivers / irqchip / irq-renesas-intc-irqpin.c
blob3ee78f02e5d7d940d531aa6ab03c8dc681c9cb3c
1 /*
2 * Renesas INTC External IRQ Pin Driver
3 *
4 * Copyright (C) 2013 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/init.h>
21 #include <linux/of.h>
22 #include <linux/platform_device.h>
23 #include <linux/spinlock.h>
24 #include <linux/interrupt.h>
25 #include <linux/ioport.h>
26 #include <linux/io.h>
27 #include <linux/irq.h>
28 #include <linux/irqdomain.h>
29 #include <linux/err.h>
30 #include <linux/slab.h>
31 #include <linux/module.h>
32 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
33
34 #define INTC_IRQPIN_MAX 8 /* maximum 8 interrupts per driver instance */
35
36 #define INTC_IRQPIN_REG_SENSE 0 /* ICRn */
37 #define INTC_IRQPIN_REG_PRIO 1 /* INTPRInn */
38 #define INTC_IRQPIN_REG_SOURCE 2 /* INTREQnn */
39 #define INTC_IRQPIN_REG_MASK 3 /* INTMSKnn */
40 #define INTC_IRQPIN_REG_CLEAR 4 /* INTMSKCLRnn */
41 #define INTC_IRQPIN_REG_NR 5
42
43 /* INTC external IRQ PIN hardware register access:
44 *
45 * SENSE is read-write 32-bit with 2-bits or 4-bits per IRQ (*)
46 * PRIO is read-write 32-bit with 4-bits per IRQ (**)
47 * SOURCE is read-only 32-bit or 8-bit with 1-bit per IRQ (***)
48 * MASK is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
49 * CLEAR is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
50 *
51 * (*) May be accessed by more than one driver instance - lock needed
52 * (**) Read-modify-write access by one driver instance - lock needed
53 * (***) Accessed by one driver instance only - no locking needed
54 */
55
56 struct intc_irqpin_iomem {
57 void __iomem *iomem;
58 unsigned long (*read)(void __iomem *iomem);
59 void (*write)(void __iomem *iomem, unsigned long data);
60 int width;
61 };
62
63 struct intc_irqpin_irq {
64 int hw_irq;
65 int requested_irq;
66 int domain_irq;
67 struct intc_irqpin_priv *p;
68 };
69
70 struct intc_irqpin_priv {
71 struct intc_irqpin_iomem iomem[INTC_IRQPIN_REG_NR];
72 struct intc_irqpin_irq irq[INTC_IRQPIN_MAX];
73 struct renesas_intc_irqpin_config config;
74 unsigned int number_of_irqs;
75 struct platform_device *pdev;
76 struct irq_chip irq_chip;
77 struct irq_domain *irq_domain;
78 bool shared_irqs;
79 u8 shared_irq_mask;
80 };
81
82 static unsigned long intc_irqpin_read32(void __iomem *iomem)
83 {
84 return ioread32(iomem);
85 }
86
87 static unsigned long intc_irqpin_read8(void __iomem *iomem)
88 {
89 return ioread8(iomem);
90 }
91
92 static void intc_irqpin_write32(void __iomem *iomem, unsigned long data)
93 {
94 iowrite32(data, iomem);
95 }
96
97 static void intc_irqpin_write8(void __iomem *iomem, unsigned long data)
98 {
99 iowrite8(data, iomem);
100 }
101
102 static inline unsigned long intc_irqpin_read(struct intc_irqpin_priv *p,
103 int reg)
104 {
105 struct intc_irqpin_iomem *i = &p->iomem[reg];
106
107 return i->read(i->iomem);
108 }
109
110 static inline void intc_irqpin_write(struct intc_irqpin_priv *p,
111 int reg, unsigned long data)
112 {
113 struct intc_irqpin_iomem *i = &p->iomem[reg];
114
115 i->write(i->iomem, data);
116 }
117
118 static inline unsigned long intc_irqpin_hwirq_mask(struct intc_irqpin_priv *p,
119 int reg, int hw_irq)
120 {
121 return BIT((p->iomem[reg].width - 1) - hw_irq);
122 }
123
124 static inline void intc_irqpin_irq_write_hwirq(struct intc_irqpin_priv *p,
125 int reg, int hw_irq)
126 {
127 intc_irqpin_write(p, reg, intc_irqpin_hwirq_mask(p, reg, hw_irq));
128 }
129
130 static DEFINE_RAW_SPINLOCK(intc_irqpin_lock); /* only used by slow path */
131
132 static void intc_irqpin_read_modify_write(struct intc_irqpin_priv *p,
133 int reg, int shift,
134 int width, int value)
135 {
136 unsigned long flags;
137 unsigned long tmp;
138
139 raw_spin_lock_irqsave(&intc_irqpin_lock, flags);
140
141 tmp = intc_irqpin_read(p, reg);
142 tmp &= ~(((1 << width) - 1) << shift);
143 tmp |= value << shift;
144 intc_irqpin_write(p, reg, tmp);
145
146 raw_spin_unlock_irqrestore(&intc_irqpin_lock, flags);
147 }
148
149 static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p,
150 int irq, int do_mask)
151 {
152 /* The PRIO register is assumed to be 32-bit with fixed 4-bit fields. */
153 int bitfield_width = 4;
154 int shift = 32 - (irq + 1) * bitfield_width;
155
156 intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_PRIO,
157 shift, bitfield_width,
158 do_mask ? 0 : (1 << bitfield_width) - 1);
159 }
160
161 static int intc_irqpin_set_sense(struct intc_irqpin_priv *p, int irq, int value)
162 {
163 /* The SENSE register is assumed to be 32-bit. */
164 int bitfield_width = p->config.sense_bitfield_width;
165 int shift = 32 - (irq + 1) * bitfield_width;
166
167 dev_dbg(&p->pdev->dev, "sense irq = %d, mode = %d\n", irq, value);
168
169 if (value >= (1 << bitfield_width))
170 return -EINVAL;
171
172 intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_SENSE, shift,
173 bitfield_width, value);
174 return 0;
175 }
176
177 static void intc_irqpin_dbg(struct intc_irqpin_irq *i, char *str)
178 {
179 dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n",
180 str, i->requested_irq, i->hw_irq, i->domain_irq);
181 }
182
183 static void intc_irqpin_irq_enable(struct irq_data *d)
184 {
185 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
186 int hw_irq = irqd_to_hwirq(d);
187
188 intc_irqpin_dbg(&p->irq[hw_irq], "enable");
189 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);
190 }
191
192 static void intc_irqpin_irq_disable(struct irq_data *d)
193 {
194 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
195 int hw_irq = irqd_to_hwirq(d);
196
197 intc_irqpin_dbg(&p->irq[hw_irq], "disable");
198 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);
199 }
200
201 static void intc_irqpin_shared_irq_enable(struct irq_data *d)
202 {
203 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
204 int hw_irq = irqd_to_hwirq(d);
205
206 intc_irqpin_dbg(&p->irq[hw_irq], "shared enable");
207 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);
208
209 p->shared_irq_mask &= ~BIT(hw_irq);
210 }
211
212 static void intc_irqpin_shared_irq_disable(struct irq_data *d)
213 {
214 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
215 int hw_irq = irqd_to_hwirq(d);
216
217 intc_irqpin_dbg(&p->irq[hw_irq], "shared disable");
218 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);
219
220 p->shared_irq_mask |= BIT(hw_irq);
221 }
222
223 static void intc_irqpin_irq_enable_force(struct irq_data *d)
224 {
225 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
226 int irq = p->irq[irqd_to_hwirq(d)].requested_irq;
227
228 intc_irqpin_irq_enable(d);
229
230 /* enable interrupt through parent interrupt controller,
231 * assumes non-shared interrupt with 1:1 mapping
232 * needed for busted IRQs on some SoCs like sh73a0
233 */
234 irq_get_chip(irq)->irq_unmask(irq_get_irq_data(irq));
235 }
236
237 static void intc_irqpin_irq_disable_force(struct irq_data *d)
238 {
239 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
240 int irq = p->irq[irqd_to_hwirq(d)].requested_irq;
241
242 /* disable interrupt through parent interrupt controller,
243 * assumes non-shared interrupt with 1:1 mapping
244 * needed for busted IRQs on some SoCs like sh73a0
245 */
246 irq_get_chip(irq)->irq_mask(irq_get_irq_data(irq));
247 intc_irqpin_irq_disable(d);
248 }
249
250 #define INTC_IRQ_SENSE_VALID 0x10
251 #define INTC_IRQ_SENSE(x) (x + INTC_IRQ_SENSE_VALID)
252
253 static unsigned char intc_irqpin_sense[IRQ_TYPE_SENSE_MASK + 1] = {
254 [IRQ_TYPE_EDGE_FALLING] = INTC_IRQ_SENSE(0x00),
255 [IRQ_TYPE_EDGE_RISING] = INTC_IRQ_SENSE(0x01),
256 [IRQ_TYPE_LEVEL_LOW] = INTC_IRQ_SENSE(0x02),
257 [IRQ_TYPE_LEVEL_HIGH] = INTC_IRQ_SENSE(0x03),
258 [IRQ_TYPE_EDGE_BOTH] = INTC_IRQ_SENSE(0x04),
259 };
260
261 static int intc_irqpin_irq_set_type(struct irq_data *d, unsigned int type)
262 {
263 unsigned char value = intc_irqpin_sense[type & IRQ_TYPE_SENSE_MASK];
264 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
265
266 if (!(value & INTC_IRQ_SENSE_VALID))
267 return -EINVAL;
268
269 return intc_irqpin_set_sense(p, irqd_to_hwirq(d),
270 value ^ INTC_IRQ_SENSE_VALID);
271 }
272
273 static irqreturn_t intc_irqpin_irq_handler(int irq, void *dev_id)
274 {
275 struct intc_irqpin_irq *i = dev_id;
276 struct intc_irqpin_priv *p = i->p;
277 unsigned long bit;
278
279 intc_irqpin_dbg(i, "demux1");
280 bit = intc_irqpin_hwirq_mask(p, INTC_IRQPIN_REG_SOURCE, i->hw_irq);
281
282 if (intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE) & bit) {
283 intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, ~bit);
284 intc_irqpin_dbg(i, "demux2");
285 generic_handle_irq(i->domain_irq);
286 return IRQ_HANDLED;
287 }
288 return IRQ_NONE;
289 }
290
291 static irqreturn_t intc_irqpin_shared_irq_handler(int irq, void *dev_id)
292 {
293 struct intc_irqpin_priv *p = dev_id;
294 unsigned int reg_source = intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE);
295 irqreturn_t status = IRQ_NONE;
296 int k;
297
298 for (k = 0; k < 8; k++) {
299 if (reg_source & BIT(7 - k)) {
300 if (BIT(k) & p->shared_irq_mask)
301 continue;
302
303 status |= intc_irqpin_irq_handler(irq, &p->irq[k]);
304 }
305 }
306
307 return status;
308 }
309
310 static int intc_irqpin_irq_domain_map(struct irq_domain *h, unsigned int virq,
311 irq_hw_number_t hw)
312 {
313 struct intc_irqpin_priv *p = h->host_data;
314
315 p->irq[hw].domain_irq = virq;
316 p->irq[hw].hw_irq = hw;
317
318 intc_irqpin_dbg(&p->irq[hw], "map");
319 irq_set_chip_data(virq, h->host_data);
320 irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
321 set_irq_flags(virq, IRQF_VALID); /* kill me now */
322 return 0;
323 }
324
325 static struct irq_domain_ops intc_irqpin_irq_domain_ops = {
326 .map = intc_irqpin_irq_domain_map,
327 .xlate = irq_domain_xlate_twocell,
328 };
329
330 static int intc_irqpin_probe(struct platform_device *pdev)
331 {
332 struct renesas_intc_irqpin_config *pdata = pdev->dev.platform_data;
333 struct intc_irqpin_priv *p;
334 struct intc_irqpin_iomem *i;
335 struct resource *io[INTC_IRQPIN_REG_NR];
336 struct resource *irq;
337 struct irq_chip *irq_chip;
338 void (*enable_fn)(struct irq_data *d);
339 void (*disable_fn)(struct irq_data *d);
340 const char *name = dev_name(&pdev->dev);
341 int ref_irq;
342 int ret;
343 int k;
344
345 p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
346 if (!p) {
347 dev_err(&pdev->dev, "failed to allocate driver data\n");
348 ret = -ENOMEM;
349 goto err0;
350 }
351
352 /* deal with driver instance configuration */
353 if (pdata) {
354 memcpy(&p->config, pdata, sizeof(*pdata));
355 } else {
356 of_property_read_u32(pdev->dev.of_node, "sense-bitfield-width",
357 &p->config.sense_bitfield_width);
358 p->config.control_parent = of_property_read_bool(pdev->dev.of_node,
359 "control-parent");
360 }
361 if (!p->config.sense_bitfield_width)
362 p->config.sense_bitfield_width = 4; /* default to 4 bits */
363
364 p->pdev = pdev;
365 platform_set_drvdata(pdev, p);
366
367 /* get hold of manadatory IOMEM */
368 for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
369 io[k] = platform_get_resource(pdev, IORESOURCE_MEM, k);
370 if (!io[k]) {
371 dev_err(&pdev->dev, "not enough IOMEM resources\n");
372 ret = -EINVAL;
373 goto err0;
374 }
375 }
376
377 /* allow any number of IRQs between 1 and INTC_IRQPIN_MAX */
378 for (k = 0; k < INTC_IRQPIN_MAX; k++) {
379 irq = platform_get_resource(pdev, IORESOURCE_IRQ, k);
380 if (!irq)
381 break;
382
383 p->irq[k].p = p;
384 p->irq[k].requested_irq = irq->start;
385 }
386
387 p->number_of_irqs = k;
388 if (p->number_of_irqs < 1) {
389 dev_err(&pdev->dev, "not enough IRQ resources\n");
390 ret = -EINVAL;
391 goto err0;
392 }
393
394 /* ioremap IOMEM and setup read/write callbacks */
395 for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
396 i = &p->iomem[k];
397
398 switch (resource_size(io[k])) {
399 case 1:
400 i->width = 8;
401 i->read = intc_irqpin_read8;
402 i->write = intc_irqpin_write8;
403 break;
404 case 4:
405 i->width = 32;
406 i->read = intc_irqpin_read32;
407 i->write = intc_irqpin_write32;
408 break;
409 default:
410 dev_err(&pdev->dev, "IOMEM size mismatch\n");
411 ret = -EINVAL;
412 goto err0;
413 }
414
415 i->iomem = devm_ioremap_nocache(&pdev->dev, io[k]->start,
416 resource_size(io[k]));
417 if (!i->iomem) {
418 dev_err(&pdev->dev, "failed to remap IOMEM\n");
419 ret = -ENXIO;
420 goto err0;
421 }
422 }
423
424 /* mask all interrupts using priority */
425 for (k = 0; k < p->number_of_irqs; k++)
426 intc_irqpin_mask_unmask_prio(p, k, 1);
427
428 /* clear all pending interrupts */
429 intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, 0x0);
430
431 /* scan for shared interrupt lines */
432 ref_irq = p->irq[0].requested_irq;
433 p->shared_irqs = true;
434 for (k = 1; k < p->number_of_irqs; k++) {
435 if (ref_irq != p->irq[k].requested_irq) {
436 p->shared_irqs = false;
437 break;
438 }
439 }
440
441 /* use more severe masking method if requested */
442 if (p->config.control_parent) {
443 enable_fn = intc_irqpin_irq_enable_force;
444 disable_fn = intc_irqpin_irq_disable_force;
445 } else if (!p->shared_irqs) {
446 enable_fn = intc_irqpin_irq_enable;
447 disable_fn = intc_irqpin_irq_disable;
448 } else {
449 enable_fn = intc_irqpin_shared_irq_enable;
450 disable_fn = intc_irqpin_shared_irq_disable;
451 }
452
453 irq_chip = &p->irq_chip;
454 irq_chip->name = name;
455 irq_chip->irq_mask = disable_fn;
456 irq_chip->irq_unmask = enable_fn;
457 irq_chip->irq_enable = enable_fn;
458 irq_chip->irq_disable = disable_fn;
459 irq_chip->irq_set_type = intc_irqpin_irq_set_type;
460 irq_chip->flags = IRQCHIP_SKIP_SET_WAKE;
461
462 p->irq_domain = irq_domain_add_simple(pdev->dev.of_node,
463 p->number_of_irqs,
464 p->config.irq_base,
465 &intc_irqpin_irq_domain_ops, p);
466 if (!p->irq_domain) {
467 ret = -ENXIO;
468 dev_err(&pdev->dev, "cannot initialize irq domain\n");
469 goto err0;
470 }
471
472 if (p->shared_irqs) {
473 /* request one shared interrupt */
474 if (devm_request_irq(&pdev->dev, p->irq[0].requested_irq,
475 intc_irqpin_shared_irq_handler,
476 IRQF_SHARED, name, p)) {
477 dev_err(&pdev->dev, "failed to request low IRQ\n");
478 ret = -ENOENT;
479 goto err1;
480 }
481 } else {
482 /* request interrupts one by one */
483 for (k = 0; k < p->number_of_irqs; k++) {
484 if (devm_request_irq(&pdev->dev,
485 p->irq[k].requested_irq,
486 intc_irqpin_irq_handler,
487 0, name, &p->irq[k])) {
488 dev_err(&pdev->dev,
489 "failed to request low IRQ\n");
490 ret = -ENOENT;
491 goto err1;
492 }
493 }
494 }
495
496 /* unmask all interrupts on prio level */
497 for (k = 0; k < p->number_of_irqs; k++)
498 intc_irqpin_mask_unmask_prio(p, k, 0);
499
500 dev_info(&pdev->dev, "driving %d irqs\n", p->number_of_irqs);
501
502 /* warn in case of mismatch if irq base is specified */
503 if (p->config.irq_base) {
504 if (p->config.irq_base != p->irq[0].domain_irq)
505 dev_warn(&pdev->dev, "irq base mismatch (%d/%d)\n",
506 p->config.irq_base, p->irq[0].domain_irq);
507 }
508
509 return 0;
510
511 err1:
512 irq_domain_remove(p->irq_domain);
513 err0:
514 return ret;
515 }
516
517 static int intc_irqpin_remove(struct platform_device *pdev)
518 {
519 struct intc_irqpin_priv *p = platform_get_drvdata(pdev);
520
521 irq_domain_remove(p->irq_domain);
522
523 return 0;
524 }
525
526 static const struct of_device_id intc_irqpin_dt_ids[] = {
527 { .compatible = "renesas,intc-irqpin", },
528 {},
529 };
530 MODULE_DEVICE_TABLE(of, intc_irqpin_dt_ids);
531
532 static struct platform_driver intc_irqpin_device_driver = {
533 .probe = intc_irqpin_probe,
534 .remove = intc_irqpin_remove,
535 .driver = {
536 .name = "renesas_intc_irqpin",
537 .of_match_table = intc_irqpin_dt_ids,
538 .owner = THIS_MODULE,
539 }
540 };
541
542 static int __init intc_irqpin_init(void)
543 {
544 return platform_driver_register(&intc_irqpin_device_driver);
545 }
546 postcore_initcall(intc_irqpin_init);
547
548 static void __exit intc_irqpin_exit(void)
549 {
550 platform_driver_unregister(&intc_irqpin_device_driver);
551 }
552 module_exit(intc_irqpin_exit);
553
554 MODULE_AUTHOR("Magnus Damm");
555 MODULE_DESCRIPTION("Renesas INTC External IRQ Pin Driver");
556 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support