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hyperv: Remove recv_pkt_list and lock
[linux/fpc-iii.git] / drivers / mtd / nand / omap2.c
blob1ff49b80bdaf7e3a454c02574165d1a59a04a72b
1 /*
2 * Copyright © 2004 Texas Instruments, Jian Zhang <jzhang@ti.com>
3 * Copyright © 2004 Micron Technology Inc.
4 * Copyright © 2004 David Brownell
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #include <linux/platform_device.h>
12 #include <linux/dmaengine.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/delay.h>
15 #include <linux/module.h>
16 #include <linux/interrupt.h>
17 #include <linux/jiffies.h>
18 #include <linux/sched.h>
19 #include <linux/mtd/mtd.h>
20 #include <linux/mtd/nand.h>
21 #include <linux/mtd/partitions.h>
22 #include <linux/omap-dma.h>
23 #include <linux/io.h>
24 #include <linux/slab.h>
25 #include <linux/of.h>
26 #include <linux/of_device.h>
27
28 #include <linux/mtd/nand_bch.h>
29 #include <linux/platform_data/elm.h>
30
31 #include <linux/platform_data/mtd-nand-omap2.h>
32
33 #define DRIVER_NAME "omap2-nand"
34 #define OMAP_NAND_TIMEOUT_MS 5000
35
36 #define NAND_Ecc_P1e (1 << 0)
37 #define NAND_Ecc_P2e (1 << 1)
38 #define NAND_Ecc_P4e (1 << 2)
39 #define NAND_Ecc_P8e (1 << 3)
40 #define NAND_Ecc_P16e (1 << 4)
41 #define NAND_Ecc_P32e (1 << 5)
42 #define NAND_Ecc_P64e (1 << 6)
43 #define NAND_Ecc_P128e (1 << 7)
44 #define NAND_Ecc_P256e (1 << 8)
45 #define NAND_Ecc_P512e (1 << 9)
46 #define NAND_Ecc_P1024e (1 << 10)
47 #define NAND_Ecc_P2048e (1 << 11)
48
49 #define NAND_Ecc_P1o (1 << 16)
50 #define NAND_Ecc_P2o (1 << 17)
51 #define NAND_Ecc_P4o (1 << 18)
52 #define NAND_Ecc_P8o (1 << 19)
53 #define NAND_Ecc_P16o (1 << 20)
54 #define NAND_Ecc_P32o (1 << 21)
55 #define NAND_Ecc_P64o (1 << 22)
56 #define NAND_Ecc_P128o (1 << 23)
57 #define NAND_Ecc_P256o (1 << 24)
58 #define NAND_Ecc_P512o (1 << 25)
59 #define NAND_Ecc_P1024o (1 << 26)
60 #define NAND_Ecc_P2048o (1 << 27)
61
62 #define TF(value) (value ? 1 : 0)
63
64 #define P2048e(a) (TF(a & NAND_Ecc_P2048e) << 0)
65 #define P2048o(a) (TF(a & NAND_Ecc_P2048o) << 1)
66 #define P1e(a) (TF(a & NAND_Ecc_P1e) << 2)
67 #define P1o(a) (TF(a & NAND_Ecc_P1o) << 3)
68 #define P2e(a) (TF(a & NAND_Ecc_P2e) << 4)
69 #define P2o(a) (TF(a & NAND_Ecc_P2o) << 5)
70 #define P4e(a) (TF(a & NAND_Ecc_P4e) << 6)
71 #define P4o(a) (TF(a & NAND_Ecc_P4o) << 7)
72
73 #define P8e(a) (TF(a & NAND_Ecc_P8e) << 0)
74 #define P8o(a) (TF(a & NAND_Ecc_P8o) << 1)
75 #define P16e(a) (TF(a & NAND_Ecc_P16e) << 2)
76 #define P16o(a) (TF(a & NAND_Ecc_P16o) << 3)
77 #define P32e(a) (TF(a & NAND_Ecc_P32e) << 4)
78 #define P32o(a) (TF(a & NAND_Ecc_P32o) << 5)
79 #define P64e(a) (TF(a & NAND_Ecc_P64e) << 6)
80 #define P64o(a) (TF(a & NAND_Ecc_P64o) << 7)
81
82 #define P128e(a) (TF(a & NAND_Ecc_P128e) << 0)
83 #define P128o(a) (TF(a & NAND_Ecc_P128o) << 1)
84 #define P256e(a) (TF(a & NAND_Ecc_P256e) << 2)
85 #define P256o(a) (TF(a & NAND_Ecc_P256o) << 3)
86 #define P512e(a) (TF(a & NAND_Ecc_P512e) << 4)
87 #define P512o(a) (TF(a & NAND_Ecc_P512o) << 5)
88 #define P1024e(a) (TF(a & NAND_Ecc_P1024e) << 6)
89 #define P1024o(a) (TF(a & NAND_Ecc_P1024o) << 7)
90
91 #define P8e_s(a) (TF(a & NAND_Ecc_P8e) << 0)
92 #define P8o_s(a) (TF(a & NAND_Ecc_P8o) << 1)
93 #define P16e_s(a) (TF(a & NAND_Ecc_P16e) << 2)
94 #define P16o_s(a) (TF(a & NAND_Ecc_P16o) << 3)
95 #define P1e_s(a) (TF(a & NAND_Ecc_P1e) << 4)
96 #define P1o_s(a) (TF(a & NAND_Ecc_P1o) << 5)
97 #define P2e_s(a) (TF(a & NAND_Ecc_P2e) << 6)
98 #define P2o_s(a) (TF(a & NAND_Ecc_P2o) << 7)
99
100 #define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0)
101 #define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1)
102
103 #define PREFETCH_CONFIG1_CS_SHIFT 24
104 #define ECC_CONFIG_CS_SHIFT 1
105 #define CS_MASK 0x7
106 #define ENABLE_PREFETCH (0x1 << 7)
107 #define DMA_MPU_MODE_SHIFT 2
108 #define ECCSIZE0_SHIFT 12
109 #define ECCSIZE1_SHIFT 22
110 #define ECC1RESULTSIZE 0x1
111 #define ECCCLEAR 0x100
112 #define ECC1 0x1
113 #define PREFETCH_FIFOTHRESHOLD_MAX 0x40
114 #define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8)
115 #define PREFETCH_STATUS_COUNT(val) (val & 0x00003fff)
116 #define PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F)
117 #define STATUS_BUFF_EMPTY 0x00000001
118
119 #define OMAP24XX_DMA_GPMC 4
120
121 #define SECTOR_BYTES 512
122 /* 4 bit padding to make byte aligned, 56 = 52 + 4 */
123 #define BCH4_BIT_PAD 4
124
125 /* GPMC ecc engine settings for read */
126 #define BCH_WRAPMODE_1 1 /* BCH wrap mode 1 */
127 #define BCH8R_ECC_SIZE0 0x1a /* ecc_size0 = 26 */
128 #define BCH8R_ECC_SIZE1 0x2 /* ecc_size1 = 2 */
129 #define BCH4R_ECC_SIZE0 0xd /* ecc_size0 = 13 */
130 #define BCH4R_ECC_SIZE1 0x3 /* ecc_size1 = 3 */
131
132 /* GPMC ecc engine settings for write */
133 #define BCH_WRAPMODE_6 6 /* BCH wrap mode 6 */
134 #define BCH_ECC_SIZE0 0x0 /* ecc_size0 = 0, no oob protection */
135 #define BCH_ECC_SIZE1 0x20 /* ecc_size1 = 32 */
136
137 #define BADBLOCK_MARKER_LENGTH 2
138
139 #ifdef CONFIG_MTD_NAND_OMAP_BCH
140 static u_char bch8_vector[] = {0xf3, 0xdb, 0x14, 0x16, 0x8b, 0xd2, 0xbe, 0xcc,
141 0xac, 0x6b, 0xff, 0x99, 0x7b};
142 static u_char bch4_vector[] = {0x00, 0x6b, 0x31, 0xdd, 0x41, 0xbc, 0x10};
143 #endif
144
145 /* oob info generated runtime depending on ecc algorithm and layout selected */
146 static struct nand_ecclayout omap_oobinfo;
147
148 struct omap_nand_info {
149 struct nand_hw_control controller;
150 struct omap_nand_platform_data *pdata;
151 struct mtd_info mtd;
152 struct nand_chip nand;
153 struct platform_device *pdev;
154
155 int gpmc_cs;
156 unsigned long phys_base;
157 enum omap_ecc ecc_opt;
158 struct completion comp;
159 struct dma_chan *dma;
160 int gpmc_irq_fifo;
161 int gpmc_irq_count;
162 enum {
163 OMAP_NAND_IO_READ = 0, /* read */
164 OMAP_NAND_IO_WRITE, /* write */
165 } iomode;
166 u_char *buf;
167 int buf_len;
168 struct gpmc_nand_regs reg;
169 /* fields specific for BCHx_HW ECC scheme */
170 struct device *elm_dev;
171 struct device_node *of_node;
172 };
173
174 /**
175 * omap_prefetch_enable - configures and starts prefetch transfer
176 * @cs: cs (chip select) number
177 * @fifo_th: fifo threshold to be used for read/ write
178 * @dma_mode: dma mode enable (1) or disable (0)
179 * @u32_count: number of bytes to be transferred
180 * @is_write: prefetch read(0) or write post(1) mode
181 */
182 static int omap_prefetch_enable(int cs, int fifo_th, int dma_mode,
183 unsigned int u32_count, int is_write, struct omap_nand_info *info)
184 {
185 u32 val;
186
187 if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX)
188 return -1;
189
190 if (readl(info->reg.gpmc_prefetch_control))
191 return -EBUSY;
192
193 /* Set the amount of bytes to be prefetched */
194 writel(u32_count, info->reg.gpmc_prefetch_config2);
195
196 /* Set dma/mpu mode, the prefetch read / post write and
197 * enable the engine. Set which cs is has requested for.
198 */
199 val = ((cs << PREFETCH_CONFIG1_CS_SHIFT) |
200 PREFETCH_FIFOTHRESHOLD(fifo_th) | ENABLE_PREFETCH |
201 (dma_mode << DMA_MPU_MODE_SHIFT) | (0x1 & is_write));
202 writel(val, info->reg.gpmc_prefetch_config1);
203
204 /* Start the prefetch engine */
205 writel(0x1, info->reg.gpmc_prefetch_control);
206
207 return 0;
208 }
209
210 /**
211 * omap_prefetch_reset - disables and stops the prefetch engine
212 */
213 static int omap_prefetch_reset(int cs, struct omap_nand_info *info)
214 {
215 u32 config1;
216
217 /* check if the same module/cs is trying to reset */
218 config1 = readl(info->reg.gpmc_prefetch_config1);
219 if (((config1 >> PREFETCH_CONFIG1_CS_SHIFT) & CS_MASK) != cs)
220 return -EINVAL;
221
222 /* Stop the PFPW engine */
223 writel(0x0, info->reg.gpmc_prefetch_control);
224
225 /* Reset/disable the PFPW engine */
226 writel(0x0, info->reg.gpmc_prefetch_config1);
227
228 return 0;
229 }
230
231 /**
232 * omap_hwcontrol - hardware specific access to control-lines
233 * @mtd: MTD device structure
234 * @cmd: command to device
235 * @ctrl:
236 * NAND_NCE: bit 0 -> don't care
237 * NAND_CLE: bit 1 -> Command Latch
238 * NAND_ALE: bit 2 -> Address Latch
239 *
240 * NOTE: boards may use different bits for these!!
241 */
242 static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
243 {
244 struct omap_nand_info *info = container_of(mtd,
245 struct omap_nand_info, mtd);
246
247 if (cmd != NAND_CMD_NONE) {
248 if (ctrl & NAND_CLE)
249 writeb(cmd, info->reg.gpmc_nand_command);
250
251 else if (ctrl & NAND_ALE)
252 writeb(cmd, info->reg.gpmc_nand_address);
253
254 else /* NAND_NCE */
255 writeb(cmd, info->reg.gpmc_nand_data);
256 }
257 }
258
259 /**
260 * omap_read_buf8 - read data from NAND controller into buffer
261 * @mtd: MTD device structure
262 * @buf: buffer to store date
263 * @len: number of bytes to read
264 */
265 static void omap_read_buf8(struct mtd_info *mtd, u_char *buf, int len)
266 {
267 struct nand_chip *nand = mtd->priv;
268
269 ioread8_rep(nand->IO_ADDR_R, buf, len);
270 }
271
272 /**
273 * omap_write_buf8 - write buffer to NAND controller
274 * @mtd: MTD device structure
275 * @buf: data buffer
276 * @len: number of bytes to write
277 */
278 static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len)
279 {
280 struct omap_nand_info *info = container_of(mtd,
281 struct omap_nand_info, mtd);
282 u_char *p = (u_char *)buf;
283 u32 status = 0;
284
285 while (len--) {
286 iowrite8(*p++, info->nand.IO_ADDR_W);
287 /* wait until buffer is available for write */
288 do {
289 status = readl(info->reg.gpmc_status) &
290 STATUS_BUFF_EMPTY;
291 } while (!status);
292 }
293 }
294
295 /**
296 * omap_read_buf16 - read data from NAND controller into buffer
297 * @mtd: MTD device structure
298 * @buf: buffer to store date
299 * @len: number of bytes to read
300 */
301 static void omap_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
302 {
303 struct nand_chip *nand = mtd->priv;
304
305 ioread16_rep(nand->IO_ADDR_R, buf, len / 2);
306 }
307
308 /**
309 * omap_write_buf16 - write buffer to NAND controller
310 * @mtd: MTD device structure
311 * @buf: data buffer
312 * @len: number of bytes to write
313 */
314 static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len)
315 {
316 struct omap_nand_info *info = container_of(mtd,
317 struct omap_nand_info, mtd);
318 u16 *p = (u16 *) buf;
319 u32 status = 0;
320 /* FIXME try bursts of writesw() or DMA ... */
321 len >>= 1;
322
323 while (len--) {
324 iowrite16(*p++, info->nand.IO_ADDR_W);
325 /* wait until buffer is available for write */
326 do {
327 status = readl(info->reg.gpmc_status) &
328 STATUS_BUFF_EMPTY;
329 } while (!status);
330 }
331 }
332
333 /**
334 * omap_read_buf_pref - read data from NAND controller into buffer
335 * @mtd: MTD device structure
336 * @buf: buffer to store date
337 * @len: number of bytes to read
338 */
339 static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
340 {
341 struct omap_nand_info *info = container_of(mtd,
342 struct omap_nand_info, mtd);
343 uint32_t r_count = 0;
344 int ret = 0;
345 u32 *p = (u32 *)buf;
346
347 /* take care of subpage reads */
348 if (len % 4) {
349 if (info->nand.options & NAND_BUSWIDTH_16)
350 omap_read_buf16(mtd, buf, len % 4);
351 else
352 omap_read_buf8(mtd, buf, len % 4);
353 p = (u32 *) (buf + len % 4);
354 len -= len % 4;
355 }
356
357 /* configure and start prefetch transfer */
358 ret = omap_prefetch_enable(info->gpmc_cs,
359 PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0, info);
360 if (ret) {
361 /* PFPW engine is busy, use cpu copy method */
362 if (info->nand.options & NAND_BUSWIDTH_16)
363 omap_read_buf16(mtd, (u_char *)p, len);
364 else
365 omap_read_buf8(mtd, (u_char *)p, len);
366 } else {
367 do {
368 r_count = readl(info->reg.gpmc_prefetch_status);
369 r_count = PREFETCH_STATUS_FIFO_CNT(r_count);
370 r_count = r_count >> 2;
371 ioread32_rep(info->nand.IO_ADDR_R, p, r_count);
372 p += r_count;
373 len -= r_count << 2;
374 } while (len);
375 /* disable and stop the PFPW engine */
376 omap_prefetch_reset(info->gpmc_cs, info);
377 }
378 }
379
380 /**
381 * omap_write_buf_pref - write buffer to NAND controller
382 * @mtd: MTD device structure
383 * @buf: data buffer
384 * @len: number of bytes to write
385 */
386 static void omap_write_buf_pref(struct mtd_info *mtd,
387 const u_char *buf, int len)
388 {
389 struct omap_nand_info *info = container_of(mtd,
390 struct omap_nand_info, mtd);
391 uint32_t w_count = 0;
392 int i = 0, ret = 0;
393 u16 *p = (u16 *)buf;
394 unsigned long tim, limit;
395 u32 val;
396
397 /* take care of subpage writes */
398 if (len % 2 != 0) {
399 writeb(*buf, info->nand.IO_ADDR_W);
400 p = (u16 *)(buf + 1);
401 len--;
402 }
403
404 /* configure and start prefetch transfer */
405 ret = omap_prefetch_enable(info->gpmc_cs,
406 PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1, info);
407 if (ret) {
408 /* PFPW engine is busy, use cpu copy method */
409 if (info->nand.options & NAND_BUSWIDTH_16)
410 omap_write_buf16(mtd, (u_char *)p, len);
411 else
412 omap_write_buf8(mtd, (u_char *)p, len);
413 } else {
414 while (len) {
415 w_count = readl(info->reg.gpmc_prefetch_status);
416 w_count = PREFETCH_STATUS_FIFO_CNT(w_count);
417 w_count = w_count >> 1;
418 for (i = 0; (i < w_count) && len; i++, len -= 2)
419 iowrite16(*p++, info->nand.IO_ADDR_W);
420 }
421 /* wait for data to flushed-out before reset the prefetch */
422 tim = 0;
423 limit = (loops_per_jiffy *
424 msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
425 do {
426 cpu_relax();
427 val = readl(info->reg.gpmc_prefetch_status);
428 val = PREFETCH_STATUS_COUNT(val);
429 } while (val && (tim++ < limit));
430
431 /* disable and stop the PFPW engine */
432 omap_prefetch_reset(info->gpmc_cs, info);
433 }
434 }
435
436 /*
437 * omap_nand_dma_callback: callback on the completion of dma transfer
438 * @data: pointer to completion data structure
439 */
440 static void omap_nand_dma_callback(void *data)
441 {
442 complete((struct completion *) data);
443 }
444
445 /*
446 * omap_nand_dma_transfer: configure and start dma transfer
447 * @mtd: MTD device structure
448 * @addr: virtual address in RAM of source/destination
449 * @len: number of data bytes to be transferred
450 * @is_write: flag for read/write operation
451 */
452 static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
453 unsigned int len, int is_write)
454 {
455 struct omap_nand_info *info = container_of(mtd,
456 struct omap_nand_info, mtd);
457 struct dma_async_tx_descriptor *tx;
458 enum dma_data_direction dir = is_write ? DMA_TO_DEVICE :
459 DMA_FROM_DEVICE;
460 struct scatterlist sg;
461 unsigned long tim, limit;
462 unsigned n;
463 int ret;
464 u32 val;
465
466 if (addr >= high_memory) {
467 struct page *p1;
468
469 if (((size_t)addr & PAGE_MASK) !=
470 ((size_t)(addr + len - 1) & PAGE_MASK))
471 goto out_copy;
472 p1 = vmalloc_to_page(addr);
473 if (!p1)
474 goto out_copy;
475 addr = page_address(p1) + ((size_t)addr & ~PAGE_MASK);
476 }
477
478 sg_init_one(&sg, addr, len);
479 n = dma_map_sg(info->dma->device->dev, &sg, 1, dir);
480 if (n == 0) {
481 dev_err(&info->pdev->dev,
482 "Couldn't DMA map a %d byte buffer\n", len);
483 goto out_copy;
484 }
485
486 tx = dmaengine_prep_slave_sg(info->dma, &sg, n,
487 is_write ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
488 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
489 if (!tx)
490 goto out_copy_unmap;
491
492 tx->callback = omap_nand_dma_callback;
493 tx->callback_param = &info->comp;
494 dmaengine_submit(tx);
495
496 /* configure and start prefetch transfer */
497 ret = omap_prefetch_enable(info->gpmc_cs,
498 PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write, info);
499 if (ret)
500 /* PFPW engine is busy, use cpu copy method */
501 goto out_copy_unmap;
502
503 init_completion(&info->comp);
504 dma_async_issue_pending(info->dma);
505
506 /* setup and start DMA using dma_addr */
507 wait_for_completion(&info->comp);
508 tim = 0;
509 limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
510
511 do {
512 cpu_relax();
513 val = readl(info->reg.gpmc_prefetch_status);
514 val = PREFETCH_STATUS_COUNT(val);
515 } while (val && (tim++ < limit));
516
517 /* disable and stop the PFPW engine */
518 omap_prefetch_reset(info->gpmc_cs, info);
519
520 dma_unmap_sg(info->dma->device->dev, &sg, 1, dir);
521 return 0;
522
523 out_copy_unmap:
524 dma_unmap_sg(info->dma->device->dev, &sg, 1, dir);
525 out_copy:
526 if (info->nand.options & NAND_BUSWIDTH_16)
527 is_write == 0 ? omap_read_buf16(mtd, (u_char *) addr, len)
528 : omap_write_buf16(mtd, (u_char *) addr, len);
529 else
530 is_write == 0 ? omap_read_buf8(mtd, (u_char *) addr, len)
531 : omap_write_buf8(mtd, (u_char *) addr, len);
532 return 0;
533 }
534
535 /**
536 * omap_read_buf_dma_pref - read data from NAND controller into buffer
537 * @mtd: MTD device structure
538 * @buf: buffer to store date
539 * @len: number of bytes to read
540 */
541 static void omap_read_buf_dma_pref(struct mtd_info *mtd, u_char *buf, int len)
542 {
543 if (len <= mtd->oobsize)
544 omap_read_buf_pref(mtd, buf, len);
545 else
546 /* start transfer in DMA mode */
547 omap_nand_dma_transfer(mtd, buf, len, 0x0);
548 }
549
550 /**
551 * omap_write_buf_dma_pref - write buffer to NAND controller
552 * @mtd: MTD device structure
553 * @buf: data buffer
554 * @len: number of bytes to write
555 */
556 static void omap_write_buf_dma_pref(struct mtd_info *mtd,
557 const u_char *buf, int len)
558 {
559 if (len <= mtd->oobsize)
560 omap_write_buf_pref(mtd, buf, len);
561 else
562 /* start transfer in DMA mode */
563 omap_nand_dma_transfer(mtd, (u_char *) buf, len, 0x1);
564 }
565
566 /*
567 * omap_nand_irq - GPMC irq handler
568 * @this_irq: gpmc irq number
569 * @dev: omap_nand_info structure pointer is passed here
570 */
571 static irqreturn_t omap_nand_irq(int this_irq, void *dev)
572 {
573 struct omap_nand_info *info = (struct omap_nand_info *) dev;
574 u32 bytes;
575
576 bytes = readl(info->reg.gpmc_prefetch_status);
577 bytes = PREFETCH_STATUS_FIFO_CNT(bytes);
578 bytes = bytes & 0xFFFC; /* io in multiple of 4 bytes */
579 if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */
580 if (this_irq == info->gpmc_irq_count)
581 goto done;
582
583 if (info->buf_len && (info->buf_len < bytes))
584 bytes = info->buf_len;
585 else if (!info->buf_len)
586 bytes = 0;
587 iowrite32_rep(info->nand.IO_ADDR_W,
588 (u32 *)info->buf, bytes >> 2);
589 info->buf = info->buf + bytes;
590 info->buf_len -= bytes;
591
592 } else {
593 ioread32_rep(info->nand.IO_ADDR_R,
594 (u32 *)info->buf, bytes >> 2);
595 info->buf = info->buf + bytes;
596
597 if (this_irq == info->gpmc_irq_count)
598 goto done;
599 }
600
601 return IRQ_HANDLED;
602
603 done:
604 complete(&info->comp);
605
606 disable_irq_nosync(info->gpmc_irq_fifo);
607 disable_irq_nosync(info->gpmc_irq_count);
608
609 return IRQ_HANDLED;
610 }
611
612 /*
613 * omap_read_buf_irq_pref - read data from NAND controller into buffer
614 * @mtd: MTD device structure
615 * @buf: buffer to store date
616 * @len: number of bytes to read
617 */
618 static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len)
619 {
620 struct omap_nand_info *info = container_of(mtd,
621 struct omap_nand_info, mtd);
622 int ret = 0;
623
624 if (len <= mtd->oobsize) {
625 omap_read_buf_pref(mtd, buf, len);
626 return;
627 }
628
629 info->iomode = OMAP_NAND_IO_READ;
630 info->buf = buf;
631 init_completion(&info->comp);
632
633 /* configure and start prefetch transfer */
634 ret = omap_prefetch_enable(info->gpmc_cs,
635 PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0, info);
636 if (ret)
637 /* PFPW engine is busy, use cpu copy method */
638 goto out_copy;
639
640 info->buf_len = len;
641
642 enable_irq(info->gpmc_irq_count);
643 enable_irq(info->gpmc_irq_fifo);
644
645 /* waiting for read to complete */
646 wait_for_completion(&info->comp);
647
648 /* disable and stop the PFPW engine */
649 omap_prefetch_reset(info->gpmc_cs, info);
650 return;
651
652 out_copy:
653 if (info->nand.options & NAND_BUSWIDTH_16)
654 omap_read_buf16(mtd, buf, len);
655 else
656 omap_read_buf8(mtd, buf, len);
657 }
658
659 /*
660 * omap_write_buf_irq_pref - write buffer to NAND controller
661 * @mtd: MTD device structure
662 * @buf: data buffer
663 * @len: number of bytes to write
664 */
665 static void omap_write_buf_irq_pref(struct mtd_info *mtd,
666 const u_char *buf, int len)
667 {
668 struct omap_nand_info *info = container_of(mtd,
669 struct omap_nand_info, mtd);
670 int ret = 0;
671 unsigned long tim, limit;
672 u32 val;
673
674 if (len <= mtd->oobsize) {
675 omap_write_buf_pref(mtd, buf, len);
676 return;
677 }
678
679 info->iomode = OMAP_NAND_IO_WRITE;
680 info->buf = (u_char *) buf;
681 init_completion(&info->comp);
682
683 /* configure and start prefetch transfer : size=24 */
684 ret = omap_prefetch_enable(info->gpmc_cs,
685 (PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1, info);
686 if (ret)
687 /* PFPW engine is busy, use cpu copy method */
688 goto out_copy;
689
690 info->buf_len = len;
691
692 enable_irq(info->gpmc_irq_count);
693 enable_irq(info->gpmc_irq_fifo);
694
695 /* waiting for write to complete */
696 wait_for_completion(&info->comp);
697
698 /* wait for data to flushed-out before reset the prefetch */
699 tim = 0;
700 limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
701 do {
702 val = readl(info->reg.gpmc_prefetch_status);
703 val = PREFETCH_STATUS_COUNT(val);
704 cpu_relax();
705 } while (val && (tim++ < limit));
706
707 /* disable and stop the PFPW engine */
708 omap_prefetch_reset(info->gpmc_cs, info);
709 return;
710
711 out_copy:
712 if (info->nand.options & NAND_BUSWIDTH_16)
713 omap_write_buf16(mtd, buf, len);
714 else
715 omap_write_buf8(mtd, buf, len);
716 }
717
718 /**
719 * gen_true_ecc - This function will generate true ECC value
720 * @ecc_buf: buffer to store ecc code
721 *
722 * This generated true ECC value can be used when correcting
723 * data read from NAND flash memory core
724 */
725 static void gen_true_ecc(u8 *ecc_buf)
726 {
727 u32 tmp = ecc_buf[0] | (ecc_buf[1] << 16) |
728 ((ecc_buf[2] & 0xF0) << 20) | ((ecc_buf[2] & 0x0F) << 8);
729
730 ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) |
731 P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp));
732 ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) |
733 P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp));
734 ecc_buf[2] = ~(P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) |
735 P1e(tmp) | P2048o(tmp) | P2048e(tmp));
736 }
737
738 /**
739 * omap_compare_ecc - Detect (2 bits) and correct (1 bit) error in data
740 * @ecc_data1: ecc code from nand spare area
741 * @ecc_data2: ecc code from hardware register obtained from hardware ecc
742 * @page_data: page data
743 *
744 * This function compares two ECC's and indicates if there is an error.
745 * If the error can be corrected it will be corrected to the buffer.
746 * If there is no error, %0 is returned. If there is an error but it
747 * was corrected, %1 is returned. Otherwise, %-1 is returned.
748 */
749 static int omap_compare_ecc(u8 *ecc_data1, /* read from NAND memory */
750 u8 *ecc_data2, /* read from register */
751 u8 *page_data)
752 {
753 uint i;
754 u8 tmp0_bit[8], tmp1_bit[8], tmp2_bit[8];
755 u8 comp0_bit[8], comp1_bit[8], comp2_bit[8];
756 u8 ecc_bit[24];
757 u8 ecc_sum = 0;
758 u8 find_bit = 0;
759 uint find_byte = 0;
760 int isEccFF;
761
762 isEccFF = ((*(u32 *)ecc_data1 & 0xFFFFFF) == 0xFFFFFF);
763
764 gen_true_ecc(ecc_data1);
765 gen_true_ecc(ecc_data2);
766
767 for (i = 0; i <= 2; i++) {
768 *(ecc_data1 + i) = ~(*(ecc_data1 + i));
769 *(ecc_data2 + i) = ~(*(ecc_data2 + i));
770 }
771
772 for (i = 0; i < 8; i++) {
773 tmp0_bit[i] = *ecc_data1 % 2;
774 *ecc_data1 = *ecc_data1 / 2;
775 }
776
777 for (i = 0; i < 8; i++) {
778 tmp1_bit[i] = *(ecc_data1 + 1) % 2;
779 *(ecc_data1 + 1) = *(ecc_data1 + 1) / 2;
780 }
781
782 for (i = 0; i < 8; i++) {
783 tmp2_bit[i] = *(ecc_data1 + 2) % 2;
784 *(ecc_data1 + 2) = *(ecc_data1 + 2) / 2;
785 }
786
787 for (i = 0; i < 8; i++) {
788 comp0_bit[i] = *ecc_data2 % 2;
789 *ecc_data2 = *ecc_data2 / 2;
790 }
791
792 for (i = 0; i < 8; i++) {
793 comp1_bit[i] = *(ecc_data2 + 1) % 2;
794 *(ecc_data2 + 1) = *(ecc_data2 + 1) / 2;
795 }
796
797 for (i = 0; i < 8; i++) {
798 comp2_bit[i] = *(ecc_data2 + 2) % 2;
799 *(ecc_data2 + 2) = *(ecc_data2 + 2) / 2;
800 }
801
802 for (i = 0; i < 6; i++)
803 ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2];
804
805 for (i = 0; i < 8; i++)
806 ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i];
807
808 for (i = 0; i < 8; i++)
809 ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i];
810
811 ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0];
812 ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1];
813
814 for (i = 0; i < 24; i++)
815 ecc_sum += ecc_bit[i];
816
817 switch (ecc_sum) {
818 case 0:
819 /* Not reached because this function is not called if
820 * ECC values are equal
821 */
822 return 0;
823
824 case 1:
825 /* Uncorrectable error */
826 pr_debug("ECC UNCORRECTED_ERROR 1\n");
827 return -1;
828
829 case 11:
830 /* UN-Correctable error */
831 pr_debug("ECC UNCORRECTED_ERROR B\n");
832 return -1;
833
834 case 12:
835 /* Correctable error */
836 find_byte = (ecc_bit[23] << 8) +
837 (ecc_bit[21] << 7) +
838 (ecc_bit[19] << 6) +
839 (ecc_bit[17] << 5) +
840 (ecc_bit[15] << 4) +
841 (ecc_bit[13] << 3) +
842 (ecc_bit[11] << 2) +
843 (ecc_bit[9] << 1) +
844 ecc_bit[7];
845
846 find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1];
847
848 pr_debug("Correcting single bit ECC error at offset: "
849 "%d, bit: %d\n", find_byte, find_bit);
850
851 page_data[find_byte] ^= (1 << find_bit);
852
853 return 1;
854 default:
855 if (isEccFF) {
856 if (ecc_data2[0] == 0 &&
857 ecc_data2[1] == 0 &&
858 ecc_data2[2] == 0)
859 return 0;
860 }
861 pr_debug("UNCORRECTED_ERROR default\n");
862 return -1;
863 }
864 }
865
866 /**
867 * omap_correct_data - Compares the ECC read with HW generated ECC
868 * @mtd: MTD device structure
869 * @dat: page data
870 * @read_ecc: ecc read from nand flash
871 * @calc_ecc: ecc read from HW ECC registers
872 *
873 * Compares the ecc read from nand spare area with ECC registers values
874 * and if ECC's mismatched, it will call 'omap_compare_ecc' for error
875 * detection and correction. If there are no errors, %0 is returned. If
876 * there were errors and all of the errors were corrected, the number of
877 * corrected errors is returned. If uncorrectable errors exist, %-1 is
878 * returned.
879 */
880 static int omap_correct_data(struct mtd_info *mtd, u_char *dat,
881 u_char *read_ecc, u_char *calc_ecc)
882 {
883 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
884 mtd);
885 int blockCnt = 0, i = 0, ret = 0;
886 int stat = 0;
887
888 /* Ex NAND_ECC_HW12_2048 */
889 if ((info->nand.ecc.mode == NAND_ECC_HW) &&
890 (info->nand.ecc.size == 2048))
891 blockCnt = 4;
892 else
893 blockCnt = 1;
894
895 for (i = 0; i < blockCnt; i++) {
896 if (memcmp(read_ecc, calc_ecc, 3) != 0) {
897 ret = omap_compare_ecc(read_ecc, calc_ecc, dat);
898 if (ret < 0)
899 return ret;
900 /* keep track of the number of corrected errors */
901 stat += ret;
902 }
903 read_ecc += 3;
904 calc_ecc += 3;
905 dat += 512;
906 }
907 return stat;
908 }
909
910 /**
911 * omap_calcuate_ecc - Generate non-inverted ECC bytes.
912 * @mtd: MTD device structure
913 * @dat: The pointer to data on which ecc is computed
914 * @ecc_code: The ecc_code buffer
915 *
916 * Using noninverted ECC can be considered ugly since writing a blank
917 * page ie. padding will clear the ECC bytes. This is no problem as long
918 * nobody is trying to write data on the seemingly unused page. Reading
919 * an erased page will produce an ECC mismatch between generated and read
920 * ECC bytes that has to be dealt with separately.
921 */
922 static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
923 u_char *ecc_code)
924 {
925 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
926 mtd);
927 u32 val;
928
929 val = readl(info->reg.gpmc_ecc_config);
930 if (((val >> ECC_CONFIG_CS_SHIFT) & ~CS_MASK) != info->gpmc_cs)
931 return -EINVAL;
932
933 /* read ecc result */
934 val = readl(info->reg.gpmc_ecc1_result);
935 *ecc_code++ = val; /* P128e, ..., P1e */
936 *ecc_code++ = val >> 16; /* P128o, ..., P1o */
937 /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
938 *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0);
939
940 return 0;
941 }
942
943 /**
944 * omap_enable_hwecc - This function enables the hardware ecc functionality
945 * @mtd: MTD device structure
946 * @mode: Read/Write mode
947 */
948 static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
949 {
950 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
951 mtd);
952 struct nand_chip *chip = mtd->priv;
953 unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
954 u32 val;
955
956 /* clear ecc and enable bits */
957 val = ECCCLEAR | ECC1;
958 writel(val, info->reg.gpmc_ecc_control);
959
960 /* program ecc and result sizes */
961 val = ((((info->nand.ecc.size >> 1) - 1) << ECCSIZE1_SHIFT) |
962 ECC1RESULTSIZE);
963 writel(val, info->reg.gpmc_ecc_size_config);
964
965 switch (mode) {
966 case NAND_ECC_READ:
967 case NAND_ECC_WRITE:
968 writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control);
969 break;
970 case NAND_ECC_READSYN:
971 writel(ECCCLEAR, info->reg.gpmc_ecc_control);
972 break;
973 default:
974 dev_info(&info->pdev->dev,
975 "error: unrecognized Mode[%d]!\n", mode);
976 break;
977 }
978
979 /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */
980 val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1);
981 writel(val, info->reg.gpmc_ecc_config);
982 }
983
984 /**
985 * omap_wait - wait until the command is done
986 * @mtd: MTD device structure
987 * @chip: NAND Chip structure
988 *
989 * Wait function is called during Program and erase operations and
990 * the way it is called from MTD layer, we should wait till the NAND
991 * chip is ready after the programming/erase operation has completed.
992 *
993 * Erase can take up to 400ms and program up to 20ms according to
994 * general NAND and SmartMedia specs
995 */
996 static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip)
997 {
998 struct nand_chip *this = mtd->priv;
999 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1000 mtd);
1001 unsigned long timeo = jiffies;
1002 int status, state = this->state;
1003
1004 if (state == FL_ERASING)
1005 timeo += msecs_to_jiffies(400);
1006 else
1007 timeo += msecs_to_jiffies(20);
1008
1009 writeb(NAND_CMD_STATUS & 0xFF, info->reg.gpmc_nand_command);
1010 while (time_before(jiffies, timeo)) {
1011 status = readb(info->reg.gpmc_nand_data);
1012 if (status & NAND_STATUS_READY)
1013 break;
1014 cond_resched();
1015 }
1016
1017 status = readb(info->reg.gpmc_nand_data);
1018 return status;
1019 }
1020
1021 /**
1022 * omap_dev_ready - calls the platform specific dev_ready function
1023 * @mtd: MTD device structure
1024 */
1025 static int omap_dev_ready(struct mtd_info *mtd)
1026 {
1027 unsigned int val = 0;
1028 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1029 mtd);
1030
1031 val = readl(info->reg.gpmc_status);
1032
1033 if ((val & 0x100) == 0x100) {
1034 return 1;
1035 } else {
1036 return 0;
1037 }
1038 }
1039
1040 /**
1041 * omap_enable_hwecc_bch - Program GPMC to perform BCH ECC calculation
1042 * @mtd: MTD device structure
1043 * @mode: Read/Write mode
1044 *
1045 * When using BCH, sector size is hardcoded to 512 bytes.
1046 * Using wrapping mode 6 both for reading and writing if ELM module not uses
1047 * for error correction.
1048 * On writing,
1049 * eccsize0 = 0 (no additional protected byte in spare area)
1050 * eccsize1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area)
1051 */
1052 static void __maybe_unused omap_enable_hwecc_bch(struct mtd_info *mtd, int mode)
1053 {
1054 unsigned int bch_type;
1055 unsigned int dev_width, nsectors;
1056 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1057 mtd);
1058 enum omap_ecc ecc_opt = info->ecc_opt;
1059 struct nand_chip *chip = mtd->priv;
1060 u32 val, wr_mode;
1061 unsigned int ecc_size1, ecc_size0;
1062
1063 /* GPMC configurations for calculating ECC */
1064 switch (ecc_opt) {
1065 case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1066 bch_type = 0;
1067 nsectors = 1;
1068 if (mode == NAND_ECC_READ) {
1069 wr_mode = BCH_WRAPMODE_6;
1070 ecc_size0 = BCH_ECC_SIZE0;
1071 ecc_size1 = BCH_ECC_SIZE1;
1072 } else {
1073 wr_mode = BCH_WRAPMODE_6;
1074 ecc_size0 = BCH_ECC_SIZE0;
1075 ecc_size1 = BCH_ECC_SIZE1;
1076 }
1077 break;
1078 case OMAP_ECC_BCH4_CODE_HW:
1079 bch_type = 0;
1080 nsectors = chip->ecc.steps;
1081 if (mode == NAND_ECC_READ) {
1082 wr_mode = BCH_WRAPMODE_1;
1083 ecc_size0 = BCH4R_ECC_SIZE0;
1084 ecc_size1 = BCH4R_ECC_SIZE1;
1085 } else {
1086 wr_mode = BCH_WRAPMODE_6;
1087 ecc_size0 = BCH_ECC_SIZE0;
1088 ecc_size1 = BCH_ECC_SIZE1;
1089 }
1090 break;
1091 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1092 bch_type = 1;
1093 nsectors = 1;
1094 if (mode == NAND_ECC_READ) {
1095 wr_mode = BCH_WRAPMODE_6;
1096 ecc_size0 = BCH_ECC_SIZE0;
1097 ecc_size1 = BCH_ECC_SIZE1;
1098 } else {
1099 wr_mode = BCH_WRAPMODE_6;
1100 ecc_size0 = BCH_ECC_SIZE0;
1101 ecc_size1 = BCH_ECC_SIZE1;
1102 }
1103 break;
1104 case OMAP_ECC_BCH8_CODE_HW:
1105 bch_type = 1;
1106 nsectors = chip->ecc.steps;
1107 if (mode == NAND_ECC_READ) {
1108 wr_mode = BCH_WRAPMODE_1;
1109 ecc_size0 = BCH8R_ECC_SIZE0;
1110 ecc_size1 = BCH8R_ECC_SIZE1;
1111 } else {
1112 wr_mode = BCH_WRAPMODE_6;
1113 ecc_size0 = BCH_ECC_SIZE0;
1114 ecc_size1 = BCH_ECC_SIZE1;
1115 }
1116 break;
1117 default:
1118 return;
1119 }
1120
1121 writel(ECC1, info->reg.gpmc_ecc_control);
1122
1123 /* Configure ecc size for BCH */
1124 val = (ecc_size1 << ECCSIZE1_SHIFT) | (ecc_size0 << ECCSIZE0_SHIFT);
1125 writel(val, info->reg.gpmc_ecc_size_config);
1126
1127 dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
1128
1129 /* BCH configuration */
1130 val = ((1 << 16) | /* enable BCH */
1131 (bch_type << 12) | /* BCH4/BCH8/BCH16 */
1132 (wr_mode << 8) | /* wrap mode */
1133 (dev_width << 7) | /* bus width */
1134 (((nsectors-1) & 0x7) << 4) | /* number of sectors */
1135 (info->gpmc_cs << 1) | /* ECC CS */
1136 (0x1)); /* enable ECC */
1137
1138 writel(val, info->reg.gpmc_ecc_config);
1139
1140 /* Clear ecc and enable bits */
1141 writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control);
1142 }
1143
1144 static u8 bch4_polynomial[] = {0x28, 0x13, 0xcc, 0x39, 0x96, 0xac, 0x7f};
1145 static u8 bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2,
1146 0x97, 0x79, 0xe5, 0x24, 0xb5};
1147
1148 /**
1149 * omap_calculate_ecc_bch - Generate bytes of ECC bytes
1150 * @mtd: MTD device structure
1151 * @dat: The pointer to data on which ecc is computed
1152 * @ecc_code: The ecc_code buffer
1153 *
1154 * Support calculating of BCH4/8 ecc vectors for the page
1155 */
1156 static int __maybe_unused omap_calculate_ecc_bch(struct mtd_info *mtd,
1157 const u_char *dat, u_char *ecc_calc)
1158 {
1159 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1160 mtd);
1161 int eccbytes = info->nand.ecc.bytes;
1162 struct gpmc_nand_regs *gpmc_regs = &info->reg;
1163 u8 *ecc_code;
1164 unsigned long nsectors, bch_val1, bch_val2, bch_val3, bch_val4;
1165 int i;
1166
1167 nsectors = ((readl(info->reg.gpmc_ecc_config) >> 4) & 0x7) + 1;
1168 for (i = 0; i < nsectors; i++) {
1169 ecc_code = ecc_calc;
1170 switch (info->ecc_opt) {
1171 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1172 case OMAP_ECC_BCH8_CODE_HW:
1173 bch_val1 = readl(gpmc_regs->gpmc_bch_result0[i]);
1174 bch_val2 = readl(gpmc_regs->gpmc_bch_result1[i]);
1175 bch_val3 = readl(gpmc_regs->gpmc_bch_result2[i]);
1176 bch_val4 = readl(gpmc_regs->gpmc_bch_result3[i]);
1177 *ecc_code++ = (bch_val4 & 0xFF);
1178 *ecc_code++ = ((bch_val3 >> 24) & 0xFF);
1179 *ecc_code++ = ((bch_val3 >> 16) & 0xFF);
1180 *ecc_code++ = ((bch_val3 >> 8) & 0xFF);
1181 *ecc_code++ = (bch_val3 & 0xFF);
1182 *ecc_code++ = ((bch_val2 >> 24) & 0xFF);
1183 *ecc_code++ = ((bch_val2 >> 16) & 0xFF);
1184 *ecc_code++ = ((bch_val2 >> 8) & 0xFF);
1185 *ecc_code++ = (bch_val2 & 0xFF);
1186 *ecc_code++ = ((bch_val1 >> 24) & 0xFF);
1187 *ecc_code++ = ((bch_val1 >> 16) & 0xFF);
1188 *ecc_code++ = ((bch_val1 >> 8) & 0xFF);
1189 *ecc_code++ = (bch_val1 & 0xFF);
1190 break;
1191 case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1192 case OMAP_ECC_BCH4_CODE_HW:
1193 bch_val1 = readl(gpmc_regs->gpmc_bch_result0[i]);
1194 bch_val2 = readl(gpmc_regs->gpmc_bch_result1[i]);
1195 *ecc_code++ = ((bch_val2 >> 12) & 0xFF);
1196 *ecc_code++ = ((bch_val2 >> 4) & 0xFF);
1197 *ecc_code++ = ((bch_val2 & 0xF) << 4) |
1198 ((bch_val1 >> 28) & 0xF);
1199 *ecc_code++ = ((bch_val1 >> 20) & 0xFF);
1200 *ecc_code++ = ((bch_val1 >> 12) & 0xFF);
1201 *ecc_code++ = ((bch_val1 >> 4) & 0xFF);
1202 *ecc_code++ = ((bch_val1 & 0xF) << 4);
1203 break;
1204 default:
1205 return -EINVAL;
1206 }
1207
1208 /* ECC scheme specific syndrome customizations */
1209 switch (info->ecc_opt) {
1210 case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1211 /* Add constant polynomial to remainder, so that
1212 * ECC of blank pages results in 0x0 on reading back */
1213 for (i = 0; i < eccbytes; i++)
1214 ecc_calc[i] ^= bch4_polynomial[i];
1215 break;
1216 case OMAP_ECC_BCH4_CODE_HW:
1217 /* Set 8th ECC byte as 0x0 for ROM compatibility */
1218 ecc_calc[eccbytes - 1] = 0x0;
1219 break;
1220 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1221 /* Add constant polynomial to remainder, so that
1222 * ECC of blank pages results in 0x0 on reading back */
1223 for (i = 0; i < eccbytes; i++)
1224 ecc_calc[i] ^= bch8_polynomial[i];
1225 break;
1226 case OMAP_ECC_BCH8_CODE_HW:
1227 /* Set 14th ECC byte as 0x0 for ROM compatibility */
1228 ecc_calc[eccbytes - 1] = 0x0;
1229 break;
1230 default:
1231 return -EINVAL;
1232 }
1233
1234 ecc_calc += eccbytes;
1235 }
1236
1237 return 0;
1238 }
1239
1240 /**
1241 * erased_sector_bitflips - count bit flips
1242 * @data: data sector buffer
1243 * @oob: oob buffer
1244 * @info: omap_nand_info
1245 *
1246 * Check the bit flips in erased page falls below correctable level.
1247 * If falls below, report the page as erased with correctable bit
1248 * flip, else report as uncorrectable page.
1249 */
1250 static int erased_sector_bitflips(u_char *data, u_char *oob,
1251 struct omap_nand_info *info)
1252 {
1253 int flip_bits = 0, i;
1254
1255 for (i = 0; i < info->nand.ecc.size; i++) {
1256 flip_bits += hweight8(~data[i]);
1257 if (flip_bits > info->nand.ecc.strength)
1258 return 0;
1259 }
1260
1261 for (i = 0; i < info->nand.ecc.bytes - 1; i++) {
1262 flip_bits += hweight8(~oob[i]);
1263 if (flip_bits > info->nand.ecc.strength)
1264 return 0;
1265 }
1266
1267 /*
1268 * Bit flips falls in correctable level.
1269 * Fill data area with 0xFF
1270 */
1271 if (flip_bits) {
1272 memset(data, 0xFF, info->nand.ecc.size);
1273 memset(oob, 0xFF, info->nand.ecc.bytes);
1274 }
1275
1276 return flip_bits;
1277 }
1278
1279 #ifdef CONFIG_MTD_NAND_OMAP_BCH
1280 /**
1281 * omap_elm_correct_data - corrects page data area in case error reported
1282 * @mtd: MTD device structure
1283 * @data: page data
1284 * @read_ecc: ecc read from nand flash
1285 * @calc_ecc: ecc read from HW ECC registers
1286 *
1287 * Calculated ecc vector reported as zero in case of non-error pages.
1288 * In case of non-zero ecc vector, first filter out erased-pages, and
1289 * then process data via ELM to detect bit-flips.
1290 */
1291 static int omap_elm_correct_data(struct mtd_info *mtd, u_char *data,
1292 u_char *read_ecc, u_char *calc_ecc)
1293 {
1294 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1295 mtd);
1296 struct nand_ecc_ctrl *ecc = &info->nand.ecc;
1297 int eccsteps = info->nand.ecc.steps;
1298 int i , j, stat = 0;
1299 int eccflag, actual_eccbytes;
1300 struct elm_errorvec err_vec[ERROR_VECTOR_MAX];
1301 u_char *ecc_vec = calc_ecc;
1302 u_char *spare_ecc = read_ecc;
1303 u_char *erased_ecc_vec;
1304 u_char *buf;
1305 int bitflip_count;
1306 bool is_error_reported = false;
1307 u32 bit_pos, byte_pos, error_max, pos;
1308 int err;
1309
1310 switch (info->ecc_opt) {
1311 case OMAP_ECC_BCH4_CODE_HW:
1312 /* omit 7th ECC byte reserved for ROM code compatibility */
1313 actual_eccbytes = ecc->bytes - 1;
1314 erased_ecc_vec = bch4_vector;
1315 break;
1316 case OMAP_ECC_BCH8_CODE_HW:
1317 /* omit 14th ECC byte reserved for ROM code compatibility */
1318 actual_eccbytes = ecc->bytes - 1;
1319 erased_ecc_vec = bch8_vector;
1320 break;
1321 default:
1322 pr_err("invalid driver configuration\n");
1323 return -EINVAL;
1324 }
1325
1326 /* Initialize elm error vector to zero */
1327 memset(err_vec, 0, sizeof(err_vec));
1328
1329 for (i = 0; i < eccsteps ; i++) {
1330 eccflag = 0; /* initialize eccflag */
1331
1332 /*
1333 * Check any error reported,
1334 * In case of error, non zero ecc reported.
1335 */
1336 for (j = 0; j < actual_eccbytes; j++) {
1337 if (calc_ecc[j] != 0) {
1338 eccflag = 1; /* non zero ecc, error present */
1339 break;
1340 }
1341 }
1342
1343 if (eccflag == 1) {
1344 if (memcmp(calc_ecc, erased_ecc_vec,
1345 actual_eccbytes) == 0) {
1346 /*
1347 * calc_ecc[] matches pattern for ECC(all 0xff)
1348 * so this is definitely an erased-page
1349 */
1350 } else {
1351 buf = &data[info->nand.ecc.size * i];
1352 /*
1353 * count number of 0-bits in read_buf.
1354 * This check can be removed once a similar
1355 * check is introduced in generic NAND driver
1356 */
1357 bitflip_count = erased_sector_bitflips(
1358 buf, read_ecc, info);
1359 if (bitflip_count) {
1360 /*
1361 * number of 0-bits within ECC limits
1362 * So this may be an erased-page
1363 */
1364 stat += bitflip_count;
1365 } else {
1366 /*
1367 * Too many 0-bits. It may be a
1368 * - programmed-page, OR
1369 * - erased-page with many bit-flips
1370 * So this page requires check by ELM
1371 */
1372 err_vec[i].error_reported = true;
1373 is_error_reported = true;
1374 }
1375 }
1376 }
1377
1378 /* Update the ecc vector */
1379 calc_ecc += ecc->bytes;
1380 read_ecc += ecc->bytes;
1381 }
1382
1383 /* Check if any error reported */
1384 if (!is_error_reported)
1385 return 0;
1386
1387 /* Decode BCH error using ELM module */
1388 elm_decode_bch_error_page(info->elm_dev, ecc_vec, err_vec);
1389
1390 err = 0;
1391 for (i = 0; i < eccsteps; i++) {
1392 if (err_vec[i].error_uncorrectable) {
1393 pr_err("nand: uncorrectable bit-flips found\n");
1394 err = -EBADMSG;
1395 } else if (err_vec[i].error_reported) {
1396 for (j = 0; j < err_vec[i].error_count; j++) {
1397 switch (info->ecc_opt) {
1398 case OMAP_ECC_BCH4_CODE_HW:
1399 /* Add 4 bits to take care of padding */
1400 pos = err_vec[i].error_loc[j] +
1401 BCH4_BIT_PAD;
1402 break;
1403 case OMAP_ECC_BCH8_CODE_HW:
1404 pos = err_vec[i].error_loc[j];
1405 break;
1406 default:
1407 return -EINVAL;
1408 }
1409 error_max = (ecc->size + actual_eccbytes) * 8;
1410 /* Calculate bit position of error */
1411 bit_pos = pos % 8;
1412
1413 /* Calculate byte position of error */
1414 byte_pos = (error_max - pos - 1) / 8;
1415
1416 if (pos < error_max) {
1417 if (byte_pos < 512) {
1418 pr_debug("bitflip@dat[%d]=%x\n",
1419 byte_pos, data[byte_pos]);
1420 data[byte_pos] ^= 1 << bit_pos;
1421 } else {
1422 pr_debug("bitflip@oob[%d]=%x\n",
1423 (byte_pos - 512),
1424 spare_ecc[byte_pos - 512]);
1425 spare_ecc[byte_pos - 512] ^=
1426 1 << bit_pos;
1427 }
1428 } else {
1429 pr_err("invalid bit-flip @ %d:%d\n",
1430 byte_pos, bit_pos);
1431 err = -EBADMSG;
1432 }
1433 }
1434 }
1435
1436 /* Update number of correctable errors */
1437 stat += err_vec[i].error_count;
1438
1439 /* Update page data with sector size */
1440 data += ecc->size;
1441 spare_ecc += ecc->bytes;
1442 }
1443
1444 return (err) ? err : stat;
1445 }
1446
1447 /**
1448 * omap_write_page_bch - BCH ecc based write page function for entire page
1449 * @mtd: mtd info structure
1450 * @chip: nand chip info structure
1451 * @buf: data buffer
1452 * @oob_required: must write chip->oob_poi to OOB
1453 *
1454 * Custom write page method evolved to support multi sector writing in one shot
1455 */
1456 static int omap_write_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
1457 const uint8_t *buf, int oob_required)
1458 {
1459 int i;
1460 uint8_t *ecc_calc = chip->buffers->ecccalc;
1461 uint32_t *eccpos = chip->ecc.layout->eccpos;
1462
1463 /* Enable GPMC ecc engine */
1464 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1465
1466 /* Write data */
1467 chip->write_buf(mtd, buf, mtd->writesize);
1468
1469 /* Update ecc vector from GPMC result registers */
1470 chip->ecc.calculate(mtd, buf, &ecc_calc[0]);
1471
1472 for (i = 0; i < chip->ecc.total; i++)
1473 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1474
1475 /* Write ecc vector to OOB area */
1476 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1477 return 0;
1478 }
1479
1480 /**
1481 * omap_read_page_bch - BCH ecc based page read function for entire page
1482 * @mtd: mtd info structure
1483 * @chip: nand chip info structure
1484 * @buf: buffer to store read data
1485 * @oob_required: caller requires OOB data read to chip->oob_poi
1486 * @page: page number to read
1487 *
1488 * For BCH ecc scheme, GPMC used for syndrome calculation and ELM module
1489 * used for error correction.
1490 * Custom method evolved to support ELM error correction & multi sector
1491 * reading. On reading page data area is read along with OOB data with
1492 * ecc engine enabled. ecc vector updated after read of OOB data.
1493 * For non error pages ecc vector reported as zero.
1494 */
1495 static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
1496 uint8_t *buf, int oob_required, int page)
1497 {
1498 uint8_t *ecc_calc = chip->buffers->ecccalc;
1499 uint8_t *ecc_code = chip->buffers->ecccode;
1500 uint32_t *eccpos = chip->ecc.layout->eccpos;
1501 uint8_t *oob = &chip->oob_poi[eccpos[0]];
1502 uint32_t oob_pos = mtd->writesize + chip->ecc.layout->eccpos[0];
1503 int stat;
1504 unsigned int max_bitflips = 0;
1505
1506 /* Enable GPMC ecc engine */
1507 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1508
1509 /* Read data */
1510 chip->read_buf(mtd, buf, mtd->writesize);
1511
1512 /* Read oob bytes */
1513 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, -1);
1514 chip->read_buf(mtd, oob, chip->ecc.total);
1515
1516 /* Calculate ecc bytes */
1517 chip->ecc.calculate(mtd, buf, ecc_calc);
1518
1519 memcpy(ecc_code, &chip->oob_poi[eccpos[0]], chip->ecc.total);
1520
1521 stat = chip->ecc.correct(mtd, buf, ecc_code, ecc_calc);
1522
1523 if (stat < 0) {
1524 mtd->ecc_stats.failed++;
1525 } else {
1526 mtd->ecc_stats.corrected += stat;
1527 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1528 }
1529
1530 return max_bitflips;
1531 }
1532
1533 /**
1534 * is_elm_present - checks for presence of ELM module by scanning DT nodes
1535 * @omap_nand_info: NAND device structure containing platform data
1536 * @bch_type: 0x0=BCH4, 0x1=BCH8, 0x2=BCH16
1537 */
1538 static int is_elm_present(struct omap_nand_info *info,
1539 struct device_node *elm_node, enum bch_ecc bch_type)
1540 {
1541 struct platform_device *pdev;
1542 struct nand_ecc_ctrl *ecc = &info->nand.ecc;
1543 int err;
1544 /* check whether elm-id is passed via DT */
1545 if (!elm_node) {
1546 pr_err("nand: error: ELM DT node not found\n");
1547 return -ENODEV;
1548 }
1549 pdev = of_find_device_by_node(elm_node);
1550 /* check whether ELM device is registered */
1551 if (!pdev) {
1552 pr_err("nand: error: ELM device not found\n");
1553 return -ENODEV;
1554 }
1555 /* ELM module available, now configure it */
1556 info->elm_dev = &pdev->dev;
1557 err = elm_config(info->elm_dev, bch_type,
1558 (info->mtd.writesize / ecc->size), ecc->size, ecc->bytes);
1559
1560 return err;
1561 }
1562 #endif /* CONFIG_MTD_NAND_ECC_BCH */
1563
1564 static int omap_nand_probe(struct platform_device *pdev)
1565 {
1566 struct omap_nand_info *info;
1567 struct omap_nand_platform_data *pdata;
1568 struct mtd_info *mtd;
1569 struct nand_chip *nand_chip;
1570 struct nand_ecclayout *ecclayout;
1571 int err;
1572 int i;
1573 dma_cap_mask_t mask;
1574 unsigned sig;
1575 unsigned oob_index;
1576 struct resource *res;
1577 struct mtd_part_parser_data ppdata = {};
1578
1579 pdata = dev_get_platdata(&pdev->dev);
1580 if (pdata == NULL) {
1581 dev_err(&pdev->dev, "platform data missing\n");
1582 return -ENODEV;
1583 }
1584
1585 info = devm_kzalloc(&pdev->dev, sizeof(struct omap_nand_info),
1586 GFP_KERNEL);
1587 if (!info)
1588 return -ENOMEM;
1589
1590 platform_set_drvdata(pdev, info);
1591
1592 spin_lock_init(&info->controller.lock);
1593 init_waitqueue_head(&info->controller.wq);
1594
1595 info->pdev = pdev;
1596 info->gpmc_cs = pdata->cs;
1597 info->reg = pdata->reg;
1598 info->of_node = pdata->of_node;
1599 info->ecc_opt = pdata->ecc_opt;
1600 mtd = &info->mtd;
1601 mtd->priv = &info->nand;
1602 mtd->name = dev_name(&pdev->dev);
1603 mtd->owner = THIS_MODULE;
1604 nand_chip = &info->nand;
1605 nand_chip->ecc.priv = NULL;
1606 nand_chip->options |= NAND_SKIP_BBTSCAN;
1607
1608 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1609 nand_chip->IO_ADDR_R = devm_ioremap_resource(&pdev->dev, res);
1610 if (IS_ERR(nand_chip->IO_ADDR_R))
1611 return PTR_ERR(nand_chip->IO_ADDR_R);
1612
1613 info->phys_base = res->start;
1614
1615 nand_chip->controller = &info->controller;
1616
1617 nand_chip->IO_ADDR_W = nand_chip->IO_ADDR_R;
1618 nand_chip->cmd_ctrl = omap_hwcontrol;
1619
1620 /*
1621 * If RDY/BSY line is connected to OMAP then use the omap ready
1622 * function and the generic nand_wait function which reads the status
1623 * register after monitoring the RDY/BSY line. Otherwise use a standard
1624 * chip delay which is slightly more than tR (AC Timing) of the NAND
1625 * device and read status register until you get a failure or success
1626 */
1627 if (pdata->dev_ready) {
1628 nand_chip->dev_ready = omap_dev_ready;
1629 nand_chip->chip_delay = 0;
1630 } else {
1631 nand_chip->waitfunc = omap_wait;
1632 nand_chip->chip_delay = 50;
1633 }
1634
1635 /* scan NAND device connected to chip controller */
1636 nand_chip->options |= pdata->devsize & NAND_BUSWIDTH_16;
1637 if (nand_scan_ident(mtd, 1, NULL)) {
1638 pr_err("nand device scan failed, may be bus-width mismatch\n");
1639 err = -ENXIO;
1640 goto return_error;
1641 }
1642
1643 /* check for small page devices */
1644 if ((mtd->oobsize < 64) && (pdata->ecc_opt != OMAP_ECC_HAM1_CODE_HW)) {
1645 pr_err("small page devices are not supported\n");
1646 err = -EINVAL;
1647 goto return_error;
1648 }
1649
1650 /* re-populate low-level callbacks based on xfer modes */
1651 switch (pdata->xfer_type) {
1652 case NAND_OMAP_PREFETCH_POLLED:
1653 nand_chip->read_buf = omap_read_buf_pref;
1654 nand_chip->write_buf = omap_write_buf_pref;
1655 break;
1656
1657 case NAND_OMAP_POLLED:
1658 /* Use nand_base defaults for {read,write}_buf */
1659 break;
1660
1661 case NAND_OMAP_PREFETCH_DMA:
1662 dma_cap_zero(mask);
1663 dma_cap_set(DMA_SLAVE, mask);
1664 sig = OMAP24XX_DMA_GPMC;
1665 info->dma = dma_request_channel(mask, omap_dma_filter_fn, &sig);
1666 if (!info->dma) {
1667 dev_err(&pdev->dev, "DMA engine request failed\n");
1668 err = -ENXIO;
1669 goto return_error;
1670 } else {
1671 struct dma_slave_config cfg;
1672
1673 memset(&cfg, 0, sizeof(cfg));
1674 cfg.src_addr = info->phys_base;
1675 cfg.dst_addr = info->phys_base;
1676 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1677 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1678 cfg.src_maxburst = 16;
1679 cfg.dst_maxburst = 16;
1680 err = dmaengine_slave_config(info->dma, &cfg);
1681 if (err) {
1682 dev_err(&pdev->dev, "DMA engine slave config failed: %d\n",
1683 err);
1684 goto return_error;
1685 }
1686 nand_chip->read_buf = omap_read_buf_dma_pref;
1687 nand_chip->write_buf = omap_write_buf_dma_pref;
1688 }
1689 break;
1690
1691 case NAND_OMAP_PREFETCH_IRQ:
1692 info->gpmc_irq_fifo = platform_get_irq(pdev, 0);
1693 if (info->gpmc_irq_fifo <= 0) {
1694 dev_err(&pdev->dev, "error getting fifo irq\n");
1695 err = -ENODEV;
1696 goto return_error;
1697 }
1698 err = devm_request_irq(&pdev->dev, info->gpmc_irq_fifo,
1699 omap_nand_irq, IRQF_SHARED,
1700 "gpmc-nand-fifo", info);
1701 if (err) {
1702 dev_err(&pdev->dev, "requesting irq(%d) error:%d",
1703 info->gpmc_irq_fifo, err);
1704 info->gpmc_irq_fifo = 0;
1705 goto return_error;
1706 }
1707
1708 info->gpmc_irq_count = platform_get_irq(pdev, 1);
1709 if (info->gpmc_irq_count <= 0) {
1710 dev_err(&pdev->dev, "error getting count irq\n");
1711 err = -ENODEV;
1712 goto return_error;
1713 }
1714 err = devm_request_irq(&pdev->dev, info->gpmc_irq_count,
1715 omap_nand_irq, IRQF_SHARED,
1716 "gpmc-nand-count", info);
1717 if (err) {
1718 dev_err(&pdev->dev, "requesting irq(%d) error:%d",
1719 info->gpmc_irq_count, err);
1720 info->gpmc_irq_count = 0;
1721 goto return_error;
1722 }
1723
1724 nand_chip->read_buf = omap_read_buf_irq_pref;
1725 nand_chip->write_buf = omap_write_buf_irq_pref;
1726
1727 break;
1728
1729 default:
1730 dev_err(&pdev->dev,
1731 "xfer_type(%d) not supported!\n", pdata->xfer_type);
1732 err = -EINVAL;
1733 goto return_error;
1734 }
1735
1736 /* populate MTD interface based on ECC scheme */
1737 nand_chip->ecc.layout = &omap_oobinfo;
1738 ecclayout = &omap_oobinfo;
1739 switch (info->ecc_opt) {
1740 case OMAP_ECC_HAM1_CODE_HW:
1741 pr_info("nand: using OMAP_ECC_HAM1_CODE_HW\n");
1742 nand_chip->ecc.mode = NAND_ECC_HW;
1743 nand_chip->ecc.bytes = 3;
1744 nand_chip->ecc.size = 512;
1745 nand_chip->ecc.strength = 1;
1746 nand_chip->ecc.calculate = omap_calculate_ecc;
1747 nand_chip->ecc.hwctl = omap_enable_hwecc;
1748 nand_chip->ecc.correct = omap_correct_data;
1749 /* define ECC layout */
1750 ecclayout->eccbytes = nand_chip->ecc.bytes *
1751 (mtd->writesize /
1752 nand_chip->ecc.size);
1753 if (nand_chip->options & NAND_BUSWIDTH_16)
1754 oob_index = BADBLOCK_MARKER_LENGTH;
1755 else
1756 oob_index = 1;
1757 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++)
1758 ecclayout->eccpos[i] = oob_index;
1759 /* no reserved-marker in ecclayout for this ecc-scheme */
1760 ecclayout->oobfree->offset =
1761 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
1762 break;
1763
1764 case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1765 #ifdef CONFIG_MTD_NAND_ECC_BCH
1766 pr_info("nand: using OMAP_ECC_BCH4_CODE_HW_DETECTION_SW\n");
1767 nand_chip->ecc.mode = NAND_ECC_HW;
1768 nand_chip->ecc.size = 512;
1769 nand_chip->ecc.bytes = 7;
1770 nand_chip->ecc.strength = 4;
1771 nand_chip->ecc.hwctl = omap_enable_hwecc_bch;
1772 nand_chip->ecc.correct = nand_bch_correct_data;
1773 nand_chip->ecc.calculate = omap_calculate_ecc_bch;
1774 /* define ECC layout */
1775 ecclayout->eccbytes = nand_chip->ecc.bytes *
1776 (mtd->writesize /
1777 nand_chip->ecc.size);
1778 oob_index = BADBLOCK_MARKER_LENGTH;
1779 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++) {
1780 ecclayout->eccpos[i] = oob_index;
1781 if (((i + 1) % nand_chip->ecc.bytes) == 0)
1782 oob_index++;
1783 }
1784 /* include reserved-marker in ecclayout->oobfree calculation */
1785 ecclayout->oobfree->offset = 1 +
1786 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
1787 /* software bch library is used for locating errors */
1788 nand_chip->ecc.priv = nand_bch_init(mtd,
1789 nand_chip->ecc.size,
1790 nand_chip->ecc.bytes,
1791 &nand_chip->ecc.layout);
1792 if (!nand_chip->ecc.priv) {
1793 pr_err("nand: error: unable to use s/w BCH library\n");
1794 err = -EINVAL;
1795 }
1796 break;
1797 #else
1798 pr_err("nand: error: CONFIG_MTD_NAND_ECC_BCH not enabled\n");
1799 err = -EINVAL;
1800 goto return_error;
1801 #endif
1802
1803 case OMAP_ECC_BCH4_CODE_HW:
1804 #ifdef CONFIG_MTD_NAND_OMAP_BCH
1805 pr_info("nand: using OMAP_ECC_BCH4_CODE_HW ECC scheme\n");
1806 nand_chip->ecc.mode = NAND_ECC_HW;
1807 nand_chip->ecc.size = 512;
1808 /* 14th bit is kept reserved for ROM-code compatibility */
1809 nand_chip->ecc.bytes = 7 + 1;
1810 nand_chip->ecc.strength = 4;
1811 nand_chip->ecc.hwctl = omap_enable_hwecc_bch;
1812 nand_chip->ecc.correct = omap_elm_correct_data;
1813 nand_chip->ecc.calculate = omap_calculate_ecc_bch;
1814 nand_chip->ecc.read_page = omap_read_page_bch;
1815 nand_chip->ecc.write_page = omap_write_page_bch;
1816 /* define ECC layout */
1817 ecclayout->eccbytes = nand_chip->ecc.bytes *
1818 (mtd->writesize /
1819 nand_chip->ecc.size);
1820 oob_index = BADBLOCK_MARKER_LENGTH;
1821 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++)
1822 ecclayout->eccpos[i] = oob_index;
1823 /* reserved marker already included in ecclayout->eccbytes */
1824 ecclayout->oobfree->offset =
1825 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
1826 /* This ECC scheme requires ELM H/W block */
1827 if (is_elm_present(info, pdata->elm_of_node, BCH4_ECC) < 0) {
1828 pr_err("nand: error: could not initialize ELM\n");
1829 err = -ENODEV;
1830 goto return_error;
1831 }
1832 break;
1833 #else
1834 pr_err("nand: error: CONFIG_MTD_NAND_OMAP_BCH not enabled\n");
1835 err = -EINVAL;
1836 goto return_error;
1837 #endif
1838
1839 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1840 #ifdef CONFIG_MTD_NAND_ECC_BCH
1841 pr_info("nand: using OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n");
1842 nand_chip->ecc.mode = NAND_ECC_HW;
1843 nand_chip->ecc.size = 512;
1844 nand_chip->ecc.bytes = 13;
1845 nand_chip->ecc.strength = 8;
1846 nand_chip->ecc.hwctl = omap_enable_hwecc_bch;
1847 nand_chip->ecc.correct = nand_bch_correct_data;
1848 nand_chip->ecc.calculate = omap_calculate_ecc_bch;
1849 /* define ECC layout */
1850 ecclayout->eccbytes = nand_chip->ecc.bytes *
1851 (mtd->writesize /
1852 nand_chip->ecc.size);
1853 oob_index = BADBLOCK_MARKER_LENGTH;
1854 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++) {
1855 ecclayout->eccpos[i] = oob_index;
1856 if (((i + 1) % nand_chip->ecc.bytes) == 0)
1857 oob_index++;
1858 }
1859 /* include reserved-marker in ecclayout->oobfree calculation */
1860 ecclayout->oobfree->offset = 1 +
1861 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
1862 /* software bch library is used for locating errors */
1863 nand_chip->ecc.priv = nand_bch_init(mtd,
1864 nand_chip->ecc.size,
1865 nand_chip->ecc.bytes,
1866 &nand_chip->ecc.layout);
1867 if (!nand_chip->ecc.priv) {
1868 pr_err("nand: error: unable to use s/w BCH library\n");
1869 err = -EINVAL;
1870 goto return_error;
1871 }
1872 break;
1873 #else
1874 pr_err("nand: error: CONFIG_MTD_NAND_ECC_BCH not enabled\n");
1875 err = -EINVAL;
1876 goto return_error;
1877 #endif
1878
1879 case OMAP_ECC_BCH8_CODE_HW:
1880 #ifdef CONFIG_MTD_NAND_OMAP_BCH
1881 pr_info("nand: using OMAP_ECC_BCH8_CODE_HW ECC scheme\n");
1882 nand_chip->ecc.mode = NAND_ECC_HW;
1883 nand_chip->ecc.size = 512;
1884 /* 14th bit is kept reserved for ROM-code compatibility */
1885 nand_chip->ecc.bytes = 13 + 1;
1886 nand_chip->ecc.strength = 8;
1887 nand_chip->ecc.hwctl = omap_enable_hwecc_bch;
1888 nand_chip->ecc.correct = omap_elm_correct_data;
1889 nand_chip->ecc.calculate = omap_calculate_ecc_bch;
1890 nand_chip->ecc.read_page = omap_read_page_bch;
1891 nand_chip->ecc.write_page = omap_write_page_bch;
1892 /* This ECC scheme requires ELM H/W block */
1893 err = is_elm_present(info, pdata->elm_of_node, BCH8_ECC);
1894 if (err < 0) {
1895 pr_err("nand: error: could not initialize ELM\n");
1896 goto return_error;
1897 }
1898 /* define ECC layout */
1899 ecclayout->eccbytes = nand_chip->ecc.bytes *
1900 (mtd->writesize /
1901 nand_chip->ecc.size);
1902 oob_index = BADBLOCK_MARKER_LENGTH;
1903 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++)
1904 ecclayout->eccpos[i] = oob_index;
1905 /* reserved marker already included in ecclayout->eccbytes */
1906 ecclayout->oobfree->offset =
1907 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
1908 break;
1909 #else
1910 pr_err("nand: error: CONFIG_MTD_NAND_OMAP_BCH not enabled\n");
1911 err = -EINVAL;
1912 goto return_error;
1913 #endif
1914
1915 default:
1916 pr_err("nand: error: invalid or unsupported ECC scheme\n");
1917 err = -EINVAL;
1918 goto return_error;
1919 }
1920
1921 /* all OOB bytes from oobfree->offset till end off OOB are free */
1922 ecclayout->oobfree->length = mtd->oobsize - ecclayout->oobfree->offset;
1923 /* check if NAND device's OOB is enough to store ECC signatures */
1924 if (mtd->oobsize < (ecclayout->eccbytes + BADBLOCK_MARKER_LENGTH)) {
1925 pr_err("not enough OOB bytes required = %d, available=%d\n",
1926 ecclayout->eccbytes, mtd->oobsize);
1927 err = -EINVAL;
1928 goto return_error;
1929 }
1930
1931 /* second phase scan */
1932 if (nand_scan_tail(mtd)) {
1933 err = -ENXIO;
1934 goto return_error;
1935 }
1936
1937 ppdata.of_node = pdata->of_node;
1938 mtd_device_parse_register(mtd, NULL, &ppdata, pdata->parts,
1939 pdata->nr_parts);
1940
1941 platform_set_drvdata(pdev, mtd);
1942
1943 return 0;
1944
1945 return_error:
1946 if (info->dma)
1947 dma_release_channel(info->dma);
1948 if (nand_chip->ecc.priv) {
1949 nand_bch_free(nand_chip->ecc.priv);
1950 nand_chip->ecc.priv = NULL;
1951 }
1952 return err;
1953 }
1954
1955 static int omap_nand_remove(struct platform_device *pdev)
1956 {
1957 struct mtd_info *mtd = platform_get_drvdata(pdev);
1958 struct nand_chip *nand_chip = mtd->priv;
1959 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1960 mtd);
1961 if (nand_chip->ecc.priv) {
1962 nand_bch_free(nand_chip->ecc.priv);
1963 nand_chip->ecc.priv = NULL;
1964 }
1965 if (info->dma)
1966 dma_release_channel(info->dma);
1967 nand_release(mtd);
1968 return 0;
1969 }
1970
1971 static struct platform_driver omap_nand_driver = {
1972 .probe = omap_nand_probe,
1973 .remove = omap_nand_remove,
1974 .driver = {
1975 .name = DRIVER_NAME,
1976 .owner = THIS_MODULE,
1977 },
1978 };
1979
1980 module_platform_driver(omap_nand_driver);
1981
1982 MODULE_ALIAS("platform:" DRIVER_NAME);
1983 MODULE_LICENSE("GPL");
1984 MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards");
Linux with added FPC-III support