drivers/spi/spi-sirf.c

   1 /*
   2  * SPI bus driver for CSR SiRFprimaII
   3  *
   4  * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
   5  *
   6  * Licensed under GPLv2 or later.
   7  */
   8
   9 #include <linux/module.h>
  10 #include <linux/kernel.h>
  11 #include <linux/slab.h>
  12 #include <linux/clk.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/io.h>
  15 #include <linux/of.h>
  16 #include <linux/bitops.h>
  17 #include <linux/err.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/of_gpio.h>
  20 #include <linux/spi/spi.h>
  21 #include <linux/spi/spi_bitbang.h>
  22 #include <linux/dmaengine.h>
  23 #include <linux/dma-direction.h>
  24 #include <linux/dma-mapping.h>
  25
  26 #define DRIVER_NAME "sirfsoc_spi"
  27
  28 #define SIRFSOC_SPI_CTRL                0x0000
  29 #define SIRFSOC_SPI_CMD                 0x0004
  30 #define SIRFSOC_SPI_TX_RX_EN            0x0008
  31 #define SIRFSOC_SPI_INT_EN              0x000C
  32 #define SIRFSOC_SPI_INT_STATUS          0x0010
  33 #define SIRFSOC_SPI_TX_DMA_IO_CTRL      0x0100
  34 #define SIRFSOC_SPI_TX_DMA_IO_LEN       0x0104
  35 #define SIRFSOC_SPI_TXFIFO_CTRL         0x0108
  36 #define SIRFSOC_SPI_TXFIFO_LEVEL_CHK    0x010C
  37 #define SIRFSOC_SPI_TXFIFO_OP           0x0110
  38 #define SIRFSOC_SPI_TXFIFO_STATUS       0x0114
  39 #define SIRFSOC_SPI_TXFIFO_DATA         0x0118
  40 #define SIRFSOC_SPI_RX_DMA_IO_CTRL      0x0120
  41 #define SIRFSOC_SPI_RX_DMA_IO_LEN       0x0124
  42 #define SIRFSOC_SPI_RXFIFO_CTRL         0x0128
  43 #define SIRFSOC_SPI_RXFIFO_LEVEL_CHK    0x012C
  44 #define SIRFSOC_SPI_RXFIFO_OP           0x0130
  45 #define SIRFSOC_SPI_RXFIFO_STATUS       0x0134
  46 #define SIRFSOC_SPI_RXFIFO_DATA         0x0138
  47 #define SIRFSOC_SPI_DUMMY_DELAY_CTL     0x0144
  48
  49 /* SPI CTRL register defines */
  50 #define SIRFSOC_SPI_SLV_MODE            BIT(16)
  51 #define SIRFSOC_SPI_CMD_MODE            BIT(17)
  52 #define SIRFSOC_SPI_CS_IO_OUT           BIT(18)
  53 #define SIRFSOC_SPI_CS_IO_MODE          BIT(19)
  54 #define SIRFSOC_SPI_CLK_IDLE_STAT       BIT(20)
  55 #define SIRFSOC_SPI_CS_IDLE_STAT        BIT(21)
  56 #define SIRFSOC_SPI_TRAN_MSB            BIT(22)
  57 #define SIRFSOC_SPI_DRV_POS_EDGE        BIT(23)
  58 #define SIRFSOC_SPI_CS_HOLD_TIME        BIT(24)
  59 #define SIRFSOC_SPI_CLK_SAMPLE_MODE     BIT(25)
  60 #define SIRFSOC_SPI_TRAN_DAT_FORMAT_8   (0 << 26)
  61 #define SIRFSOC_SPI_TRAN_DAT_FORMAT_12  (1 << 26)
  62 #define SIRFSOC_SPI_TRAN_DAT_FORMAT_16  (2 << 26)
  63 #define SIRFSOC_SPI_TRAN_DAT_FORMAT_32  (3 << 26)
  64 #define SIRFSOC_SPI_CMD_BYTE_NUM(x)             ((x & 3) << 28)
  65 #define SIRFSOC_SPI_ENA_AUTO_CLR                BIT(30)
  66 #define SIRFSOC_SPI_MUL_DAT_MODE                BIT(31)
  67
  68 /* Interrupt Enable */
  69 #define SIRFSOC_SPI_RX_DONE_INT_EN              BIT(0)
  70 #define SIRFSOC_SPI_TX_DONE_INT_EN              BIT(1)
  71 #define SIRFSOC_SPI_RX_OFLOW_INT_EN             BIT(2)
  72 #define SIRFSOC_SPI_TX_UFLOW_INT_EN             BIT(3)
  73 #define SIRFSOC_SPI_RX_IO_DMA_INT_EN    BIT(4)
  74 #define SIRFSOC_SPI_TX_IO_DMA_INT_EN    BIT(5)
  75 #define SIRFSOC_SPI_RXFIFO_FULL_INT_EN  BIT(6)
  76 #define SIRFSOC_SPI_TXFIFO_EMPTY_INT_EN BIT(7)
  77 #define SIRFSOC_SPI_RXFIFO_THD_INT_EN   BIT(8)
  78 #define SIRFSOC_SPI_TXFIFO_THD_INT_EN   BIT(9)
  79 #define SIRFSOC_SPI_FRM_END_INT_EN      BIT(10)
  80
  81 #define SIRFSOC_SPI_INT_MASK_ALL                0x1FFF
  82
  83 /* Interrupt status */
  84 #define SIRFSOC_SPI_RX_DONE             BIT(0)
  85 #define SIRFSOC_SPI_TX_DONE             BIT(1)
  86 #define SIRFSOC_SPI_RX_OFLOW            BIT(2)
  87 #define SIRFSOC_SPI_TX_UFLOW            BIT(3)
  88 #define SIRFSOC_SPI_RX_FIFO_FULL        BIT(6)
  89 #define SIRFSOC_SPI_TXFIFO_EMPTY        BIT(7)
  90 #define SIRFSOC_SPI_RXFIFO_THD_REACH    BIT(8)
  91 #define SIRFSOC_SPI_TXFIFO_THD_REACH    BIT(9)
  92 #define SIRFSOC_SPI_FRM_END             BIT(10)
  93
  94 /* TX RX enable */
  95 #define SIRFSOC_SPI_RX_EN               BIT(0)
  96 #define SIRFSOC_SPI_TX_EN               BIT(1)
  97 #define SIRFSOC_SPI_CMD_TX_EN           BIT(2)
  98
  99 #define SIRFSOC_SPI_IO_MODE_SEL         BIT(0)
 100 #define SIRFSOC_SPI_RX_DMA_FLUSH        BIT(2)
 101
 102 /* FIFO OPs */
 103 #define SIRFSOC_SPI_FIFO_RESET          BIT(0)
 104 #define SIRFSOC_SPI_FIFO_START          BIT(1)
 105
 106 /* FIFO CTRL */
 107 #define SIRFSOC_SPI_FIFO_WIDTH_BYTE     (0 << 0)
 108 #define SIRFSOC_SPI_FIFO_WIDTH_WORD     (1 << 0)
 109 #define SIRFSOC_SPI_FIFO_WIDTH_DWORD    (2 << 0)
 110
 111 /* FIFO Status */
 112 #define SIRFSOC_SPI_FIFO_LEVEL_MASK     0xFF
 113 #define SIRFSOC_SPI_FIFO_FULL           BIT(8)
 114 #define SIRFSOC_SPI_FIFO_EMPTY          BIT(9)
 115
 116 /* 256 bytes rx/tx FIFO */
 117 #define SIRFSOC_SPI_FIFO_SIZE           256
 118 #define SIRFSOC_SPI_DAT_FRM_LEN_MAX     (64 * 1024)
 119
 120 #define SIRFSOC_SPI_FIFO_SC(x)          ((x) & 0x3F)
 121 #define SIRFSOC_SPI_FIFO_LC(x)          (((x) & 0x3F) << 10)
 122 #define SIRFSOC_SPI_FIFO_HC(x)          (((x) & 0x3F) << 20)
 123 #define SIRFSOC_SPI_FIFO_THD(x)         (((x) & 0xFF) << 2)
 124
 125 /*
 126  * only if the rx/tx buffer and transfer size are 4-bytes aligned, we use dma
 127  * due to the limitation of dma controller
 128  */
 129
 130 #define ALIGNED(x) (!((u32)x & 0x3))
 131 #define IS_DMA_VALID(x) (x && ALIGNED(x->tx_buf) && ALIGNED(x->rx_buf) && \
 132         ALIGNED(x->len) && (x->len < 2 * PAGE_SIZE))
 133
 134 #define SIRFSOC_MAX_CMD_BYTES   4
 135
 136 struct sirfsoc_spi {
 137         struct spi_bitbang bitbang;
 138         struct completion rx_done;
 139         struct completion tx_done;
 140
 141         void __iomem *base;
 142         u32 ctrl_freq;  /* SPI controller clock speed */
 143         struct clk *clk;
 144
 145         /* rx & tx bufs from the spi_transfer */
 146         const void *tx;
 147         void *rx;
 148
 149         /* place received word into rx buffer */
 150         void (*rx_word) (struct sirfsoc_spi *);
 151         /* get word from tx buffer for sending */
 152         void (*tx_word) (struct sirfsoc_spi *);
 153
 154         /* number of words left to be tranmitted/received */
 155         unsigned int left_tx_word;
 156         unsigned int left_rx_word;
 157
 158         /* rx & tx DMA channels */
 159         struct dma_chan *rx_chan;
 160         struct dma_chan *tx_chan;
 161         dma_addr_t src_start;
 162         dma_addr_t dst_start;
 163         void *dummypage;
 164         int word_width; /* in bytes */
 165
 166         /*
 167          * if tx size is not more than 4 and rx size is NULL, use
 168          * command model
 169          */
 170         bool    tx_by_cmd;
 171
 172         int chipselect[0];
 173 };
 174
 175 static void spi_sirfsoc_rx_word_u8(struct sirfsoc_spi *sspi)
 176 {
 177         u32 data;
 178         u8 *rx = sspi->rx;
 179
 180         data = readl(sspi->base + SIRFSOC_SPI_RXFIFO_DATA);
 181
 182         if (rx) {
 183                 *rx++ = (u8) data;
 184                 sspi->rx = rx;
 185         }
 186
 187         sspi->left_rx_word--;
 188 }
 189
 190 static void spi_sirfsoc_tx_word_u8(struct sirfsoc_spi *sspi)
 191 {
 192         u32 data = 0;
 193         const u8 *tx = sspi->tx;
 194
 195         if (tx) {
 196                 data = *tx++;
 197                 sspi->tx = tx;
 198         }
 199
 200         writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA);
 201         sspi->left_tx_word--;
 202 }
 203
 204 static void spi_sirfsoc_rx_word_u16(struct sirfsoc_spi *sspi)
 205 {
 206         u32 data;
 207         u16 *rx = sspi->rx;
 208
 209         data = readl(sspi->base + SIRFSOC_SPI_RXFIFO_DATA);
 210
 211         if (rx) {
 212                 *rx++ = (u16) data;
 213                 sspi->rx = rx;
 214         }
 215
 216         sspi->left_rx_word--;
 217 }
 218
 219 static void spi_sirfsoc_tx_word_u16(struct sirfsoc_spi *sspi)
 220 {
 221         u32 data = 0;
 222         const u16 *tx = sspi->tx;
 223
 224         if (tx) {
 225                 data = *tx++;
 226                 sspi->tx = tx;
 227         }
 228
 229         writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA);
 230         sspi->left_tx_word--;
 231 }
 232
 233 static void spi_sirfsoc_rx_word_u32(struct sirfsoc_spi *sspi)
 234 {
 235         u32 data;
 236         u32 *rx = sspi->rx;
 237
 238         data = readl(sspi->base + SIRFSOC_SPI_RXFIFO_DATA);
 239
 240         if (rx) {
 241                 *rx++ = (u32) data;
 242                 sspi->rx = rx;
 243         }
 244
 245         sspi->left_rx_word--;
 246
 247 }
 248
 249 static void spi_sirfsoc_tx_word_u32(struct sirfsoc_spi *sspi)
 250 {
 251         u32 data = 0;
 252         const u32 *tx = sspi->tx;
 253
 254         if (tx) {
 255                 data = *tx++;
 256                 sspi->tx = tx;
 257         }
 258
 259         writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA);
 260         sspi->left_tx_word--;
 261 }
 262
 263 static irqreturn_t spi_sirfsoc_irq(int irq, void *dev_id)
 264 {
 265         struct sirfsoc_spi *sspi = dev_id;
 266         u32 spi_stat = readl(sspi->base + SIRFSOC_SPI_INT_STATUS);
 267
 268         writel(spi_stat, sspi->base + SIRFSOC_SPI_INT_STATUS);
 269
 270         if (sspi->tx_by_cmd && (spi_stat & SIRFSOC_SPI_FRM_END)) {
 271                 complete(&sspi->tx_done);
 272                 writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN);
 273                 return IRQ_HANDLED;
 274         }
 275
 276         /* Error Conditions */
 277         if (spi_stat & SIRFSOC_SPI_RX_OFLOW ||
 278                         spi_stat & SIRFSOC_SPI_TX_UFLOW) {
 279                 complete(&sspi->rx_done);
 280                 writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN);
 281         }
 282
 283         if (spi_stat & (SIRFSOC_SPI_FRM_END
 284                         | SIRFSOC_SPI_RXFIFO_THD_REACH))
 285                 while (!((readl(sspi->base + SIRFSOC_SPI_RXFIFO_STATUS)
 286                                 & SIRFSOC_SPI_FIFO_EMPTY)) &&
 287                                 sspi->left_rx_word)
 288                         sspi->rx_word(sspi);
 289
 290         if (spi_stat & (SIRFSOC_SPI_FIFO_EMPTY
 291                         | SIRFSOC_SPI_TXFIFO_THD_REACH))
 292                 while (!((readl(sspi->base + SIRFSOC_SPI_TXFIFO_STATUS)
 293                                 & SIRFSOC_SPI_FIFO_FULL)) &&
 294                                 sspi->left_tx_word)
 295                         sspi->tx_word(sspi);
 296
 297         /* Received all words */
 298         if ((sspi->left_rx_word == 0) && (sspi->left_tx_word == 0)) {
 299                 complete(&sspi->rx_done);
 300                 writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN);
 301         }
 302         return IRQ_HANDLED;
 303 }
 304
 305 static void spi_sirfsoc_dma_fini_callback(void *data)
 306 {
 307         struct completion *dma_complete = data;
 308
 309         complete(dma_complete);
 310 }
 311
 312 static int spi_sirfsoc_transfer(struct spi_device *spi, struct spi_transfer *t)
 313 {
 314         struct sirfsoc_spi *sspi;
 315         int timeout = t->len * 10;
 316         sspi = spi_master_get_devdata(spi->master);
 317
 318         sspi->tx = t->tx_buf ? t->tx_buf : sspi->dummypage;
 319         sspi->rx = t->rx_buf ? t->rx_buf : sspi->dummypage;
 320         sspi->left_tx_word = sspi->left_rx_word = t->len / sspi->word_width;
 321         reinit_completion(&sspi->rx_done);
 322         reinit_completion(&sspi->tx_done);
 323
 324         writel(SIRFSOC_SPI_INT_MASK_ALL, sspi->base + SIRFSOC_SPI_INT_STATUS);
 325
 326         /*
 327          * fill tx_buf into command register and wait for its completion
 328          */
 329         if (sspi->tx_by_cmd) {
 330                 u32 cmd;
 331                 memcpy(&cmd, sspi->tx, t->len);
 332
 333                 if (sspi->word_width == 1 && !(spi->mode & SPI_LSB_FIRST))
 334                         cmd = cpu_to_be32(cmd) >>
 335                                 ((SIRFSOC_MAX_CMD_BYTES - t->len) * 8);
 336                 if (sspi->word_width == 2 && t->len == 4 &&
 337                                 (!(spi->mode & SPI_LSB_FIRST)))
 338                         cmd = ((cmd & 0xffff) << 16) | (cmd >> 16);
 339
 340                 writel(cmd, sspi->base + SIRFSOC_SPI_CMD);
 341                 writel(SIRFSOC_SPI_FRM_END_INT_EN,
 342                         sspi->base + SIRFSOC_SPI_INT_EN);
 343                 writel(SIRFSOC_SPI_CMD_TX_EN,
 344                         sspi->base + SIRFSOC_SPI_TX_RX_EN);
 345
 346                 if (wait_for_completion_timeout(&sspi->tx_done, timeout) == 0) {
 347                         dev_err(&spi->dev, "transfer timeout\n");
 348                         return 0;
 349                 }
 350
 351                 return t->len;
 352         }
 353
 354         if (sspi->left_tx_word == 1) {
 355                 writel(readl(sspi->base + SIRFSOC_SPI_CTRL) |
 356                         SIRFSOC_SPI_ENA_AUTO_CLR,
 357                         sspi->base + SIRFSOC_SPI_CTRL);
 358                 writel(0, sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN);
 359                 writel(0, sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN);
 360         } else if ((sspi->left_tx_word > 1) && (sspi->left_tx_word <
 361                                 SIRFSOC_SPI_DAT_FRM_LEN_MAX)) {
 362                 writel(readl(sspi->base + SIRFSOC_SPI_CTRL) |
 363                                 SIRFSOC_SPI_MUL_DAT_MODE |
 364                                 SIRFSOC_SPI_ENA_AUTO_CLR,
 365                         sspi->base + SIRFSOC_SPI_CTRL);
 366                 writel(sspi->left_tx_word - 1,
 367                                 sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN);
 368                 writel(sspi->left_tx_word - 1,
 369                                 sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN);
 370         } else {
 371                 writel(readl(sspi->base + SIRFSOC_SPI_CTRL),
 372                         sspi->base + SIRFSOC_SPI_CTRL);
 373                 writel(0, sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN);
 374                 writel(0, sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN);
 375         }
 376
 377         writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
 378         writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
 379         writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
 380         writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
 381
 382         if (IS_DMA_VALID(t)) {
 383                 struct dma_async_tx_descriptor *rx_desc, *tx_desc;
 384
 385                 sspi->dst_start = dma_map_single(&spi->dev, sspi->rx, t->len, DMA_FROM_DEVICE);
 386                 rx_desc = dmaengine_prep_slave_single(sspi->rx_chan,
 387                         sspi->dst_start, t->len, DMA_DEV_TO_MEM,
 388                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 389                 rx_desc->callback = spi_sirfsoc_dma_fini_callback;
 390                 rx_desc->callback_param = &sspi->rx_done;
 391
 392                 sspi->src_start = dma_map_single(&spi->dev, (void *)sspi->tx, t->len, DMA_TO_DEVICE);
 393                 tx_desc = dmaengine_prep_slave_single(sspi->tx_chan,
 394                         sspi->src_start, t->len, DMA_MEM_TO_DEV,
 395                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 396                 tx_desc->callback = spi_sirfsoc_dma_fini_callback;
 397                 tx_desc->callback_param = &sspi->tx_done;
 398
 399                 dmaengine_submit(tx_desc);
 400                 dmaengine_submit(rx_desc);
 401                 dma_async_issue_pending(sspi->tx_chan);
 402                 dma_async_issue_pending(sspi->rx_chan);
 403         } else {
 404                 /* Send the first word to trigger the whole tx/rx process */
 405                 sspi->tx_word(sspi);
 406
 407                 writel(SIRFSOC_SPI_RX_OFLOW_INT_EN | SIRFSOC_SPI_TX_UFLOW_INT_EN |
 408                         SIRFSOC_SPI_RXFIFO_THD_INT_EN | SIRFSOC_SPI_TXFIFO_THD_INT_EN |
 409                         SIRFSOC_SPI_FRM_END_INT_EN | SIRFSOC_SPI_RXFIFO_FULL_INT_EN |
 410                         SIRFSOC_SPI_TXFIFO_EMPTY_INT_EN, sspi->base + SIRFSOC_SPI_INT_EN);
 411         }
 412
 413         writel(SIRFSOC_SPI_RX_EN | SIRFSOC_SPI_TX_EN, sspi->base + SIRFSOC_SPI_TX_RX_EN);
 414
 415         if (!IS_DMA_VALID(t)) { /* for PIO */
 416                 if (wait_for_completion_timeout(&sspi->rx_done, timeout) == 0)
 417                         dev_err(&spi->dev, "transfer timeout\n");
 418         } else if (wait_for_completion_timeout(&sspi->rx_done, timeout) == 0) {
 419                 dev_err(&spi->dev, "transfer timeout\n");
 420                 dmaengine_terminate_all(sspi->rx_chan);
 421         } else
 422                 sspi->left_rx_word = 0;
 423
 424         /*
 425          * we only wait tx-done event if transferring by DMA. for PIO,
 426          * we get rx data by writing tx data, so if rx is done, tx has
 427          * done earlier
 428          */
 429         if (IS_DMA_VALID(t)) {
 430                 if (wait_for_completion_timeout(&sspi->tx_done, timeout) == 0) {
 431                         dev_err(&spi->dev, "transfer timeout\n");
 432                         dmaengine_terminate_all(sspi->tx_chan);
 433                 }
 434         }
 435
 436         if (IS_DMA_VALID(t)) {
 437                 dma_unmap_single(&spi->dev, sspi->src_start, t->len, DMA_TO_DEVICE);
 438                 dma_unmap_single(&spi->dev, sspi->dst_start, t->len, DMA_FROM_DEVICE);
 439         }
 440
 441         /* TX, RX FIFO stop */
 442         writel(0, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
 443         writel(0, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
 444         writel(0, sspi->base + SIRFSOC_SPI_TX_RX_EN);
 445         writel(0, sspi->base + SIRFSOC_SPI_INT_EN);
 446
 447         return t->len - sspi->left_rx_word * sspi->word_width;
 448 }
 449
 450 static void spi_sirfsoc_chipselect(struct spi_device *spi, int value)
 451 {
 452         struct sirfsoc_spi *sspi = spi_master_get_devdata(spi->master);
 453
 454         if (sspi->chipselect[spi->chip_select] == 0) {
 455                 u32 regval = readl(sspi->base + SIRFSOC_SPI_CTRL);
 456                 switch (value) {
 457                 case BITBANG_CS_ACTIVE:
 458                         if (spi->mode & SPI_CS_HIGH)
 459                                 regval |= SIRFSOC_SPI_CS_IO_OUT;
 460                         else
 461                                 regval &= ~SIRFSOC_SPI_CS_IO_OUT;
 462                         break;
 463                 case BITBANG_CS_INACTIVE:
 464                         if (spi->mode & SPI_CS_HIGH)
 465                                 regval &= ~SIRFSOC_SPI_CS_IO_OUT;
 466                         else
 467                                 regval |= SIRFSOC_SPI_CS_IO_OUT;
 468                         break;
 469                 }
 470                 writel(regval, sspi->base + SIRFSOC_SPI_CTRL);
 471         } else {
 472                 int gpio = sspi->chipselect[spi->chip_select];
 473                 gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1);
 474         }
 475 }
 476
 477 static int
 478 spi_sirfsoc_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
 479 {
 480         struct sirfsoc_spi *sspi;
 481         u8 bits_per_word = 0;
 482         int hz = 0;
 483         u32 regval;
 484         u32 txfifo_ctrl, rxfifo_ctrl;
 485         u32 fifo_size = SIRFSOC_SPI_FIFO_SIZE / 4;
 486
 487         sspi = spi_master_get_devdata(spi->master);
 488
 489         bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word;
 490         hz = t && t->speed_hz ? t->speed_hz : spi->max_speed_hz;
 491
 492         regval = (sspi->ctrl_freq / (2 * hz)) - 1;
 493         if (regval > 0xFFFF || regval < 0) {
 494                 dev_err(&spi->dev, "Speed %d not supported\n", hz);
 495                 return -EINVAL;
 496         }
 497
 498         switch (bits_per_word) {
 499         case 8:
 500                 regval |= SIRFSOC_SPI_TRAN_DAT_FORMAT_8;
 501                 sspi->rx_word = spi_sirfsoc_rx_word_u8;
 502                 sspi->tx_word = spi_sirfsoc_tx_word_u8;
 503                 break;
 504         case 12:
 505         case 16:
 506                 regval |= (bits_per_word ==  12) ? SIRFSOC_SPI_TRAN_DAT_FORMAT_12 :
 507                         SIRFSOC_SPI_TRAN_DAT_FORMAT_16;
 508                 sspi->rx_word = spi_sirfsoc_rx_word_u16;
 509                 sspi->tx_word = spi_sirfsoc_tx_word_u16;
 510                 break;
 511         case 32:
 512                 regval |= SIRFSOC_SPI_TRAN_DAT_FORMAT_32;
 513                 sspi->rx_word = spi_sirfsoc_rx_word_u32;
 514                 sspi->tx_word = spi_sirfsoc_tx_word_u32;
 515                 break;
 516         default:
 517                 BUG();
 518         }
 519
 520         sspi->word_width = DIV_ROUND_UP(bits_per_word, 8);
 521         txfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
 522                                            sspi->word_width;
 523         rxfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
 524                                            sspi->word_width;
 525
 526         if (!(spi->mode & SPI_CS_HIGH))
 527                 regval |= SIRFSOC_SPI_CS_IDLE_STAT;
 528         if (!(spi->mode & SPI_LSB_FIRST))
 529                 regval |= SIRFSOC_SPI_TRAN_MSB;
 530         if (spi->mode & SPI_CPOL)
 531                 regval |= SIRFSOC_SPI_CLK_IDLE_STAT;
 532
 533         /*
 534          * Data should be driven at least 1/2 cycle before the fetch edge to make
 535          * sure that data gets stable at the fetch edge.
 536          */
 537         if (((spi->mode & SPI_CPOL) && (spi->mode & SPI_CPHA)) ||
 538             (!(spi->mode & SPI_CPOL) && !(spi->mode & SPI_CPHA)))
 539                 regval &= ~SIRFSOC_SPI_DRV_POS_EDGE;
 540         else
 541                 regval |= SIRFSOC_SPI_DRV_POS_EDGE;
 542
 543         writel(SIRFSOC_SPI_FIFO_SC(fifo_size - 2) |
 544                         SIRFSOC_SPI_FIFO_LC(fifo_size / 2) |
 545                         SIRFSOC_SPI_FIFO_HC(2),
 546                 sspi->base + SIRFSOC_SPI_TXFIFO_LEVEL_CHK);
 547         writel(SIRFSOC_SPI_FIFO_SC(2) |
 548                         SIRFSOC_SPI_FIFO_LC(fifo_size / 2) |
 549                         SIRFSOC_SPI_FIFO_HC(fifo_size - 2),
 550                 sspi->base + SIRFSOC_SPI_RXFIFO_LEVEL_CHK);
 551         writel(txfifo_ctrl, sspi->base + SIRFSOC_SPI_TXFIFO_CTRL);
 552         writel(rxfifo_ctrl, sspi->base + SIRFSOC_SPI_RXFIFO_CTRL);
 553
 554         if (t && t->tx_buf && !t->rx_buf && (t->len <= SIRFSOC_MAX_CMD_BYTES)) {
 555                 regval |= (SIRFSOC_SPI_CMD_BYTE_NUM((t->len - 1)) |
 556                                 SIRFSOC_SPI_CMD_MODE);
 557                 sspi->tx_by_cmd = true;
 558         } else {
 559                 regval &= ~SIRFSOC_SPI_CMD_MODE;
 560                 sspi->tx_by_cmd = false;
 561         }
 562         writel(regval, sspi->base + SIRFSOC_SPI_CTRL);
 563
 564         if (IS_DMA_VALID(t)) {
 565                 /* Enable DMA mode for RX, TX */
 566                 writel(0, sspi->base + SIRFSOC_SPI_TX_DMA_IO_CTRL);
 567                 writel(SIRFSOC_SPI_RX_DMA_FLUSH, sspi->base + SIRFSOC_SPI_RX_DMA_IO_CTRL);
 568         } else {
 569                 /* Enable IO mode for RX, TX */
 570                 writel(SIRFSOC_SPI_IO_MODE_SEL, sspi->base + SIRFSOC_SPI_TX_DMA_IO_CTRL);
 571                 writel(SIRFSOC_SPI_IO_MODE_SEL, sspi->base + SIRFSOC_SPI_RX_DMA_IO_CTRL);
 572         }
 573
 574         return 0;
 575 }
 576
 577 static int spi_sirfsoc_setup(struct spi_device *spi)
 578 {
 579         if (!spi->max_speed_hz)
 580                 return -EINVAL;
 581
 582         return spi_sirfsoc_setup_transfer(spi, NULL);
 583 }
 584
 585 static int spi_sirfsoc_probe(struct platform_device *pdev)
 586 {
 587         struct sirfsoc_spi *sspi;
 588         struct spi_master *master;
 589         struct resource *mem_res;
 590         int num_cs, cs_gpio, irq;
 591         int i;
 592         int ret;
 593
 594         ret = of_property_read_u32(pdev->dev.of_node,
 595                         "sirf,spi-num-chipselects", &num_cs);
 596         if (ret < 0) {
 597                 dev_err(&pdev->dev, "Unable to get chip select number\n");
 598                 goto err_cs;
 599         }
 600
 601         master = spi_alloc_master(&pdev->dev, sizeof(*sspi) + sizeof(int) * num_cs);
 602         if (!master) {
 603                 dev_err(&pdev->dev, "Unable to allocate SPI master\n");
 604                 return -ENOMEM;
 605         }
 606         platform_set_drvdata(pdev, master);
 607         sspi = spi_master_get_devdata(master);
 608
 609         master->num_chipselect = num_cs;
 610
 611         for (i = 0; i < master->num_chipselect; i++) {
 612                 cs_gpio = of_get_named_gpio(pdev->dev.of_node, "cs-gpios", i);
 613                 if (cs_gpio < 0) {
 614                         dev_err(&pdev->dev, "can't get cs gpio from DT\n");
 615                         ret = -ENODEV;
 616                         goto free_master;
 617                 }
 618
 619                 sspi->chipselect[i] = cs_gpio;
 620                 if (cs_gpio == 0)
 621                         continue; /* use cs from spi controller */
 622
 623                 ret = gpio_request(cs_gpio, DRIVER_NAME);
 624                 if (ret) {
 625                         while (i > 0) {
 626                                 i--;
 627                                 if (sspi->chipselect[i] > 0)
 628                                         gpio_free(sspi->chipselect[i]);
 629                         }
 630                         dev_err(&pdev->dev, "fail to request cs gpios\n");
 631                         goto free_master;
 632                 }
 633         }
 634
 635         mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 636         sspi->base = devm_ioremap_resource(&pdev->dev, mem_res);
 637         if (IS_ERR(sspi->base)) {
 638                 ret = PTR_ERR(sspi->base);
 639                 goto free_master;
 640         }
 641
 642         irq = platform_get_irq(pdev, 0);
 643         if (irq < 0) {
 644                 ret = -ENXIO;
 645                 goto free_master;
 646         }
 647         ret = devm_request_irq(&pdev->dev, irq, spi_sirfsoc_irq, 0,
 648                                 DRIVER_NAME, sspi);
 649         if (ret)
 650                 goto free_master;
 651
 652         sspi->bitbang.master = master;
 653         sspi->bitbang.chipselect = spi_sirfsoc_chipselect;
 654         sspi->bitbang.setup_transfer = spi_sirfsoc_setup_transfer;
 655         sspi->bitbang.txrx_bufs = spi_sirfsoc_transfer;
 656         sspi->bitbang.master->setup = spi_sirfsoc_setup;
 657         master->bus_num = pdev->id;
 658         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH;
 659         master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(12) |
 660                                         SPI_BPW_MASK(16) | SPI_BPW_MASK(32);
 661         sspi->bitbang.master->dev.of_node = pdev->dev.of_node;
 662
 663         /* request DMA channels */
 664         sspi->rx_chan = dma_request_slave_channel(&pdev->dev, "rx");
 665         if (!sspi->rx_chan) {
 666                 dev_err(&pdev->dev, "can not allocate rx dma channel\n");
 667                 ret = -ENODEV;
 668                 goto free_master;
 669         }
 670         sspi->tx_chan = dma_request_slave_channel(&pdev->dev, "tx");
 671         if (!sspi->tx_chan) {
 672                 dev_err(&pdev->dev, "can not allocate tx dma channel\n");
 673                 ret = -ENODEV;
 674                 goto free_rx_dma;
 675         }
 676
 677         sspi->clk = clk_get(&pdev->dev, NULL);
 678         if (IS_ERR(sspi->clk)) {
 679                 ret = PTR_ERR(sspi->clk);
 680                 goto free_tx_dma;
 681         }
 682         clk_prepare_enable(sspi->clk);
 683         sspi->ctrl_freq = clk_get_rate(sspi->clk);
 684
 685         init_completion(&sspi->rx_done);
 686         init_completion(&sspi->tx_done);
 687
 688         writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
 689         writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
 690         writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
 691         writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
 692         /* We are not using dummy delay between command and data */
 693         writel(0, sspi->base + SIRFSOC_SPI_DUMMY_DELAY_CTL);
 694
 695         sspi->dummypage = kmalloc(2 * PAGE_SIZE, GFP_KERNEL);
 696         if (!sspi->dummypage) {
 697                 ret = -ENOMEM;
 698                 goto free_clk;
 699         }
 700
 701         ret = spi_bitbang_start(&sspi->bitbang);
 702         if (ret)
 703                 goto free_dummypage;
 704
 705         dev_info(&pdev->dev, "registerred, bus number = %d\n", master->bus_num);
 706
 707         return 0;
 708 free_dummypage:
 709         kfree(sspi->dummypage);
 710 free_clk:
 711         clk_disable_unprepare(sspi->clk);
 712         clk_put(sspi->clk);
 713 free_tx_dma:
 714         dma_release_channel(sspi->tx_chan);
 715 free_rx_dma:
 716         dma_release_channel(sspi->rx_chan);
 717 free_master:
 718         spi_master_put(master);
 719 err_cs:
 720         return ret;
 721 }
 722
 723 static int  spi_sirfsoc_remove(struct platform_device *pdev)
 724 {
 725         struct spi_master *master;
 726         struct sirfsoc_spi *sspi;
 727         int i;
 728
 729         master = platform_get_drvdata(pdev);
 730         sspi = spi_master_get_devdata(master);
 731
 732         spi_bitbang_stop(&sspi->bitbang);
 733         for (i = 0; i < master->num_chipselect; i++) {
 734                 if (sspi->chipselect[i] > 0)
 735                         gpio_free(sspi->chipselect[i]);
 736         }
 737         kfree(sspi->dummypage);
 738         clk_disable_unprepare(sspi->clk);
 739         clk_put(sspi->clk);
 740         dma_release_channel(sspi->rx_chan);
 741         dma_release_channel(sspi->tx_chan);
 742         spi_master_put(master);
 743         return 0;
 744 }
 745
 746 #ifdef CONFIG_PM_SLEEP
 747 static int spi_sirfsoc_suspend(struct device *dev)
 748 {
 749         struct spi_master *master = dev_get_drvdata(dev);
 750         struct sirfsoc_spi *sspi = spi_master_get_devdata(master);
 751         int ret;
 752
 753         ret = spi_master_suspend(master);
 754         if (ret)
 755                 return ret;
 756
 757         clk_disable(sspi->clk);
 758         return 0;
 759 }
 760
 761 static int spi_sirfsoc_resume(struct device *dev)
 762 {
 763         struct spi_master *master = dev_get_drvdata(dev);
 764         struct sirfsoc_spi *sspi = spi_master_get_devdata(master);
 765
 766         clk_enable(sspi->clk);
 767         writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
 768         writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
 769         writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
 770         writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
 771
 772         return spi_master_resume(master);
 773 }
 774 #endif
 775
 776 static SIMPLE_DEV_PM_OPS(spi_sirfsoc_pm_ops, spi_sirfsoc_suspend,
 777                          spi_sirfsoc_resume);
 778
 779 static const struct of_device_id spi_sirfsoc_of_match[] = {
 780         { .compatible = "sirf,prima2-spi", },
 781         { .compatible = "sirf,marco-spi", },
 782         {}
 783 };
 784 MODULE_DEVICE_TABLE(of, spi_sirfsoc_of_match);
 785
 786 static struct platform_driver spi_sirfsoc_driver = {
 787         .driver = {
 788                 .name = DRIVER_NAME,
 789                 .owner = THIS_MODULE,
 790                 .pm     = &spi_sirfsoc_pm_ops,
 791                 .of_match_table = spi_sirfsoc_of_match,
 792         },
 793         .probe = spi_sirfsoc_probe,
 794         .remove = spi_sirfsoc_remove,
 795 };
 796 module_platform_driver(spi_sirfsoc_driver);
 797
 798 MODULE_DESCRIPTION("SiRF SoC SPI master driver");
 799 MODULE_AUTHOR("Zhiwu Song <Zhiwu.Song@csr.com>, "
 800                 "Barry Song <Baohua.Song@csr.com>");
 801 MODULE_LICENSE("GPL v2");