| blob | 7f86e9a59df49c3dec2b869bc62ca3db16b58b8c |
1 /*
2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
3 * Copyright (c) BayLibre, SAS.
4 * Author : Neil Armstrong <narmstrong@baylibre.com>
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
16 #ifndef _DT_BINDINGS_RESET_GCC_MDM9615_H
17 #define _DT_BINDINGS_RESET_GCC_MDM9615_H
19 #define SFAB_MSS_Q6_SW_RESET 0
20 #define SFAB_MSS_Q6_FW_RESET 1
21 #define QDSS_STM_RESET 2
22 #define AFAB_SMPSS_S_RESET 3
23 #define AFAB_SMPSS_M1_RESET 4
24 #define AFAB_SMPSS_M0_RESET 5
25 #define AFAB_EBI1_CH0_RESET 6
26 #define AFAB_EBI1_CH1_RESET 7
27 #define SFAB_ADM0_M0_RESET 8
28 #define SFAB_ADM0_M1_RESET 9
29 #define SFAB_ADM0_M2_RESET 10
30 #define ADM0_C2_RESET 11
31 #define ADM0_C1_RESET 12
32 #define ADM0_C0_RESET 13
33 #define ADM0_PBUS_RESET 14
34 #define ADM0_RESET 15
35 #define QDSS_CLKS_SW_RESET 16
36 #define QDSS_POR_RESET 17
37 #define QDSS_TSCTR_RESET 18
38 #define QDSS_HRESET_RESET 19
39 #define QDSS_AXI_RESET 20
40 #define QDSS_DBG_RESET 21
41 #define PCIE_A_RESET 22
42 #define PCIE_AUX_RESET 23
43 #define PCIE_H_RESET 24
44 #define SFAB_PCIE_M_RESET 25
45 #define SFAB_PCIE_S_RESET 26
46 #define SFAB_MSS_M_RESET 27
47 #define SFAB_USB3_M_RESET 28
48 #define SFAB_RIVA_M_RESET 29
49 #define SFAB_LPASS_RESET 30
50 #define SFAB_AFAB_M_RESET 31
51 #define AFAB_SFAB_M0_RESET 32
52 #define AFAB_SFAB_M1_RESET 33
53 #define SFAB_SATA_S_RESET 34
54 #define SFAB_DFAB_M_RESET 35
55 #define DFAB_SFAB_M_RESET 36
56 #define DFAB_SWAY0_RESET 37
57 #define DFAB_SWAY1_RESET 38
58 #define DFAB_ARB0_RESET 39
59 #define DFAB_ARB1_RESET 40
60 #define PPSS_PROC_RESET 41
61 #define PPSS_RESET 42
62 #define DMA_BAM_RESET 43
63 #define SPS_TIC_H_RESET 44
64 #define SLIMBUS_H_RESET 45
65 #define SFAB_CFPB_M_RESET 46
66 #define SFAB_CFPB_S_RESET 47
67 #define TSIF_H_RESET 48
68 #define CE1_H_RESET 49
69 #define CE1_CORE_RESET 50
70 #define CE1_SLEEP_RESET 51
71 #define CE2_H_RESET 52
72 #define CE2_CORE_RESET 53
73 #define SFAB_SFPB_M_RESET 54
74 #define SFAB_SFPB_S_RESET 55
75 #define RPM_PROC_RESET 56
76 #define PMIC_SSBI2_RESET 57
77 #define SDC1_RESET 58
78 #define SDC2_RESET 59
79 #define SDC3_RESET 60
80 #define SDC4_RESET 61
81 #define SDC5_RESET 62
82 #define DFAB_A2_RESET 63
83 #define USB_HS1_RESET 64
84 #define USB_HSIC_RESET 65
85 #define USB_FS1_XCVR_RESET 66
86 #define USB_FS1_RESET 67
87 #define USB_FS2_XCVR_RESET 68
88 #define USB_FS2_RESET 69
89 #define GSBI1_RESET 70
90 #define GSBI2_RESET 71
91 #define GSBI3_RESET 72
92 #define GSBI4_RESET 73
93 #define GSBI5_RESET 74
94 #define GSBI6_RESET 75
95 #define GSBI7_RESET 76
96 #define GSBI8_RESET 77
97 #define GSBI9_RESET 78
98 #define GSBI10_RESET 79
99 #define GSBI11_RESET 80
100 #define GSBI12_RESET 81
101 #define SPDM_RESET 82
102 #define TLMM_H_RESET 83
103 #define SFAB_MSS_S_RESET 84
104 #define MSS_SLP_RESET 85
105 #define MSS_Q6SW_JTAG_RESET 86
106 #define MSS_Q6FW_JTAG_RESET 87
107 #define MSS_RESET 88
108 #define SATA_H_RESET 89
109 #define SATA_RXOOB_RESE 90
110 #define SATA_PMALIVE_RESET 91
111 #define SATA_SFAB_M_RESET 92
112 #define TSSC_RESET 93
113 #define PDM_RESET 94
114 #define MPM_H_RESET 95
115 #define MPM_RESET 96
116 #define SFAB_SMPSS_S_RESET 97
117 #define PRNG_RESET 98
118 #define RIVA_RESET 99
119 #define USB_HS3_RESET 100
120 #define USB_HS4_RESET 101
121 #define CE3_RESET 102
122 #define PCIE_EXT_PCI_RESET 103
123 #define PCIE_PHY_RESET 104
124 #define PCIE_PCI_RESET 105
125 #define PCIE_POR_RESET 106
126 #define PCIE_HCLK_RESET 107
127 #define PCIE_ACLK_RESET 108
128 #define CE3_H_RESET 109
129 #define SFAB_CE3_M_RESET 110
130 #define SFAB_CE3_S_RESET 111
131 #define SATA_RESET 112
132 #define CE3_SLEEP_RESET 113
133 #define GSS_SLP_RESET 114
134 #define GSS_RESET 115
136 #endif