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Staging: unisys: Remove FAIL_WPOSTCODE_1 macro
[linux/fpc-iii.git] / drivers / pinctrl / pinctrl-nomadik.c
blob53a11114927fc2278456444dc22ae6ac8f1af964
1 /*
2 * Generic GPIO driver for logic cells found in the Nomadik SoC
3 *
4 * Copyright (C) 2008,2009 STMicroelectronics
5 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
6 * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com>
7 * Copyright (C) 2011-2013 Linus Walleij <linus.walleij@linaro.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/device.h>
17 #include <linux/platform_device.h>
18 #include <linux/io.h>
19 #include <linux/clk.h>
20 #include <linux/err.h>
21 #include <linux/gpio.h>
22 #include <linux/spinlock.h>
23 #include <linux/interrupt.h>
24 #include <linux/irq.h>
25 #include <linux/irqdomain.h>
26 #include <linux/irqchip/chained_irq.h>
27 #include <linux/slab.h>
28 #include <linux/of_device.h>
29 #include <linux/of_address.h>
30 #include <linux/pinctrl/machine.h>
31 #include <linux/pinctrl/pinctrl.h>
32 #include <linux/pinctrl/pinmux.h>
33 #include <linux/pinctrl/pinconf.h>
34 /* Since we request GPIOs from ourself */
35 #include <linux/pinctrl/consumer.h>
36 #include "pinctrl-nomadik.h"
37 #include "core.h"
38
39 /*
40 * The GPIO module in the Nomadik family of Systems-on-Chip is an
41 * AMBA device, managing 32 pins and alternate functions. The logic block
42 * is currently used in the Nomadik and ux500.
43 *
44 * Symbols in this file are called "nmk_gpio" for "nomadik gpio"
45 */
46
47 /*
48 * pin configurations are represented by 32-bit integers:
49 *
50 * bit 0.. 8 - Pin Number (512 Pins Maximum)
51 * bit 9..10 - Alternate Function Selection
52 * bit 11..12 - Pull up/down state
53 * bit 13 - Sleep mode behaviour
54 * bit 14 - Direction
55 * bit 15 - Value (if output)
56 * bit 16..18 - SLPM pull up/down state
57 * bit 19..20 - SLPM direction
58 * bit 21..22 - SLPM Value (if output)
59 * bit 23..25 - PDIS value (if input)
60 * bit 26 - Gpio mode
61 * bit 27 - Sleep mode
62 *
63 * to facilitate the definition, the following macros are provided
64 *
65 * PIN_CFG_DEFAULT - default config (0):
66 * pull up/down = disabled
67 * sleep mode = input/wakeup
68 * direction = input
69 * value = low
70 * SLPM direction = same as normal
71 * SLPM pull = same as normal
72 * SLPM value = same as normal
73 *
74 * PIN_CFG - default config with alternate function
75 */
76
77 typedef unsigned long pin_cfg_t;
78
79 #define PIN_NUM_MASK 0x1ff
80 #define PIN_NUM(x) ((x) & PIN_NUM_MASK)
81
82 #define PIN_ALT_SHIFT 9
83 #define PIN_ALT_MASK (0x3 << PIN_ALT_SHIFT)
84 #define PIN_ALT(x) (((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT)
85 #define PIN_GPIO (NMK_GPIO_ALT_GPIO << PIN_ALT_SHIFT)
86 #define PIN_ALT_A (NMK_GPIO_ALT_A << PIN_ALT_SHIFT)
87 #define PIN_ALT_B (NMK_GPIO_ALT_B << PIN_ALT_SHIFT)
88 #define PIN_ALT_C (NMK_GPIO_ALT_C << PIN_ALT_SHIFT)
89
90 #define PIN_PULL_SHIFT 11
91 #define PIN_PULL_MASK (0x3 << PIN_PULL_SHIFT)
92 #define PIN_PULL(x) (((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT)
93 #define PIN_PULL_NONE (NMK_GPIO_PULL_NONE << PIN_PULL_SHIFT)
94 #define PIN_PULL_UP (NMK_GPIO_PULL_UP << PIN_PULL_SHIFT)
95 #define PIN_PULL_DOWN (NMK_GPIO_PULL_DOWN << PIN_PULL_SHIFT)
96
97 #define PIN_SLPM_SHIFT 13
98 #define PIN_SLPM_MASK (0x1 << PIN_SLPM_SHIFT)
99 #define PIN_SLPM(x) (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT)
100 #define PIN_SLPM_MAKE_INPUT (NMK_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT)
101 #define PIN_SLPM_NOCHANGE (NMK_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT)
102 /* These two replace the above in DB8500v2+ */
103 #define PIN_SLPM_WAKEUP_ENABLE (NMK_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT)
104 #define PIN_SLPM_WAKEUP_DISABLE (NMK_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT)
105 #define PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP PIN_SLPM_WAKEUP_DISABLE
106
107 #define PIN_SLPM_GPIO PIN_SLPM_WAKEUP_ENABLE /* In SLPM, pin is a gpio */
108 #define PIN_SLPM_ALTFUNC PIN_SLPM_WAKEUP_DISABLE /* In SLPM, pin is altfunc */
109
110 #define PIN_DIR_SHIFT 14
111 #define PIN_DIR_MASK (0x1 << PIN_DIR_SHIFT)
112 #define PIN_DIR(x) (((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT)
113 #define PIN_DIR_INPUT (0 << PIN_DIR_SHIFT)
114 #define PIN_DIR_OUTPUT (1 << PIN_DIR_SHIFT)
115
116 #define PIN_VAL_SHIFT 15
117 #define PIN_VAL_MASK (0x1 << PIN_VAL_SHIFT)
118 #define PIN_VAL(x) (((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT)
119 #define PIN_VAL_LOW (0 << PIN_VAL_SHIFT)
120 #define PIN_VAL_HIGH (1 << PIN_VAL_SHIFT)
121
122 #define PIN_SLPM_PULL_SHIFT 16
123 #define PIN_SLPM_PULL_MASK (0x7 << PIN_SLPM_PULL_SHIFT)
124 #define PIN_SLPM_PULL(x) \
125 (((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT)
126 #define PIN_SLPM_PULL_NONE \
127 ((1 + NMK_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT)
128 #define PIN_SLPM_PULL_UP \
129 ((1 + NMK_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT)
130 #define PIN_SLPM_PULL_DOWN \
131 ((1 + NMK_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT)
132
133 #define PIN_SLPM_DIR_SHIFT 19
134 #define PIN_SLPM_DIR_MASK (0x3 << PIN_SLPM_DIR_SHIFT)
135 #define PIN_SLPM_DIR(x) \
136 (((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT)
137 #define PIN_SLPM_DIR_INPUT ((1 + 0) << PIN_SLPM_DIR_SHIFT)
138 #define PIN_SLPM_DIR_OUTPUT ((1 + 1) << PIN_SLPM_DIR_SHIFT)
139
140 #define PIN_SLPM_VAL_SHIFT 21
141 #define PIN_SLPM_VAL_MASK (0x3 << PIN_SLPM_VAL_SHIFT)
142 #define PIN_SLPM_VAL(x) \
143 (((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT)
144 #define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT)
145 #define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT)
146
147 #define PIN_SLPM_PDIS_SHIFT 23
148 #define PIN_SLPM_PDIS_MASK (0x3 << PIN_SLPM_PDIS_SHIFT)
149 #define PIN_SLPM_PDIS(x) \
150 (((x) & PIN_SLPM_PDIS_MASK) >> PIN_SLPM_PDIS_SHIFT)
151 #define PIN_SLPM_PDIS_NO_CHANGE (0 << PIN_SLPM_PDIS_SHIFT)
152 #define PIN_SLPM_PDIS_DISABLED (1 << PIN_SLPM_PDIS_SHIFT)
153 #define PIN_SLPM_PDIS_ENABLED (2 << PIN_SLPM_PDIS_SHIFT)
154
155 #define PIN_LOWEMI_SHIFT 25
156 #define PIN_LOWEMI_MASK (0x1 << PIN_LOWEMI_SHIFT)
157 #define PIN_LOWEMI(x) (((x) & PIN_LOWEMI_MASK) >> PIN_LOWEMI_SHIFT)
158 #define PIN_LOWEMI_DISABLED (0 << PIN_LOWEMI_SHIFT)
159 #define PIN_LOWEMI_ENABLED (1 << PIN_LOWEMI_SHIFT)
160
161 #define PIN_GPIOMODE_SHIFT 26
162 #define PIN_GPIOMODE_MASK (0x1 << PIN_GPIOMODE_SHIFT)
163 #define PIN_GPIOMODE(x) (((x) & PIN_GPIOMODE_MASK) >> PIN_GPIOMODE_SHIFT)
164 #define PIN_GPIOMODE_DISABLED (0 << PIN_GPIOMODE_SHIFT)
165 #define PIN_GPIOMODE_ENABLED (1 << PIN_GPIOMODE_SHIFT)
166
167 #define PIN_SLEEPMODE_SHIFT 27
168 #define PIN_SLEEPMODE_MASK (0x1 << PIN_SLEEPMODE_SHIFT)
169 #define PIN_SLEEPMODE(x) (((x) & PIN_SLEEPMODE_MASK) >> PIN_SLEEPMODE_SHIFT)
170 #define PIN_SLEEPMODE_DISABLED (0 << PIN_SLEEPMODE_SHIFT)
171 #define PIN_SLEEPMODE_ENABLED (1 << PIN_SLEEPMODE_SHIFT)
172
173
174 /* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */
175 #define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN)
176 #define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP)
177 #define PIN_INPUT_NOPULL (PIN_DIR_INPUT | PIN_PULL_NONE)
178 #define PIN_OUTPUT_LOW (PIN_DIR_OUTPUT | PIN_VAL_LOW)
179 #define PIN_OUTPUT_HIGH (PIN_DIR_OUTPUT | PIN_VAL_HIGH)
180
181 #define PIN_SLPM_INPUT_PULLDOWN (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN)
182 #define PIN_SLPM_INPUT_PULLUP (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP)
183 #define PIN_SLPM_INPUT_NOPULL (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE)
184 #define PIN_SLPM_OUTPUT_LOW (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW)
185 #define PIN_SLPM_OUTPUT_HIGH (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH)
186
187 #define PIN_CFG_DEFAULT (0)
188
189 #define PIN_CFG(num, alt) \
190 (PIN_CFG_DEFAULT |\
191 (PIN_NUM(num) | PIN_##alt))
192
193 #define PIN_CFG_INPUT(num, alt, pull) \
194 (PIN_CFG_DEFAULT |\
195 (PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull))
196
197 #define PIN_CFG_OUTPUT(num, alt, val) \
198 (PIN_CFG_DEFAULT |\
199 (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val))
200
201 /*
202 * "nmk_gpio" and "NMK_GPIO" stand for "Nomadik GPIO", leaving
203 * the "gpio" namespace for generic and cross-machine functions
204 */
205
206 #define GPIO_BLOCK_SHIFT 5
207 #define NMK_GPIO_PER_CHIP (1 << GPIO_BLOCK_SHIFT)
208
209 /* Register in the logic block */
210 #define NMK_GPIO_DAT 0x00
211 #define NMK_GPIO_DATS 0x04
212 #define NMK_GPIO_DATC 0x08
213 #define NMK_GPIO_PDIS 0x0c
214 #define NMK_GPIO_DIR 0x10
215 #define NMK_GPIO_DIRS 0x14
216 #define NMK_GPIO_DIRC 0x18
217 #define NMK_GPIO_SLPC 0x1c
218 #define NMK_GPIO_AFSLA 0x20
219 #define NMK_GPIO_AFSLB 0x24
220 #define NMK_GPIO_LOWEMI 0x28
221
222 #define NMK_GPIO_RIMSC 0x40
223 #define NMK_GPIO_FIMSC 0x44
224 #define NMK_GPIO_IS 0x48
225 #define NMK_GPIO_IC 0x4c
226 #define NMK_GPIO_RWIMSC 0x50
227 #define NMK_GPIO_FWIMSC 0x54
228 #define NMK_GPIO_WKS 0x58
229 /* These appear in DB8540 and later ASICs */
230 #define NMK_GPIO_EDGELEVEL 0x5C
231 #define NMK_GPIO_LEVEL 0x60
232
233
234 /* Pull up/down values */
235 enum nmk_gpio_pull {
236 NMK_GPIO_PULL_NONE,
237 NMK_GPIO_PULL_UP,
238 NMK_GPIO_PULL_DOWN,
239 };
240
241 /* Sleep mode */
242 enum nmk_gpio_slpm {
243 NMK_GPIO_SLPM_INPUT,
244 NMK_GPIO_SLPM_WAKEUP_ENABLE = NMK_GPIO_SLPM_INPUT,
245 NMK_GPIO_SLPM_NOCHANGE,
246 NMK_GPIO_SLPM_WAKEUP_DISABLE = NMK_GPIO_SLPM_NOCHANGE,
247 };
248
249 /*
250 * Platform data to register a block: only the initial gpio/irq number.
251 */
252 struct nmk_gpio_platform_data {
253 char *name;
254 int first_gpio;
255 int first_irq;
256 int num_gpio;
257 u32 (*get_secondary_status)(unsigned int bank);
258 void (*set_ioforce)(bool enable);
259 bool supports_sleepmode;
260 };
261
262 struct nmk_gpio_chip {
263 struct gpio_chip chip;
264 struct irq_domain *domain;
265 void __iomem *addr;
266 struct clk *clk;
267 unsigned int bank;
268 unsigned int parent_irq;
269 int secondary_parent_irq;
270 u32 (*get_secondary_status)(unsigned int bank);
271 void (*set_ioforce)(bool enable);
272 spinlock_t lock;
273 bool sleepmode;
274 /* Keep track of configured edges */
275 u32 edge_rising;
276 u32 edge_falling;
277 u32 real_wake;
278 u32 rwimsc;
279 u32 fwimsc;
280 u32 rimsc;
281 u32 fimsc;
282 u32 pull_up;
283 u32 lowemi;
284 };
285
286 /**
287 * struct nmk_pinctrl - state container for the Nomadik pin controller
288 * @dev: containing device pointer
289 * @pctl: corresponding pin controller device
290 * @soc: SoC data for this specific chip
291 * @prcm_base: PRCM register range virtual base
292 */
293 struct nmk_pinctrl {
294 struct device *dev;
295 struct pinctrl_dev *pctl;
296 const struct nmk_pinctrl_soc_data *soc;
297 void __iomem *prcm_base;
298 };
299
300 static struct nmk_gpio_chip *
301 nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)];
302
303 static DEFINE_SPINLOCK(nmk_gpio_slpm_lock);
304
305 #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips)
306
307 static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,
308 unsigned offset, int gpio_mode)
309 {
310 u32 bit = 1 << offset;
311 u32 afunc, bfunc;
312
313 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit;
314 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit;
315 if (gpio_mode & NMK_GPIO_ALT_A)
316 afunc |= bit;
317 if (gpio_mode & NMK_GPIO_ALT_B)
318 bfunc |= bit;
319 writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
320 writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
321 }
322
323 static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip,
324 unsigned offset, enum nmk_gpio_slpm mode)
325 {
326 u32 bit = 1 << offset;
327 u32 slpm;
328
329 slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC);
330 if (mode == NMK_GPIO_SLPM_NOCHANGE)
331 slpm |= bit;
332 else
333 slpm &= ~bit;
334 writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC);
335 }
336
337 static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,
338 unsigned offset, enum nmk_gpio_pull pull)
339 {
340 u32 bit = 1 << offset;
341 u32 pdis;
342
343 pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS);
344 if (pull == NMK_GPIO_PULL_NONE) {
345 pdis |= bit;
346 nmk_chip->pull_up &= ~bit;
347 } else {
348 pdis &= ~bit;
349 }
350
351 writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);
352
353 if (pull == NMK_GPIO_PULL_UP) {
354 nmk_chip->pull_up |= bit;
355 writel(bit, nmk_chip->addr + NMK_GPIO_DATS);
356 } else if (pull == NMK_GPIO_PULL_DOWN) {
357 nmk_chip->pull_up &= ~bit;
358 writel(bit, nmk_chip->addr + NMK_GPIO_DATC);
359 }
360 }
361
362 static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip,
363 unsigned offset, bool lowemi)
364 {
365 u32 bit = BIT(offset);
366 bool enabled = nmk_chip->lowemi & bit;
367
368 if (lowemi == enabled)
369 return;
370
371 if (lowemi)
372 nmk_chip->lowemi |= bit;
373 else
374 nmk_chip->lowemi &= ~bit;
375
376 writel_relaxed(nmk_chip->lowemi,
377 nmk_chip->addr + NMK_GPIO_LOWEMI);
378 }
379
380 static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,
381 unsigned offset)
382 {
383 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
384 }
385
386 static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip,
387 unsigned offset, int val)
388 {
389 if (val)
390 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS);
391 else
392 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC);
393 }
394
395 static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,
396 unsigned offset, int val)
397 {
398 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS);
399 __nmk_gpio_set_output(nmk_chip, offset, val);
400 }
401
402 static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,
403 unsigned offset, int gpio_mode,
404 bool glitch)
405 {
406 u32 rwimsc = nmk_chip->rwimsc;
407 u32 fwimsc = nmk_chip->fwimsc;
408
409 if (glitch && nmk_chip->set_ioforce) {
410 u32 bit = BIT(offset);
411
412 /* Prevent spurious wakeups */
413 writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC);
414 writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC);
415
416 nmk_chip->set_ioforce(true);
417 }
418
419 __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode);
420
421 if (glitch && nmk_chip->set_ioforce) {
422 nmk_chip->set_ioforce(false);
423
424 writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC);
425 writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC);
426 }
427 }
428
429 static void
430 nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset)
431 {
432 u32 falling = nmk_chip->fimsc & BIT(offset);
433 u32 rising = nmk_chip->rimsc & BIT(offset);
434 int gpio = nmk_chip->chip.base + offset;
435 int irq = irq_find_mapping(nmk_chip->domain, offset);
436 struct irq_data *d = irq_get_irq_data(irq);
437
438 if (!rising && !falling)
439 return;
440
441 if (!d || !irqd_irq_disabled(d))
442 return;
443
444 if (rising) {
445 nmk_chip->rimsc &= ~BIT(offset);
446 writel_relaxed(nmk_chip->rimsc,
447 nmk_chip->addr + NMK_GPIO_RIMSC);
448 }
449
450 if (falling) {
451 nmk_chip->fimsc &= ~BIT(offset);
452 writel_relaxed(nmk_chip->fimsc,
453 nmk_chip->addr + NMK_GPIO_FIMSC);
454 }
455
456 dev_dbg(nmk_chip->chip.dev, "%d: clearing interrupt mask\n", gpio);
457 }
458
459 static void nmk_write_masked(void __iomem *reg, u32 mask, u32 value)
460 {
461 u32 val;
462
463 val = readl(reg);
464 val = ((val & ~mask) | (value & mask));
465 writel(val, reg);
466 }
467
468 static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl *npct,
469 unsigned offset, unsigned alt_num)
470 {
471 int i;
472 u16 reg;
473 u8 bit;
474 u8 alt_index;
475 const struct prcm_gpiocr_altcx_pin_desc *pin_desc;
476 const u16 *gpiocr_regs;
477
478 if (!npct->prcm_base)
479 return;
480
481 if (alt_num > PRCM_IDX_GPIOCR_ALTC_MAX) {
482 dev_err(npct->dev, "PRCM GPIOCR: alternate-C%i is invalid\n",
483 alt_num);
484 return;
485 }
486
487 for (i = 0 ; i < npct->soc->npins_altcx ; i++) {
488 if (npct->soc->altcx_pins[i].pin == offset)
489 break;
490 }
491 if (i == npct->soc->npins_altcx) {
492 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i is not found\n",
493 offset);
494 return;
495 }
496
497 pin_desc = npct->soc->altcx_pins + i;
498 gpiocr_regs = npct->soc->prcm_gpiocr_registers;
499
500 /*
501 * If alt_num is NULL, just clear current ALTCx selection
502 * to make sure we come back to a pure ALTC selection
503 */
504 if (!alt_num) {
505 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {
506 if (pin_desc->altcx[i].used == true) {
507 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
508 bit = pin_desc->altcx[i].control_bit;
509 if (readl(npct->prcm_base + reg) & BIT(bit)) {
510 nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0);
511 dev_dbg(npct->dev,
512 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
513 offset, i+1);
514 }
515 }
516 }
517 return;
518 }
519
520 alt_index = alt_num - 1;
521 if (pin_desc->altcx[alt_index].used == false) {
522 dev_warn(npct->dev,
523 "PRCM GPIOCR: pin %i: alternate-C%i does not exist\n",
524 offset, alt_num);
525 return;
526 }
527
528 /*
529 * Check if any other ALTCx functions are activated on this pin
530 * and disable it first.
531 */
532 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {
533 if (i == alt_index)
534 continue;
535 if (pin_desc->altcx[i].used == true) {
536 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
537 bit = pin_desc->altcx[i].control_bit;
538 if (readl(npct->prcm_base + reg) & BIT(bit)) {
539 nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0);
540 dev_dbg(npct->dev,
541 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
542 offset, i+1);
543 }
544 }
545 }
546
547 reg = gpiocr_regs[pin_desc->altcx[alt_index].reg_index];
548 bit = pin_desc->altcx[alt_index].control_bit;
549 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i: alternate-C%i has been selected\n",
550 offset, alt_index+1);
551 nmk_write_masked(npct->prcm_base + reg, BIT(bit), BIT(bit));
552 }
553
554 /*
555 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
556 * - Save SLPM registers
557 * - Set SLPM=0 for the IOs you want to switch and others to 1
558 * - Configure the GPIO registers for the IOs that are being switched
559 * - Set IOFORCE=1
560 * - Modify the AFLSA/B registers for the IOs that are being switched
561 * - Set IOFORCE=0
562 * - Restore SLPM registers
563 * - Any spurious wake up event during switch sequence to be ignored and
564 * cleared
565 */
566 static void nmk_gpio_glitch_slpm_init(unsigned int *slpm)
567 {
568 int i;
569
570 for (i = 0; i < NUM_BANKS; i++) {
571 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
572 unsigned int temp = slpm[i];
573
574 if (!chip)
575 break;
576
577 clk_enable(chip->clk);
578
579 slpm[i] = readl(chip->addr + NMK_GPIO_SLPC);
580 writel(temp, chip->addr + NMK_GPIO_SLPC);
581 }
582 }
583
584 static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm)
585 {
586 int i;
587
588 for (i = 0; i < NUM_BANKS; i++) {
589 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
590
591 if (!chip)
592 break;
593
594 writel(slpm[i], chip->addr + NMK_GPIO_SLPC);
595
596 clk_disable(chip->clk);
597 }
598 }
599
600 static int __maybe_unused nmk_prcm_gpiocr_get_mode(struct pinctrl_dev *pctldev, int gpio)
601 {
602 int i;
603 u16 reg;
604 u8 bit;
605 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
606 const struct prcm_gpiocr_altcx_pin_desc *pin_desc;
607 const u16 *gpiocr_regs;
608
609 if (!npct->prcm_base)
610 return NMK_GPIO_ALT_C;
611
612 for (i = 0; i < npct->soc->npins_altcx; i++) {
613 if (npct->soc->altcx_pins[i].pin == gpio)
614 break;
615 }
616 if (i == npct->soc->npins_altcx)
617 return NMK_GPIO_ALT_C;
618
619 pin_desc = npct->soc->altcx_pins + i;
620 gpiocr_regs = npct->soc->prcm_gpiocr_registers;
621 for (i = 0; i < PRCM_IDX_GPIOCR_ALTC_MAX; i++) {
622 if (pin_desc->altcx[i].used == true) {
623 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
624 bit = pin_desc->altcx[i].control_bit;
625 if (readl(npct->prcm_base + reg) & BIT(bit))
626 return NMK_GPIO_ALT_C+i+1;
627 }
628 }
629 return NMK_GPIO_ALT_C;
630 }
631
632 int nmk_gpio_get_mode(int gpio)
633 {
634 struct nmk_gpio_chip *nmk_chip;
635 u32 afunc, bfunc, bit;
636
637 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
638 if (!nmk_chip)
639 return -EINVAL;
640
641 bit = 1 << (gpio % NMK_GPIO_PER_CHIP);
642
643 clk_enable(nmk_chip->clk);
644
645 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit;
646 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit;
647
648 clk_disable(nmk_chip->clk);
649
650 return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0);
651 }
652 EXPORT_SYMBOL(nmk_gpio_get_mode);
653
654
655 /* IRQ functions */
656 static inline int nmk_gpio_get_bitmask(int gpio)
657 {
658 return 1 << (gpio % NMK_GPIO_PER_CHIP);
659 }
660
661 static void nmk_gpio_irq_ack(struct irq_data *d)
662 {
663 struct nmk_gpio_chip *nmk_chip;
664
665 nmk_chip = irq_data_get_irq_chip_data(d);
666 if (!nmk_chip)
667 return;
668
669 clk_enable(nmk_chip->clk);
670 writel(nmk_gpio_get_bitmask(d->hwirq), nmk_chip->addr + NMK_GPIO_IC);
671 clk_disable(nmk_chip->clk);
672 }
673
674 enum nmk_gpio_irq_type {
675 NORMAL,
676 WAKE,
677 };
678
679 static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
680 int gpio, enum nmk_gpio_irq_type which,
681 bool enable)
682 {
683 u32 bitmask = nmk_gpio_get_bitmask(gpio);
684 u32 *rimscval;
685 u32 *fimscval;
686 u32 rimscreg;
687 u32 fimscreg;
688
689 if (which == NORMAL) {
690 rimscreg = NMK_GPIO_RIMSC;
691 fimscreg = NMK_GPIO_FIMSC;
692 rimscval = &nmk_chip->rimsc;
693 fimscval = &nmk_chip->fimsc;
694 } else {
695 rimscreg = NMK_GPIO_RWIMSC;
696 fimscreg = NMK_GPIO_FWIMSC;
697 rimscval = &nmk_chip->rwimsc;
698 fimscval = &nmk_chip->fwimsc;
699 }
700
701 /* we must individually set/clear the two edges */
702 if (nmk_chip->edge_rising & bitmask) {
703 if (enable)
704 *rimscval |= bitmask;
705 else
706 *rimscval &= ~bitmask;
707 writel(*rimscval, nmk_chip->addr + rimscreg);
708 }
709 if (nmk_chip->edge_falling & bitmask) {
710 if (enable)
711 *fimscval |= bitmask;
712 else
713 *fimscval &= ~bitmask;
714 writel(*fimscval, nmk_chip->addr + fimscreg);
715 }
716 }
717
718 static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,
719 int gpio, bool on)
720 {
721 /*
722 * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is
723 * disabled, since setting SLPM to 1 increases power consumption, and
724 * wakeup is anyhow controlled by the RIMSC and FIMSC registers.
725 */
726 if (nmk_chip->sleepmode && on) {
727 __nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP,
728 NMK_GPIO_SLPM_WAKEUP_ENABLE);
729 }
730
731 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on);
732 }
733
734 static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable)
735 {
736 struct nmk_gpio_chip *nmk_chip;
737 unsigned long flags;
738 u32 bitmask;
739
740 nmk_chip = irq_data_get_irq_chip_data(d);
741 bitmask = nmk_gpio_get_bitmask(d->hwirq);
742 if (!nmk_chip)
743 return -EINVAL;
744
745 clk_enable(nmk_chip->clk);
746 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
747 spin_lock(&nmk_chip->lock);
748
749 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable);
750
751 if (!(nmk_chip->real_wake & bitmask))
752 __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable);
753
754 spin_unlock(&nmk_chip->lock);
755 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
756 clk_disable(nmk_chip->clk);
757
758 return 0;
759 }
760
761 static void nmk_gpio_irq_mask(struct irq_data *d)
762 {
763 nmk_gpio_irq_maskunmask(d, false);
764 }
765
766 static void nmk_gpio_irq_unmask(struct irq_data *d)
767 {
768 nmk_gpio_irq_maskunmask(d, true);
769 }
770
771 static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
772 {
773 struct nmk_gpio_chip *nmk_chip;
774 unsigned long flags;
775 u32 bitmask;
776
777 nmk_chip = irq_data_get_irq_chip_data(d);
778 if (!nmk_chip)
779 return -EINVAL;
780 bitmask = nmk_gpio_get_bitmask(d->hwirq);
781
782 clk_enable(nmk_chip->clk);
783 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
784 spin_lock(&nmk_chip->lock);
785
786 if (irqd_irq_disabled(d))
787 __nmk_gpio_set_wake(nmk_chip, d->hwirq, on);
788
789 if (on)
790 nmk_chip->real_wake |= bitmask;
791 else
792 nmk_chip->real_wake &= ~bitmask;
793
794 spin_unlock(&nmk_chip->lock);
795 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
796 clk_disable(nmk_chip->clk);
797
798 return 0;
799 }
800
801 static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
802 {
803 bool enabled = !irqd_irq_disabled(d);
804 bool wake = irqd_is_wakeup_set(d);
805 struct nmk_gpio_chip *nmk_chip;
806 unsigned long flags;
807 u32 bitmask;
808
809 nmk_chip = irq_data_get_irq_chip_data(d);
810 bitmask = nmk_gpio_get_bitmask(d->hwirq);
811 if (!nmk_chip)
812 return -EINVAL;
813 if (type & IRQ_TYPE_LEVEL_HIGH)
814 return -EINVAL;
815 if (type & IRQ_TYPE_LEVEL_LOW)
816 return -EINVAL;
817
818 clk_enable(nmk_chip->clk);
819 spin_lock_irqsave(&nmk_chip->lock, flags);
820
821 if (enabled)
822 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false);
823
824 if (enabled || wake)
825 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false);
826
827 nmk_chip->edge_rising &= ~bitmask;
828 if (type & IRQ_TYPE_EDGE_RISING)
829 nmk_chip->edge_rising |= bitmask;
830
831 nmk_chip->edge_falling &= ~bitmask;
832 if (type & IRQ_TYPE_EDGE_FALLING)
833 nmk_chip->edge_falling |= bitmask;
834
835 if (enabled)
836 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true);
837
838 if (enabled || wake)
839 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true);
840
841 spin_unlock_irqrestore(&nmk_chip->lock, flags);
842 clk_disable(nmk_chip->clk);
843
844 return 0;
845 }
846
847 static unsigned int nmk_gpio_irq_startup(struct irq_data *d)
848 {
849 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
850
851 if (gpio_lock_as_irq(&nmk_chip->chip, d->hwirq))
852 dev_err(nmk_chip->chip.dev,
853 "unable to lock HW IRQ %lu for IRQ\n",
854 d->hwirq);
855 clk_enable(nmk_chip->clk);
856 nmk_gpio_irq_unmask(d);
857 return 0;
858 }
859
860 static void nmk_gpio_irq_shutdown(struct irq_data *d)
861 {
862 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
863
864 nmk_gpio_irq_mask(d);
865 clk_disable(nmk_chip->clk);
866 gpio_unlock_as_irq(&nmk_chip->chip, d->hwirq);
867 }
868
869 static struct irq_chip nmk_gpio_irq_chip = {
870 .name = "Nomadik-GPIO",
871 .irq_ack = nmk_gpio_irq_ack,
872 .irq_mask = nmk_gpio_irq_mask,
873 .irq_unmask = nmk_gpio_irq_unmask,
874 .irq_set_type = nmk_gpio_irq_set_type,
875 .irq_set_wake = nmk_gpio_irq_set_wake,
876 .irq_startup = nmk_gpio_irq_startup,
877 .irq_shutdown = nmk_gpio_irq_shutdown,
878 .flags = IRQCHIP_MASK_ON_SUSPEND,
879 };
880
881 static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
882 u32 status)
883 {
884 struct nmk_gpio_chip *nmk_chip;
885 struct irq_chip *host_chip = irq_get_chip(irq);
886
887 chained_irq_enter(host_chip, desc);
888
889 nmk_chip = irq_get_handler_data(irq);
890 while (status) {
891 int bit = __ffs(status);
892
893 generic_handle_irq(irq_find_mapping(nmk_chip->domain, bit));
894 status &= ~BIT(bit);
895 }
896
897 chained_irq_exit(host_chip, desc);
898 }
899
900 static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
901 {
902 struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
903 u32 status;
904
905 clk_enable(nmk_chip->clk);
906 status = readl(nmk_chip->addr + NMK_GPIO_IS);
907 clk_disable(nmk_chip->clk);
908
909 __nmk_gpio_irq_handler(irq, desc, status);
910 }
911
912 static void nmk_gpio_secondary_irq_handler(unsigned int irq,
913 struct irq_desc *desc)
914 {
915 struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
916 u32 status = nmk_chip->get_secondary_status(nmk_chip->bank);
917
918 __nmk_gpio_irq_handler(irq, desc, status);
919 }
920
921 static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip)
922 {
923 irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler);
924 irq_set_handler_data(nmk_chip->parent_irq, nmk_chip);
925
926 if (nmk_chip->secondary_parent_irq >= 0) {
927 irq_set_chained_handler(nmk_chip->secondary_parent_irq,
928 nmk_gpio_secondary_irq_handler);
929 irq_set_handler_data(nmk_chip->secondary_parent_irq, nmk_chip);
930 }
931
932 return 0;
933 }
934
935 /* I/O Functions */
936
937 static int nmk_gpio_request(struct gpio_chip *chip, unsigned offset)
938 {
939 /*
940 * Map back to global GPIO space and request muxing, the direction
941 * parameter does not matter for this controller.
942 */
943 int gpio = chip->base + offset;
944
945 return pinctrl_request_gpio(gpio);
946 }
947
948 static void nmk_gpio_free(struct gpio_chip *chip, unsigned offset)
949 {
950 int gpio = chip->base + offset;
951
952 pinctrl_free_gpio(gpio);
953 }
954
955 static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset)
956 {
957 struct nmk_gpio_chip *nmk_chip =
958 container_of(chip, struct nmk_gpio_chip, chip);
959
960 clk_enable(nmk_chip->clk);
961
962 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
963
964 clk_disable(nmk_chip->clk);
965
966 return 0;
967 }
968
969 static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset)
970 {
971 struct nmk_gpio_chip *nmk_chip =
972 container_of(chip, struct nmk_gpio_chip, chip);
973 u32 bit = 1 << offset;
974 int value;
975
976 clk_enable(nmk_chip->clk);
977
978 value = (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0;
979
980 clk_disable(nmk_chip->clk);
981
982 return value;
983 }
984
985 static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset,
986 int val)
987 {
988 struct nmk_gpio_chip *nmk_chip =
989 container_of(chip, struct nmk_gpio_chip, chip);
990
991 clk_enable(nmk_chip->clk);
992
993 __nmk_gpio_set_output(nmk_chip, offset, val);
994
995 clk_disable(nmk_chip->clk);
996 }
997
998 static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
999 int val)
1000 {
1001 struct nmk_gpio_chip *nmk_chip =
1002 container_of(chip, struct nmk_gpio_chip, chip);
1003
1004 clk_enable(nmk_chip->clk);
1005
1006 __nmk_gpio_make_output(nmk_chip, offset, val);
1007
1008 clk_disable(nmk_chip->clk);
1009
1010 return 0;
1011 }
1012
1013 static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
1014 {
1015 struct nmk_gpio_chip *nmk_chip =
1016 container_of(chip, struct nmk_gpio_chip, chip);
1017
1018 return irq_create_mapping(nmk_chip->domain, offset);
1019 }
1020
1021 #ifdef CONFIG_DEBUG_FS
1022
1023 #include <linux/seq_file.h>
1024
1025 static void nmk_gpio_dbg_show_one(struct seq_file *s,
1026 struct pinctrl_dev *pctldev, struct gpio_chip *chip,
1027 unsigned offset, unsigned gpio)
1028 {
1029 const char *label = gpiochip_is_requested(chip, offset);
1030 struct nmk_gpio_chip *nmk_chip =
1031 container_of(chip, struct nmk_gpio_chip, chip);
1032 int mode;
1033 bool is_out;
1034 bool pull;
1035 u32 bit = 1 << offset;
1036 const char *modes[] = {
1037 [NMK_GPIO_ALT_GPIO] = "gpio",
1038 [NMK_GPIO_ALT_A] = "altA",
1039 [NMK_GPIO_ALT_B] = "altB",
1040 [NMK_GPIO_ALT_C] = "altC",
1041 [NMK_GPIO_ALT_C+1] = "altC1",
1042 [NMK_GPIO_ALT_C+2] = "altC2",
1043 [NMK_GPIO_ALT_C+3] = "altC3",
1044 [NMK_GPIO_ALT_C+4] = "altC4",
1045 };
1046
1047 clk_enable(nmk_chip->clk);
1048 is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & bit);
1049 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit);
1050 mode = nmk_gpio_get_mode(gpio);
1051 if ((mode == NMK_GPIO_ALT_C) && pctldev)
1052 mode = nmk_prcm_gpiocr_get_mode(pctldev, gpio);
1053
1054 seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s",
1055 gpio, label ?: "(none)",
1056 is_out ? "out" : "in ",
1057 chip->get
1058 ? (chip->get(chip, offset) ? "hi" : "lo")
1059 : "? ",
1060 (mode < 0) ? "unknown" : modes[mode],
1061 pull ? "pull" : "none");
1062
1063 if (!is_out) {
1064 int irq = gpio_to_irq(gpio);
1065 struct irq_desc *desc = irq_to_desc(irq);
1066
1067 /* This races with request_irq(), set_irq_type(),
1068 * and set_irq_wake() ... but those are "rare".
1069 */
1070 if (irq > 0 && desc && desc->action) {
1071 char *trigger;
1072 u32 bitmask = nmk_gpio_get_bitmask(gpio);
1073
1074 if (nmk_chip->edge_rising & bitmask)
1075 trigger = "edge-rising";
1076 else if (nmk_chip->edge_falling & bitmask)
1077 trigger = "edge-falling";
1078 else
1079 trigger = "edge-undefined";
1080
1081 seq_printf(s, " irq-%d %s%s",
1082 irq, trigger,
1083 irqd_is_wakeup_set(&desc->irq_data)
1084 ? " wakeup" : "");
1085 }
1086 }
1087 clk_disable(nmk_chip->clk);
1088 }
1089
1090 static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1091 {
1092 unsigned i;
1093 unsigned gpio = chip->base;
1094
1095 for (i = 0; i < chip->ngpio; i++, gpio++) {
1096 nmk_gpio_dbg_show_one(s, NULL, chip, i, gpio);
1097 seq_printf(s, "\n");
1098 }
1099 }
1100
1101 #else
1102 static inline void nmk_gpio_dbg_show_one(struct seq_file *s,
1103 struct pinctrl_dev *pctldev,
1104 struct gpio_chip *chip,
1105 unsigned offset, unsigned gpio)
1106 {
1107 }
1108 #define nmk_gpio_dbg_show NULL
1109 #endif
1110
1111 /* This structure is replicated for each GPIO block allocated at probe time */
1112 static struct gpio_chip nmk_gpio_template = {
1113 .request = nmk_gpio_request,
1114 .free = nmk_gpio_free,
1115 .direction_input = nmk_gpio_make_input,
1116 .get = nmk_gpio_get_input,
1117 .direction_output = nmk_gpio_make_output,
1118 .set = nmk_gpio_set_output,
1119 .to_irq = nmk_gpio_to_irq,
1120 .dbg_show = nmk_gpio_dbg_show,
1121 .can_sleep = false,
1122 };
1123
1124 void nmk_gpio_clocks_enable(void)
1125 {
1126 int i;
1127
1128 for (i = 0; i < NUM_BANKS; i++) {
1129 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1130
1131 if (!chip)
1132 continue;
1133
1134 clk_enable(chip->clk);
1135 }
1136 }
1137
1138 void nmk_gpio_clocks_disable(void)
1139 {
1140 int i;
1141
1142 for (i = 0; i < NUM_BANKS; i++) {
1143 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1144
1145 if (!chip)
1146 continue;
1147
1148 clk_disable(chip->clk);
1149 }
1150 }
1151
1152 /*
1153 * Called from the suspend/resume path to only keep the real wakeup interrupts
1154 * (those that have had set_irq_wake() called on them) as wakeup interrupts,
1155 * and not the rest of the interrupts which we needed to have as wakeups for
1156 * cpuidle.
1157 *
1158 * PM ops are not used since this needs to be done at the end, after all the
1159 * other drivers are done with their suspend callbacks.
1160 */
1161 void nmk_gpio_wakeups_suspend(void)
1162 {
1163 int i;
1164
1165 for (i = 0; i < NUM_BANKS; i++) {
1166 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1167
1168 if (!chip)
1169 break;
1170
1171 clk_enable(chip->clk);
1172
1173 writel(chip->rwimsc & chip->real_wake,
1174 chip->addr + NMK_GPIO_RWIMSC);
1175 writel(chip->fwimsc & chip->real_wake,
1176 chip->addr + NMK_GPIO_FWIMSC);
1177
1178 clk_disable(chip->clk);
1179 }
1180 }
1181
1182 void nmk_gpio_wakeups_resume(void)
1183 {
1184 int i;
1185
1186 for (i = 0; i < NUM_BANKS; i++) {
1187 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1188
1189 if (!chip)
1190 break;
1191
1192 clk_enable(chip->clk);
1193
1194 writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC);
1195 writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC);
1196
1197 clk_disable(chip->clk);
1198 }
1199 }
1200
1201 /*
1202 * Read the pull up/pull down status.
1203 * A bit set in 'pull_up' means that pull up
1204 * is selected if pull is enabled in PDIS register.
1205 * Note: only pull up/down set via this driver can
1206 * be detected due to HW limitations.
1207 */
1208 void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up)
1209 {
1210 if (gpio_bank < NUM_BANKS) {
1211 struct nmk_gpio_chip *chip = nmk_gpio_chips[gpio_bank];
1212
1213 if (!chip)
1214 return;
1215
1216 *pull_up = chip->pull_up;
1217 }
1218 }
1219
1220 static int nmk_gpio_irq_map(struct irq_domain *d, unsigned int irq,
1221 irq_hw_number_t hwirq)
1222 {
1223 struct nmk_gpio_chip *nmk_chip = d->host_data;
1224
1225 if (!nmk_chip)
1226 return -EINVAL;
1227
1228 irq_set_chip_and_handler(irq, &nmk_gpio_irq_chip, handle_edge_irq);
1229 set_irq_flags(irq, IRQF_VALID);
1230 irq_set_chip_data(irq, nmk_chip);
1231 irq_set_irq_type(irq, IRQ_TYPE_EDGE_FALLING);
1232
1233 return 0;
1234 }
1235
1236 static const struct irq_domain_ops nmk_gpio_irq_simple_ops = {
1237 .map = nmk_gpio_irq_map,
1238 .xlate = irq_domain_xlate_twocell,
1239 };
1240
1241 static int nmk_gpio_probe(struct platform_device *dev)
1242 {
1243 struct nmk_gpio_platform_data *pdata;
1244 struct device_node *np = dev->dev.of_node;
1245 struct nmk_gpio_chip *nmk_chip;
1246 struct gpio_chip *chip;
1247 struct resource *res;
1248 struct clk *clk;
1249 int secondary_irq;
1250 void __iomem *base;
1251 int irq;
1252 int ret;
1253
1254 pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL);
1255 if (!pdata)
1256 return -ENOMEM;
1257
1258 if (of_get_property(np, "st,supports-sleepmode", NULL))
1259 pdata->supports_sleepmode = true;
1260
1261 if (of_property_read_u32(np, "gpio-bank", &dev->id)) {
1262 dev_err(&dev->dev, "gpio-bank property not found\n");
1263 return -EINVAL;
1264 }
1265
1266 pdata->first_gpio = dev->id * NMK_GPIO_PER_CHIP;
1267 pdata->num_gpio = NMK_GPIO_PER_CHIP;
1268
1269 irq = platform_get_irq(dev, 0);
1270 if (irq < 0)
1271 return irq;
1272
1273 secondary_irq = platform_get_irq(dev, 1);
1274 if (secondary_irq >= 0 && !pdata->get_secondary_status)
1275 return -EINVAL;
1276
1277 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1278 base = devm_ioremap_resource(&dev->dev, res);
1279 if (IS_ERR(base))
1280 return PTR_ERR(base);
1281
1282 clk = devm_clk_get(&dev->dev, NULL);
1283 if (IS_ERR(clk))
1284 return PTR_ERR(clk);
1285 clk_prepare(clk);
1286
1287 nmk_chip = devm_kzalloc(&dev->dev, sizeof(*nmk_chip), GFP_KERNEL);
1288 if (!nmk_chip)
1289 return -ENOMEM;
1290
1291 /*
1292 * The virt address in nmk_chip->addr is in the nomadik register space,
1293 * so we can simply convert the resource address, without remapping
1294 */
1295 nmk_chip->bank = dev->id;
1296 nmk_chip->clk = clk;
1297 nmk_chip->addr = base;
1298 nmk_chip->chip = nmk_gpio_template;
1299 nmk_chip->parent_irq = irq;
1300 nmk_chip->secondary_parent_irq = secondary_irq;
1301 nmk_chip->get_secondary_status = pdata->get_secondary_status;
1302 nmk_chip->set_ioforce = pdata->set_ioforce;
1303 nmk_chip->sleepmode = pdata->supports_sleepmode;
1304 spin_lock_init(&nmk_chip->lock);
1305
1306 chip = &nmk_chip->chip;
1307 chip->base = pdata->first_gpio;
1308 chip->ngpio = pdata->num_gpio;
1309 chip->label = pdata->name ?: dev_name(&dev->dev);
1310 chip->dev = &dev->dev;
1311 chip->owner = THIS_MODULE;
1312
1313 clk_enable(nmk_chip->clk);
1314 nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI);
1315 clk_disable(nmk_chip->clk);
1316 chip->of_node = np;
1317
1318 ret = gpiochip_add(&nmk_chip->chip);
1319 if (ret)
1320 return ret;
1321
1322 BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));
1323
1324 nmk_gpio_chips[nmk_chip->bank] = nmk_chip;
1325
1326 platform_set_drvdata(dev, nmk_chip);
1327
1328 nmk_chip->domain = irq_domain_add_simple(np,
1329 NMK_GPIO_PER_CHIP, 0,
1330 &nmk_gpio_irq_simple_ops, nmk_chip);
1331 if (!nmk_chip->domain) {
1332 dev_err(&dev->dev, "failed to create irqdomain\n");
1333 /* Just do this, no matter if it fails */
1334 ret = gpiochip_remove(&nmk_chip->chip);
1335 return -ENOSYS;
1336 }
1337
1338 nmk_gpio_init_irq(nmk_chip);
1339
1340 dev_info(&dev->dev, "at address %p\n", nmk_chip->addr);
1341
1342 return 0;
1343 }
1344
1345 static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev)
1346 {
1347 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1348
1349 return npct->soc->ngroups;
1350 }
1351
1352 static const char *nmk_get_group_name(struct pinctrl_dev *pctldev,
1353 unsigned selector)
1354 {
1355 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1356
1357 return npct->soc->groups[selector].name;
1358 }
1359
1360 static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
1361 const unsigned **pins,
1362 unsigned *num_pins)
1363 {
1364 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1365
1366 *pins = npct->soc->groups[selector].pins;
1367 *num_pins = npct->soc->groups[selector].npins;
1368 return 0;
1369 }
1370
1371 static struct pinctrl_gpio_range *
1372 nmk_match_gpio_range(struct pinctrl_dev *pctldev, unsigned offset)
1373 {
1374 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1375 int i;
1376
1377 for (i = 0; i < npct->soc->gpio_num_ranges; i++) {
1378 struct pinctrl_gpio_range *range;
1379
1380 range = &npct->soc->gpio_ranges[i];
1381 if (offset >= range->pin_base &&
1382 offset <= (range->pin_base + range->npins - 1))
1383 return range;
1384 }
1385 return NULL;
1386 }
1387
1388 static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
1389 unsigned offset)
1390 {
1391 struct pinctrl_gpio_range *range;
1392 struct gpio_chip *chip;
1393
1394 range = nmk_match_gpio_range(pctldev, offset);
1395 if (!range || !range->gc) {
1396 seq_printf(s, "invalid pin offset");
1397 return;
1398 }
1399 chip = range->gc;
1400 nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset);
1401 }
1402
1403 static void nmk_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
1404 struct pinctrl_map *map, unsigned num_maps)
1405 {
1406 int i;
1407
1408 for (i = 0; i < num_maps; i++)
1409 if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
1410 kfree(map[i].data.configs.configs);
1411 kfree(map);
1412 }
1413
1414 static int nmk_dt_reserve_map(struct pinctrl_map **map, unsigned *reserved_maps,
1415 unsigned *num_maps, unsigned reserve)
1416 {
1417 unsigned old_num = *reserved_maps;
1418 unsigned new_num = *num_maps + reserve;
1419 struct pinctrl_map *new_map;
1420
1421 if (old_num >= new_num)
1422 return 0;
1423
1424 new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
1425 if (!new_map)
1426 return -ENOMEM;
1427
1428 memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
1429
1430 *map = new_map;
1431 *reserved_maps = new_num;
1432
1433 return 0;
1434 }
1435
1436 static int nmk_dt_add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps,
1437 unsigned *num_maps, const char *group,
1438 const char *function)
1439 {
1440 if (*num_maps == *reserved_maps)
1441 return -ENOSPC;
1442
1443 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
1444 (*map)[*num_maps].data.mux.group = group;
1445 (*map)[*num_maps].data.mux.function = function;
1446 (*num_maps)++;
1447
1448 return 0;
1449 }
1450
1451 static int nmk_dt_add_map_configs(struct pinctrl_map **map,
1452 unsigned *reserved_maps,
1453 unsigned *num_maps, const char *group,
1454 unsigned long *configs, unsigned num_configs)
1455 {
1456 unsigned long *dup_configs;
1457
1458 if (*num_maps == *reserved_maps)
1459 return -ENOSPC;
1460
1461 dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
1462 GFP_KERNEL);
1463 if (!dup_configs)
1464 return -ENOMEM;
1465
1466 (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN;
1467
1468 (*map)[*num_maps].data.configs.group_or_pin = group;
1469 (*map)[*num_maps].data.configs.configs = dup_configs;
1470 (*map)[*num_maps].data.configs.num_configs = num_configs;
1471 (*num_maps)++;
1472
1473 return 0;
1474 }
1475
1476 #define NMK_CONFIG_PIN(x, y) { .property = x, .config = y, }
1477 #define NMK_CONFIG_PIN_ARRAY(x, y) { .property = x, .choice = y, \
1478 .size = ARRAY_SIZE(y), }
1479
1480 static const unsigned long nmk_pin_input_modes[] = {
1481 PIN_INPUT_NOPULL,
1482 PIN_INPUT_PULLUP,
1483 PIN_INPUT_PULLDOWN,
1484 };
1485
1486 static const unsigned long nmk_pin_output_modes[] = {
1487 PIN_OUTPUT_LOW,
1488 PIN_OUTPUT_HIGH,
1489 PIN_DIR_OUTPUT,
1490 };
1491
1492 static const unsigned long nmk_pin_sleep_modes[] = {
1493 PIN_SLEEPMODE_DISABLED,
1494 PIN_SLEEPMODE_ENABLED,
1495 };
1496
1497 static const unsigned long nmk_pin_sleep_input_modes[] = {
1498 PIN_SLPM_INPUT_NOPULL,
1499 PIN_SLPM_INPUT_PULLUP,
1500 PIN_SLPM_INPUT_PULLDOWN,
1501 PIN_SLPM_DIR_INPUT,
1502 };
1503
1504 static const unsigned long nmk_pin_sleep_output_modes[] = {
1505 PIN_SLPM_OUTPUT_LOW,
1506 PIN_SLPM_OUTPUT_HIGH,
1507 PIN_SLPM_DIR_OUTPUT,
1508 };
1509
1510 static const unsigned long nmk_pin_sleep_wakeup_modes[] = {
1511 PIN_SLPM_WAKEUP_DISABLE,
1512 PIN_SLPM_WAKEUP_ENABLE,
1513 };
1514
1515 static const unsigned long nmk_pin_gpio_modes[] = {
1516 PIN_GPIOMODE_DISABLED,
1517 PIN_GPIOMODE_ENABLED,
1518 };
1519
1520 static const unsigned long nmk_pin_sleep_pdis_modes[] = {
1521 PIN_SLPM_PDIS_DISABLED,
1522 PIN_SLPM_PDIS_ENABLED,
1523 };
1524
1525 struct nmk_cfg_param {
1526 const char *property;
1527 unsigned long config;
1528 const unsigned long *choice;
1529 int size;
1530 };
1531
1532 static const struct nmk_cfg_param nmk_cfg_params[] = {
1533 NMK_CONFIG_PIN_ARRAY("ste,input", nmk_pin_input_modes),
1534 NMK_CONFIG_PIN_ARRAY("ste,output", nmk_pin_output_modes),
1535 NMK_CONFIG_PIN_ARRAY("ste,sleep", nmk_pin_sleep_modes),
1536 NMK_CONFIG_PIN_ARRAY("ste,sleep-input", nmk_pin_sleep_input_modes),
1537 NMK_CONFIG_PIN_ARRAY("ste,sleep-output", nmk_pin_sleep_output_modes),
1538 NMK_CONFIG_PIN_ARRAY("ste,sleep-wakeup", nmk_pin_sleep_wakeup_modes),
1539 NMK_CONFIG_PIN_ARRAY("ste,gpio", nmk_pin_gpio_modes),
1540 NMK_CONFIG_PIN_ARRAY("ste,sleep-pull-disable", nmk_pin_sleep_pdis_modes),
1541 };
1542
1543 static int nmk_dt_pin_config(int index, int val, unsigned long *config)
1544 {
1545 int ret = 0;
1546
1547 if (nmk_cfg_params[index].choice == NULL)
1548 *config = nmk_cfg_params[index].config;
1549 else {
1550 /* test if out of range */
1551 if (val < nmk_cfg_params[index].size) {
1552 *config = nmk_cfg_params[index].config |
1553 nmk_cfg_params[index].choice[val];
1554 }
1555 }
1556 return ret;
1557 }
1558
1559 static const char *nmk_find_pin_name(struct pinctrl_dev *pctldev, const char *pin_name)
1560 {
1561 int i, pin_number;
1562 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1563
1564 if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1)
1565 for (i = 0; i < npct->soc->npins; i++)
1566 if (npct->soc->pins[i].number == pin_number)
1567 return npct->soc->pins[i].name;
1568 return NULL;
1569 }
1570
1571 static bool nmk_pinctrl_dt_get_config(struct device_node *np,
1572 unsigned long *configs)
1573 {
1574 bool has_config = 0;
1575 unsigned long cfg = 0;
1576 int i, val, ret;
1577
1578 for (i = 0; i < ARRAY_SIZE(nmk_cfg_params); i++) {
1579 ret = of_property_read_u32(np,
1580 nmk_cfg_params[i].property, &val);
1581 if (ret != -EINVAL) {
1582 if (nmk_dt_pin_config(i, val, &cfg) == 0) {
1583 *configs |= cfg;
1584 has_config = 1;
1585 }
1586 }
1587 }
1588
1589 return has_config;
1590 }
1591
1592 static int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
1593 struct device_node *np,
1594 struct pinctrl_map **map,
1595 unsigned *reserved_maps,
1596 unsigned *num_maps)
1597 {
1598 int ret;
1599 const char *function = NULL;
1600 unsigned long configs = 0;
1601 bool has_config = 0;
1602 unsigned reserve = 0;
1603 struct property *prop;
1604 const char *group, *gpio_name;
1605 struct device_node *np_config;
1606
1607 ret = of_property_read_string(np, "ste,function", &function);
1608 if (ret >= 0)
1609 reserve = 1;
1610
1611 has_config = nmk_pinctrl_dt_get_config(np, &configs);
1612
1613 np_config = of_parse_phandle(np, "ste,config", 0);
1614 if (np_config)
1615 has_config |= nmk_pinctrl_dt_get_config(np_config, &configs);
1616
1617 ret = of_property_count_strings(np, "ste,pins");
1618 if (ret < 0)
1619 goto exit;
1620
1621 if (has_config)
1622 reserve++;
1623
1624 reserve *= ret;
1625
1626 ret = nmk_dt_reserve_map(map, reserved_maps, num_maps, reserve);
1627 if (ret < 0)
1628 goto exit;
1629
1630 of_property_for_each_string(np, "ste,pins", prop, group) {
1631 if (function) {
1632 ret = nmk_dt_add_map_mux(map, reserved_maps, num_maps,
1633 group, function);
1634 if (ret < 0)
1635 goto exit;
1636 }
1637 if (has_config) {
1638 gpio_name = nmk_find_pin_name(pctldev, group);
1639
1640 ret = nmk_dt_add_map_configs(map, reserved_maps, num_maps,
1641 gpio_name, &configs, 1);
1642 if (ret < 0)
1643 goto exit;
1644 }
1645
1646 }
1647 exit:
1648 return ret;
1649 }
1650
1651 static int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
1652 struct device_node *np_config,
1653 struct pinctrl_map **map, unsigned *num_maps)
1654 {
1655 unsigned reserved_maps;
1656 struct device_node *np;
1657 int ret;
1658
1659 reserved_maps = 0;
1660 *map = NULL;
1661 *num_maps = 0;
1662
1663 for_each_child_of_node(np_config, np) {
1664 ret = nmk_pinctrl_dt_subnode_to_map(pctldev, np, map,
1665 &reserved_maps, num_maps);
1666 if (ret < 0) {
1667 nmk_pinctrl_dt_free_map(pctldev, *map, *num_maps);
1668 return ret;
1669 }
1670 }
1671
1672 return 0;
1673 }
1674
1675 static const struct pinctrl_ops nmk_pinctrl_ops = {
1676 .get_groups_count = nmk_get_groups_cnt,
1677 .get_group_name = nmk_get_group_name,
1678 .get_group_pins = nmk_get_group_pins,
1679 .pin_dbg_show = nmk_pin_dbg_show,
1680 .dt_node_to_map = nmk_pinctrl_dt_node_to_map,
1681 .dt_free_map = nmk_pinctrl_dt_free_map,
1682 };
1683
1684 static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
1685 {
1686 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1687
1688 return npct->soc->nfunctions;
1689 }
1690
1691 static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev,
1692 unsigned function)
1693 {
1694 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1695
1696 return npct->soc->functions[function].name;
1697 }
1698
1699 static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
1700 unsigned function,
1701 const char * const **groups,
1702 unsigned * const num_groups)
1703 {
1704 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1705
1706 *groups = npct->soc->functions[function].groups;
1707 *num_groups = npct->soc->functions[function].ngroups;
1708
1709 return 0;
1710 }
1711
1712 static int nmk_pmx_enable(struct pinctrl_dev *pctldev, unsigned function,
1713 unsigned group)
1714 {
1715 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1716 const struct nmk_pingroup *g;
1717 static unsigned int slpm[NUM_BANKS];
1718 unsigned long flags = 0;
1719 bool glitch;
1720 int ret = -EINVAL;
1721 int i;
1722
1723 g = &npct->soc->groups[group];
1724
1725 if (g->altsetting < 0)
1726 return -EINVAL;
1727
1728 dev_dbg(npct->dev, "enable group %s, %u pins\n", g->name, g->npins);
1729
1730 /*
1731 * If we're setting altfunc C by setting both AFSLA and AFSLB to 1,
1732 * we may pass through an undesired state. In this case we take
1733 * some extra care.
1734 *
1735 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
1736 * - Save SLPM registers (since we have a shadow register in the
1737 * nmk_chip we're using that as backup)
1738 * - Set SLPM=0 for the IOs you want to switch and others to 1
1739 * - Configure the GPIO registers for the IOs that are being switched
1740 * - Set IOFORCE=1
1741 * - Modify the AFLSA/B registers for the IOs that are being switched
1742 * - Set IOFORCE=0
1743 * - Restore SLPM registers
1744 * - Any spurious wake up event during switch sequence to be ignored
1745 * and cleared
1746 *
1747 * We REALLY need to save ALL slpm registers, because the external
1748 * IOFORCE will switch *all* ports to their sleepmode setting to as
1749 * to avoid glitches. (Not just one port!)
1750 */
1751 glitch = ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C);
1752
1753 if (glitch) {
1754 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
1755
1756 /* Initially don't put any pins to sleep when switching */
1757 memset(slpm, 0xff, sizeof(slpm));
1758
1759 /*
1760 * Then mask the pins that need to be sleeping now when we're
1761 * switching to the ALT C function.
1762 */
1763 for (i = 0; i < g->npins; i++)
1764 slpm[g->pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->pins[i]);
1765 nmk_gpio_glitch_slpm_init(slpm);
1766 }
1767
1768 for (i = 0; i < g->npins; i++) {
1769 struct pinctrl_gpio_range *range;
1770 struct nmk_gpio_chip *nmk_chip;
1771 struct gpio_chip *chip;
1772 unsigned bit;
1773
1774 range = nmk_match_gpio_range(pctldev, g->pins[i]);
1775 if (!range) {
1776 dev_err(npct->dev,
1777 "invalid pin offset %d in group %s at index %d\n",
1778 g->pins[i], g->name, i);
1779 goto out_glitch;
1780 }
1781 if (!range->gc) {
1782 dev_err(npct->dev, "GPIO chip missing in range for pin offset %d in group %s at index %d\n",
1783 g->pins[i], g->name, i);
1784 goto out_glitch;
1785 }
1786 chip = range->gc;
1787 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1788 dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting);
1789
1790 clk_enable(nmk_chip->clk);
1791 bit = g->pins[i] % NMK_GPIO_PER_CHIP;
1792 /*
1793 * If the pin is switching to altfunc, and there was an
1794 * interrupt installed on it which has been lazy disabled,
1795 * actually mask the interrupt to prevent spurious interrupts
1796 * that would occur while the pin is under control of the
1797 * peripheral. Only SKE does this.
1798 */
1799 nmk_gpio_disable_lazy_irq(nmk_chip, bit);
1800
1801 __nmk_gpio_set_mode_safe(nmk_chip, bit,
1802 (g->altsetting & NMK_GPIO_ALT_C), glitch);
1803 clk_disable(nmk_chip->clk);
1804
1805 /*
1806 * Call PRCM GPIOCR config function in case ALTC
1807 * has been selected:
1808 * - If selection is a ALTCx, some bits in PRCM GPIOCR registers
1809 * must be set.
1810 * - If selection is pure ALTC and previous selection was ALTCx,
1811 * then some bits in PRCM GPIOCR registers must be cleared.
1812 */
1813 if ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C)
1814 nmk_prcm_altcx_set_mode(npct, g->pins[i],
1815 g->altsetting >> NMK_GPIO_ALT_CX_SHIFT);
1816 }
1817
1818 /* When all pins are successfully reconfigured we get here */
1819 ret = 0;
1820
1821 out_glitch:
1822 if (glitch) {
1823 nmk_gpio_glitch_slpm_restore(slpm);
1824 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
1825 }
1826
1827 return ret;
1828 }
1829
1830 static void nmk_pmx_disable(struct pinctrl_dev *pctldev,
1831 unsigned function, unsigned group)
1832 {
1833 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1834 const struct nmk_pingroup *g;
1835
1836 g = &npct->soc->groups[group];
1837
1838 if (g->altsetting < 0)
1839 return;
1840
1841 /* Poke out the mux, set the pin to some default state? */
1842 dev_dbg(npct->dev, "disable group %s, %u pins\n", g->name, g->npins);
1843 }
1844
1845 static int nmk_gpio_request_enable(struct pinctrl_dev *pctldev,
1846 struct pinctrl_gpio_range *range,
1847 unsigned offset)
1848 {
1849 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1850 struct nmk_gpio_chip *nmk_chip;
1851 struct gpio_chip *chip;
1852 unsigned bit;
1853
1854 if (!range) {
1855 dev_err(npct->dev, "invalid range\n");
1856 return -EINVAL;
1857 }
1858 if (!range->gc) {
1859 dev_err(npct->dev, "missing GPIO chip in range\n");
1860 return -EINVAL;
1861 }
1862 chip = range->gc;
1863 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1864
1865 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
1866
1867 clk_enable(nmk_chip->clk);
1868 bit = offset % NMK_GPIO_PER_CHIP;
1869 /* There is no glitch when converting any pin to GPIO */
1870 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1871 clk_disable(nmk_chip->clk);
1872
1873 return 0;
1874 }
1875
1876 static void nmk_gpio_disable_free(struct pinctrl_dev *pctldev,
1877 struct pinctrl_gpio_range *range,
1878 unsigned offset)
1879 {
1880 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1881
1882 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
1883 /* Set the pin to some default state, GPIO is usually default */
1884 }
1885
1886 static const struct pinmux_ops nmk_pinmux_ops = {
1887 .get_functions_count = nmk_pmx_get_funcs_cnt,
1888 .get_function_name = nmk_pmx_get_func_name,
1889 .get_function_groups = nmk_pmx_get_func_groups,
1890 .enable = nmk_pmx_enable,
1891 .disable = nmk_pmx_disable,
1892 .gpio_request_enable = nmk_gpio_request_enable,
1893 .gpio_disable_free = nmk_gpio_disable_free,
1894 };
1895
1896 static int nmk_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
1897 unsigned long *config)
1898 {
1899 /* Not implemented */
1900 return -EINVAL;
1901 }
1902
1903 static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
1904 unsigned long *configs, unsigned num_configs)
1905 {
1906 static const char *pullnames[] = {
1907 [NMK_GPIO_PULL_NONE] = "none",
1908 [NMK_GPIO_PULL_UP] = "up",
1909 [NMK_GPIO_PULL_DOWN] = "down",
1910 [3] /* illegal */ = "??"
1911 };
1912 static const char *slpmnames[] = {
1913 [NMK_GPIO_SLPM_INPUT] = "input/wakeup",
1914 [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup",
1915 };
1916 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1917 struct nmk_gpio_chip *nmk_chip;
1918 struct pinctrl_gpio_range *range;
1919 struct gpio_chip *chip;
1920 unsigned bit;
1921 pin_cfg_t cfg;
1922 int pull, slpm, output, val, i;
1923 bool lowemi, gpiomode, sleep;
1924
1925 range = nmk_match_gpio_range(pctldev, pin);
1926 if (!range) {
1927 dev_err(npct->dev, "invalid pin offset %d\n", pin);
1928 return -EINVAL;
1929 }
1930 if (!range->gc) {
1931 dev_err(npct->dev, "GPIO chip missing in range for pin %d\n",
1932 pin);
1933 return -EINVAL;
1934 }
1935 chip = range->gc;
1936 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1937
1938 for (i = 0; i < num_configs; i++) {
1939 /*
1940 * The pin config contains pin number and altfunction fields,
1941 * here we just ignore that part. It's being handled by the
1942 * framework and pinmux callback respectively.
1943 */
1944 cfg = (pin_cfg_t) configs[i];
1945 pull = PIN_PULL(cfg);
1946 slpm = PIN_SLPM(cfg);
1947 output = PIN_DIR(cfg);
1948 val = PIN_VAL(cfg);
1949 lowemi = PIN_LOWEMI(cfg);
1950 gpiomode = PIN_GPIOMODE(cfg);
1951 sleep = PIN_SLEEPMODE(cfg);
1952
1953 if (sleep) {
1954 int slpm_pull = PIN_SLPM_PULL(cfg);
1955 int slpm_output = PIN_SLPM_DIR(cfg);
1956 int slpm_val = PIN_SLPM_VAL(cfg);
1957
1958 /* All pins go into GPIO mode at sleep */
1959 gpiomode = true;
1960
1961 /*
1962 * The SLPM_* values are normal values + 1 to allow zero
1963 * to mean "same as normal".
1964 */
1965 if (slpm_pull)
1966 pull = slpm_pull - 1;
1967 if (slpm_output)
1968 output = slpm_output - 1;
1969 if (slpm_val)
1970 val = slpm_val - 1;
1971
1972 dev_dbg(nmk_chip->chip.dev,
1973 "pin %d: sleep pull %s, dir %s, val %s\n",
1974 pin,
1975 slpm_pull ? pullnames[pull] : "same",
1976 slpm_output ? (output ? "output" : "input")
1977 : "same",
1978 slpm_val ? (val ? "high" : "low") : "same");
1979 }
1980
1981 dev_dbg(nmk_chip->chip.dev,
1982 "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n",
1983 pin, cfg, pullnames[pull], slpmnames[slpm],
1984 output ? "output " : "input",
1985 output ? (val ? "high" : "low") : "",
1986 lowemi ? "on" : "off");
1987
1988 clk_enable(nmk_chip->clk);
1989 bit = pin % NMK_GPIO_PER_CHIP;
1990 if (gpiomode)
1991 /* No glitch when going to GPIO mode */
1992 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1993 if (output)
1994 __nmk_gpio_make_output(nmk_chip, bit, val);
1995 else {
1996 __nmk_gpio_make_input(nmk_chip, bit);
1997 __nmk_gpio_set_pull(nmk_chip, bit, pull);
1998 }
1999 /* TODO: isn't this only applicable on output pins? */
2000 __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi);
2001
2002 __nmk_gpio_set_slpm(nmk_chip, bit, slpm);
2003 clk_disable(nmk_chip->clk);
2004 } /* for each config */
2005
2006 return 0;
2007 }
2008
2009 static const struct pinconf_ops nmk_pinconf_ops = {
2010 .pin_config_get = nmk_pin_config_get,
2011 .pin_config_set = nmk_pin_config_set,
2012 };
2013
2014 static struct pinctrl_desc nmk_pinctrl_desc = {
2015 .name = "pinctrl-nomadik",
2016 .pctlops = &nmk_pinctrl_ops,
2017 .pmxops = &nmk_pinmux_ops,
2018 .confops = &nmk_pinconf_ops,
2019 .owner = THIS_MODULE,
2020 };
2021
2022 static const struct of_device_id nmk_pinctrl_match[] = {
2023 {
2024 .compatible = "stericsson,stn8815-pinctrl",
2025 .data = (void *)PINCTRL_NMK_STN8815,
2026 },
2027 {
2028 .compatible = "stericsson,db8500-pinctrl",
2029 .data = (void *)PINCTRL_NMK_DB8500,
2030 },
2031 {
2032 .compatible = "stericsson,db8540-pinctrl",
2033 .data = (void *)PINCTRL_NMK_DB8540,
2034 },
2035 {},
2036 };
2037
2038 static int nmk_pinctrl_suspend(struct platform_device *pdev, pm_message_t state)
2039 {
2040 struct nmk_pinctrl *npct;
2041
2042 npct = platform_get_drvdata(pdev);
2043 if (!npct)
2044 return -EINVAL;
2045
2046 return pinctrl_force_sleep(npct->pctl);
2047 }
2048
2049 static int nmk_pinctrl_resume(struct platform_device *pdev)
2050 {
2051 struct nmk_pinctrl *npct;
2052
2053 npct = platform_get_drvdata(pdev);
2054 if (!npct)
2055 return -EINVAL;
2056
2057 return pinctrl_force_default(npct->pctl);
2058 }
2059
2060 static int nmk_pinctrl_probe(struct platform_device *pdev)
2061 {
2062 const struct of_device_id *match;
2063 struct device_node *np = pdev->dev.of_node;
2064 struct device_node *prcm_np;
2065 struct nmk_pinctrl *npct;
2066 unsigned int version = 0;
2067 int i;
2068
2069 npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL);
2070 if (!npct)
2071 return -ENOMEM;
2072
2073 match = of_match_device(nmk_pinctrl_match, &pdev->dev);
2074 if (!match)
2075 return -ENODEV;
2076 version = (unsigned int) match->data;
2077
2078 /* Poke in other ASIC variants here */
2079 if (version == PINCTRL_NMK_STN8815)
2080 nmk_pinctrl_stn8815_init(&npct->soc);
2081 if (version == PINCTRL_NMK_DB8500)
2082 nmk_pinctrl_db8500_init(&npct->soc);
2083 if (version == PINCTRL_NMK_DB8540)
2084 nmk_pinctrl_db8540_init(&npct->soc);
2085
2086 prcm_np = of_parse_phandle(np, "prcm", 0);
2087 if (prcm_np)
2088 npct->prcm_base = of_iomap(prcm_np, 0);
2089 if (!npct->prcm_base) {
2090 if (version == PINCTRL_NMK_STN8815) {
2091 dev_info(&pdev->dev,
2092 "No PRCM base, "
2093 "assuming no ALT-Cx control is available\n");
2094 } else {
2095 dev_err(&pdev->dev, "missing PRCM base address\n");
2096 return -EINVAL;
2097 }
2098 }
2099
2100 /*
2101 * We need all the GPIO drivers to probe FIRST, or we will not be able
2102 * to obtain references to the struct gpio_chip * for them, and we
2103 * need this to proceed.
2104 */
2105 for (i = 0; i < npct->soc->gpio_num_ranges; i++) {
2106 if (!nmk_gpio_chips[npct->soc->gpio_ranges[i].id]) {
2107 dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i);
2108 return -EPROBE_DEFER;
2109 }
2110 npct->soc->gpio_ranges[i].gc = &nmk_gpio_chips[npct->soc->gpio_ranges[i].id]->chip;
2111 }
2112
2113 nmk_pinctrl_desc.pins = npct->soc->pins;
2114 nmk_pinctrl_desc.npins = npct->soc->npins;
2115 npct->dev = &pdev->dev;
2116
2117 npct->pctl = pinctrl_register(&nmk_pinctrl_desc, &pdev->dev, npct);
2118 if (!npct->pctl) {
2119 dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n");
2120 return -EINVAL;
2121 }
2122
2123 /* We will handle a range of GPIO pins */
2124 for (i = 0; i < npct->soc->gpio_num_ranges; i++)
2125 pinctrl_add_gpio_range(npct->pctl, &npct->soc->gpio_ranges[i]);
2126
2127 platform_set_drvdata(pdev, npct);
2128 dev_info(&pdev->dev, "initialized Nomadik pin control driver\n");
2129
2130 return 0;
2131 }
2132
2133 static const struct of_device_id nmk_gpio_match[] = {
2134 { .compatible = "st,nomadik-gpio", },
2135 {}
2136 };
2137
2138 static struct platform_driver nmk_gpio_driver = {
2139 .driver = {
2140 .owner = THIS_MODULE,
2141 .name = "gpio",
2142 .of_match_table = nmk_gpio_match,
2143 },
2144 .probe = nmk_gpio_probe,
2145 };
2146
2147 static struct platform_driver nmk_pinctrl_driver = {
2148 .driver = {
2149 .owner = THIS_MODULE,
2150 .name = "pinctrl-nomadik",
2151 .of_match_table = nmk_pinctrl_match,
2152 },
2153 .probe = nmk_pinctrl_probe,
2154 #ifdef CONFIG_PM
2155 .suspend = nmk_pinctrl_suspend,
2156 .resume = nmk_pinctrl_resume,
2157 #endif
2158 };
2159
2160 static int __init nmk_gpio_init(void)
2161 {
2162 int ret;
2163
2164 ret = platform_driver_register(&nmk_gpio_driver);
2165 if (ret)
2166 return ret;
2167 return platform_driver_register(&nmk_pinctrl_driver);
2168 }
2169
2170 core_initcall(nmk_gpio_init);
2171
2172 MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini");
2173 MODULE_DESCRIPTION("Nomadik GPIO Driver");
2174 MODULE_LICENSE("GPL");
Linux with added FPC-III support