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IB/rdmavt, IB/qib, IB/hfi1: Use new QP put get routines
[linux/fpc-iii.git] / drivers / phy / tegra / xusb-tegra210.c
blob9d0689ebd28c685d39e718583ead6a2c53959031
1 /*
2 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
3 * Copyright (C) 2015 Google, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 */
14
15 #include <linux/clk.h>
16 #include <linux/clk/tegra.h>
17 #include <linux/delay.h>
18 #include <linux/io.h>
19 #include <linux/mailbox_client.h>
20 #include <linux/module.h>
21 #include <linux/of.h>
22 #include <linux/phy/phy.h>
23 #include <linux/platform_device.h>
24 #include <linux/regulator/consumer.h>
25 #include <linux/reset.h>
26 #include <linux/slab.h>
27
28 #include <soc/tegra/fuse.h>
29
30 #include "xusb.h"
31
32 #define FUSE_SKU_CALIB_HS_CURR_LEVEL_PADX_SHIFT(x) \
33 ((x) ? (11 + ((x) - 1) * 6) : 0)
34 #define FUSE_SKU_CALIB_HS_CURR_LEVEL_PAD_MASK 0x3f
35 #define FUSE_SKU_CALIB_HS_TERM_RANGE_ADJ_SHIFT 7
36 #define FUSE_SKU_CALIB_HS_TERM_RANGE_ADJ_MASK 0xf
37
38 #define FUSE_USB_CALIB_EXT_RPD_CTRL_SHIFT 0
39 #define FUSE_USB_CALIB_EXT_RPD_CTRL_MASK 0x1f
40
41 #define XUSB_PADCTL_USB2_PAD_MUX 0x004
42 #define XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_SHIFT 16
43 #define XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_MASK 0x3
44 #define XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_XUSB 0x1
45 #define XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_SHIFT 18
46 #define XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_MASK 0x3
47 #define XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_XUSB 0x1
48
49 #define XUSB_PADCTL_USB2_PORT_CAP 0x008
50 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_HOST(x) (0x1 << ((x) * 4))
51 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_MASK(x) (0x3 << ((x) * 4))
52
53 #define XUSB_PADCTL_SS_PORT_MAP 0x014
54 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(x) (1 << (((x) * 5) + 4))
55 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_SHIFT(x) ((x) * 5)
56 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(x) (0x7 << ((x) * 5))
57 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(x, v) (((v) & 0x7) << ((x) * 5))
58
59 #define XUSB_PADCTL_ELPG_PROGRAM1 0x024
60 #define XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN (1 << 31)
61 #define XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 30)
62 #define XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN (1 << 29)
63 #define XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(x) (1 << (2 + (x) * 3))
64 #define XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(x) \
65 (1 << (1 + (x) * 3))
66 #define XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(x) (1 << ((x) * 3))
67
68 #define XUSB_PADCTL_USB3_PAD_MUX 0x028
69 #define XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(x) (1 << (1 + (x)))
70 #define XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(x) (1 << (8 + (x)))
71
72 #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL1(x) (0x084 + (x) * 0x40)
73 #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_SHIFT 7
74 #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_MASK 0x3
75 #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_FIX18 (1 << 6)
76
77 #define XUSB_PADCTL_USB2_OTG_PADX_CTL0(x) (0x088 + (x) * 0x40)
78 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD_ZI (1 << 29)
79 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD2 (1 << 27)
80 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD (1 << 26)
81 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_SHIFT 0
82 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_MASK 0x3f
83
84 #define XUSB_PADCTL_USB2_OTG_PADX_CTL1(x) (0x08c + (x) * 0x40)
85 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_RPD_CTRL_SHIFT 26
86 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_RPD_CTRL_MASK 0x1f
87 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ_SHIFT 3
88 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ_MASK 0xf
89 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR (1 << 2)
90 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DISC_OVRD (1 << 1)
91 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_CHRP_OVRD (1 << 0)
92
93 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0 0x284
94 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD (1 << 11)
95 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_SHIFT 3
96 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_MASK 0x7
97 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_VAL 0x7
98 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_SHIFT 0
99 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_MASK 0x7
100 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_VAL 0x2
101
102 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1 0x288
103 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_PD_TRK (1 << 26)
104 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_SHIFT 19
105 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_MASK 0x7f
106 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_VAL 0x0a
107 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_SHIFT 12
108 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_MASK 0x7f
109 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_VAL 0x1e
110
111 #define XUSB_PADCTL_HSIC_PADX_CTL0(x) (0x300 + (x) * 0x20)
112 #define XUSB_PADCTL_HSIC_PAD_CTL0_RPU_STROBE (1 << 18)
113 #define XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA1 (1 << 17)
114 #define XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA0 (1 << 16)
115 #define XUSB_PADCTL_HSIC_PAD_CTL0_RPD_STROBE (1 << 15)
116 #define XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA1 (1 << 14)
117 #define XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA0 (1 << 13)
118 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_STROBE (1 << 9)
119 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA1 (1 << 8)
120 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA0 (1 << 7)
121 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_STROBE (1 << 6)
122 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA1 (1 << 5)
123 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA0 (1 << 4)
124 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_STROBE (1 << 3)
125 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA1 (1 << 2)
126 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA0 (1 << 1)
127
128 #define XUSB_PADCTL_HSIC_PADX_CTL1(x) (0x304 + (x) * 0x20)
129 #define XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_SHIFT 0
130 #define XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_MASK 0xf
131
132 #define XUSB_PADCTL_HSIC_PADX_CTL2(x) (0x308 + (x) * 0x20)
133 #define XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_SHIFT 8
134 #define XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_MASK 0xf
135 #define XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_SHIFT 0
136 #define XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_MASK 0xff
137
138 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL 0x340
139 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL_PD_TRK (1 << 19)
140 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_SHIFT 12
141 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_MASK 0x7f
142 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_VAL 0x0a
143 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_SHIFT 5
144 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_MASK 0x7f
145 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_VAL 0x1e
146
147 #define XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL 0x344
148
149 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1 0x360
150 #define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SHIFT 20
151 #define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_MASK 0xff
152 #define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_USB_VAL 0x19
153 #define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SATA_VAL 0x1e
154 #define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_SHIFT 16
155 #define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_MASK 0x3
156 #define XUSB_PADCTL_UPHY_PLL_CTL1_LOCKDET_STATUS (1 << 15)
157 #define XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD (1 << 4)
158 #define XUSB_PADCTL_UPHY_PLL_CTL1_ENABLE (1 << 3)
159 #define XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_SHIFT 1
160 #define XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_MASK 0x3
161 #define XUSB_PADCTL_UPHY_PLL_CTL1_IDDQ (1 << 0)
162
163 #define XUSB_PADCTL_UPHY_PLL_P0_CTL2 0x364
164 #define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_SHIFT 4
165 #define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_MASK 0xffffff
166 #define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_VAL 0x136
167 #define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD (1 << 2)
168 #define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE (1 << 1)
169 #define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN (1 << 0)
170
171 #define XUSB_PADCTL_UPHY_PLL_P0_CTL4 0x36c
172 #define XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_EN (1 << 15)
173 #define XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SHIFT 12
174 #define XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_MASK 0x3
175 #define XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_USB_VAL 0x2
176 #define XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SATA_VAL 0x0
177 #define XUSB_PADCTL_UPHY_PLL_CTL4_REFCLKBUF_EN (1 << 8)
178 #define XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_SHIFT 4
179 #define XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_MASK 0xf
180
181 #define XUSB_PADCTL_UPHY_PLL_P0_CTL5 0x370
182 #define XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_SHIFT 16
183 #define XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_MASK 0xff
184 #define XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_VAL 0x2a
185
186 #define XUSB_PADCTL_UPHY_PLL_P0_CTL8 0x37c
187 #define XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE (1 << 31)
188 #define XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD (1 << 15)
189 #define XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN (1 << 13)
190 #define XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN (1 << 12)
191
192 #define XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL1(x) (0x460 + (x) * 0x40)
193 #define XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_SHIFT 20
194 #define XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_MASK 0x3
195 #define XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_VAL 0x1
196 #define XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_TERM_EN BIT(18)
197 #define XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_MODE_OVRD BIT(13)
198
199 #define XUSB_PADCTL_UPHY_PLL_S0_CTL1 0x860
200
201 #define XUSB_PADCTL_UPHY_PLL_S0_CTL2 0x864
202
203 #define XUSB_PADCTL_UPHY_PLL_S0_CTL4 0x86c
204
205 #define XUSB_PADCTL_UPHY_PLL_S0_CTL5 0x870
206
207 #define XUSB_PADCTL_UPHY_PLL_S0_CTL8 0x87c
208
209 #define XUSB_PADCTL_UPHY_MISC_PAD_S0_CTL1 0x960
210
211 #define XUSB_PADCTL_UPHY_USB3_PADX_ECTL1(x) (0xa60 + (x) * 0x40)
212 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_SHIFT 16
213 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_MASK 0x3
214 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_VAL 0x2
215
216 #define XUSB_PADCTL_UPHY_USB3_PADX_ECTL2(x) (0xa64 + (x) * 0x40)
217 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_SHIFT 0
218 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_MASK 0xffff
219 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_VAL 0x00fc
220
221 #define XUSB_PADCTL_UPHY_USB3_PADX_ECTL3(x) (0xa68 + (x) * 0x40)
222 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL3_RX_DFE_VAL 0xc0077f1f
223
224 #define XUSB_PADCTL_UPHY_USB3_PADX_ECTL4(x) (0xa6c + (x) * 0x40)
225 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_SHIFT 16
226 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_MASK 0xffff
227 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_VAL 0x01c7
228
229 #define XUSB_PADCTL_UPHY_USB3_PADX_ECTL6(x) (0xa74 + (x) * 0x40)
230 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL6_RX_EQ_CTRL_H_VAL 0xfcf01368
231
232 struct tegra210_xusb_fuse_calibration {
233 u32 hs_curr_level[4];
234 u32 hs_term_range_adj;
235 u32 rpd_ctrl;
236 };
237
238 struct tegra210_xusb_padctl {
239 struct tegra_xusb_padctl base;
240
241 struct tegra210_xusb_fuse_calibration fuse;
242 };
243
244 static inline struct tegra210_xusb_padctl *
245 to_tegra210_xusb_padctl(struct tegra_xusb_padctl *padctl)
246 {
247 return container_of(padctl, struct tegra210_xusb_padctl, base);
248 }
249
250 /* must be called under padctl->lock */
251 static int tegra210_pex_uphy_enable(struct tegra_xusb_padctl *padctl)
252 {
253 struct tegra_xusb_pcie_pad *pcie = to_pcie_pad(padctl->pcie);
254 unsigned long timeout;
255 u32 value;
256 int err;
257
258 if (pcie->enable > 0) {
259 pcie->enable++;
260 return 0;
261 }
262
263 err = clk_prepare_enable(pcie->pll);
264 if (err < 0)
265 return err;
266
267 err = reset_control_deassert(pcie->rst);
268 if (err < 0)
269 goto disable;
270
271 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
272 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_MASK <<
273 XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_SHIFT);
274 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_VAL <<
275 XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_SHIFT;
276 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
277
278 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL5);
279 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_MASK <<
280 XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_SHIFT);
281 value |= XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_VAL <<
282 XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_SHIFT;
283 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL5);
284
285 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
286 value |= XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD;
287 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
288
289 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
290 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD;
291 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
292
293 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
294 value |= XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD;
295 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
296
297 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
298 value &= ~((XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_MASK <<
299 XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SHIFT) |
300 (XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_MASK <<
301 XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_SHIFT));
302 value |= (XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_USB_VAL <<
303 XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SHIFT) |
304 XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_EN;
305 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
306
307 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
308 value &= ~((XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_MASK <<
309 XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_SHIFT) |
310 (XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_MASK <<
311 XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SHIFT));
312 value |= XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_USB_VAL <<
313 XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SHIFT;
314 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
315
316 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
317 value &= ~XUSB_PADCTL_UPHY_PLL_CTL1_IDDQ;
318 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
319
320 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
321 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_MASK <<
322 XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_SHIFT);
323 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
324
325 usleep_range(10, 20);
326
327 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
328 value |= XUSB_PADCTL_UPHY_PLL_CTL4_REFCLKBUF_EN;
329 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
330
331 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
332 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN;
333 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
334
335 timeout = jiffies + msecs_to_jiffies(100);
336
337 while (time_before(jiffies, timeout)) {
338 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
339 if (value & XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE)
340 break;
341
342 usleep_range(10, 20);
343 }
344
345 if (time_after_eq(jiffies, timeout)) {
346 err = -ETIMEDOUT;
347 goto reset;
348 }
349
350 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
351 value &= ~XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN;
352 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
353
354 timeout = jiffies + msecs_to_jiffies(100);
355
356 while (time_before(jiffies, timeout)) {
357 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
358 if (!(value & XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE))
359 break;
360
361 usleep_range(10, 20);
362 }
363
364 if (time_after_eq(jiffies, timeout)) {
365 err = -ETIMEDOUT;
366 goto reset;
367 }
368
369 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
370 value |= XUSB_PADCTL_UPHY_PLL_CTL1_ENABLE;
371 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
372
373 timeout = jiffies + msecs_to_jiffies(100);
374
375 while (time_before(jiffies, timeout)) {
376 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
377 if (value & XUSB_PADCTL_UPHY_PLL_CTL1_LOCKDET_STATUS)
378 break;
379
380 usleep_range(10, 20);
381 }
382
383 if (time_after_eq(jiffies, timeout)) {
384 err = -ETIMEDOUT;
385 goto reset;
386 }
387
388 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
389 value |= XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN |
390 XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN;
391 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
392
393 timeout = jiffies + msecs_to_jiffies(100);
394
395 while (time_before(jiffies, timeout)) {
396 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
397 if (value & XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE)
398 break;
399
400 usleep_range(10, 20);
401 }
402
403 if (time_after_eq(jiffies, timeout)) {
404 err = -ETIMEDOUT;
405 goto reset;
406 }
407
408 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
409 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN;
410 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
411
412 timeout = jiffies + msecs_to_jiffies(100);
413
414 while (time_before(jiffies, timeout)) {
415 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
416 if (!(value & XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE))
417 break;
418
419 usleep_range(10, 20);
420 }
421
422 if (time_after_eq(jiffies, timeout)) {
423 err = -ETIMEDOUT;
424 goto reset;
425 }
426
427 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
428 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN;
429 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
430
431 tegra210_xusb_pll_hw_control_enable();
432
433 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
434 value &= ~XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD;
435 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
436
437 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
438 value &= ~XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD;
439 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
440
441 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
442 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD;
443 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
444
445 usleep_range(10, 20);
446
447 tegra210_xusb_pll_hw_sequence_start();
448
449 pcie->enable++;
450
451 return 0;
452
453 reset:
454 reset_control_assert(pcie->rst);
455 disable:
456 clk_disable_unprepare(pcie->pll);
457 return err;
458 }
459
460 static void tegra210_pex_uphy_disable(struct tegra_xusb_padctl *padctl)
461 {
462 struct tegra_xusb_pcie_pad *pcie = to_pcie_pad(padctl->pcie);
463
464 mutex_lock(&padctl->lock);
465
466 if (WARN_ON(pcie->enable == 0))
467 goto unlock;
468
469 if (--pcie->enable > 0)
470 goto unlock;
471
472 reset_control_assert(pcie->rst);
473 clk_disable_unprepare(pcie->pll);
474
475 unlock:
476 mutex_unlock(&padctl->lock);
477 }
478
479 /* must be called under padctl->lock */
480 static int tegra210_sata_uphy_enable(struct tegra_xusb_padctl *padctl, bool usb)
481 {
482 struct tegra_xusb_sata_pad *sata = to_sata_pad(padctl->sata);
483 unsigned long timeout;
484 u32 value;
485 int err;
486
487 if (sata->enable > 0) {
488 sata->enable++;
489 return 0;
490 }
491
492 err = clk_prepare_enable(sata->pll);
493 if (err < 0)
494 return err;
495
496 err = reset_control_deassert(sata->rst);
497 if (err < 0)
498 goto disable;
499
500 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
501 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_MASK <<
502 XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_SHIFT);
503 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_VAL <<
504 XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_SHIFT;
505 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
506
507 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL5);
508 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_MASK <<
509 XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_SHIFT);
510 value |= XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_VAL <<
511 XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_SHIFT;
512 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL5);
513
514 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
515 value |= XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD;
516 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
517
518 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
519 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD;
520 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
521
522 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
523 value |= XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD;
524 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
525
526 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL4);
527 value &= ~((XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_MASK <<
528 XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SHIFT) |
529 (XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_MASK <<
530 XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_SHIFT));
531 value |= XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_EN;
532
533 if (usb)
534 value |= (XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_USB_VAL <<
535 XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SHIFT);
536 else
537 value |= (XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SATA_VAL <<
538 XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SHIFT);
539
540 /* XXX PLL0_XDIGCLK_EN */
541 /*
542 value &= ~(1 << 19);
543 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL4);
544 */
545
546 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
547 value &= ~((XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_MASK <<
548 XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_SHIFT) |
549 (XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_MASK <<
550 XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SHIFT));
551
552 if (usb)
553 value |= XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_USB_VAL <<
554 XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SHIFT;
555 else
556 value |= XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SATA_VAL <<
557 XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SHIFT;
558
559 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
560
561 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
562 value &= ~XUSB_PADCTL_UPHY_PLL_CTL1_IDDQ;
563 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
564
565 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
566 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_MASK <<
567 XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_SHIFT);
568 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
569
570 usleep_range(10, 20);
571
572 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL4);
573 value |= XUSB_PADCTL_UPHY_PLL_CTL4_REFCLKBUF_EN;
574 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL4);
575
576 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
577 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN;
578 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
579
580 timeout = jiffies + msecs_to_jiffies(100);
581
582 while (time_before(jiffies, timeout)) {
583 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
584 if (value & XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE)
585 break;
586
587 usleep_range(10, 20);
588 }
589
590 if (time_after_eq(jiffies, timeout)) {
591 err = -ETIMEDOUT;
592 goto reset;
593 }
594
595 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
596 value &= ~XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN;
597 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
598
599 timeout = jiffies + msecs_to_jiffies(100);
600
601 while (time_before(jiffies, timeout)) {
602 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
603 if (!(value & XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE))
604 break;
605
606 usleep_range(10, 20);
607 }
608
609 if (time_after_eq(jiffies, timeout)) {
610 err = -ETIMEDOUT;
611 goto reset;
612 }
613
614 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
615 value |= XUSB_PADCTL_UPHY_PLL_CTL1_ENABLE;
616 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
617
618 timeout = jiffies + msecs_to_jiffies(100);
619
620 while (time_before(jiffies, timeout)) {
621 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
622 if (value & XUSB_PADCTL_UPHY_PLL_CTL1_LOCKDET_STATUS)
623 break;
624
625 usleep_range(10, 20);
626 }
627
628 if (time_after_eq(jiffies, timeout)) {
629 err = -ETIMEDOUT;
630 goto reset;
631 }
632
633 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
634 value |= XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN |
635 XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN;
636 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
637
638 timeout = jiffies + msecs_to_jiffies(100);
639
640 while (time_before(jiffies, timeout)) {
641 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
642 if (value & XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE)
643 break;
644
645 usleep_range(10, 20);
646 }
647
648 if (time_after_eq(jiffies, timeout)) {
649 err = -ETIMEDOUT;
650 goto reset;
651 }
652
653 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
654 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN;
655 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
656
657 timeout = jiffies + msecs_to_jiffies(100);
658
659 while (time_before(jiffies, timeout)) {
660 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
661 if (!(value & XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE))
662 break;
663
664 usleep_range(10, 20);
665 }
666
667 if (time_after_eq(jiffies, timeout)) {
668 err = -ETIMEDOUT;
669 goto reset;
670 }
671
672 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
673 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN;
674 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
675
676 tegra210_sata_pll_hw_control_enable();
677
678 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
679 value &= ~XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD;
680 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
681
682 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
683 value &= ~XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD;
684 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
685
686 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
687 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD;
688 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
689
690 usleep_range(10, 20);
691
692 tegra210_sata_pll_hw_sequence_start();
693
694 sata->enable++;
695
696 return 0;
697
698 reset:
699 reset_control_assert(sata->rst);
700 disable:
701 clk_disable_unprepare(sata->pll);
702 return err;
703 }
704
705 static void tegra210_sata_uphy_disable(struct tegra_xusb_padctl *padctl)
706 {
707 struct tegra_xusb_sata_pad *sata = to_sata_pad(padctl->sata);
708
709 mutex_lock(&padctl->lock);
710
711 if (WARN_ON(sata->enable == 0))
712 goto unlock;
713
714 if (--sata->enable > 0)
715 goto unlock;
716
717 reset_control_assert(sata->rst);
718 clk_disable_unprepare(sata->pll);
719
720 unlock:
721 mutex_unlock(&padctl->lock);
722 }
723
724 static int tegra210_xusb_padctl_enable(struct tegra_xusb_padctl *padctl)
725 {
726 u32 value;
727
728 mutex_lock(&padctl->lock);
729
730 if (padctl->enable++ > 0)
731 goto out;
732
733 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
734 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN;
735 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
736
737 usleep_range(100, 200);
738
739 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
740 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY;
741 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
742
743 usleep_range(100, 200);
744
745 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
746 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN;
747 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
748
749 out:
750 mutex_unlock(&padctl->lock);
751 return 0;
752 }
753
754 static int tegra210_xusb_padctl_disable(struct tegra_xusb_padctl *padctl)
755 {
756 u32 value;
757
758 mutex_lock(&padctl->lock);
759
760 if (WARN_ON(padctl->enable == 0))
761 goto out;
762
763 if (--padctl->enable > 0)
764 goto out;
765
766 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
767 value |= XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN;
768 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
769
770 usleep_range(100, 200);
771
772 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
773 value |= XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY;
774 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
775
776 usleep_range(100, 200);
777
778 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
779 value |= XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN;
780 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
781
782 out:
783 mutex_unlock(&padctl->lock);
784 return 0;
785 }
786
787 static int tegra210_hsic_set_idle(struct tegra_xusb_padctl *padctl,
788 unsigned int index, bool idle)
789 {
790 u32 value;
791
792 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL0(index));
793
794 value &= ~(XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA0 |
795 XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA1 |
796 XUSB_PADCTL_HSIC_PAD_CTL0_RPD_STROBE);
797
798 if (idle)
799 value |= XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA0 |
800 XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA1 |
801 XUSB_PADCTL_HSIC_PAD_CTL0_RPU_STROBE;
802 else
803 value &= ~(XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA0 |
804 XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA1 |
805 XUSB_PADCTL_HSIC_PAD_CTL0_RPU_STROBE);
806
807 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL0(index));
808
809 return 0;
810 }
811
812 static int tegra210_usb3_set_lfps_detect(struct tegra_xusb_padctl *padctl,
813 unsigned int index, bool enable)
814 {
815 struct tegra_xusb_port *port;
816 struct tegra_xusb_lane *lane;
817 u32 value, offset;
818
819 port = tegra_xusb_find_port(padctl, "usb3", index);
820 if (!port)
821 return -ENODEV;
822
823 lane = port->lane;
824
825 if (lane->pad == padctl->pcie)
826 offset = XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL1(lane->index);
827 else
828 offset = XUSB_PADCTL_UPHY_MISC_PAD_S0_CTL1;
829
830 value = padctl_readl(padctl, offset);
831
832 value &= ~((XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_MASK <<
833 XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_SHIFT) |
834 XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_TERM_EN |
835 XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_MODE_OVRD);
836
837 if (!enable) {
838 value |= (XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_VAL <<
839 XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_SHIFT) |
840 XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_TERM_EN |
841 XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_MODE_OVRD;
842 }
843
844 padctl_writel(padctl, value, offset);
845
846 return 0;
847 }
848
849 #define TEGRA210_LANE(_name, _offset, _shift, _mask, _type) \
850 { \
851 .name = _name, \
852 .offset = _offset, \
853 .shift = _shift, \
854 .mask = _mask, \
855 .num_funcs = ARRAY_SIZE(tegra210_##_type##_functions), \
856 .funcs = tegra210_##_type##_functions, \
857 }
858
859 static const char *tegra210_usb2_functions[] = {
860 "snps",
861 "xusb",
862 "uart"
863 };
864
865 static const struct tegra_xusb_lane_soc tegra210_usb2_lanes[] = {
866 TEGRA210_LANE("usb2-0", 0x004, 0, 0x3, usb2),
867 TEGRA210_LANE("usb2-1", 0x004, 2, 0x3, usb2),
868 TEGRA210_LANE("usb2-2", 0x004, 4, 0x3, usb2),
869 TEGRA210_LANE("usb2-3", 0x004, 6, 0x3, usb2),
870 };
871
872 static struct tegra_xusb_lane *
873 tegra210_usb2_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np,
874 unsigned int index)
875 {
876 struct tegra_xusb_usb2_lane *usb2;
877 int err;
878
879 usb2 = kzalloc(sizeof(*usb2), GFP_KERNEL);
880 if (!usb2)
881 return ERR_PTR(-ENOMEM);
882
883 INIT_LIST_HEAD(&usb2->base.list);
884 usb2->base.soc = &pad->soc->lanes[index];
885 usb2->base.index = index;
886 usb2->base.pad = pad;
887 usb2->base.np = np;
888
889 err = tegra_xusb_lane_parse_dt(&usb2->base, np);
890 if (err < 0) {
891 kfree(usb2);
892 return ERR_PTR(err);
893 }
894
895 return &usb2->base;
896 }
897
898 static void tegra210_usb2_lane_remove(struct tegra_xusb_lane *lane)
899 {
900 struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane);
901
902 kfree(usb2);
903 }
904
905 static const struct tegra_xusb_lane_ops tegra210_usb2_lane_ops = {
906 .probe = tegra210_usb2_lane_probe,
907 .remove = tegra210_usb2_lane_remove,
908 };
909
910 static int tegra210_usb2_phy_init(struct phy *phy)
911 {
912 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
913 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
914 u32 value;
915
916 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX);
917 value &= ~(XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_MASK <<
918 XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_SHIFT);
919 value |= XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_XUSB <<
920 XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_SHIFT;
921 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PAD_MUX);
922
923 return tegra210_xusb_padctl_enable(padctl);
924 }
925
926 static int tegra210_usb2_phy_exit(struct phy *phy)
927 {
928 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
929
930 return tegra210_xusb_padctl_disable(lane->pad->padctl);
931 }
932
933 static int tegra210_usb2_phy_power_on(struct phy *phy)
934 {
935 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
936 struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane);
937 struct tegra_xusb_usb2_pad *pad = to_usb2_pad(lane->pad);
938 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
939 struct tegra210_xusb_padctl *priv;
940 struct tegra_xusb_usb2_port *port;
941 unsigned int index = lane->index;
942 u32 value;
943 int err;
944
945 port = tegra_xusb_find_usb2_port(padctl, index);
946 if (!port) {
947 dev_err(&phy->dev, "no port found for USB2 lane %u\n", index);
948 return -ENODEV;
949 }
950
951 priv = to_tegra210_xusb_padctl(padctl);
952
953 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
954 value &= ~((XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_MASK <<
955 XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_SHIFT) |
956 (XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_MASK <<
957 XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_SHIFT));
958 value |= (XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_VAL <<
959 XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_SHIFT);
960
961 if (tegra_sku_info.revision < TEGRA_REVISION_A02)
962 value |=
963 (XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_VAL <<
964 XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_SHIFT);
965
966 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
967
968 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP);
969 value &= ~XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_MASK(index);
970 value |= XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_HOST(index);
971 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PORT_CAP);
972
973 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
974 value &= ~((XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_MASK <<
975 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_SHIFT) |
976 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD |
977 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD2 |
978 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD_ZI);
979 value |= (priv->fuse.hs_curr_level[index] +
980 usb2->hs_curr_level_offset) <<
981 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_SHIFT;
982 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
983
984 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
985 value &= ~((XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ_MASK <<
986 XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ_SHIFT) |
987 (XUSB_PADCTL_USB2_OTG_PAD_CTL1_RPD_CTRL_MASK <<
988 XUSB_PADCTL_USB2_OTG_PAD_CTL1_RPD_CTRL_SHIFT) |
989 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR |
990 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_CHRP_OVRD |
991 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DISC_OVRD);
992 value |= (priv->fuse.hs_term_range_adj <<
993 XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ_SHIFT) |
994 (priv->fuse.rpd_ctrl <<
995 XUSB_PADCTL_USB2_OTG_PAD_CTL1_RPD_CTRL_SHIFT);
996 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
997
998 value = padctl_readl(padctl,
999 XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL1(index));
1000 value &= ~(XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_MASK <<
1001 XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_SHIFT);
1002 value |= XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_FIX18;
1003 padctl_writel(padctl, value,
1004 XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL1(index));
1005
1006 err = regulator_enable(port->supply);
1007 if (err)
1008 return err;
1009
1010 mutex_lock(&padctl->lock);
1011
1012 if (pad->enable > 0) {
1013 pad->enable++;
1014 mutex_unlock(&padctl->lock);
1015 return 0;
1016 }
1017
1018 err = clk_prepare_enable(pad->clk);
1019 if (err)
1020 goto disable_regulator;
1021
1022 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
1023 value &= ~((XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_MASK <<
1024 XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_SHIFT) |
1025 (XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_MASK <<
1026 XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_SHIFT));
1027 value |= (XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_VAL <<
1028 XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_SHIFT) |
1029 (XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_VAL <<
1030 XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_SHIFT);
1031 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
1032
1033 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
1034 value &= ~XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD;
1035 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
1036
1037 udelay(1);
1038
1039 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
1040 value &= ~XUSB_PADCTL_USB2_BIAS_PAD_CTL1_PD_TRK;
1041 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
1042
1043 udelay(50);
1044
1045 clk_disable_unprepare(pad->clk);
1046
1047 pad->enable++;
1048 mutex_unlock(&padctl->lock);
1049
1050 return 0;
1051
1052 disable_regulator:
1053 regulator_disable(port->supply);
1054 mutex_unlock(&padctl->lock);
1055 return err;
1056 }
1057
1058 static int tegra210_usb2_phy_power_off(struct phy *phy)
1059 {
1060 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1061 struct tegra_xusb_usb2_pad *pad = to_usb2_pad(lane->pad);
1062 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1063 struct tegra_xusb_usb2_port *port;
1064 u32 value;
1065
1066 port = tegra_xusb_find_usb2_port(padctl, lane->index);
1067 if (!port) {
1068 dev_err(&phy->dev, "no port found for USB2 lane %u\n",
1069 lane->index);
1070 return -ENODEV;
1071 }
1072
1073 mutex_lock(&padctl->lock);
1074
1075 if (WARN_ON(pad->enable == 0))
1076 goto out;
1077
1078 if (--pad->enable > 0)
1079 goto out;
1080
1081 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
1082 value |= XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD;
1083 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
1084
1085 out:
1086 regulator_disable(port->supply);
1087 mutex_unlock(&padctl->lock);
1088 return 0;
1089 }
1090
1091 static const struct phy_ops tegra210_usb2_phy_ops = {
1092 .init = tegra210_usb2_phy_init,
1093 .exit = tegra210_usb2_phy_exit,
1094 .power_on = tegra210_usb2_phy_power_on,
1095 .power_off = tegra210_usb2_phy_power_off,
1096 .owner = THIS_MODULE,
1097 };
1098
1099 static struct tegra_xusb_pad *
1100 tegra210_usb2_pad_probe(struct tegra_xusb_padctl *padctl,
1101 const struct tegra_xusb_pad_soc *soc,
1102 struct device_node *np)
1103 {
1104 struct tegra_xusb_usb2_pad *usb2;
1105 struct tegra_xusb_pad *pad;
1106 int err;
1107
1108 usb2 = kzalloc(sizeof(*usb2), GFP_KERNEL);
1109 if (!usb2)
1110 return ERR_PTR(-ENOMEM);
1111
1112 pad = &usb2->base;
1113 pad->ops = &tegra210_usb2_lane_ops;
1114 pad->soc = soc;
1115
1116 err = tegra_xusb_pad_init(pad, padctl, np);
1117 if (err < 0) {
1118 kfree(usb2);
1119 goto out;
1120 }
1121
1122 usb2->clk = devm_clk_get(&pad->dev, "trk");
1123 if (IS_ERR(usb2->clk)) {
1124 err = PTR_ERR(usb2->clk);
1125 dev_err(&pad->dev, "failed to get trk clock: %d\n", err);
1126 goto unregister;
1127 }
1128
1129 err = tegra_xusb_pad_register(pad, &tegra210_usb2_phy_ops);
1130 if (err < 0)
1131 goto unregister;
1132
1133 dev_set_drvdata(&pad->dev, pad);
1134
1135 return pad;
1136
1137 unregister:
1138 device_unregister(&pad->dev);
1139 out:
1140 return ERR_PTR(err);
1141 }
1142
1143 static void tegra210_usb2_pad_remove(struct tegra_xusb_pad *pad)
1144 {
1145 struct tegra_xusb_usb2_pad *usb2 = to_usb2_pad(pad);
1146
1147 kfree(usb2);
1148 }
1149
1150 static const struct tegra_xusb_pad_ops tegra210_usb2_ops = {
1151 .probe = tegra210_usb2_pad_probe,
1152 .remove = tegra210_usb2_pad_remove,
1153 };
1154
1155 static const struct tegra_xusb_pad_soc tegra210_usb2_pad = {
1156 .name = "usb2",
1157 .num_lanes = ARRAY_SIZE(tegra210_usb2_lanes),
1158 .lanes = tegra210_usb2_lanes,
1159 .ops = &tegra210_usb2_ops,
1160 };
1161
1162 static const char *tegra210_hsic_functions[] = {
1163 "snps",
1164 "xusb",
1165 };
1166
1167 static const struct tegra_xusb_lane_soc tegra210_hsic_lanes[] = {
1168 TEGRA210_LANE("hsic-0", 0x004, 14, 0x1, hsic),
1169 };
1170
1171 static struct tegra_xusb_lane *
1172 tegra210_hsic_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np,
1173 unsigned int index)
1174 {
1175 struct tegra_xusb_hsic_lane *hsic;
1176 int err;
1177
1178 hsic = kzalloc(sizeof(*hsic), GFP_KERNEL);
1179 if (!hsic)
1180 return ERR_PTR(-ENOMEM);
1181
1182 INIT_LIST_HEAD(&hsic->base.list);
1183 hsic->base.soc = &pad->soc->lanes[index];
1184 hsic->base.index = index;
1185 hsic->base.pad = pad;
1186 hsic->base.np = np;
1187
1188 err = tegra_xusb_lane_parse_dt(&hsic->base, np);
1189 if (err < 0) {
1190 kfree(hsic);
1191 return ERR_PTR(err);
1192 }
1193
1194 return &hsic->base;
1195 }
1196
1197 static void tegra210_hsic_lane_remove(struct tegra_xusb_lane *lane)
1198 {
1199 struct tegra_xusb_hsic_lane *hsic = to_hsic_lane(lane);
1200
1201 kfree(hsic);
1202 }
1203
1204 static const struct tegra_xusb_lane_ops tegra210_hsic_lane_ops = {
1205 .probe = tegra210_hsic_lane_probe,
1206 .remove = tegra210_hsic_lane_remove,
1207 };
1208
1209 static int tegra210_hsic_phy_init(struct phy *phy)
1210 {
1211 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1212 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1213 u32 value;
1214
1215 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX);
1216 value &= ~(XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_MASK <<
1217 XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_SHIFT);
1218 value |= XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_XUSB <<
1219 XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_SHIFT;
1220 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PAD_MUX);
1221
1222 return tegra210_xusb_padctl_enable(padctl);
1223 }
1224
1225 static int tegra210_hsic_phy_exit(struct phy *phy)
1226 {
1227 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1228
1229 return tegra210_xusb_padctl_disable(lane->pad->padctl);
1230 }
1231
1232 static int tegra210_hsic_phy_power_on(struct phy *phy)
1233 {
1234 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1235 struct tegra_xusb_hsic_lane *hsic = to_hsic_lane(lane);
1236 struct tegra_xusb_hsic_pad *pad = to_hsic_pad(lane->pad);
1237 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1238 struct tegra210_xusb_padctl *priv;
1239 unsigned int index = lane->index;
1240 u32 value;
1241 int err;
1242
1243 priv = to_tegra210_xusb_padctl(padctl);
1244
1245 err = regulator_enable(pad->supply);
1246 if (err)
1247 return err;
1248
1249 padctl_writel(padctl, hsic->strobe_trim,
1250 XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL);
1251
1252 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL1(index));
1253 value &= ~(XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_MASK <<
1254 XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_SHIFT);
1255 value |= (hsic->tx_rtune_p <<
1256 XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_SHIFT);
1257 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL1(index));
1258
1259 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL2(index));
1260 value &= ~((XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_MASK <<
1261 XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_SHIFT) |
1262 (XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_MASK <<
1263 XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_SHIFT));
1264 value |= (hsic->rx_strobe_trim <<
1265 XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_SHIFT) |
1266 (hsic->rx_data_trim <<
1267 XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_SHIFT);
1268 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL2(index));
1269
1270 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL0(index));
1271 value &= ~(XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA0 |
1272 XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA1 |
1273 XUSB_PADCTL_HSIC_PAD_CTL0_RPU_STROBE |
1274 XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA0 |
1275 XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA1 |
1276 XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_STROBE |
1277 XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA0 |
1278 XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA1 |
1279 XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_STROBE |
1280 XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA0 |
1281 XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA1 |
1282 XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_STROBE);
1283 value |= XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA0 |
1284 XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA1 |
1285 XUSB_PADCTL_HSIC_PAD_CTL0_RPD_STROBE;
1286 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL0(index));
1287
1288 err = clk_prepare_enable(pad->clk);
1289 if (err)
1290 goto disable;
1291
1292 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PAD_TRK_CTL);
1293 value &= ~((XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_MASK <<
1294 XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_SHIFT) |
1295 (XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_MASK <<
1296 XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_SHIFT));
1297 value |= (XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_VAL <<
1298 XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_SHIFT) |
1299 (XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_VAL <<
1300 XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_SHIFT);
1301 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PAD_TRK_CTL);
1302
1303 udelay(1);
1304
1305 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PAD_TRK_CTL);
1306 value &= ~XUSB_PADCTL_HSIC_PAD_TRK_CTL_PD_TRK;
1307 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PAD_TRK_CTL);
1308
1309 udelay(50);
1310
1311 clk_disable_unprepare(pad->clk);
1312
1313 return 0;
1314
1315 disable:
1316 regulator_disable(pad->supply);
1317 return err;
1318 }
1319
1320 static int tegra210_hsic_phy_power_off(struct phy *phy)
1321 {
1322 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1323 struct tegra_xusb_hsic_pad *pad = to_hsic_pad(lane->pad);
1324 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1325 unsigned int index = lane->index;
1326 u32 value;
1327
1328 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL0(index));
1329 value |= XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA0 |
1330 XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA1 |
1331 XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_STROBE |
1332 XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA0 |
1333 XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA1 |
1334 XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_STROBE |
1335 XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA0 |
1336 XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA1 |
1337 XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_STROBE;
1338 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL1(index));
1339
1340 regulator_disable(pad->supply);
1341
1342 return 0;
1343 }
1344
1345 static const struct phy_ops tegra210_hsic_phy_ops = {
1346 .init = tegra210_hsic_phy_init,
1347 .exit = tegra210_hsic_phy_exit,
1348 .power_on = tegra210_hsic_phy_power_on,
1349 .power_off = tegra210_hsic_phy_power_off,
1350 .owner = THIS_MODULE,
1351 };
1352
1353 static struct tegra_xusb_pad *
1354 tegra210_hsic_pad_probe(struct tegra_xusb_padctl *padctl,
1355 const struct tegra_xusb_pad_soc *soc,
1356 struct device_node *np)
1357 {
1358 struct tegra_xusb_hsic_pad *hsic;
1359 struct tegra_xusb_pad *pad;
1360 int err;
1361
1362 hsic = kzalloc(sizeof(*hsic), GFP_KERNEL);
1363 if (!hsic)
1364 return ERR_PTR(-ENOMEM);
1365
1366 pad = &hsic->base;
1367 pad->ops = &tegra210_hsic_lane_ops;
1368 pad->soc = soc;
1369
1370 err = tegra_xusb_pad_init(pad, padctl, np);
1371 if (err < 0) {
1372 kfree(hsic);
1373 goto out;
1374 }
1375
1376 hsic->clk = devm_clk_get(&pad->dev, "trk");
1377 if (IS_ERR(hsic->clk)) {
1378 err = PTR_ERR(hsic->clk);
1379 dev_err(&pad->dev, "failed to get trk clock: %d\n", err);
1380 goto unregister;
1381 }
1382
1383 err = tegra_xusb_pad_register(pad, &tegra210_hsic_phy_ops);
1384 if (err < 0)
1385 goto unregister;
1386
1387 dev_set_drvdata(&pad->dev, pad);
1388
1389 return pad;
1390
1391 unregister:
1392 device_unregister(&pad->dev);
1393 out:
1394 return ERR_PTR(err);
1395 }
1396
1397 static void tegra210_hsic_pad_remove(struct tegra_xusb_pad *pad)
1398 {
1399 struct tegra_xusb_hsic_pad *hsic = to_hsic_pad(pad);
1400
1401 kfree(hsic);
1402 }
1403
1404 static const struct tegra_xusb_pad_ops tegra210_hsic_ops = {
1405 .probe = tegra210_hsic_pad_probe,
1406 .remove = tegra210_hsic_pad_remove,
1407 };
1408
1409 static const struct tegra_xusb_pad_soc tegra210_hsic_pad = {
1410 .name = "hsic",
1411 .num_lanes = ARRAY_SIZE(tegra210_hsic_lanes),
1412 .lanes = tegra210_hsic_lanes,
1413 .ops = &tegra210_hsic_ops,
1414 };
1415
1416 static const char *tegra210_pcie_functions[] = {
1417 "pcie-x1",
1418 "usb3-ss",
1419 "sata",
1420 "pcie-x4",
1421 };
1422
1423 static const struct tegra_xusb_lane_soc tegra210_pcie_lanes[] = {
1424 TEGRA210_LANE("pcie-0", 0x028, 12, 0x3, pcie),
1425 TEGRA210_LANE("pcie-1", 0x028, 14, 0x3, pcie),
1426 TEGRA210_LANE("pcie-2", 0x028, 16, 0x3, pcie),
1427 TEGRA210_LANE("pcie-3", 0x028, 18, 0x3, pcie),
1428 TEGRA210_LANE("pcie-4", 0x028, 20, 0x3, pcie),
1429 TEGRA210_LANE("pcie-5", 0x028, 22, 0x3, pcie),
1430 TEGRA210_LANE("pcie-6", 0x028, 24, 0x3, pcie),
1431 };
1432
1433 static struct tegra_xusb_lane *
1434 tegra210_pcie_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np,
1435 unsigned int index)
1436 {
1437 struct tegra_xusb_pcie_lane *pcie;
1438 int err;
1439
1440 pcie = kzalloc(sizeof(*pcie), GFP_KERNEL);
1441 if (!pcie)
1442 return ERR_PTR(-ENOMEM);
1443
1444 INIT_LIST_HEAD(&pcie->base.list);
1445 pcie->base.soc = &pad->soc->lanes[index];
1446 pcie->base.index = index;
1447 pcie->base.pad = pad;
1448 pcie->base.np = np;
1449
1450 err = tegra_xusb_lane_parse_dt(&pcie->base, np);
1451 if (err < 0) {
1452 kfree(pcie);
1453 return ERR_PTR(err);
1454 }
1455
1456 return &pcie->base;
1457 }
1458
1459 static void tegra210_pcie_lane_remove(struct tegra_xusb_lane *lane)
1460 {
1461 struct tegra_xusb_pcie_lane *pcie = to_pcie_lane(lane);
1462
1463 kfree(pcie);
1464 }
1465
1466 static const struct tegra_xusb_lane_ops tegra210_pcie_lane_ops = {
1467 .probe = tegra210_pcie_lane_probe,
1468 .remove = tegra210_pcie_lane_remove,
1469 };
1470
1471 static int tegra210_pcie_phy_init(struct phy *phy)
1472 {
1473 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1474
1475 return tegra210_xusb_padctl_enable(lane->pad->padctl);
1476 }
1477
1478 static int tegra210_pcie_phy_exit(struct phy *phy)
1479 {
1480 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1481
1482 return tegra210_xusb_padctl_disable(lane->pad->padctl);
1483 }
1484
1485 static int tegra210_pcie_phy_power_on(struct phy *phy)
1486 {
1487 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1488 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1489 u32 value;
1490 int err;
1491
1492 mutex_lock(&padctl->lock);
1493
1494 err = tegra210_pex_uphy_enable(padctl);
1495 if (err < 0)
1496 goto unlock;
1497
1498 value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX);
1499 value |= XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->index);
1500 padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX);
1501
1502 unlock:
1503 mutex_unlock(&padctl->lock);
1504 return err;
1505 }
1506
1507 static int tegra210_pcie_phy_power_off(struct phy *phy)
1508 {
1509 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1510 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1511 u32 value;
1512
1513 value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX);
1514 value &= ~XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->index);
1515 padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX);
1516
1517 tegra210_pex_uphy_disable(padctl);
1518
1519 return 0;
1520 }
1521
1522 static const struct phy_ops tegra210_pcie_phy_ops = {
1523 .init = tegra210_pcie_phy_init,
1524 .exit = tegra210_pcie_phy_exit,
1525 .power_on = tegra210_pcie_phy_power_on,
1526 .power_off = tegra210_pcie_phy_power_off,
1527 .owner = THIS_MODULE,
1528 };
1529
1530 static struct tegra_xusb_pad *
1531 tegra210_pcie_pad_probe(struct tegra_xusb_padctl *padctl,
1532 const struct tegra_xusb_pad_soc *soc,
1533 struct device_node *np)
1534 {
1535 struct tegra_xusb_pcie_pad *pcie;
1536 struct tegra_xusb_pad *pad;
1537 int err;
1538
1539 pcie = kzalloc(sizeof(*pcie), GFP_KERNEL);
1540 if (!pcie)
1541 return ERR_PTR(-ENOMEM);
1542
1543 pad = &pcie->base;
1544 pad->ops = &tegra210_pcie_lane_ops;
1545 pad->soc = soc;
1546
1547 err = tegra_xusb_pad_init(pad, padctl, np);
1548 if (err < 0) {
1549 kfree(pcie);
1550 goto out;
1551 }
1552
1553 pcie->pll = devm_clk_get(&pad->dev, "pll");
1554 if (IS_ERR(pcie->pll)) {
1555 err = PTR_ERR(pcie->pll);
1556 dev_err(&pad->dev, "failed to get PLL: %d\n", err);
1557 goto unregister;
1558 }
1559
1560 pcie->rst = devm_reset_control_get(&pad->dev, "phy");
1561 if (IS_ERR(pcie->rst)) {
1562 err = PTR_ERR(pcie->rst);
1563 dev_err(&pad->dev, "failed to get PCIe pad reset: %d\n", err);
1564 goto unregister;
1565 }
1566
1567 err = tegra_xusb_pad_register(pad, &tegra210_pcie_phy_ops);
1568 if (err < 0)
1569 goto unregister;
1570
1571 dev_set_drvdata(&pad->dev, pad);
1572
1573 return pad;
1574
1575 unregister:
1576 device_unregister(&pad->dev);
1577 out:
1578 return ERR_PTR(err);
1579 }
1580
1581 static void tegra210_pcie_pad_remove(struct tegra_xusb_pad *pad)
1582 {
1583 struct tegra_xusb_pcie_pad *pcie = to_pcie_pad(pad);
1584
1585 kfree(pcie);
1586 }
1587
1588 static const struct tegra_xusb_pad_ops tegra210_pcie_ops = {
1589 .probe = tegra210_pcie_pad_probe,
1590 .remove = tegra210_pcie_pad_remove,
1591 };
1592
1593 static const struct tegra_xusb_pad_soc tegra210_pcie_pad = {
1594 .name = "pcie",
1595 .num_lanes = ARRAY_SIZE(tegra210_pcie_lanes),
1596 .lanes = tegra210_pcie_lanes,
1597 .ops = &tegra210_pcie_ops,
1598 };
1599
1600 static const struct tegra_xusb_lane_soc tegra210_sata_lanes[] = {
1601 TEGRA210_LANE("sata-0", 0x028, 30, 0x3, pcie),
1602 };
1603
1604 static struct tegra_xusb_lane *
1605 tegra210_sata_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np,
1606 unsigned int index)
1607 {
1608 struct tegra_xusb_sata_lane *sata;
1609 int err;
1610
1611 sata = kzalloc(sizeof(*sata), GFP_KERNEL);
1612 if (!sata)
1613 return ERR_PTR(-ENOMEM);
1614
1615 INIT_LIST_HEAD(&sata->base.list);
1616 sata->base.soc = &pad->soc->lanes[index];
1617 sata->base.index = index;
1618 sata->base.pad = pad;
1619 sata->base.np = np;
1620
1621 err = tegra_xusb_lane_parse_dt(&sata->base, np);
1622 if (err < 0) {
1623 kfree(sata);
1624 return ERR_PTR(err);
1625 }
1626
1627 return &sata->base;
1628 }
1629
1630 static void tegra210_sata_lane_remove(struct tegra_xusb_lane *lane)
1631 {
1632 struct tegra_xusb_sata_lane *sata = to_sata_lane(lane);
1633
1634 kfree(sata);
1635 }
1636
1637 static const struct tegra_xusb_lane_ops tegra210_sata_lane_ops = {
1638 .probe = tegra210_sata_lane_probe,
1639 .remove = tegra210_sata_lane_remove,
1640 };
1641
1642 static int tegra210_sata_phy_init(struct phy *phy)
1643 {
1644 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1645
1646 return tegra210_xusb_padctl_enable(lane->pad->padctl);
1647 }
1648
1649 static int tegra210_sata_phy_exit(struct phy *phy)
1650 {
1651 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1652
1653 return tegra210_xusb_padctl_disable(lane->pad->padctl);
1654 }
1655
1656 static int tegra210_sata_phy_power_on(struct phy *phy)
1657 {
1658 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1659 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1660 u32 value;
1661 int err;
1662
1663 mutex_lock(&padctl->lock);
1664
1665 err = tegra210_sata_uphy_enable(padctl, false);
1666 if (err < 0)
1667 goto unlock;
1668
1669 value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX);
1670 value |= XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(lane->index);
1671 padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX);
1672
1673 unlock:
1674 mutex_unlock(&padctl->lock);
1675 return err;
1676 }
1677
1678 static int tegra210_sata_phy_power_off(struct phy *phy)
1679 {
1680 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1681 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1682 u32 value;
1683
1684 value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX);
1685 value &= ~XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(lane->index);
1686 padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX);
1687
1688 tegra210_sata_uphy_disable(lane->pad->padctl);
1689
1690 return 0;
1691 }
1692
1693 static const struct phy_ops tegra210_sata_phy_ops = {
1694 .init = tegra210_sata_phy_init,
1695 .exit = tegra210_sata_phy_exit,
1696 .power_on = tegra210_sata_phy_power_on,
1697 .power_off = tegra210_sata_phy_power_off,
1698 .owner = THIS_MODULE,
1699 };
1700
1701 static struct tegra_xusb_pad *
1702 tegra210_sata_pad_probe(struct tegra_xusb_padctl *padctl,
1703 const struct tegra_xusb_pad_soc *soc,
1704 struct device_node *np)
1705 {
1706 struct tegra_xusb_sata_pad *sata;
1707 struct tegra_xusb_pad *pad;
1708 int err;
1709
1710 sata = kzalloc(sizeof(*sata), GFP_KERNEL);
1711 if (!sata)
1712 return ERR_PTR(-ENOMEM);
1713
1714 pad = &sata->base;
1715 pad->ops = &tegra210_sata_lane_ops;
1716 pad->soc = soc;
1717
1718 err = tegra_xusb_pad_init(pad, padctl, np);
1719 if (err < 0) {
1720 kfree(sata);
1721 goto out;
1722 }
1723
1724 sata->rst = devm_reset_control_get(&pad->dev, "phy");
1725 if (IS_ERR(sata->rst)) {
1726 err = PTR_ERR(sata->rst);
1727 dev_err(&pad->dev, "failed to get SATA pad reset: %d\n", err);
1728 goto unregister;
1729 }
1730
1731 err = tegra_xusb_pad_register(pad, &tegra210_sata_phy_ops);
1732 if (err < 0)
1733 goto unregister;
1734
1735 dev_set_drvdata(&pad->dev, pad);
1736
1737 return pad;
1738
1739 unregister:
1740 device_unregister(&pad->dev);
1741 out:
1742 return ERR_PTR(err);
1743 }
1744
1745 static void tegra210_sata_pad_remove(struct tegra_xusb_pad *pad)
1746 {
1747 struct tegra_xusb_sata_pad *sata = to_sata_pad(pad);
1748
1749 kfree(sata);
1750 }
1751
1752 static const struct tegra_xusb_pad_ops tegra210_sata_ops = {
1753 .probe = tegra210_sata_pad_probe,
1754 .remove = tegra210_sata_pad_remove,
1755 };
1756
1757 static const struct tegra_xusb_pad_soc tegra210_sata_pad = {
1758 .name = "sata",
1759 .num_lanes = ARRAY_SIZE(tegra210_sata_lanes),
1760 .lanes = tegra210_sata_lanes,
1761 .ops = &tegra210_sata_ops,
1762 };
1763
1764 static const struct tegra_xusb_pad_soc * const tegra210_pads[] = {
1765 &tegra210_usb2_pad,
1766 &tegra210_hsic_pad,
1767 &tegra210_pcie_pad,
1768 &tegra210_sata_pad,
1769 };
1770
1771 static int tegra210_usb2_port_enable(struct tegra_xusb_port *port)
1772 {
1773 return 0;
1774 }
1775
1776 static void tegra210_usb2_port_disable(struct tegra_xusb_port *port)
1777 {
1778 }
1779
1780 static struct tegra_xusb_lane *
1781 tegra210_usb2_port_map(struct tegra_xusb_port *port)
1782 {
1783 return tegra_xusb_find_lane(port->padctl, "usb2", port->index);
1784 }
1785
1786 static const struct tegra_xusb_port_ops tegra210_usb2_port_ops = {
1787 .enable = tegra210_usb2_port_enable,
1788 .disable = tegra210_usb2_port_disable,
1789 .map = tegra210_usb2_port_map,
1790 };
1791
1792 static int tegra210_hsic_port_enable(struct tegra_xusb_port *port)
1793 {
1794 return 0;
1795 }
1796
1797 static void tegra210_hsic_port_disable(struct tegra_xusb_port *port)
1798 {
1799 }
1800
1801 static struct tegra_xusb_lane *
1802 tegra210_hsic_port_map(struct tegra_xusb_port *port)
1803 {
1804 return tegra_xusb_find_lane(port->padctl, "hsic", port->index);
1805 }
1806
1807 static const struct tegra_xusb_port_ops tegra210_hsic_port_ops = {
1808 .enable = tegra210_hsic_port_enable,
1809 .disable = tegra210_hsic_port_disable,
1810 .map = tegra210_hsic_port_map,
1811 };
1812
1813 static int tegra210_usb3_port_enable(struct tegra_xusb_port *port)
1814 {
1815 struct tegra_xusb_usb3_port *usb3 = to_usb3_port(port);
1816 struct tegra_xusb_padctl *padctl = port->padctl;
1817 struct tegra_xusb_lane *lane = usb3->base.lane;
1818 unsigned int index = port->index;
1819 u32 value;
1820 int err;
1821
1822 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP);
1823
1824 if (!usb3->internal)
1825 value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(index);
1826 else
1827 value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(index);
1828
1829 value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(index);
1830 value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(index, usb3->port);
1831 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP);
1832
1833 /*
1834 * TODO: move this code into the PCIe/SATA PHY ->power_on() callbacks
1835 * and conditionalize based on mux function? This seems to work, but
1836 * might not be the exact proper sequence.
1837 */
1838 err = regulator_enable(usb3->supply);
1839 if (err < 0)
1840 return err;
1841
1842 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL1(index));
1843 value &= ~(XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_MASK <<
1844 XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_SHIFT);
1845 value |= XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_VAL <<
1846 XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_SHIFT;
1847 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL1(index));
1848
1849 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL2(index));
1850 value &= ~(XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_MASK <<
1851 XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_SHIFT);
1852 value |= XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_VAL <<
1853 XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_SHIFT;
1854 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL2(index));
1855
1856 padctl_writel(padctl, XUSB_PADCTL_UPHY_USB3_PAD_ECTL3_RX_DFE_VAL,
1857 XUSB_PADCTL_UPHY_USB3_PADX_ECTL3(index));
1858
1859 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL4(index));
1860 value &= ~(XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_MASK <<
1861 XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_SHIFT);
1862 value |= XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_VAL <<
1863 XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_SHIFT;
1864 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL4(index));
1865
1866 padctl_writel(padctl, XUSB_PADCTL_UPHY_USB3_PAD_ECTL6_RX_EQ_CTRL_H_VAL,
1867 XUSB_PADCTL_UPHY_USB3_PADX_ECTL6(index));
1868
1869 if (lane->pad == padctl->sata)
1870 err = tegra210_sata_uphy_enable(padctl, true);
1871 else
1872 err = tegra210_pex_uphy_enable(padctl);
1873
1874 if (err) {
1875 dev_err(&port->dev, "%s: failed to enable UPHY: %d\n",
1876 __func__, err);
1877 return err;
1878 }
1879
1880 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
1881 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(index);
1882 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
1883
1884 usleep_range(100, 200);
1885
1886 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
1887 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(index);
1888 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
1889
1890 usleep_range(100, 200);
1891
1892 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
1893 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(index);
1894 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
1895
1896 return 0;
1897 }
1898
1899 static void tegra210_usb3_port_disable(struct tegra_xusb_port *port)
1900 {
1901 struct tegra_xusb_usb3_port *usb3 = to_usb3_port(port);
1902 struct tegra_xusb_padctl *padctl = port->padctl;
1903 struct tegra_xusb_lane *lane = port->lane;
1904 unsigned int index = port->index;
1905 u32 value;
1906
1907 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
1908 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(index);
1909 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
1910
1911 usleep_range(100, 200);
1912
1913 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
1914 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(index);
1915 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
1916
1917 usleep_range(250, 350);
1918
1919 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
1920 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(index);
1921 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
1922
1923 if (lane->pad == padctl->sata)
1924 tegra210_sata_uphy_disable(padctl);
1925 else
1926 tegra210_pex_uphy_disable(padctl);
1927
1928 regulator_disable(usb3->supply);
1929
1930 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP);
1931 value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(index);
1932 value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(index, 0x7);
1933 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP);
1934 }
1935
1936 static const struct tegra_xusb_lane_map tegra210_usb3_map[] = {
1937 { 0, "pcie", 6 },
1938 { 1, "pcie", 5 },
1939 { 2, "pcie", 0 },
1940 { 2, "pcie", 3 },
1941 { 3, "pcie", 4 },
1942 { 3, "pcie", 4 },
1943 { 0, NULL, 0 }
1944 };
1945
1946 static struct tegra_xusb_lane *
1947 tegra210_usb3_port_map(struct tegra_xusb_port *port)
1948 {
1949 return tegra_xusb_port_find_lane(port, tegra210_usb3_map, "usb3-ss");
1950 }
1951
1952 static const struct tegra_xusb_port_ops tegra210_usb3_port_ops = {
1953 .enable = tegra210_usb3_port_enable,
1954 .disable = tegra210_usb3_port_disable,
1955 .map = tegra210_usb3_port_map,
1956 };
1957
1958 static int
1959 tegra210_xusb_read_fuse_calibration(struct tegra210_xusb_fuse_calibration *fuse)
1960 {
1961 unsigned int i;
1962 u32 value;
1963 int err;
1964
1965 err = tegra_fuse_readl(TEGRA_FUSE_SKU_CALIB_0, &value);
1966 if (err < 0)
1967 return err;
1968
1969 for (i = 0; i < ARRAY_SIZE(fuse->hs_curr_level); i++) {
1970 fuse->hs_curr_level[i] =
1971 (value >> FUSE_SKU_CALIB_HS_CURR_LEVEL_PADX_SHIFT(i)) &
1972 FUSE_SKU_CALIB_HS_CURR_LEVEL_PAD_MASK;
1973 }
1974
1975 fuse->hs_term_range_adj =
1976 (value >> FUSE_SKU_CALIB_HS_TERM_RANGE_ADJ_SHIFT) &
1977 FUSE_SKU_CALIB_HS_TERM_RANGE_ADJ_MASK;
1978
1979 err = tegra_fuse_readl(TEGRA_FUSE_USB_CALIB_EXT_0, &value);
1980 if (err < 0)
1981 return err;
1982
1983 fuse->rpd_ctrl =
1984 (value >> FUSE_USB_CALIB_EXT_RPD_CTRL_SHIFT) &
1985 FUSE_USB_CALIB_EXT_RPD_CTRL_MASK;
1986
1987 return 0;
1988 }
1989
1990 static struct tegra_xusb_padctl *
1991 tegra210_xusb_padctl_probe(struct device *dev,
1992 const struct tegra_xusb_padctl_soc *soc)
1993 {
1994 struct tegra210_xusb_padctl *padctl;
1995 int err;
1996
1997 padctl = devm_kzalloc(dev, sizeof(*padctl), GFP_KERNEL);
1998 if (!padctl)
1999 return ERR_PTR(-ENOMEM);
2000
2001 padctl->base.dev = dev;
2002 padctl->base.soc = soc;
2003
2004 err = tegra210_xusb_read_fuse_calibration(&padctl->fuse);
2005 if (err < 0)
2006 return ERR_PTR(err);
2007
2008 return &padctl->base;
2009 }
2010
2011 static void tegra210_xusb_padctl_remove(struct tegra_xusb_padctl *padctl)
2012 {
2013 }
2014
2015 static const struct tegra_xusb_padctl_ops tegra210_xusb_padctl_ops = {
2016 .probe = tegra210_xusb_padctl_probe,
2017 .remove = tegra210_xusb_padctl_remove,
2018 .usb3_set_lfps_detect = tegra210_usb3_set_lfps_detect,
2019 .hsic_set_idle = tegra210_hsic_set_idle,
2020 };
2021
2022 const struct tegra_xusb_padctl_soc tegra210_xusb_padctl_soc = {
2023 .num_pads = ARRAY_SIZE(tegra210_pads),
2024 .pads = tegra210_pads,
2025 .ports = {
2026 .usb2 = {
2027 .ops = &tegra210_usb2_port_ops,
2028 .count = 4,
2029 },
2030 .hsic = {
2031 .ops = &tegra210_hsic_port_ops,
2032 .count = 1,
2033 },
2034 .usb3 = {
2035 .ops = &tegra210_usb3_port_ops,
2036 .count = 4,
2037 },
2038 },
2039 .ops = &tegra210_xusb_padctl_ops,
2040 };
2041 EXPORT_SYMBOL_GPL(tegra210_xusb_padctl_soc);
2042
2043 MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>");
2044 MODULE_DESCRIPTION("NVIDIA Tegra 210 XUSB Pad Controller driver");
2045 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support