arch/arc/plat-arcfpga/smp.c

   1 /*
   2  * ARC700 Simulation-only Extensions for SMP
   3  *
   4  * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  *  Vineet Gupta    - 2012 : split off arch common and plat specific SMP
  11  *  Rajeshwar Ranga - 2007 : Interrupt Distribution Unit API's
  12  */
  13
  14 #include <linux/smp.h>
  15 #include <linux/irq.h>
  16 #include <plat/irq.h>
  17 #include <plat/smp.h>
  18
  19 static char smp_cpuinfo_buf[128];
  20
  21 /*
  22  *-------------------------------------------------------------------
  23  * Platform specific callbacks expected by arch SMP code
  24  *-------------------------------------------------------------------
  25  */
  26
  27 /*
  28  * Master kick starting another CPU
  29  */
  30 static void iss_model_smp_wakeup_cpu(int cpu, unsigned long pc)
  31 {
  32         /* setup the start PC */
  33         write_aux_reg(ARC_AUX_XTL_REG_PARAM, pc);
  34
  35         /* Trigger WRITE_PC cmd for this cpu */
  36         write_aux_reg(ARC_AUX_XTL_REG_CMD,
  37                         (ARC_XTL_CMD_WRITE_PC | (cpu << 8)));
  38
  39         /* Take the cpu out of Halt */
  40         write_aux_reg(ARC_AUX_XTL_REG_CMD,
  41                         (ARC_XTL_CMD_CLEAR_HALT | (cpu << 8)));
  42
  43 }
  44
  45 static inline int get_hw_config_num_irq(void)
  46 {
  47         uint32_t val = read_aux_reg(ARC_REG_VECBASE_BCR);
  48
  49         switch (val & 0x03) {
  50         case 0:
  51                 return 16;
  52         case 1:
  53                 return 32;
  54         case 2:
  55                 return 8;
  56         default:
  57                 return 0;
  58         }
  59
  60         return 0;
  61 }
  62
  63 /*
  64  * Any SMP specific init any CPU does when it comes up.
  65  * Here we setup the CPU to enable Inter-Processor-Interrupts
  66  * Called for each CPU
  67  * -Master      : init_IRQ()
  68  * -Other(s)    : start_kernel_secondary()
  69  */
  70 void iss_model_init_smp(unsigned int cpu)
  71 {
  72         /* Check if CPU is configured for more than 16 interrupts */
  73         if (NR_IRQS <= 16 || get_hw_config_num_irq() <= 16)
  74                 panic("[arcfpga] IRQ system can't support IDU IPI\n");
  75
  76         idu_disable();
  77
  78         /****************************************************************
  79          * IDU provides a set of Common IRQs, each of which can be dynamically
  80          * attached to (1|many|all) CPUs.
  81          * The Common IRQs [0-15] are mapped as CPU pvt [16-31]
  82          *
  83          * Here we use a simple 1:1 mapping:
  84          * A CPU 'x' is wired to Common IRQ 'x'.
  85          * So an IDU ASSERT on IRQ 'x' will trigger Interupt on CPU 'x', which
  86          * makes up for our simple IPI plumbing.
  87          *
  88          * TBD: Have a dedicated multicast IRQ for sending IPIs to all CPUs
  89          *      w/o having to do one-at-a-time
  90          ******************************************************************/
  91
  92         /*
  93          * Claim an IRQ which would trigger IPI on this CPU.
  94          * In IDU parlance it involves setting up a cpu bitmask for the IRQ
  95          * The bitmap here contains only 1 CPU (self).
  96          */
  97         idu_irq_set_tgtcpu(cpu, 0x1 << cpu);
  98
  99         /* Set the IRQ destination to use the bitmask above */
 100         idu_irq_set_mode(cpu, 7, /* XXX: IDU_IRQ_MOD_TCPU_ALLRECP: ISS bug */
 101                          IDU_IRQ_MODE_PULSE_TRIG);
 102
 103         idu_enable();
 104
 105         /* Attach the arch-common IPI ISR to our IDU IRQ */
 106         smp_ipi_irq_setup(cpu, IDU_INTERRUPT_0 + cpu);
 107 }
 108
 109 static void iss_model_ipi_send(int cpu)
 110 {
 111         idu_irq_assert(cpu);
 112 }
 113
 114 static void iss_model_ipi_clear(int irq)
 115 {
 116         idu_irq_clear(IDU_INTERRUPT_0 + smp_processor_id());
 117 }
 118
 119 void iss_model_init_early_smp(void)
 120 {
 121 #define IS_AVAIL1(var, str)    ((var) ? str : "")
 122
 123         struct bcr_mp mp;
 124
 125         READ_BCR(ARC_REG_MP_BCR, mp);
 126
 127         sprintf(smp_cpuinfo_buf, "Extn [ISS-SMP]: v%d, arch(%d) %s %s %s\n",
 128                 mp.ver, mp.mp_arch, IS_AVAIL1(mp.scu, "SCU"),
 129                 IS_AVAIL1(mp.idu, "IDU"), IS_AVAIL1(mp.sdu, "SDU"));
 130
 131         plat_smp_ops.info = smp_cpuinfo_buf;
 132
 133         plat_smp_ops.cpu_kick = iss_model_smp_wakeup_cpu;
 134         plat_smp_ops.ipi_send = iss_model_ipi_send;
 135         plat_smp_ops.ipi_clear = iss_model_ipi_clear;
 136 }
 137
 138 /*
 139  *-------------------------------------------------------------------
 140  * Low level Platform IPI Providers
 141  *-------------------------------------------------------------------
 142  */
 143
 144 /* Set the Mode for the Common IRQ */
 145 void idu_irq_set_mode(uint8_t irq, uint8_t dest_mode, uint8_t trig_mode)
 146 {
 147         uint32_t par = IDU_IRQ_MODE_PARAM(dest_mode, trig_mode);
 148
 149         IDU_SET_PARAM(par);
 150         IDU_SET_COMMAND(irq, IDU_IRQ_WMODE);
 151 }
 152
 153 /* Set the target cpu Bitmask for Common IRQ */
 154 void idu_irq_set_tgtcpu(uint8_t irq, uint32_t mask)
 155 {
 156         IDU_SET_PARAM(mask);
 157         IDU_SET_COMMAND(irq, IDU_IRQ_WBITMASK);
 158 }
 159
 160 /* Get the Interrupt Acknowledged status for IRQ (as CPU Bitmask) */
 161 bool idu_irq_get_ack(uint8_t irq)
 162 {
 163         uint32_t val;
 164
 165         IDU_SET_COMMAND(irq, IDU_IRQ_ACK);
 166         val = IDU_GET_PARAM();
 167
 168         return val & (1 << irq);
 169 }
 170
 171 /*
 172  * Get the Interrupt Pending status for IRQ (as CPU Bitmask)
 173  * -Pending means CPU has not yet noticed the IRQ (e.g. disabled)
 174  * -After Interrupt has been taken, the IPI expcitily needs to be
 175  *  cleared, to be acknowledged.
 176  */
 177 bool idu_irq_get_pend(uint8_t irq)
 178 {
 179         uint32_t val;
 180
 181         IDU_SET_COMMAND(irq, IDU_IRQ_PEND);
 182         val = IDU_GET_PARAM();
 183
 184         return val & (1 << irq);
 185 }