2 * Copyright (C) 2012 ARM Ltd.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 #ifndef __ASM_SPINLOCK_H
17 #define __ASM_SPINLOCK_H
19 #include <asm/spinlock_types.h>
20 #include <asm/processor.h>
23 * Spinlock implementation.
25 * The memory barriers are implicit with the load-acquire and store-release
29 #define arch_spin_unlock_wait(lock) \
30 do { while (arch_spin_is_locked(lock)) cpu_relax(); } while (0)
32 #define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock)
34 static inline void arch_spin_lock(arch_spinlock_t
*lock
)
37 arch_spinlock_t lockval
, newval
;
40 /* Atomically increment the next ticket. */
41 " prfm pstl1strm, %3\n"
43 " add %w1, %w0, %w5\n"
44 " stxr %w2, %w1, %3\n"
46 /* Did we get the lock? */
47 " eor %w1, %w0, %w0, ror #16\n"
50 * No: spin on the owner. Send a local event to avoid missing an
51 * unlock before the exclusive load.
56 " eor %w1, %w2, %w0, lsr #16\n"
58 /* We got the lock. Critical section starts here. */
60 : "=&r" (lockval
), "=&r" (newval
), "=&r" (tmp
), "+Q" (*lock
)
61 : "Q" (lock
->owner
), "I" (1 << TICKET_SHIFT
)
65 static inline int arch_spin_trylock(arch_spinlock_t
*lock
)
68 arch_spinlock_t lockval
;
71 " prfm pstl1strm, %2\n"
73 " eor %w1, %w0, %w0, ror #16\n"
76 " stxr %w1, %w0, %2\n"
79 : "=&r" (lockval
), "=&r" (tmp
), "+Q" (*lock
)
80 : "I" (1 << TICKET_SHIFT
)
86 static inline void arch_spin_unlock(arch_spinlock_t
*lock
)
91 : "r" (lock
->owner
+ 1)
95 static inline int arch_spin_value_unlocked(arch_spinlock_t lock
)
97 return lock
.owner
== lock
.next
;
100 static inline int arch_spin_is_locked(arch_spinlock_t
*lock
)
102 return !arch_spin_value_unlocked(ACCESS_ONCE(*lock
));
105 static inline int arch_spin_is_contended(arch_spinlock_t
*lock
)
107 arch_spinlock_t lockval
= ACCESS_ONCE(*lock
);
108 return (lockval
.next
- lockval
.owner
) > 1;
110 #define arch_spin_is_contended arch_spin_is_contended
113 * Write lock implementation.
115 * Write locks set bit 31. Unlocking, is done by writing 0 since the lock is
118 * The memory barriers are implicit with the load-acquire and store-release
122 static inline void arch_write_lock(arch_rwlock_t
*rw
)
131 " stxr %w0, %w2, %1\n"
133 : "=&r" (tmp
), "+Q" (rw
->lock
)
138 static inline int arch_write_trylock(arch_rwlock_t
*rw
)
145 " stxr %w0, %w2, %1\n"
147 : "=&r" (tmp
), "+Q" (rw
->lock
)
154 static inline void arch_write_unlock(arch_rwlock_t
*rw
)
158 : "=Q" (rw
->lock
) : "r" (0) : "memory");
161 /* write_can_lock - would write_trylock() succeed? */
162 #define arch_write_can_lock(x) ((x)->lock == 0)
165 * Read lock implementation.
167 * It exclusively loads the lock value, increments it and stores the new value
168 * back if positive and the CPU still exclusively owns the location. If the
169 * value is negative, the lock is already held.
171 * During unlocking there may be multiple active read locks but no write lock.
173 * The memory barriers are implicit with the load-acquire and store-release
176 static inline void arch_read_lock(arch_rwlock_t
*rw
)
178 unsigned int tmp
, tmp2
;
184 " add %w0, %w0, #1\n"
185 " tbnz %w0, #31, 1b\n"
186 " stxr %w1, %w0, %2\n"
188 : "=&r" (tmp
), "=&r" (tmp2
), "+Q" (rw
->lock
)
193 static inline void arch_read_unlock(arch_rwlock_t
*rw
)
195 unsigned int tmp
, tmp2
;
199 " sub %w0, %w0, #1\n"
200 " stlxr %w1, %w0, %2\n"
202 : "=&r" (tmp
), "=&r" (tmp2
), "+Q" (rw
->lock
)
207 static inline int arch_read_trylock(arch_rwlock_t
*rw
)
209 unsigned int tmp
, tmp2
= 1;
213 " add %w0, %w0, #1\n"
214 " tbnz %w0, #31, 1f\n"
215 " stxr %w1, %w0, %2\n"
217 : "=&r" (tmp
), "+r" (tmp2
), "+Q" (rw
->lock
)
224 /* read_can_lock - would read_trylock() succeed? */
225 #define arch_read_can_lock(x) ((x)->lock < 0x80000000)
227 #define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
228 #define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
230 #define arch_spin_relax(lock) cpu_relax()
231 #define arch_read_relax(lock) cpu_relax()
232 #define arch_write_relax(lock) cpu_relax()
234 #endif /* __ASM_SPINLOCK_H */