| blob | bed028364a93235006b467c20daeb8725b9a4615 |
1 /*
2 * Low-level CPU initialisation
3 * Based on arch/arm/kernel/head.S
4 *
5 * Copyright (C) 1994-2002 Russell King
6 * Copyright (C) 2003-2012 ARM Ltd.
7 * Authors: Catalin Marinas <catalin.marinas@arm.com>
8 * Will Deacon <will.deacon@arm.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 */
23 #include <linux/linkage.h>
24 #include <linux/init.h>
25 #include <linux/irqchip/arm-gic-v3.h>
27 #include <asm/assembler.h>
28 #include <asm/ptrace.h>
29 #include <asm/asm-offsets.h>
30 #include <asm/cache.h>
31 #include <asm/cputype.h>
32 #include <asm/memory.h>
33 #include <asm/thread_info.h>
34 #include <asm/pgtable-hwdef.h>
35 #include <asm/pgtable.h>
36 #include <asm/page.h>
37 #include <asm/virt.h>
39 #define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET)
41 #if (TEXT_OFFSET & 0xfff) != 0
42 #error TEXT_OFFSET must be at least 4KB aligned
43 #elif (PAGE_OFFSET & 0x1fffff) != 0
44 #error PAGE_OFFSET must be at least 2MB aligned
45 #elif TEXT_OFFSET > 0x1fffff
46 #error TEXT_OFFSET must be less than 2MB
47 #endif
49 .macro pgtbl, ttb0, ttb1, virt_to_phys
50 ldr \ttb1, =swapper_pg_dir
51 ldr \ttb0, =idmap_pg_dir
52 add \ttb1, \ttb1, \virt_to_phys
53 add \ttb0, \ttb0, \virt_to_phys
54 .endm
56 #ifdef CONFIG_ARM64_64K_PAGES
57 #define BLOCK_SHIFT PAGE_SHIFT
58 #define BLOCK_SIZE PAGE_SIZE
59 #define TABLE_SHIFT PMD_SHIFT
60 #else
61 #define BLOCK_SHIFT SECTION_SHIFT
62 #define BLOCK_SIZE SECTION_SIZE
63 #define TABLE_SHIFT PUD_SHIFT
64 #endif
66 #define KERNEL_START KERNEL_RAM_VADDR
67 #define KERNEL_END _end
69 /*
70 * Initial memory map attributes.
71 */
72 #ifndef CONFIG_SMP
73 #define PTE_FLAGS PTE_TYPE_PAGE | PTE_AF
74 #define PMD_FLAGS PMD_TYPE_SECT | PMD_SECT_AF
75 #else
76 #define PTE_FLAGS PTE_TYPE_PAGE | PTE_AF | PTE_SHARED
77 #define PMD_FLAGS PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S
78 #endif
80 #ifdef CONFIG_ARM64_64K_PAGES
81 #define MM_MMUFLAGS PTE_ATTRINDX(MT_NORMAL) | PTE_FLAGS
82 #else
83 #define MM_MMUFLAGS PMD_ATTRINDX(MT_NORMAL) | PMD_FLAGS
84 #endif
86 /*
87 * Kernel startup entry point.
88 * ---------------------------
89 *
90 * The requirements are:
91 * MMU = off, D-cache = off, I-cache = on or off,
92 * x0 = physical address to the FDT blob.
93 *
94 * This code is mostly position independent so you call this at
95 * __pa(PAGE_OFFSET + TEXT_OFFSET).
96 *
97 * Note that the callee-saved registers are used for storing variables
98 * that are useful before the MMU is enabled. The allocations are described
99 * in the entry routines.
100 */
101 __HEAD
103 /*
104 * DO NOT MODIFY. Image header expected by Linux boot-loaders.
105 */
106 #ifdef CONFIG_EFI
107 efi_head:
108 /*
109 * This add instruction has no meaningful effect except that
110 * its opcode forms the magic "MZ" signature required by UEFI.
111 */
112 add x13, x18, #0x16
113 b stext
114 #else
115 b stext // branch to kernel start, magic
116 .long 0 // reserved
117 #endif
118 .quad _kernel_offset_le // Image load offset from start of RAM, little-endian
119 .quad _kernel_size_le // Effective size of kernel image, little-endian
120 .quad _kernel_flags_le // Informative flags, little-endian
121 .quad 0 // reserved
122 .quad 0 // reserved
123 .quad 0 // reserved
124 .byte 0x41 // Magic number, "ARM\x64"
125 .byte 0x52
126 .byte 0x4d
127 .byte 0x64
128 #ifdef CONFIG_EFI
129 .long pe_header - efi_head // Offset to the PE header.
130 #else
131 .word 0 // reserved
132 #endif
134 #ifdef CONFIG_EFI
135 .align 3
136 pe_header:
137 .ascii "PE"
138 .short 0
139 coff_header:
140 .short 0xaa64 // AArch64
141 .short 2 // nr_sections
142 .long 0 // TimeDateStamp
143 .long 0 // PointerToSymbolTable
144 .long 1 // NumberOfSymbols
145 .short section_table - optional_header // SizeOfOptionalHeader
146 .short 0x206 // Characteristics.
147 // IMAGE_FILE_DEBUG_STRIPPED |
148 // IMAGE_FILE_EXECUTABLE_IMAGE |
149 // IMAGE_FILE_LINE_NUMS_STRIPPED
150 optional_header:
151 .short 0x20b // PE32+ format
152 .byte 0x02 // MajorLinkerVersion
153 .byte 0x14 // MinorLinkerVersion
154 .long _edata - stext // SizeOfCode
155 .long 0 // SizeOfInitializedData
156 .long 0 // SizeOfUninitializedData
157 .long efi_stub_entry - efi_head // AddressOfEntryPoint
158 .long stext - efi_head // BaseOfCode
160 extra_header_fields:
161 .quad 0 // ImageBase
162 .long 0x20 // SectionAlignment
163 .long 0x8 // FileAlignment
164 .short 0 // MajorOperatingSystemVersion
165 .short 0 // MinorOperatingSystemVersion
166 .short 0 // MajorImageVersion
167 .short 0 // MinorImageVersion
168 .short 0 // MajorSubsystemVersion
169 .short 0 // MinorSubsystemVersion
170 .long 0 // Win32VersionValue
172 .long _edata - efi_head // SizeOfImage
174 // Everything before the kernel image is considered part of the header
175 .long stext - efi_head // SizeOfHeaders
176 .long 0 // CheckSum
177 .short 0xa // Subsystem (EFI application)
178 .short 0 // DllCharacteristics
179 .quad 0 // SizeOfStackReserve
180 .quad 0 // SizeOfStackCommit
181 .quad 0 // SizeOfHeapReserve
182 .quad 0 // SizeOfHeapCommit
183 .long 0 // LoaderFlags
184 .long 0x6 // NumberOfRvaAndSizes
186 .quad 0 // ExportTable
187 .quad 0 // ImportTable
188 .quad 0 // ResourceTable
189 .quad 0 // ExceptionTable
190 .quad 0 // CertificationTable
191 .quad 0 // BaseRelocationTable
193 // Section table
194 section_table:
196 /*
197 * The EFI application loader requires a relocation section
198 * because EFI applications must be relocatable. This is a
199 * dummy section as far as we are concerned.
200 */
201 .ascii ".reloc"
202 .byte 0
203 .byte 0 // end of 0 padding of section name
204 .long 0
205 .long 0
206 .long 0 // SizeOfRawData
207 .long 0 // PointerToRawData
208 .long 0 // PointerToRelocations
209 .long 0 // PointerToLineNumbers
210 .short 0 // NumberOfRelocations
211 .short 0 // NumberOfLineNumbers
212 .long 0x42100040 // Characteristics (section flags)
215 .ascii ".text"
216 .byte 0
217 .byte 0
218 .byte 0 // end of 0 padding of section name
219 .long _edata - stext // VirtualSize
220 .long stext - efi_head // VirtualAddress
221 .long _edata - stext // SizeOfRawData
222 .long stext - efi_head // PointerToRawData
224 .long 0 // PointerToRelocations (0 for executables)
225 .long 0 // PointerToLineNumbers (0 for executables)
226 .short 0 // NumberOfRelocations (0 for executables)
227 .short 0 // NumberOfLineNumbers (0 for executables)
228 .long 0xe0500020 // Characteristics (section flags)
229 .align 5
230 #endif
232 ENTRY(stext)
233 mov x21, x0 // x21=FDT
234 bl el2_setup // Drop to EL1, w20=cpu_boot_mode
235 bl __calc_phys_offset // x24=PHYS_OFFSET, x28=PHYS_OFFSET-PAGE_OFFSET
236 bl set_cpu_boot_mode_flag
237 mrs x22, midr_el1 // x22=cpuid
238 mov x0, x22
239 bl lookup_processor_type
240 mov x23, x0 // x23=current cpu_table
241 cbz x23, __error_p // invalid processor (x23=0)?
242 bl __vet_fdt
243 bl __create_page_tables // x25=TTBR0, x26=TTBR1
244 /*
245 * The following calls CPU specific code in a position independent
246 * manner. See arch/arm64/mm/proc.S for details. x23 = base of
247 * cpu_info structure selected by lookup_processor_type above.
248 * On return, the CPU will be ready for the MMU to be turned on and
249 * the TCR will have been set.
250 */
251 ldr x27, __switch_data // address to jump to after
252 // MMU has been enabled
253 adr lr, __enable_mmu // return (PIC) address
254 ldr x12, [x23, #CPU_INFO_SETUP]
255 add x12, x12, x28 // __virt_to_phys
256 br x12 // initialise processor
257 ENDPROC(stext)
259 /*
260 * If we're fortunate enough to boot at EL2, ensure that the world is
261 * sane before dropping to EL1.
262 *
263 * Returns either BOOT_CPU_MODE_EL1 or BOOT_CPU_MODE_EL2 in x20 if
264 * booted in EL1 or EL2 respectively.
265 */
266 ENTRY(el2_setup)
267 mrs x0, CurrentEL
268 cmp x0, #CurrentEL_EL2
269 b.ne 1f
270 mrs x0, sctlr_el2
271 CPU_BE( orr x0, x0, #(1 << 25) ) // Set the EE bit for EL2
272 CPU_LE( bic x0, x0, #(1 << 25) ) // Clear the EE bit for EL2
273 msr sctlr_el2, x0
274 b 2f
275 1: mrs x0, sctlr_el1
276 CPU_BE( orr x0, x0, #(3 << 24) ) // Set the EE and E0E bits for EL1
277 CPU_LE( bic x0, x0, #(3 << 24) ) // Clear the EE and E0E bits for EL1
278 msr sctlr_el1, x0
279 mov w20, #BOOT_CPU_MODE_EL1 // This cpu booted in EL1
280 isb
281 ret
283 /* Hyp configuration. */
284 2: mov x0, #(1 << 31) // 64-bit EL1
285 msr hcr_el2, x0
287 /* Generic timers. */
288 mrs x0, cnthctl_el2
289 orr x0, x0, #3 // Enable EL1 physical timers
290 msr cnthctl_el2, x0
291 msr cntvoff_el2, xzr // Clear virtual offset
293 #ifdef CONFIG_ARM_GIC_V3
294 /* GICv3 system register access */
295 mrs x0, id_aa64pfr0_el1
296 ubfx x0, x0, #24, #4
297 cmp x0, #1
298 b.ne 3f
300 mrs_s x0, ICC_SRE_EL2
301 orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1
302 orr x0, x0, #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1
303 msr_s ICC_SRE_EL2, x0
304 isb // Make sure SRE is now set
305 msr_s ICH_HCR_EL2, xzr // Reset ICC_HCR_EL2 to defaults
307 3:
308 #endif
310 /* Populate ID registers. */
311 mrs x0, midr_el1
312 mrs x1, mpidr_el1
313 msr vpidr_el2, x0
314 msr vmpidr_el2, x1
316 /* sctlr_el1 */
317 mov x0, #0x0800 // Set/clear RES{1,0} bits
318 CPU_BE( movk x0, #0x33d0, lsl #16 ) // Set EE and E0E on BE systems
319 CPU_LE( movk x0, #0x30d0, lsl #16 ) // Clear EE and E0E on LE systems
320 msr sctlr_el1, x0
322 /* Coprocessor traps. */
323 mov x0, #0x33ff
324 msr cptr_el2, x0 // Disable copro. traps to EL2
326 #ifdef CONFIG_COMPAT
327 msr hstr_el2, xzr // Disable CP15 traps to EL2
328 #endif
330 /* Stage-2 translation */
331 msr vttbr_el2, xzr
333 /* Hypervisor stub */
334 adr x0, __hyp_stub_vectors
335 msr vbar_el2, x0
337 /* spsr */
338 mov x0, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT |\
339 PSR_MODE_EL1h)
340 msr spsr_el2, x0
341 msr elr_el2, lr
342 mov w20, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2
343 eret
344 ENDPROC(el2_setup)
346 /*
347 * Sets the __boot_cpu_mode flag depending on the CPU boot mode passed
348 * in x20. See arch/arm64/include/asm/virt.h for more info.
349 */
350 ENTRY(set_cpu_boot_mode_flag)
351 ldr x1, =__boot_cpu_mode // Compute __boot_cpu_mode
352 add x1, x1, x28
353 cmp w20, #BOOT_CPU_MODE_EL2
354 b.ne 1f
355 add x1, x1, #4
356 1: str w20, [x1] // This CPU has booted in EL1
357 dmb sy
358 dc ivac, x1 // Invalidate potentially stale cache line
359 ret
360 ENDPROC(set_cpu_boot_mode_flag)
362 /*
363 * We need to find out the CPU boot mode long after boot, so we need to
364 * store it in a writable variable.
365 *
366 * This is not in .bss, because we set it sufficiently early that the boot-time
367 * zeroing of .bss would clobber it.
368 */
369 .pushsection .data..cacheline_aligned
370 ENTRY(__boot_cpu_mode)
371 .align L1_CACHE_SHIFT
372 .long BOOT_CPU_MODE_EL2
373 .long 0
374 .popsection
376 .align 3
377 2: .quad .
378 .quad PAGE_OFFSET
380 #ifdef CONFIG_SMP
381 .align 3
382 1: .quad .
383 .quad secondary_holding_pen_release
385 /*
386 * This provides a "holding pen" for platforms to hold all secondary
387 * cores are held until we're ready for them to initialise.
388 */
389 ENTRY(secondary_holding_pen)
390 bl el2_setup // Drop to EL1, w20=cpu_boot_mode
391 bl __calc_phys_offset // x24=PHYS_OFFSET, x28=PHYS_OFFSET-PAGE_OFFSET
392 bl set_cpu_boot_mode_flag
393 mrs x0, mpidr_el1
394 ldr x1, =MPIDR_HWID_BITMASK
395 and x0, x0, x1
396 adr x1, 1b
397 ldp x2, x3, [x1]
398 sub x1, x1, x2
399 add x3, x3, x1
400 pen: ldr x4, [x3]
401 cmp x4, x0
402 b.eq secondary_startup
403 wfe
404 b pen
405 ENDPROC(secondary_holding_pen)
407 /*
408 * Secondary entry point that jumps straight into the kernel. Only to
409 * be used where CPUs are brought online dynamically by the kernel.
410 */
411 ENTRY(secondary_entry)
412 bl el2_setup // Drop to EL1
413 bl __calc_phys_offset // x24=PHYS_OFFSET, x28=PHYS_OFFSET-PAGE_OFFSET
414 bl set_cpu_boot_mode_flag
415 b secondary_startup
416 ENDPROC(secondary_entry)
418 ENTRY(secondary_startup)
419 /*
420 * Common entry point for secondary CPUs.
421 */
422 mrs x22, midr_el1 // x22=cpuid
423 mov x0, x22
424 bl lookup_processor_type
425 mov x23, x0 // x23=current cpu_table
426 cbz x23, __error_p // invalid processor (x23=0)?
428 pgtbl x25, x26, x28 // x25=TTBR0, x26=TTBR1
429 ldr x12, [x23, #CPU_INFO_SETUP]
430 add x12, x12, x28 // __virt_to_phys
431 blr x12 // initialise processor
433 ldr x21, =secondary_data
434 ldr x27, =__secondary_switched // address to jump to after enabling the MMU
435 b __enable_mmu
436 ENDPROC(secondary_startup)
438 ENTRY(__secondary_switched)
439 ldr x0, [x21] // get secondary_data.stack
440 mov sp, x0
441 mov x29, #0
442 b secondary_start_kernel
443 ENDPROC(__secondary_switched)
444 #endif /* CONFIG_SMP */
446 /*
447 * Setup common bits before finally enabling the MMU. Essentially this is just
448 * loading the page table pointer and vector base registers.
449 *
450 * On entry to this code, x0 must contain the SCTLR_EL1 value for turning on
451 * the MMU.
452 */
453 __enable_mmu:
454 ldr x5, =vectors
455 msr vbar_el1, x5
456 msr ttbr0_el1, x25 // load TTBR0
457 msr ttbr1_el1, x26 // load TTBR1
458 isb
459 b __turn_mmu_on
460 ENDPROC(__enable_mmu)
462 /*
463 * Enable the MMU. This completely changes the structure of the visible memory
464 * space. You will not be able to trace execution through this.
465 *
466 * x0 = system control register
467 * x27 = *virtual* address to jump to upon completion
468 *
469 * other registers depend on the function called upon completion
470 *
471 * We align the entire function to the smallest power of two larger than it to
472 * ensure it fits within a single block map entry. Otherwise were PHYS_OFFSET
473 * close to the end of a 512MB or 1GB block we might require an additional
474 * table to map the entire function.
475 */
476 .align 4
477 __turn_mmu_on:
478 msr sctlr_el1, x0
479 isb
480 br x27
481 ENDPROC(__turn_mmu_on)
483 /*
484 * Calculate the start of physical memory.
485 */
486 __calc_phys_offset:
487 adr x0, 1f
488 ldp x1, x2, [x0]
489 sub x28, x0, x1 // x28 = PHYS_OFFSET - PAGE_OFFSET
490 add x24, x2, x28 // x24 = PHYS_OFFSET
491 ret
492 ENDPROC(__calc_phys_offset)
494 .align 3
495 1: .quad .
496 .quad PAGE_OFFSET
498 /*
499 * Macro to create a table entry to the next page.
500 *
501 * tbl: page table address
502 * virt: virtual address
503 * shift: #imm page table shift
504 * ptrs: #imm pointers per table page
505 *
506 * Preserves: virt
507 * Corrupts: tmp1, tmp2
508 * Returns: tbl -> next level table page address
509 */
510 .macro create_table_entry, tbl, virt, shift, ptrs, tmp1, tmp2
511 lsr \tmp1, \virt, #\shift
512 and \tmp1, \tmp1, #\ptrs - 1 // table index
513 add \tmp2, \tbl, #PAGE_SIZE
514 orr \tmp2, \tmp2, #PMD_TYPE_TABLE // address of next table and entry type
515 str \tmp2, [\tbl, \tmp1, lsl #3]
516 add \tbl, \tbl, #PAGE_SIZE // next level table page
517 .endm
519 /*
520 * Macro to populate the PGD (and possibily PUD) for the corresponding
521 * block entry in the next level (tbl) for the given virtual address.
522 *
523 * Preserves: tbl, next, virt
524 * Corrupts: tmp1, tmp2
525 */
526 .macro create_pgd_entry, tbl, virt, tmp1, tmp2
527 create_table_entry \tbl, \virt, PGDIR_SHIFT, PTRS_PER_PGD, \tmp1, \tmp2
528 #if SWAPPER_PGTABLE_LEVELS == 3
529 create_table_entry \tbl, \virt, TABLE_SHIFT, PTRS_PER_PTE, \tmp1, \tmp2
530 #endif
531 .endm
533 /*
534 * Macro to populate block entries in the page table for the start..end
535 * virtual range (inclusive).
536 *
537 * Preserves: tbl, flags
538 * Corrupts: phys, start, end, pstate
539 */
540 .macro create_block_map, tbl, flags, phys, start, end
541 lsr \phys, \phys, #BLOCK_SHIFT
542 lsr \start, \start, #BLOCK_SHIFT
543 and \start, \start, #PTRS_PER_PTE - 1 // table index
544 orr \phys, \flags, \phys, lsl #BLOCK_SHIFT // table entry
545 lsr \end, \end, #BLOCK_SHIFT
546 and \end, \end, #PTRS_PER_PTE - 1 // table end index
547 9999: str \phys, [\tbl, \start, lsl #3] // store the entry
548 add \start, \start, #1 // next entry
549 add \phys, \phys, #BLOCK_SIZE // next block
550 cmp \start, \end
551 b.ls 9999b
552 .endm
554 /*
555 * Setup the initial page tables. We only setup the barest amount which is
556 * required to get the kernel running. The following sections are required:
557 * - identity mapping to enable the MMU (low address, TTBR0)
558 * - first few MB of the kernel linear mapping to jump to once the MMU has
559 * been enabled, including the FDT blob (TTBR1)
560 * - pgd entry for fixed mappings (TTBR1)
561 */
562 __create_page_tables:
563 pgtbl x25, x26, x28 // idmap_pg_dir and swapper_pg_dir addresses
564 mov x27, lr
566 /*
567 * Invalidate the idmap and swapper page tables to avoid potential
568 * dirty cache lines being evicted.
569 */
570 mov x0, x25
571 add x1, x26, #SWAPPER_DIR_SIZE
572 bl __inval_cache_range
574 /*
575 * Clear the idmap and swapper page tables.
576 */
577 mov x0, x25
578 add x6, x26, #SWAPPER_DIR_SIZE
579 1: stp xzr, xzr, [x0], #16
580 stp xzr, xzr, [x0], #16
581 stp xzr, xzr, [x0], #16
582 stp xzr, xzr, [x0], #16
583 cmp x0, x6
584 b.lo 1b
586 ldr x7, =MM_MMUFLAGS
588 /*
589 * Create the identity mapping.
590 */
591 mov x0, x25 // idmap_pg_dir
592 ldr x3, =KERNEL_START
593 add x3, x3, x28 // __pa(KERNEL_START)
594 create_pgd_entry x0, x3, x5, x6
595 ldr x6, =KERNEL_END
596 mov x5, x3 // __pa(KERNEL_START)
597 add x6, x6, x28 // __pa(KERNEL_END)
598 create_block_map x0, x7, x3, x5, x6
600 /*
601 * Map the kernel image (starting with PHYS_OFFSET).
602 */
603 mov x0, x26 // swapper_pg_dir
604 mov x5, #PAGE_OFFSET
605 create_pgd_entry x0, x5, x3, x6
606 ldr x6, =KERNEL_END
607 mov x3, x24 // phys offset
608 create_block_map x0, x7, x3, x5, x6
610 /*
611 * Map the FDT blob (maximum 2MB; must be within 512MB of
612 * PHYS_OFFSET).
613 */
614 mov x3, x21 // FDT phys address
615 and x3, x3, #~((1 << 21) - 1) // 2MB aligned
616 mov x6, #PAGE_OFFSET
617 sub x5, x3, x24 // subtract PHYS_OFFSET
618 tst x5, #~((1 << 29) - 1) // within 512MB?
619 csel x21, xzr, x21, ne // zero the FDT pointer
620 b.ne 1f
621 add x5, x5, x6 // __va(FDT blob)
622 add x6, x5, #1 << 21 // 2MB for the FDT blob
623 sub x6, x6, #1 // inclusive range
624 create_block_map x0, x7, x3, x5, x6
625 1:
626 /*
627 * Since the page tables have been populated with non-cacheable
628 * accesses (MMU disabled), invalidate the idmap and swapper page
629 * tables again to remove any speculatively loaded cache lines.
630 */
631 mov x0, x25
632 add x1, x26, #SWAPPER_DIR_SIZE
633 bl __inval_cache_range
635 mov lr, x27
636 ret
637 ENDPROC(__create_page_tables)
638 .ltorg
640 .align 3
641 .type __switch_data, %object
642 __switch_data:
643 .quad __mmap_switched
644 .quad __bss_start // x6
645 .quad __bss_stop // x7
646 .quad processor_id // x4
647 .quad __fdt_pointer // x5
648 .quad memstart_addr // x6
649 .quad init_thread_union + THREAD_START_SP // sp
651 /*
652 * The following fragment of code is executed with the MMU on in MMU mode, and
653 * uses absolute addresses; this is not position independent.
654 */
655 __mmap_switched:
656 adr x3, __switch_data + 8
658 ldp x6, x7, [x3], #16
659 1: cmp x6, x7
660 b.hs 2f
661 str xzr, [x6], #8 // Clear BSS
662 b 1b
663 2:
664 ldp x4, x5, [x3], #16
665 ldr x6, [x3], #8
666 ldr x16, [x3]
667 mov sp, x16
668 str x22, [x4] // Save processor ID
669 str x21, [x5] // Save FDT pointer
670 str x24, [x6] // Save PHYS_OFFSET
671 mov x29, #0
672 b start_kernel
673 ENDPROC(__mmap_switched)
675 /*
676 * Exception handling. Something went wrong and we can't proceed. We ought to
677 * tell the user, but since we don't have any guarantee that we're even
678 * running on the right architecture, we do virtually nothing.
679 */
680 __error_p:
681 ENDPROC(__error_p)
683 __error:
684 1: nop
685 b 1b
686 ENDPROC(__error)
688 /*
689 * This function gets the processor ID in w0 and searches the cpu_table[] for
690 * a match. It returns a pointer to the struct cpu_info it found. The
691 * cpu_table[] must end with an empty (all zeros) structure.
692 *
693 * This routine can be called via C code and it needs to work with the MMU
694 * both disabled and enabled (the offset is calculated automatically).
695 */
696 ENTRY(lookup_processor_type)
697 adr x1, __lookup_processor_type_data
698 ldp x2, x3, [x1]
699 sub x1, x1, x2 // get offset between VA and PA
700 add x3, x3, x1 // convert VA to PA
701 1:
702 ldp w5, w6, [x3] // load cpu_id_val and cpu_id_mask
703 cbz w5, 2f // end of list?
704 and w6, w6, w0
705 cmp w5, w6
706 b.eq 3f
707 add x3, x3, #CPU_INFO_SZ
708 b 1b
709 2:
710 mov x3, #0 // unknown processor
711 3:
712 mov x0, x3
713 ret
714 ENDPROC(lookup_processor_type)
716 .align 3
717 .type __lookup_processor_type_data, %object
718 __lookup_processor_type_data:
719 .quad .
720 .quad cpu_table
721 .size __lookup_processor_type_data, . - __lookup_processor_type_data
723 /*
724 * Determine validity of the x21 FDT pointer.
725 * The dtb must be 8-byte aligned and live in the first 512M of memory.
726 */
727 __vet_fdt:
728 tst x21, #0x7
729 b.ne 1f
730 cmp x21, x24
731 b.lt 1f
732 mov x0, #(1 << 29)
733 add x0, x0, x24
734 cmp x21, x0
735 b.ge 1f
736 ret
737 1:
738 mov x21, #0
739 ret
740 ENDPROC(__vet_fdt)