2 * Blackfin power management
4 * Copyright 2006-2009 Analog Devices Inc.
6 * Licensed under the GPL-2
7 * based on arm/mach-omap/pm.c
8 * Copyright 2001, Cliff Brake <cbrake@accelent.com> and others
11 #include <linux/suspend.h>
12 #include <linux/sched.h>
13 #include <linux/proc_fs.h>
14 #include <linux/slab.h>
16 #include <linux/irq.h>
25 struct bfin_cpu_pm_fns
*bfin_cpu_pm
;
28 void bfin_pm_suspend_standby_enter(void)
31 bfin_pm_standby_setup();
35 bfin_cpu_pm
->enter(PM_SUSPEND_STANDBY
);
37 # ifdef CONFIG_PM_BFIN_SLEEP_DEEPER
38 sleep_deeper(bfin_sic_iwr
[0], bfin_sic_iwr
[1], bfin_sic_iwr
[2]);
40 sleep_mode(bfin_sic_iwr
[0], bfin_sic_iwr
[1], bfin_sic_iwr
[2]);
45 bfin_pm_standby_restore();
50 bfin_write_SIC_IWR0(IWR_DISABLE_ALL
);
52 /* BF52x system reset does not properly reset SIC_IWR1 which
53 * will screw up the bootrom as it relies on MDMA0/1 waking it
54 * up from IDLE instructions. See this report for more info:
55 * http://blackfin.uclinux.org/gf/tracker/4323
58 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
60 bfin_write_SIC_IWR1(IWR_DISABLE_ALL
);
63 bfin_write_SIC_IWR2(IWR_DISABLE_ALL
);
66 bfin_write_SIC_IWR(IWR_DISABLE_ALL
);
72 int bf53x_suspend_l1_mem(unsigned char *memptr
)
74 dma_memcpy_nocache(memptr
, (const void *) L1_CODE_START
,
76 dma_memcpy_nocache(memptr
+ L1_CODE_LENGTH
,
77 (const void *) L1_DATA_A_START
, L1_DATA_A_LENGTH
);
78 dma_memcpy_nocache(memptr
+ L1_CODE_LENGTH
+ L1_DATA_A_LENGTH
,
79 (const void *) L1_DATA_B_START
, L1_DATA_B_LENGTH
);
80 memcpy(memptr
+ L1_CODE_LENGTH
+ L1_DATA_A_LENGTH
+
81 L1_DATA_B_LENGTH
, (const void *) L1_SCRATCH_START
,
87 int bf53x_resume_l1_mem(unsigned char *memptr
)
89 dma_memcpy_nocache((void *) L1_CODE_START
, memptr
, L1_CODE_LENGTH
);
90 dma_memcpy_nocache((void *) L1_DATA_A_START
, memptr
+ L1_CODE_LENGTH
,
92 dma_memcpy_nocache((void *) L1_DATA_B_START
, memptr
+ L1_CODE_LENGTH
+
93 L1_DATA_A_LENGTH
, L1_DATA_B_LENGTH
);
94 memcpy((void *) L1_SCRATCH_START
, memptr
+ L1_CODE_LENGTH
+
95 L1_DATA_A_LENGTH
+ L1_DATA_B_LENGTH
, L1_SCRATCH_LENGTH
);
100 #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
102 __attribute__((l1_text
))
104 static void flushinv_all_dcache(void)
106 register u32 way
, bank
, subbank
, set
;
107 register u32 status
, addr
;
108 u32 dmem_ctl
= bfin_read_DMEM_CONTROL();
110 for (bank
= 0; bank
< 2; ++bank
) {
111 if (!(dmem_ctl
& (1 << (DMC1_P
- bank
))))
114 for (way
= 0; way
< 2; ++way
)
115 for (subbank
= 0; subbank
< 4; ++subbank
)
116 for (set
= 0; set
< 64; ++set
) {
118 bfin_write_DTEST_COMMAND(
125 status
= bfin_read_DTEST_DATA0();
127 /* only worry about valid/dirty entries */
128 if ((status
& 0x3) != 0x3)
132 /* construct the address using the tag */
133 addr
= (status
& 0xFFFFC800) | (subbank
<< 12) | (set
<< 5);
136 __asm__
__volatile__("FLUSHINV[%0];" : : "a"(addr
));
142 int bfin_pm_suspend_mem_enter(void)
149 unsigned char *memptr
= kmalloc(L1_CODE_LENGTH
+ L1_DATA_A_LENGTH
150 + L1_DATA_B_LENGTH
+ L1_SCRATCH_LENGTH
,
153 if (memptr
== NULL
) {
154 panic("bf53x_suspend_l1_mem malloc failed");
159 wakeup
= bfin_read_VR_CTL() & ~FREQ
;
162 #ifdef CONFIG_PM_BFIN_WAKE_PH6
165 #ifdef CONFIG_PM_BFIN_WAKE_GP
170 ret
= blackfin_dma_suspend();
177 #ifdef CONFIG_GPIO_ADI
178 bfin_gpio_pm_hibernate_suspend();
181 #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
182 flushinv_all_dcache();
186 bf53x_suspend_l1_mem(memptr
);
189 do_hibernate(wakeup
| vr_wakeup
); /* See you later! */
191 bfin_cpu_pm
->enter(PM_SUSPEND_MEM
);
194 bf53x_resume_l1_mem(memptr
);
199 #ifdef CONFIG_GPIO_ADI
200 bfin_gpio_pm_hibernate_restore();
202 blackfin_dma_resume();
210 * bfin_pm_valid - Tell the PM core that we only support the standby sleep
212 * @state: suspend state we're checking.
215 static int bfin_pm_valid(suspend_state_t state
)
217 return (state
== PM_SUSPEND_STANDBY
218 #if !(defined(BF533_FAMILY) || defined(CONFIG_BF561))
221 * If we enter Hibernate the SCKE Pin is driven Low,
222 * so that the SDRAM enters Self Refresh Mode.
223 * However when the reset sequence that follows hibernate
224 * state is executed, SCKE is driven High, taking the
225 * SDRAM out of Self Refresh.
227 * If you reconfigure and access the SDRAM "very quickly",
228 * you are likely to avoid errors, otherwise the SDRAM
229 * start losing its contents.
230 * An external HW workaround is possible using logic gates.
232 || state
== PM_SUSPEND_MEM
238 * bfin_pm_enter - Actually enter a sleep state.
239 * @state: State we're entering.
242 static int bfin_pm_enter(suspend_state_t state
)
245 case PM_SUSPEND_STANDBY
:
246 bfin_pm_suspend_standby_enter();
249 bfin_pm_suspend_mem_enter();
258 #ifdef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH
259 void bfin_pm_end(void)
265 __asm__
__volatile__ (
271 : "=d,a" (cycle2
), "=d,a" (cycle
), "=d,a" (usec
) : : "CC"
274 usec64
= ((u64
)cycle2
<< 32) + cycle
;
275 do_div(usec64
, get_cclk() / USEC_PER_SEC
);
280 pr_info("PM: resume of kernel completes after %ld msec %03ld usec\n",
281 usec
/ USEC_PER_MSEC
, usec
% USEC_PER_MSEC
);
285 static const struct platform_suspend_ops bfin_pm_ops
= {
286 .enter
= bfin_pm_enter
,
287 .valid
= bfin_pm_valid
,
288 #ifdef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH
293 static int __init
bfin_pm_init(void)
295 suspend_set_ops(&bfin_pm_ops
);
299 __initcall(bfin_pm_init
);