arch/hexagon/include/asm/io.h

   1 /*
   2  * IO definitions for the Hexagon architecture
   3  *
   4  * Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 and
   8  * only version 2 as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  18  * 02110-1301, USA.
  19  */
  20
  21 #ifndef _ASM_IO_H
  22 #define _ASM_IO_H
  23
  24 #ifdef __KERNEL__
  25
  26 #include <linux/types.h>
  27 #include <linux/delay.h>
  28 #include <linux/vmalloc.h>
  29 #include <asm/string.h>
  30 #include <asm/mem-layout.h>
  31 #include <asm/iomap.h>
  32 #include <asm/page.h>
  33 #include <asm/cacheflush.h>
  34 #include <asm/tlbflush.h>
  35
  36 /*
  37  * We don't have PCI yet.
  38  * _IO_BASE is pointing at what should be unused virtual space.
  39  */
  40 #define IO_SPACE_LIMIT 0xffff
  41 #define _IO_BASE ((void __iomem *)0xfe000000)
  42
  43 #define IOMEM(x)        ((void __force __iomem *)(x))
  44
  45 extern int remap_area_pages(unsigned long start, unsigned long phys_addr,
  46                                 unsigned long end, unsigned long flags);
  47
  48 extern void __iounmap(const volatile void __iomem *addr);
  49
  50 /* Defined in lib/io.c, needed for smc91x driver. */
  51 extern void __raw_readsw(const void __iomem *addr, void *data, int wordlen);
  52 extern void __raw_writesw(void __iomem *addr, const void *data, int wordlen);
  53
  54 extern void __raw_readsl(const void __iomem *addr, void *data, int wordlen);
  55 extern void __raw_writesl(void __iomem *addr, const void *data, int wordlen);
  56
  57 #define readsw(p, d, l) __raw_readsw(p, d, l)
  58 #define writesw(p, d, l) __raw_writesw(p, d, l)
  59
  60 #define readsl(p, d, l)   __raw_readsl(p, d, l)
  61 #define writesl(p, d, l)  __raw_writesl(p, d, l)
  62
  63 /*
  64  * virt_to_phys - map virtual address to physical
  65  * @address:  address to map
  66  */
  67 static inline unsigned long virt_to_phys(volatile void *address)
  68 {
  69         return __pa(address);
  70 }
  71
  72 /*
  73  * phys_to_virt - map physical address to virtual
  74  * @address: address to map
  75  */
  76 static inline void *phys_to_virt(unsigned long address)
  77 {
  78         return __va(address);
  79 }
  80
  81 /*
  82  * convert a physical pointer to a virtual kernel pointer for
  83  * /dev/mem access.
  84  */
  85 #define xlate_dev_kmem_ptr(p)    __va(p)
  86 #define xlate_dev_mem_ptr(p)    __va(p)
  87
  88 /*
  89  * IO port access primitives.  Hexagon doesn't have special IO access
  90  * instructions; all I/O is memory mapped.
  91  *
  92  * in/out are used for "ports", but we don't have "port instructions",
  93  * so these are really just memory mapped too.
  94  */
  95
  96 /*
  97  * readb - read byte from memory mapped device
  98  * @addr:  pointer to memory
  99  *
 100  * Operates on "I/O bus memory space"
 101  */
 102 static inline u8 readb(const volatile void __iomem *addr)
 103 {
 104         u8 val;
 105         asm volatile(
 106                 "%0 = memb(%1);"
 107                 : "=&r" (val)
 108                 : "r" (addr)
 109         );
 110         return val;
 111 }
 112
 113 static inline u16 readw(const volatile void __iomem *addr)
 114 {
 115         u16 val;
 116         asm volatile(
 117                 "%0 = memh(%1);"
 118                 : "=&r" (val)
 119                 : "r" (addr)
 120         );
 121         return val;
 122 }
 123
 124 static inline u32 readl(const volatile void __iomem *addr)
 125 {
 126         u32 val;
 127         asm volatile(
 128                 "%0 = memw(%1);"
 129                 : "=&r" (val)
 130                 : "r" (addr)
 131         );
 132         return val;
 133 }
 134
 135 /*
 136  * writeb - write a byte to a memory location
 137  * @data: data to write to
 138  * @addr:  pointer to memory
 139  *
 140  */
 141 static inline void writeb(u8 data, volatile void __iomem *addr)
 142 {
 143         asm volatile(
 144                 "memb(%0) = %1;"
 145                 :
 146                 : "r" (addr), "r" (data)
 147                 : "memory"
 148         );
 149 }
 150
 151 static inline void writew(u16 data, volatile void __iomem *addr)
 152 {
 153         asm volatile(
 154                 "memh(%0) = %1;"
 155                 :
 156                 : "r" (addr), "r" (data)
 157                 : "memory"
 158         );
 159
 160 }
 161
 162 static inline void writel(u32 data, volatile void __iomem *addr)
 163 {
 164         asm volatile(
 165                 "memw(%0) = %1;"
 166                 :
 167                 : "r" (addr), "r" (data)
 168                 : "memory"
 169         );
 170 }
 171
 172 #define __raw_writeb writeb
 173 #define __raw_writew writew
 174 #define __raw_writel writel
 175
 176 #define __raw_readb readb
 177 #define __raw_readw readw
 178 #define __raw_readl readl
 179
 180 /*
 181  * http://comments.gmane.org/gmane.linux.ports.arm.kernel/117626
 182  */
 183
 184 #define readb_relaxed __raw_readb
 185 #define readw_relaxed __raw_readw
 186 #define readl_relaxed __raw_readl
 187
 188 #define writeb_relaxed __raw_writeb
 189 #define writew_relaxed __raw_writew
 190 #define writel_relaxed __raw_writel
 191
 192 #define mmiowb()
 193
 194 /*
 195  * Need an mtype somewhere in here, for cache type deals?
 196  * This is probably too long for an inline.
 197  */
 198 void __iomem *ioremap_nocache(unsigned long phys_addr, unsigned long size);
 199
 200 static inline void __iomem *ioremap(unsigned long phys_addr, unsigned long size)
 201 {
 202         return ioremap_nocache(phys_addr, size);
 203 }
 204
 205 static inline void iounmap(volatile void __iomem *addr)
 206 {
 207         __iounmap(addr);
 208 }
 209
 210 #define __raw_writel writel
 211
 212 static inline void memcpy_fromio(void *dst, const volatile void __iomem *src,
 213         int count)
 214 {
 215         memcpy(dst, (void *) src, count);
 216 }
 217
 218 static inline void memcpy_toio(volatile void __iomem *dst, const void *src,
 219         int count)
 220 {
 221         memcpy((void *) dst, src, count);
 222 }
 223
 224 #define PCI_IO_ADDR     (volatile void __iomem *)
 225
 226 /*
 227  * inb - read byte from I/O port or something
 228  * @port:  address in I/O space
 229  *
 230  * Operates on "I/O bus I/O space"
 231  */
 232 static inline u8 inb(unsigned long port)
 233 {
 234         return readb(_IO_BASE + (port & IO_SPACE_LIMIT));
 235 }
 236
 237 static inline u16 inw(unsigned long port)
 238 {
 239         return readw(_IO_BASE + (port & IO_SPACE_LIMIT));
 240 }
 241
 242 static inline u32 inl(unsigned long port)
 243 {
 244         return readl(_IO_BASE + (port & IO_SPACE_LIMIT));
 245 }
 246
 247 /*
 248  * outb - write a byte to a memory location
 249  * @data: data to write to
 250  * @addr:  address in I/O space
 251  */
 252 static inline void outb(u8 data, unsigned long port)
 253 {
 254         writeb(data, _IO_BASE + (port & IO_SPACE_LIMIT));
 255 }
 256
 257 static inline void outw(u16 data, unsigned long port)
 258 {
 259         writew(data, _IO_BASE + (port & IO_SPACE_LIMIT));
 260 }
 261
 262 static inline void outl(u32 data, unsigned long port)
 263 {
 264         writel(data, _IO_BASE + (port & IO_SPACE_LIMIT));
 265 }
 266
 267 #define outb_p outb
 268 #define outw_p outw
 269 #define outl_p outl
 270
 271 #define inb_p inb
 272 #define inw_p inw
 273 #define inl_p inl
 274
 275 static inline void insb(unsigned long port, void *buffer, int count)
 276 {
 277         if (count) {
 278                 u8 *buf = buffer;
 279                 do {
 280                         u8 x = inb(port);
 281                         *buf++ = x;
 282                 } while (--count);
 283         }
 284 }
 285
 286 static inline void insw(unsigned long port, void *buffer, int count)
 287 {
 288         if (count) {
 289                 u16 *buf = buffer;
 290                 do {
 291                         u16 x = inw(port);
 292                         *buf++ = x;
 293                 } while (--count);
 294         }
 295 }
 296
 297 static inline void insl(unsigned long port, void *buffer, int count)
 298 {
 299         if (count) {
 300                 u32 *buf = buffer;
 301                 do {
 302                         u32 x = inw(port);
 303                         *buf++ = x;
 304                 } while (--count);
 305         }
 306 }
 307
 308 static inline void outsb(unsigned long port, const void *buffer, int count)
 309 {
 310         if (count) {
 311                 const u8 *buf = buffer;
 312                 do {
 313                         outb(*buf++, port);
 314                 } while (--count);
 315         }
 316 }
 317
 318 static inline void outsw(unsigned long port, const void *buffer, int count)
 319 {
 320         if (count) {
 321                 const u16 *buf = buffer;
 322                 do {
 323                         outw(*buf++, port);
 324                 } while (--count);
 325         }
 326 }
 327
 328 static inline void outsl(unsigned long port, const void *buffer, int count)
 329 {
 330         if (count) {
 331                 const u32 *buf = buffer;
 332                 do {
 333                         outl(*buf++, port);
 334                 } while (--count);
 335         }
 336 }
 337
 338 #define flush_write_buffers() do { } while (0)
 339
 340 #endif /* __KERNEL__ */
 341
 342 #endif