2 * Device Tree Source for the MPC5121e based ac14xx board
4 * Copyright 2012 Anatolij Gustschin <agust@denx.de>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
13 #include <mpc5121.dtsi>
17 compatible = "ifm,ac14xx", "fsl,mpc5121";
30 timebase-frequency = <40000000>; /* 40 MHz (csb/4) */
31 bus-frequency = <160000000>; /* 160 MHz csb bus */
32 clock-frequency = <400000000>; /* 400 MHz ppc core */
37 reg = <0x00000000 0x10000000>; /* 256MB at 0 */
45 ranges = <0x0 0x0 0xfc000000 0x04000000 /* CS0: NOR flash */
46 0x1 0x0 0xe0000000 0x00010000 /* CS1: FRAM */
47 0x2 0x0 0xe0100000 0x00080000 /* CS2: asi1 */
48 0x3 0x0 0xe0300000 0x00020000 /* CS3: comm */
49 0x5 0x0 0xe0400000 0x00010000 /* CS5: safety */
50 0x6 0x0 0xe0200000 0x00080000>; /* CS6: asi2 */
53 compatible = "cfi-flash";
54 reg = <0 0x00000000 0x04000000>;
61 label = "dtb-kernel-production";
62 reg = <0x00000000 0x00400000>;
65 label = "filesystem-production";
66 reg = <0x00400000 0x03400000>;
71 reg = <0x03800000 0x00700000>;
76 reg = <0x03f00000 0x00040000>;
80 reg = <0x03f40000 0x00020000>;
84 reg = <0x03f60000 0x00020000>;
89 compatible = "ifm,ac14xx-fram", "linux,uio-pdrv-genirq";
90 reg = <1 0x00000000 0x00010000>;
94 /* masters mapping: CS, CS offset, size */
95 reg = <2 0x00000000 0x00080000
96 6 0x00000000 0x00080000>;
99 compatible = "ifm,ac14xx-asi-fpga";
101 &gpio_pic 26 0 /* prog */
102 &gpio_pic 27 0 /* done */
103 &gpio_pic 10 0 /* reset */
107 interrupts = <20 0x2>;
108 interrupt-parent = <&gpio_pic>;
109 chipselect = <2 0x00009000 0x00009100>;
110 label = "AS-i master 1";
114 interrupts = <21 0x2>;
115 interrupt-parent = <&gpio_pic>;
116 chipselect = <6 0x00009000 0x00009100>;
117 label = "AS-i master 2";
122 compatible = "ifm,netx";
123 reg = <0x3 0x00000000 0x00020000>;
124 chipselect = <3 0x00101140 0x00203100>;
125 interrupts = <17 0x8>;
126 gpios = <&gpio_pic 15 0>;
130 compatible = "ifm,safety";
131 reg = <0x5 0x00000000 0x00010000>;
132 chipselect = <5 0x00009000 0x00009100>;
133 interrupts = <22 0x2>;
134 interrupt-parent = <&gpio_pic>;
136 &gpio_pic 12 0 /* prog */
137 &gpio_pic 11 0 /* done */
144 clock-frequency = <25000000>;
149 bus-frequency = <80000000>; /* 80 MHz ips bus */
152 compatible = "fsl,mpc5121rev2-clock", "fsl,mpc5121-clock";
157 * interrupts cell = <pin nr, sense>
158 * sense == 8: Level, low assertion
159 * sense == 2: Edge, high-to-low change
161 gpio_pic: gpio@1100 {
164 interrupt-controller;
165 #interrupt-cells = <2>;
169 cd-gpios = <&gpio_pic 23 0>; /* card detect */
170 wp-gpios = <&gpio_pic 24 0>; /* write protect */
171 wp-inverted; /* WP active high */
176 clock-frequency = <400000>;
179 compatible = "at24,24c01";
184 compatible = "at24,24c01";
189 compatible = "ad,ad7414";
194 compatible = "at24,24c01";
199 compatible = "at24,24c01";
204 compatible = "at24,24c01";
209 compatible = "at24,24c01";
214 compatible = "at24,24c01";
219 compatible = "at24,24c01";
224 compatible = "at24,24c01";
229 compatible = "at24,24c01";
234 compatible = "stm,m41t00";
239 axe_pic: axe-base@2000 {
240 compatible = "fsl,mpc5121-axe-base";
241 reg = <0x2000 0x100>;
242 interrupts = <42 0x8>;
243 interrupt-controller;
244 #interrupt-cells = <2>;
248 compatible = "fsl,mpc5121-axe-app";
249 interrupt-parent = <&axe_pic>;
251 /* soft interrupts */
252 0 0x0 1 0x0 2 0x0 3 0x0
253 4 0x0 5 0x0 6 0x0 7 0x0
254 /* fifo interrupts */
255 8 0x0 9 0x0 10 0x0 11 0x0
260 edid = [00 FF FF FF FF FF FF 00 14 94 00 00 00 00 00 00
261 0A 12 01 03 80 1C 23 78 CA 88 FF 94 52 54 8E 27
262 1E 4C 50 00 00 00 01 01 01 01 01 01 01 01 01 01
263 01 01 01 01 01 01 FB 00 B0 14 00 DC 05 00 08 04
264 21 00 1C 23 00 00 00 18 00 00 00 FD 00 38 3C 1F
265 3C 01 0A 20 20 20 20 20 20 20 00 00 00 FC 00 45
266 54 30 31 38 30 30 33 44 4D 55 0A 0A 00 00 00 10
267 00 41 30 30 30 30 30 30 30 30 30 30 30 31 00 D5];
283 phy0: ethernet-phy@1f {
284 compatible = "smsc,lan8700";
289 enet: ethernet@2800 {
290 phy-handle = <&phy0>;
301 /* PSC3 serial port A, aka ttyPSC0 */
303 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
304 fsl,rx-fifo-size = <512>;
305 fsl,tx-fifo-size = <512>;
308 /* PSC4 in SPI mode */
310 compatible = "fsl,mpc5121-psc-spi", "fsl,mpc5121-psc";
311 fsl,rx-fifo-size = <768>;
312 fsl,tx-fifo-size = <768>;
313 #address-cells = <1>;
316 cs-gpios = <&gpio_pic 25 0>;
319 compatible = "st,m25p128";
320 spi-max-frequency = <20000000>;
322 #address-cells = <1>;
326 label = "spi-flash0";
327 reg = <0x00000000 0x01000000>;
332 /* PSC5 in SPI mode */
334 compatible = "fsl,mpc5121-psc-spi", "fsl,mpc5121-psc";
335 fsl,mode = "spi-master";
336 fsl,rx-fifo-size = <128>;
337 fsl,tx-fifo-size = <128>;
338 #address-cells = <1>;
342 compatible = "ilitek,ili922x";
344 spi-max-frequency = <100000>;
350 /* PSC7 serial port C, aka ttyPSC2 */
352 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
353 fsl,rx-fifo-size = <512>;
354 fsl,tx-fifo-size = <512>;
358 compatible = "gpio-matrix-keypad";
359 debounce-delay-ms = <5>;
360 col-scan-delay-us = <1>;
363 col-switch-delay-ms = <200>;
365 col-gpios = <&gpio_pic 1 0>; /* pin1 */
367 row-gpios = <&gpio_pic 2 0 /* pin2 */
368 &gpio_pic 3 0 /* pin3 */
369 &gpio_pic 4 0>; /* pin4 */
371 linux,keymap = <0x0000006e /* FN LEFT */
373 0x02000066 /* FN RIGHT */
374 0x00010069 /* LEFT */
375 0x0101006a /* DOWN */
376 0x0201006c>; /* RIGHT */
381 compatible = "gpio-leds";
385 gpios = <&gpio_pic 0 0>;
386 default-state = "keep";
390 gpios = <&gpio_pic 18 0>;
391 default-state = "keep";
395 gpios = <&gpio_pic 19 0>;
396 default-state = "keep";