arch/powerpc/boot/dts/p2020ds.dtsi

   1 /*
   2  * P2020DS Device Tree Source stub (no addresses or top-level ranges)
   3  *
   4  * Copyright 2011-2012 Freescale Semiconductor Inc.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are met:
   8  *     * Redistributions of source code must retain the above copyright
   9  *       notice, this list of conditions and the following disclaimer.
  10  *     * Redistributions in binary form must reproduce the above copyright
  11  *       notice, this list of conditions and the following disclaimer in the
  12  *       documentation and/or other materials provided with the distribution.
  13  *     * Neither the name of Freescale Semiconductor nor the
  14  *       names of its contributors may be used to endorse or promote products
  15  *       derived from this software without specific prior written permission.
  16  *
  17  *
  18  * ALTERNATIVELY, this software may be distributed under the terms of the
  19  * GNU General Public License ("GPL") as published by the Free Software
  20  * Foundation, either version 2 of that License or (at your option) any
  21  * later version.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  24  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26  * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 &board_lbc {
  36         nor@0,0 {
  37                 #address-cells = <1>;
  38                 #size-cells = <1>;
  39                 compatible = "cfi-flash";
  40                 reg = <0x0 0x0 0x8000000>;
  41                 bank-width = <2>;
  42                 device-width = <1>;
  43
  44                 ramdisk@0 {
  45                         reg = <0x0 0x03000000>;
  46                         read-only;
  47                 };
  48
  49                 diagnostic@3000000 {
  50                         reg = <0x03000000 0x00e00000>;
  51                         read-only;
  52                 };
  53
  54                 dink@3e00000 {
  55                         reg = <0x03e00000 0x00200000>;
  56                         read-only;
  57                 };
  58
  59                 kernel@4000000 {
  60                         reg = <0x04000000 0x00400000>;
  61                         read-only;
  62                 };
  63
  64                 jffs2@4400000 {
  65                         reg = <0x04400000 0x03b00000>;
  66                 };
  67
  68                 dtb@7f00000 {
  69                         reg = <0x07f00000 0x00080000>;
  70                         read-only;
  71                 };
  72
  73                 u-boot@7f80000 {
  74                         reg = <0x07f80000 0x00080000>;
  75                         read-only;
  76                 };
  77         };
  78
  79         nand@2,0 {
  80                 #address-cells = <1>;
  81                 #size-cells = <1>;
  82                 compatible = "fsl,elbc-fcm-nand";
  83                 reg = <0x2 0x0 0x40000>;
  84
  85                 u-boot@0 {
  86                         reg = <0x0 0x02000000>;
  87                         read-only;
  88                 };
  89
  90                 jffs2@2000000 {
  91                         reg = <0x02000000 0x10000000>;
  92                 };
  93
  94                 ramdisk@12000000 {
  95                         reg = <0x12000000 0x08000000>;
  96                         read-only;
  97                 };
  98
  99                 kernel@1a000000 {
 100                         reg = <0x1a000000 0x04000000>;
 101                 };
 102
 103                 dtb@1e000000 {
 104                         reg = <0x1e000000 0x01000000>;
 105                         read-only;
 106                 };
 107
 108                 empty@1f000000 {
 109                         reg = <0x1f000000 0x21000000>;
 110                 };
 111         };
 112
 113         board-control@3,0 {
 114                 compatible = "fsl,p2020ds-fpga", "fsl,fpga-ngpixis";
 115                 reg = <0x3 0x0 0x30>;
 116         };
 117
 118         nand@4,0 {
 119                 compatible = "fsl,elbc-fcm-nand";
 120                 reg = <0x4 0x0 0x40000>;
 121         };
 122
 123         nand@5,0 {
 124                 compatible = "fsl,elbc-fcm-nand";
 125                 reg = <0x5 0x0 0x40000>;
 126         };
 127
 128         nand@6,0 {
 129                 compatible = "fsl,elbc-fcm-nand";
 130                 reg = <0x6 0x0 0x40000>;
 131         };
 132 };
 133
 134 &board_soc {
 135         usb@22000 {
 136                 phy_type = "ulpi";
 137                 dr_mode = "host";
 138         };
 139
 140         mdio@24520 {
 141                 phy0: ethernet-phy@0 {
 142                         interrupts = <3 1 0 0>;
 143                         reg = <0x0>;
 144                 };
 145                 phy1: ethernet-phy@1 {
 146                         interrupts = <3 1 0 0>;
 147                         reg = <0x1>;
 148                 };
 149                 phy2: ethernet-phy@2 {
 150                         interrupts = <3 1 0 0>;
 151                         reg = <0x2>;
 152                 };
 153
 154                 sgmii_phy1: sgmii-phy@1 {
 155                         interrupts = <5 1 0 0>;
 156                         reg = <0x1c>;
 157                 };
 158                 sgmii_phy2: sgmii-phy@2 {
 159                         interrupts = <5 1 0 0>;
 160                         reg = <0x1d>;
 161                 };
 162
 163                 tbi0: tbi-phy@11 {
 164                         reg = <0x11>;
 165                         device_type = "tbi-phy";
 166                 };
 167
 168         };
 169
 170         mdio@25520 {
 171                 tbi1: tbi-phy@11 {
 172                         reg = <0x11>;
 173                         device_type = "tbi-phy";
 174                 };
 175         };
 176
 177         mdio@26520 {
 178                 tbi2: tbi-phy@11 {
 179                         reg = <0x11>;
 180                         device_type = "tbi-phy";
 181                 };
 182
 183         };
 184
 185         ptp_clock@24e00 {
 186                 fsl,tclk-period = <5>;
 187                 fsl,tmr-prsc = <200>;
 188                 fsl,tmr-add = <0xCCCCCCCD>;
 189                 fsl,tmr-fiper1 = <0x3B9AC9FB>;
 190                 fsl,tmr-fiper2 = <0x0001869B>;
 191                 fsl,max-adj = <249999999>;
 192         };
 193
 194         enet0: ethernet@24000 {
 195                 tbi-handle = <&tbi0>;
 196                 phy-handle = <&phy0>;
 197                 phy-connection-type = "rgmii-id";
 198         };
 199
 200         enet1: ethernet@25000 {
 201                 tbi-handle = <&tbi1>;
 202                 phy-handle = <&phy1>;
 203                 phy-connection-type = "rgmii-id";
 204
 205         };
 206
 207         enet2: ethernet@26000 {
 208                 tbi-handle = <&tbi2>;
 209                 phy-handle = <&phy2>;
 210                 phy-connection-type = "rgmii-id";
 211         };
 212 };
 213
 214 &board_pci1 {
 215         pcie@0 {
 216                 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
 217                 interrupt-map = <
 218
 219                         // IDSEL 0x11 func 0 - PCI slot 1
 220                         0x8800 0x0 0x0 0x1 &i8259 0x9 0x2
 221                         0x8800 0x0 0x0 0x2 &i8259 0xa 0x2
 222
 223                         // IDSEL 0x11 func 1 - PCI slot 1
 224                         0x8900 0x0 0x0 0x1 &i8259 0x9 0x2
 225                         0x8900 0x0 0x0 0x2 &i8259 0xa 0x2
 226
 227                         // IDSEL 0x11 func 2 - PCI slot 1
 228                         0x8a00 0x0 0x0 0x1 &i8259 0x9 0x2
 229                         0x8a00 0x0 0x0 0x2 &i8259 0xa 0x2
 230
 231                         // IDSEL 0x11 func 3 - PCI slot 1
 232                         0x8b00 0x0 0x0 0x1 &i8259 0x9 0x2
 233                         0x8b00 0x0 0x0 0x2 &i8259 0xa 0x2
 234
 235                         // IDSEL 0x11 func 4 - PCI slot 1
 236                         0x8c00 0x0 0x0 0x1 &i8259 0x9 0x2
 237                         0x8c00 0x0 0x0 0x2 &i8259 0xa 0x2
 238
 239                         // IDSEL 0x11 func 5 - PCI slot 1
 240                         0x8d00 0x0 0x0 0x1 &i8259 0x9 0x2
 241                         0x8d00 0x0 0x0 0x2 &i8259 0xa 0x2
 242
 243                         // IDSEL 0x11 func 6 - PCI slot 1
 244                         0x8e00 0x0 0x0 0x1 &i8259 0x9 0x2
 245                         0x8e00 0x0 0x0 0x2 &i8259 0xa 0x2
 246
 247                         // IDSEL 0x11 func 7 - PCI slot 1
 248                         0x8f00 0x0 0x0 0x1 &i8259 0x9 0x2
 249                         0x8f00 0x0 0x0 0x2 &i8259 0xa 0x2
 250
 251                         // IDSEL 0x1d  Audio
 252                         0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
 253
 254                         // IDSEL 0x1e Legacy
 255                         0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
 256                         0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
 257
 258                         // IDSEL 0x1f IDE/SATA
 259                         0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
 260                         0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
 261                         >;
 262
 263                 uli1575@0 {
 264                         reg = <0x0 0x0 0x0 0x0 0x0>;
 265                         #size-cells = <2>;
 266                         #address-cells = <3>;
 267                         ranges = <0x2000000 0x0 0xa0000000
 268                                   0x2000000 0x0 0xa0000000
 269                                   0x0 0x20000000
 270
 271                                   0x1000000 0x0 0x0
 272                                   0x1000000 0x0 0x0
 273                                   0x0 0x10000>;
 274                         isa@1e {
 275                                 device_type = "isa";
 276                                 #interrupt-cells = <2>;
 277                                 #size-cells = <1>;
 278                                 #address-cells = <2>;
 279                                 reg = <0xf000 0x0 0x0 0x0 0x0>;
 280                                 ranges = <0x1 0x0 0x1000000 0x0 0x0
 281                                           0x1000>;
 282                                 interrupt-parent = <&i8259>;
 283
 284                                 i8259: interrupt-controller@20 {
 285                                         reg = <0x1 0x20 0x2
 286                                                0x1 0xa0 0x2
 287                                                0x1 0x4d0 0x2>;
 288                                         interrupt-controller;
 289                                         device_type = "interrupt-controller";
 290                                         #address-cells = <0>;
 291                                         #interrupt-cells = <2>;
 292                                         compatible = "chrp,iic";
 293                                         interrupts = <4 1 0 0>;
 294                                         interrupt-parent = <&mpic>;
 295                                 };
 296
 297                                 i8042@60 {
 298                                         #size-cells = <0>;
 299                                         #address-cells = <1>;
 300                                         reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
 301                                         interrupts = <1 3 12 3>;
 302                                         interrupt-parent =
 303                                                 <&i8259>;
 304
 305                                         keyboard@0 {
 306                                                 reg = <0x0>;
 307                                                 compatible = "pnpPNP,303";
 308                                         };
 309
 310                                         mouse@1 {
 311                                                 reg = <0x1>;
 312                                                 compatible = "pnpPNP,f03";
 313                                         };
 314                                 };
 315
 316                                 rtc@70 {
 317                                         compatible = "pnpPNP,b00";
 318                                         reg = <0x1 0x70 0x2>;
 319                                 };
 320
 321                                 gpio@400 {
 322                                         reg = <0x1 0x400 0x80>;
 323                                 };
 324                         };
 325                 };
 326         };
 327 };