arch/powerpc/boot/dts/t208xrdb.dtsi

   1 /*
   2  * T2080PCIe-RDB Board Device Tree Source
   3  *
   4  * Copyright 2014 Freescale Semiconductor Inc.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are met:
   8  *     * Redistributions of source code must retain the above copyright
   9  *       notice, this list of conditions and the following disclaimer.
  10  *     * Redistributions in binary form must reproduce the above copyright
  11  *       notice, this list of conditions and the following disclaimer in the
  12  *       documentation and/or other materials provided with the distribution.
  13  *     * Neither the name of Freescale Semiconductor nor the
  14  *       names of its contributors may be used to endorse or promote products
  15  *       derived from this software without specific prior written permission.
  16  *
  17  *
  18  * ALTERNATIVELY, this software may be distributed under the terms of the
  19  * GNU General Public License ("GPL") as published by the Free Software
  20  * Foundation, either version 2 of that License or (at your option) any
  21  * later version.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
  24  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26  * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 / {
  36         model = "fsl,T2080RDB";
  37         compatible = "fsl,T2080RDB";
  38         #address-cells = <2>;
  39         #size-cells = <2>;
  40         interrupt-parent = <&mpic>;
  41
  42         ifc: localbus@ffe124000 {
  43                 reg = <0xf 0xfe124000 0 0x2000>;
  44                 ranges = <0 0 0xf 0xe8000000 0x08000000
  45                           2 0 0xf 0xff800000 0x00010000
  46                           3 0 0xf 0xffdf0000 0x00008000>;
  47
  48                 nor@0,0 {
  49                         #address-cells = <1>;
  50                         #size-cells = <1>;
  51                         compatible = "cfi-flash";
  52                         reg = <0x0 0x0 0x8000000>;
  53
  54                         bank-width = <2>;
  55                         device-width = <1>;
  56                 };
  57
  58                 nand@1,0 {
  59                         #address-cells = <1>;
  60                         #size-cells = <1>;
  61                         compatible = "fsl,ifc-nand";
  62                         reg = <0x2 0x0 0x10000>;
  63                 };
  64
  65                 boardctrl: board-control@2,0 {
  66                         #address-cells = <1>;
  67                         #size-cells = <1>;
  68                         compatible = "fsl,t2080-cpld";
  69                         reg = <3 0 0x300>;
  70                         ranges = <0 3 0 0x300>;
  71                 };
  72         };
  73
  74         memory {
  75                 device_type = "memory";
  76         };
  77
  78         dcsr: dcsr@f00000000 {
  79                 ranges = <0x00000000 0xf 0x00000000 0x01072000>;
  80         };
  81
  82         soc: soc@ffe000000 {
  83                 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
  84                 reg = <0xf 0xfe000000 0 0x00001000>;
  85                 spi@110000 {
  86                         flash@0 {
  87                                 #address-cells = <1>;
  88                                 #size-cells = <1>;
  89                                 compatible = "micron,n25q512a";
  90                                 reg = <0>;
  91                                 spi-max-frequency = <10000000>; /* input clock */
  92                         };
  93                 };
  94
  95                 i2c@118000 {
  96                         adt7481@4c {
  97                                 compatible = "adi,adt7481";
  98                                 reg = <0x4c>;
  99                         };
 100
 101                         rtc@68 {
 102                                 compatible = "dallas,ds1339";
 103                                 reg = <0x68>;
 104                                 interrupts = <0x1 0x1 0 0>;
 105                         };
 106
 107                         eeprom@50 {
 108                                 compatible = "atmel,24c256";
 109                                 reg = <0x50>;
 110                         };
 111                 };
 112
 113                 i2c@118100 {
 114                         pca9546@77 {
 115                                 compatible = "nxp,pca9546";
 116                                 reg = <0x77>;
 117                         };
 118                 };
 119
 120                 sdhc@114000 {
 121                         voltage-ranges = <1800 1800 3300 3300>;
 122                 };
 123         };
 124
 125         pci0: pcie@ffe240000 {
 126                 reg = <0xf 0xfe240000 0 0x10000>;
 127                 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
 128                           0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
 129                 pcie@0 {
 130                         ranges = <0x02000000 0 0xe0000000
 131                                   0x02000000 0 0xe0000000
 132                                   0 0x20000000
 133
 134                                   0x01000000 0 0x00000000
 135                                   0x01000000 0 0x00000000
 136                                   0 0x00010000>;
 137                 };
 138         };
 139
 140         pci1: pcie@ffe250000 {
 141                 reg = <0xf 0xfe250000 0 0x10000>;
 142                 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x10000000
 143                           0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
 144                 pcie@0 {
 145                         ranges = <0x02000000 0 0xe0000000
 146                                   0x02000000 0 0xe0000000
 147                                   0 0x20000000
 148
 149                                   0x01000000 0 0x00000000
 150                                   0x01000000 0 0x00000000
 151                                   0 0x00010000>;
 152                 };
 153         };
 154
 155         pci2: pcie@ffe260000 {
 156                 reg = <0xf 0xfe260000 0 0x1000>;
 157                 ranges = <0x02000000 0 0xe0000000 0xc 0x30000000 0 0x10000000
 158                           0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
 159                 pcie@0 {
 160                         ranges = <0x02000000 0 0xe0000000
 161                                   0x02000000 0 0xe0000000
 162                                   0 0x20000000
 163
 164                                   0x01000000 0 0x00000000
 165                                   0x01000000 0 0x00000000
 166                                   0 0x00010000>;
 167                 };
 168         };
 169
 170         pci3: pcie@ffe270000 {
 171                 reg = <0xf 0xfe270000 0 0x10000>;
 172                 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x10000000
 173                           0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
 174                 pcie@0 {
 175                         ranges = <0x02000000 0 0xe0000000
 176                                   0x02000000 0 0xe0000000
 177                                   0 0x20000000
 178
 179                                   0x01000000 0 0x00000000
 180                                   0x01000000 0 0x00000000
 181                                   0 0x00010000>;
 182                 };
 183         };
 184 };