2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
11 * Common pmac/prep/chrp pci routines. -- Cort
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/string.h>
22 #include <linux/init.h>
23 #include <linux/bootmem.h>
24 #include <linux/delay.h>
25 #include <linux/export.h>
26 #include <linux/of_address.h>
27 #include <linux/of_pci.h>
29 #include <linux/list.h>
30 #include <linux/syscalls.h>
31 #include <linux/irq.h>
32 #include <linux/vmalloc.h>
33 #include <linux/slab.h>
34 #include <linux/vgaarb.h>
36 #include <asm/processor.h>
39 #include <asm/pci-bridge.h>
40 #include <asm/byteorder.h>
41 #include <asm/machdep.h>
42 #include <asm/ppc-pci.h>
45 static DEFINE_SPINLOCK(hose_spinlock
);
48 /* XXX kill that some day ... */
49 static int global_phb_number
; /* Global phb counter */
51 /* ISA Memory physical address */
52 resource_size_t isa_mem_base
;
55 static struct dma_map_ops
*pci_dma_ops
= &dma_direct_ops
;
57 void set_pci_dma_ops(struct dma_map_ops
*dma_ops
)
59 pci_dma_ops
= dma_ops
;
62 struct dma_map_ops
*get_pci_dma_ops(void)
66 EXPORT_SYMBOL(get_pci_dma_ops
);
68 struct pci_controller
*pcibios_alloc_controller(struct device_node
*dev
)
70 struct pci_controller
*phb
;
72 phb
= zalloc_maybe_bootmem(sizeof(struct pci_controller
), GFP_KERNEL
);
75 spin_lock(&hose_spinlock
);
76 phb
->global_number
= global_phb_number
++;
77 list_add_tail(&phb
->list_node
, &hose_list
);
78 spin_unlock(&hose_spinlock
);
80 phb
->is_dynamic
= mem_init_done
;
83 int nid
= of_node_to_nid(dev
);
85 if (nid
< 0 || !node_online(nid
))
88 PHB_SET_NODE(phb
, nid
);
94 void pcibios_free_controller(struct pci_controller
*phb
)
96 spin_lock(&hose_spinlock
);
97 list_del(&phb
->list_node
);
98 spin_unlock(&hose_spinlock
);
105 * The function is used to return the minimal alignment
106 * for memory or I/O windows of the associated P2P bridge.
107 * By default, 4KiB alignment for I/O windows and 1MiB for
110 resource_size_t
pcibios_window_alignment(struct pci_bus
*bus
,
113 if (ppc_md
.pcibios_window_alignment
)
114 return ppc_md
.pcibios_window_alignment(bus
, type
);
117 * PCI core will figure out the default
118 * alignment: 4KiB for I/O and 1MiB for
124 void pcibios_reset_secondary_bus(struct pci_dev
*dev
)
126 if (ppc_md
.pcibios_reset_secondary_bus
) {
127 ppc_md
.pcibios_reset_secondary_bus(dev
);
131 pci_reset_secondary_bus(dev
);
134 static resource_size_t
pcibios_io_size(const struct pci_controller
*hose
)
137 return hose
->pci_io_size
;
139 return resource_size(&hose
->io_resource
);
143 int pcibios_vaddr_is_ioport(void __iomem
*address
)
146 struct pci_controller
*hose
;
147 resource_size_t size
;
149 spin_lock(&hose_spinlock
);
150 list_for_each_entry(hose
, &hose_list
, list_node
) {
151 size
= pcibios_io_size(hose
);
152 if (address
>= hose
->io_base_virt
&&
153 address
< (hose
->io_base_virt
+ size
)) {
158 spin_unlock(&hose_spinlock
);
162 unsigned long pci_address_to_pio(phys_addr_t address
)
164 struct pci_controller
*hose
;
165 resource_size_t size
;
166 unsigned long ret
= ~0;
168 spin_lock(&hose_spinlock
);
169 list_for_each_entry(hose
, &hose_list
, list_node
) {
170 size
= pcibios_io_size(hose
);
171 if (address
>= hose
->io_base_phys
&&
172 address
< (hose
->io_base_phys
+ size
)) {
174 (unsigned long)hose
->io_base_virt
- _IO_BASE
;
175 ret
= base
+ (address
- hose
->io_base_phys
);
179 spin_unlock(&hose_spinlock
);
183 EXPORT_SYMBOL_GPL(pci_address_to_pio
);
186 * Return the domain number for this bus.
188 int pci_domain_nr(struct pci_bus
*bus
)
190 struct pci_controller
*hose
= pci_bus_to_host(bus
);
192 return hose
->global_number
;
194 EXPORT_SYMBOL(pci_domain_nr
);
196 /* This routine is meant to be used early during boot, when the
197 * PCI bus numbers have not yet been assigned, and you need to
198 * issue PCI config cycles to an OF device.
199 * It could also be used to "fix" RTAS config cycles if you want
200 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
203 struct pci_controller
* pci_find_hose_for_OF_device(struct device_node
* node
)
206 struct pci_controller
*hose
, *tmp
;
207 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
)
208 if (hose
->dn
== node
)
216 * Reads the interrupt pin to determine if interrupt is use by card.
217 * If the interrupt is used, then gets the interrupt line from the
218 * openfirmware and sets it in the pci_dev and pci_config line.
220 static int pci_read_irq_line(struct pci_dev
*pci_dev
)
222 struct of_phandle_args oirq
;
225 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev
));
228 memset(&oirq
, 0xff, sizeof(oirq
));
230 /* Try to get a mapping from the device-tree */
231 if (of_irq_parse_pci(pci_dev
, &oirq
)) {
234 /* If that fails, lets fallback to what is in the config
235 * space and map that through the default controller. We
236 * also set the type to level low since that's what PCI
237 * interrupts are. If your platform does differently, then
238 * either provide a proper interrupt tree or don't use this
241 if (pci_read_config_byte(pci_dev
, PCI_INTERRUPT_PIN
, &pin
))
245 if (pci_read_config_byte(pci_dev
, PCI_INTERRUPT_LINE
, &line
) ||
246 line
== 0xff || line
== 0) {
249 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
252 virq
= irq_create_mapping(NULL
, line
);
254 irq_set_irq_type(virq
, IRQ_TYPE_LEVEL_LOW
);
256 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
257 oirq
.args_count
, oirq
.args
[0], oirq
.args
[1],
258 of_node_full_name(oirq
.np
));
260 virq
= irq_create_of_mapping(&oirq
);
263 pr_debug(" Failed to map !\n");
267 pr_debug(" Mapped to linux irq %d\n", virq
);
275 * Platform support for /proc/bus/pci/X/Y mmap()s,
276 * modelled on the sparc64 implementation by Dave Miller.
281 * Adjust vm_pgoff of VMA such that it is the physical page offset
282 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
284 * Basically, the user finds the base address for his device which he wishes
285 * to mmap. They read the 32-bit value from the config space base register,
286 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
287 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
289 * Returns negative error code on failure, zero on success.
291 static struct resource
*__pci_mmap_make_offset(struct pci_dev
*dev
,
292 resource_size_t
*offset
,
293 enum pci_mmap_state mmap_state
)
295 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
296 unsigned long io_offset
= 0;
300 return NULL
; /* should never happen */
302 /* If memory, add on the PCI bridge address offset */
303 if (mmap_state
== pci_mmap_mem
) {
304 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */
305 *offset
+= hose
->pci_mem_offset
;
307 res_bit
= IORESOURCE_MEM
;
309 io_offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
310 *offset
+= io_offset
;
311 res_bit
= IORESOURCE_IO
;
315 * Check that the offset requested corresponds to one of the
316 * resources of the device.
318 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
319 struct resource
*rp
= &dev
->resource
[i
];
320 int flags
= rp
->flags
;
322 /* treat ROM as memory (should be already) */
323 if (i
== PCI_ROM_RESOURCE
)
324 flags
|= IORESOURCE_MEM
;
326 /* Active and same type? */
327 if ((flags
& res_bit
) == 0)
330 /* In the range of this resource? */
331 if (*offset
< (rp
->start
& PAGE_MASK
) || *offset
> rp
->end
)
334 /* found it! construct the final physical address */
335 if (mmap_state
== pci_mmap_io
)
336 *offset
+= hose
->io_base_phys
- io_offset
;
344 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
347 static pgprot_t
__pci_mmap_set_pgprot(struct pci_dev
*dev
, struct resource
*rp
,
349 enum pci_mmap_state mmap_state
,
353 /* Write combine is always 0 on non-memory space mappings. On
354 * memory space, if the user didn't pass 1, we check for a
355 * "prefetchable" resource. This is a bit hackish, but we use
356 * this to workaround the inability of /sysfs to provide a write
359 if (mmap_state
!= pci_mmap_mem
)
361 else if (write_combine
== 0) {
362 if (rp
->flags
& IORESOURCE_PREFETCH
)
366 /* XXX would be nice to have a way to ask for write-through */
368 return pgprot_noncached_wc(protection
);
370 return pgprot_noncached(protection
);
374 * This one is used by /dev/mem and fbdev who have no clue about the
375 * PCI device, it tries to find the PCI device first and calls the
378 pgprot_t
pci_phys_mem_access_prot(struct file
*file
,
383 struct pci_dev
*pdev
= NULL
;
384 struct resource
*found
= NULL
;
385 resource_size_t offset
= ((resource_size_t
)pfn
) << PAGE_SHIFT
;
388 if (page_is_ram(pfn
))
391 prot
= pgprot_noncached(prot
);
392 for_each_pci_dev(pdev
) {
393 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
394 struct resource
*rp
= &pdev
->resource
[i
];
395 int flags
= rp
->flags
;
397 /* Active and same type? */
398 if ((flags
& IORESOURCE_MEM
) == 0)
400 /* In the range of this resource? */
401 if (offset
< (rp
->start
& PAGE_MASK
) ||
411 if (found
->flags
& IORESOURCE_PREFETCH
)
412 prot
= pgprot_noncached_wc(prot
);
416 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
417 (unsigned long long)offset
, pgprot_val(prot
));
424 * Perform the actual remap of the pages for a PCI device mapping, as
425 * appropriate for this architecture. The region in the process to map
426 * is described by vm_start and vm_end members of VMA, the base physical
427 * address is found in vm_pgoff.
428 * The pci device structure is provided so that architectures may make mapping
429 * decisions on a per-device or per-bus basis.
431 * Returns a negative error code on failure, zero on success.
433 int pci_mmap_page_range(struct pci_dev
*dev
, struct vm_area_struct
*vma
,
434 enum pci_mmap_state mmap_state
, int write_combine
)
436 resource_size_t offset
=
437 ((resource_size_t
)vma
->vm_pgoff
) << PAGE_SHIFT
;
441 rp
= __pci_mmap_make_offset(dev
, &offset
, mmap_state
);
445 vma
->vm_pgoff
= offset
>> PAGE_SHIFT
;
446 vma
->vm_page_prot
= __pci_mmap_set_pgprot(dev
, rp
,
448 mmap_state
, write_combine
);
450 ret
= remap_pfn_range(vma
, vma
->vm_start
, vma
->vm_pgoff
,
451 vma
->vm_end
- vma
->vm_start
, vma
->vm_page_prot
);
456 /* This provides legacy IO read access on a bus */
457 int pci_legacy_read(struct pci_bus
*bus
, loff_t port
, u32
*val
, size_t size
)
459 unsigned long offset
;
460 struct pci_controller
*hose
= pci_bus_to_host(bus
);
461 struct resource
*rp
= &hose
->io_resource
;
464 /* Check if port can be supported by that bus. We only check
465 * the ranges of the PHB though, not the bus itself as the rules
466 * for forwarding legacy cycles down bridges are not our problem
467 * here. So if the host bridge supports it, we do it.
469 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
472 if (!(rp
->flags
& IORESOURCE_IO
))
474 if (offset
< rp
->start
|| (offset
+ size
) > rp
->end
)
476 addr
= hose
->io_base_virt
+ port
;
480 *((u8
*)val
) = in_8(addr
);
485 *((u16
*)val
) = in_le16(addr
);
490 *((u32
*)val
) = in_le32(addr
);
496 /* This provides legacy IO write access on a bus */
497 int pci_legacy_write(struct pci_bus
*bus
, loff_t port
, u32 val
, size_t size
)
499 unsigned long offset
;
500 struct pci_controller
*hose
= pci_bus_to_host(bus
);
501 struct resource
*rp
= &hose
->io_resource
;
504 /* Check if port can be supported by that bus. We only check
505 * the ranges of the PHB though, not the bus itself as the rules
506 * for forwarding legacy cycles down bridges are not our problem
507 * here. So if the host bridge supports it, we do it.
509 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
512 if (!(rp
->flags
& IORESOURCE_IO
))
514 if (offset
< rp
->start
|| (offset
+ size
) > rp
->end
)
516 addr
= hose
->io_base_virt
+ port
;
518 /* WARNING: The generic code is idiotic. It gets passed a pointer
519 * to what can be a 1, 2 or 4 byte quantity and always reads that
520 * as a u32, which means that we have to correct the location of
521 * the data read within those 32 bits for size 1 and 2
525 out_8(addr
, val
>> 24);
530 out_le16(addr
, val
>> 16);
541 /* This provides legacy IO or memory mmap access on a bus */
542 int pci_mmap_legacy_page_range(struct pci_bus
*bus
,
543 struct vm_area_struct
*vma
,
544 enum pci_mmap_state mmap_state
)
546 struct pci_controller
*hose
= pci_bus_to_host(bus
);
547 resource_size_t offset
=
548 ((resource_size_t
)vma
->vm_pgoff
) << PAGE_SHIFT
;
549 resource_size_t size
= vma
->vm_end
- vma
->vm_start
;
552 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
553 pci_domain_nr(bus
), bus
->number
,
554 mmap_state
== pci_mmap_mem
? "MEM" : "IO",
555 (unsigned long long)offset
,
556 (unsigned long long)(offset
+ size
- 1));
558 if (mmap_state
== pci_mmap_mem
) {
561 * Because X is lame and can fail starting if it gets an error trying
562 * to mmap legacy_mem (instead of just moving on without legacy memory
563 * access) we fake it here by giving it anonymous memory, effectively
564 * behaving just like /dev/zero
566 if ((offset
+ size
) > hose
->isa_mem_size
) {
568 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n",
569 current
->comm
, current
->pid
, pci_domain_nr(bus
), bus
->number
);
570 if (vma
->vm_flags
& VM_SHARED
)
571 return shmem_zero_setup(vma
);
574 offset
+= hose
->isa_mem_phys
;
576 unsigned long io_offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
577 unsigned long roffset
= offset
+ io_offset
;
578 rp
= &hose
->io_resource
;
579 if (!(rp
->flags
& IORESOURCE_IO
))
581 if (roffset
< rp
->start
|| (roffset
+ size
) > rp
->end
)
583 offset
+= hose
->io_base_phys
;
585 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset
);
587 vma
->vm_pgoff
= offset
>> PAGE_SHIFT
;
588 vma
->vm_page_prot
= pgprot_noncached(vma
->vm_page_prot
);
589 return remap_pfn_range(vma
, vma
->vm_start
, vma
->vm_pgoff
,
590 vma
->vm_end
- vma
->vm_start
,
594 void pci_resource_to_user(const struct pci_dev
*dev
, int bar
,
595 const struct resource
*rsrc
,
596 resource_size_t
*start
, resource_size_t
*end
)
598 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
599 resource_size_t offset
= 0;
604 if (rsrc
->flags
& IORESOURCE_IO
)
605 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
607 /* We pass a fully fixed up address to userland for MMIO instead of
608 * a BAR value because X is lame and expects to be able to use that
609 * to pass to /dev/mem !
611 * That means that we'll have potentially 64 bits values where some
612 * userland apps only expect 32 (like X itself since it thinks only
613 * Sparc has 64 bits MMIO) but if we don't do that, we break it on
616 * Hopefully, the sysfs insterface is immune to that gunk. Once X
617 * has been fixed (and the fix spread enough), we can re-enable the
618 * 2 lines below and pass down a BAR value to userland. In that case
619 * we'll also have to re-enable the matching code in
620 * __pci_mmap_make_offset().
625 else if (rsrc
->flags
& IORESOURCE_MEM
)
626 offset
= hose
->pci_mem_offset
;
629 *start
= rsrc
->start
- offset
;
630 *end
= rsrc
->end
- offset
;
634 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
635 * @hose: newly allocated pci_controller to be setup
636 * @dev: device node of the host bridge
637 * @primary: set if primary bus (32 bits only, soon to be deprecated)
639 * This function will parse the "ranges" property of a PCI host bridge device
640 * node and setup the resource mapping of a pci controller based on its
643 * Life would be boring if it wasn't for a few issues that we have to deal
646 * - We can only cope with one IO space range and up to 3 Memory space
647 * ranges. However, some machines (thanks Apple !) tend to split their
648 * space into lots of small contiguous ranges. So we have to coalesce.
650 * - Some busses have IO space not starting at 0, which causes trouble with
651 * the way we do our IO resource renumbering. The code somewhat deals with
652 * it for 64 bits but I would expect problems on 32 bits.
654 * - Some 32 bits platforms such as 4xx can have physical space larger than
655 * 32 bits so we need to use 64 bits values for the parsing
657 void pci_process_bridge_OF_ranges(struct pci_controller
*hose
,
658 struct device_node
*dev
, int primary
)
661 struct resource
*res
;
662 struct of_pci_range range
;
663 struct of_pci_range_parser parser
;
665 printk(KERN_INFO
"PCI host bridge %s %s ranges:\n",
666 dev
->full_name
, primary
? "(primary)" : "");
668 /* Check for ranges property */
669 if (of_pci_range_parser_init(&parser
, dev
))
673 for_each_of_pci_range(&parser
, &range
) {
674 /* If we failed translation or got a zero-sized region
675 * (some FW try to feed us with non sensical zero sized regions
676 * such as power3 which look like some kind of attempt at exposing
677 * the VGA memory hole)
679 if (range
.cpu_addr
== OF_BAD_ADDR
|| range
.size
== 0)
682 /* Act based on address space type */
684 switch (range
.flags
& IORESOURCE_TYPE_BITS
) {
687 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
688 range
.cpu_addr
, range
.cpu_addr
+ range
.size
- 1,
691 /* We support only one IO range */
692 if (hose
->pci_io_size
) {
694 " \\--> Skipped (too many) !\n");
698 /* On 32 bits, limit I/O space to 16MB */
699 if (range
.size
> 0x01000000)
700 range
.size
= 0x01000000;
702 /* 32 bits needs to map IOs here */
703 hose
->io_base_virt
= ioremap(range
.cpu_addr
,
706 /* Expect trouble if pci_addr is not 0 */
709 (unsigned long)hose
->io_base_virt
;
710 #endif /* CONFIG_PPC32 */
711 /* pci_io_size and io_base_phys always represent IO
712 * space starting at 0 so we factor in pci_addr
714 hose
->pci_io_size
= range
.pci_addr
+ range
.size
;
715 hose
->io_base_phys
= range
.cpu_addr
- range
.pci_addr
;
718 res
= &hose
->io_resource
;
719 range
.cpu_addr
= range
.pci_addr
;
723 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
724 range
.cpu_addr
, range
.cpu_addr
+ range
.size
- 1,
726 (range
.pci_space
& 0x40000000) ?
729 /* We support only 3 memory ranges */
732 " \\--> Skipped (too many) !\n");
735 /* Handles ISA memory hole space here */
736 if (range
.pci_addr
== 0) {
737 if (primary
|| isa_mem_base
== 0)
738 isa_mem_base
= range
.cpu_addr
;
739 hose
->isa_mem_phys
= range
.cpu_addr
;
740 hose
->isa_mem_size
= range
.size
;
744 hose
->mem_offset
[memno
] = range
.cpu_addr
-
746 res
= &hose
->mem_resources
[memno
++];
750 of_pci_range_to_resource(&range
, dev
, res
);
755 /* Decide whether to display the domain number in /proc */
756 int pci_proc_domain(struct pci_bus
*bus
)
758 struct pci_controller
*hose
= pci_bus_to_host(bus
);
760 if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS
))
762 if (pci_has_flag(PCI_COMPAT_DOMAIN_0
))
763 return hose
->global_number
!= 0;
767 int pcibios_root_bridge_prepare(struct pci_host_bridge
*bridge
)
769 if (ppc_md
.pcibios_root_bridge_prepare
)
770 return ppc_md
.pcibios_root_bridge_prepare(bridge
);
775 /* This header fixup will do the resource fixup for all devices as they are
776 * probed, but not for bridge ranges
778 static void pcibios_fixup_resources(struct pci_dev
*dev
)
780 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
784 printk(KERN_ERR
"No host bridge for PCI dev %s !\n",
788 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
789 struct resource
*res
= dev
->resource
+ i
;
790 struct pci_bus_region reg
;
794 /* If we're going to re-assign everything, we mark all resources
795 * as unset (and 0-base them). In addition, we mark BARs starting
796 * at 0 as unset as well, except if PCI_PROBE_ONLY is also set
797 * since in that case, we don't want to re-assign anything
799 pcibios_resource_to_bus(dev
->bus
, ®
, res
);
800 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC
) ||
801 (reg
.start
== 0 && !pci_has_flag(PCI_PROBE_ONLY
))) {
802 /* Only print message if not re-assigning */
803 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC
))
804 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] "
807 (unsigned long long)res
->start
,
808 (unsigned long long)res
->end
,
809 (unsigned int)res
->flags
);
810 res
->end
-= res
->start
;
812 res
->flags
|= IORESOURCE_UNSET
;
816 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n",
818 (unsigned long long)res
->start
,\
819 (unsigned long long)res
->end
,
820 (unsigned int)res
->flags
);
823 /* Call machine specific resource fixup */
824 if (ppc_md
.pcibios_fixup_resources
)
825 ppc_md
.pcibios_fixup_resources(dev
);
827 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID
, PCI_ANY_ID
, pcibios_fixup_resources
);
829 /* This function tries to figure out if a bridge resource has been initialized
830 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
831 * things go more smoothly when it gets it right. It should covers cases such
832 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
834 static int pcibios_uninitialized_bridge_resource(struct pci_bus
*bus
,
835 struct resource
*res
)
837 struct pci_controller
*hose
= pci_bus_to_host(bus
);
838 struct pci_dev
*dev
= bus
->self
;
839 resource_size_t offset
;
840 struct pci_bus_region region
;
844 /* We don't do anything if PCI_PROBE_ONLY is set */
845 if (pci_has_flag(PCI_PROBE_ONLY
))
848 /* Job is a bit different between memory and IO */
849 if (res
->flags
& IORESOURCE_MEM
) {
850 pcibios_resource_to_bus(dev
->bus
, ®ion
, res
);
852 /* If the BAR is non-0 then it's probably been initialized */
853 if (region
.start
!= 0)
856 /* The BAR is 0, let's check if memory decoding is enabled on
857 * the bridge. If not, we consider it unassigned
859 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
860 if ((command
& PCI_COMMAND_MEMORY
) == 0)
863 /* Memory decoding is enabled and the BAR is 0. If any of the bridge
864 * resources covers that starting address (0 then it's good enough for
865 * us for memory space)
867 for (i
= 0; i
< 3; i
++) {
868 if ((hose
->mem_resources
[i
].flags
& IORESOURCE_MEM
) &&
869 hose
->mem_resources
[i
].start
== hose
->mem_offset
[i
])
873 /* Well, it starts at 0 and we know it will collide so we may as
874 * well consider it as unassigned. That covers the Apple case.
878 /* If the BAR is non-0, then we consider it assigned */
879 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
880 if (((res
->start
- offset
) & 0xfffffffful
) != 0)
883 /* Here, we are a bit different than memory as typically IO space
884 * starting at low addresses -is- valid. What we do instead if that
885 * we consider as unassigned anything that doesn't have IO enabled
886 * in the PCI command register, and that's it.
888 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
889 if (command
& PCI_COMMAND_IO
)
892 /* It's starting at 0 and IO is disabled in the bridge, consider
899 /* Fixup resources of a PCI<->PCI bridge */
900 static void pcibios_fixup_bridge(struct pci_bus
*bus
)
902 struct resource
*res
;
905 struct pci_dev
*dev
= bus
->self
;
907 pci_bus_for_each_resource(bus
, res
, i
) {
908 if (!res
|| !res
->flags
)
910 if (i
>= 3 && bus
->self
->transparent
)
913 /* If we're going to reassign everything, we can
914 * shrink the P2P resource to have size as being
915 * of 0 in order to save space.
917 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC
)) {
918 res
->flags
|= IORESOURCE_UNSET
;
924 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x]\n",
926 (unsigned long long)res
->start
,\
927 (unsigned long long)res
->end
,
928 (unsigned int)res
->flags
);
930 /* Try to detect uninitialized P2P bridge resources,
931 * and clear them out so they get re-assigned later
933 if (pcibios_uninitialized_bridge_resource(bus
, res
)) {
935 pr_debug("PCI:%s (unassigned)\n", pci_name(dev
));
940 void pcibios_setup_bus_self(struct pci_bus
*bus
)
942 /* Fix up the bus resources for P2P bridges */
943 if (bus
->self
!= NULL
)
944 pcibios_fixup_bridge(bus
);
946 /* Platform specific bus fixups. This is currently only used
947 * by fsl_pci and I'm hoping to get rid of it at some point
949 if (ppc_md
.pcibios_fixup_bus
)
950 ppc_md
.pcibios_fixup_bus(bus
);
952 /* Setup bus DMA mappings */
953 if (ppc_md
.pci_dma_bus_setup
)
954 ppc_md
.pci_dma_bus_setup(bus
);
957 static void pcibios_setup_device(struct pci_dev
*dev
)
959 /* Fixup NUMA node as it may not be setup yet by the generic
960 * code and is needed by the DMA init
962 set_dev_node(&dev
->dev
, pcibus_to_node(dev
->bus
));
964 /* Hook up default DMA ops */
965 set_dma_ops(&dev
->dev
, pci_dma_ops
);
966 set_dma_offset(&dev
->dev
, PCI_DRAM_OFFSET
);
968 /* Additional platform DMA/iommu setup */
969 if (ppc_md
.pci_dma_dev_setup
)
970 ppc_md
.pci_dma_dev_setup(dev
);
972 /* Read default IRQs and fixup if necessary */
973 pci_read_irq_line(dev
);
974 if (ppc_md
.pci_irq_fixup
)
975 ppc_md
.pci_irq_fixup(dev
);
978 int pcibios_add_device(struct pci_dev
*dev
)
981 * We can only call pcibios_setup_device() after bus setup is complete,
982 * since some of the platform specific DMA setup code depends on it.
984 if (dev
->bus
->is_added
)
985 pcibios_setup_device(dev
);
989 void pcibios_setup_bus_devices(struct pci_bus
*bus
)
993 pr_debug("PCI: Fixup bus devices %d (%s)\n",
994 bus
->number
, bus
->self
? pci_name(bus
->self
) : "PHB");
996 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
997 /* Cardbus can call us to add new devices to a bus, so ignore
998 * those who are already fully discovered
1003 pcibios_setup_device(dev
);
1007 void pcibios_set_master(struct pci_dev
*dev
)
1009 /* No special bus mastering setup handling */
1012 void pcibios_fixup_bus(struct pci_bus
*bus
)
1014 /* When called from the generic PCI probe, read PCI<->PCI bridge
1015 * bases. This is -not- called when generating the PCI tree from
1016 * the OF device-tree.
1018 pci_read_bridge_bases(bus
);
1020 /* Now fixup the bus bus */
1021 pcibios_setup_bus_self(bus
);
1023 /* Now fixup devices on that bus */
1024 pcibios_setup_bus_devices(bus
);
1026 EXPORT_SYMBOL(pcibios_fixup_bus
);
1028 void pci_fixup_cardbus(struct pci_bus
*bus
)
1030 /* Now fixup devices on that bus */
1031 pcibios_setup_bus_devices(bus
);
1035 static int skip_isa_ioresource_align(struct pci_dev
*dev
)
1037 if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN
) &&
1038 !(dev
->bus
->bridge_ctl
& PCI_BRIDGE_CTL_ISA
))
1044 * We need to avoid collisions with `mirrored' VGA ports
1045 * and other strange ISA hardware, so we always want the
1046 * addresses to be allocated in the 0x000-0x0ff region
1049 * Why? Because some silly external IO cards only decode
1050 * the low 10 bits of the IO address. The 0x00-0xff region
1051 * is reserved for motherboard devices that decode all 16
1052 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1053 * but we want to try to avoid allocating at 0x2900-0x2bff
1054 * which might have be mirrored at 0x0100-0x03ff..
1056 resource_size_t
pcibios_align_resource(void *data
, const struct resource
*res
,
1057 resource_size_t size
, resource_size_t align
)
1059 struct pci_dev
*dev
= data
;
1060 resource_size_t start
= res
->start
;
1062 if (res
->flags
& IORESOURCE_IO
) {
1063 if (skip_isa_ioresource_align(dev
))
1066 start
= (start
+ 0x3ff) & ~0x3ff;
1071 EXPORT_SYMBOL(pcibios_align_resource
);
1074 * Reparent resource children of pr that conflict with res
1075 * under res, and make res replace those children.
1077 static int reparent_resources(struct resource
*parent
,
1078 struct resource
*res
)
1080 struct resource
*p
, **pp
;
1081 struct resource
**firstpp
= NULL
;
1083 for (pp
= &parent
->child
; (p
= *pp
) != NULL
; pp
= &p
->sibling
) {
1084 if (p
->end
< res
->start
)
1086 if (res
->end
< p
->start
)
1088 if (p
->start
< res
->start
|| p
->end
> res
->end
)
1089 return -1; /* not completely contained */
1090 if (firstpp
== NULL
)
1093 if (firstpp
== NULL
)
1094 return -1; /* didn't find any conflicting entries? */
1095 res
->parent
= parent
;
1096 res
->child
= *firstpp
;
1100 for (p
= res
->child
; p
!= NULL
; p
= p
->sibling
) {
1102 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
1104 (unsigned long long)p
->start
,
1105 (unsigned long long)p
->end
, res
->name
);
1111 * Handle resources of PCI devices. If the world were perfect, we could
1112 * just allocate all the resource regions and do nothing more. It isn't.
1113 * On the other hand, we cannot just re-allocate all devices, as it would
1114 * require us to know lots of host bridge internals. So we attempt to
1115 * keep as much of the original configuration as possible, but tweak it
1116 * when it's found to be wrong.
1118 * Known BIOS problems we have to work around:
1119 * - I/O or memory regions not configured
1120 * - regions configured, but not enabled in the command register
1121 * - bogus I/O addresses above 64K used
1122 * - expansion ROMs left enabled (this may sound harmless, but given
1123 * the fact the PCI specs explicitly allow address decoders to be
1124 * shared between expansion ROMs and other resource regions, it's
1125 * at least dangerous)
1128 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1129 * This gives us fixed barriers on where we can allocate.
1130 * (2) Allocate resources for all enabled devices. If there is
1131 * a collision, just mark the resource as unallocated. Also
1132 * disable expansion ROMs during this step.
1133 * (3) Try to allocate resources for disabled devices. If the
1134 * resources were assigned correctly, everything goes well,
1135 * if they weren't, they won't disturb allocation of other
1137 * (4) Assign new addresses to resources which were either
1138 * not configured at all or misconfigured. If explicitly
1139 * requested by the user, configure expansion ROM address
1143 void pcibios_allocate_bus_resources(struct pci_bus
*bus
)
1147 struct resource
*res
, *pr
;
1149 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1150 pci_domain_nr(bus
), bus
->number
);
1152 pci_bus_for_each_resource(bus
, res
, i
) {
1153 if (!res
|| !res
->flags
|| res
->start
> res
->end
|| res
->parent
)
1156 /* If the resource was left unset at this point, we clear it */
1157 if (res
->flags
& IORESOURCE_UNSET
)
1158 goto clear_resource
;
1160 if (bus
->parent
== NULL
)
1161 pr
= (res
->flags
& IORESOURCE_IO
) ?
1162 &ioport_resource
: &iomem_resource
;
1164 pr
= pci_find_parent_resource(bus
->self
, res
);
1166 /* this happens when the generic PCI
1167 * code (wrongly) decides that this
1168 * bridge is transparent -- paulus
1174 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx "
1175 "[0x%x], parent %p (%s)\n",
1176 bus
->self
? pci_name(bus
->self
) : "PHB",
1178 (unsigned long long)res
->start
,
1179 (unsigned long long)res
->end
,
1180 (unsigned int)res
->flags
,
1181 pr
, (pr
&& pr
->name
) ? pr
->name
: "nil");
1183 if (pr
&& !(pr
->flags
& IORESOURCE_UNSET
)) {
1184 if (request_resource(pr
, res
) == 0)
1187 * Must be a conflict with an existing entry.
1188 * Move that entry (or entries) under the
1189 * bridge resource and try again.
1191 if (reparent_resources(pr
, res
) == 0)
1194 pr_warning("PCI: Cannot allocate resource region "
1195 "%d of PCI bridge %d, will remap\n", i
, bus
->number
);
1197 /* The resource might be figured out when doing
1198 * reassignment based on the resources required
1199 * by the downstream PCI devices. Here we set
1200 * the size of the resource to be 0 in order to
1208 list_for_each_entry(b
, &bus
->children
, node
)
1209 pcibios_allocate_bus_resources(b
);
1212 static inline void alloc_resource(struct pci_dev
*dev
, int idx
)
1214 struct resource
*pr
, *r
= &dev
->resource
[idx
];
1216 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
1218 (unsigned long long)r
->start
,
1219 (unsigned long long)r
->end
,
1220 (unsigned int)r
->flags
);
1222 pr
= pci_find_parent_resource(dev
, r
);
1223 if (!pr
|| (pr
->flags
& IORESOURCE_UNSET
) ||
1224 request_resource(pr
, r
) < 0) {
1225 printk(KERN_WARNING
"PCI: Cannot allocate resource region %d"
1226 " of device %s, will remap\n", idx
, pci_name(dev
));
1228 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n",
1230 (unsigned long long)pr
->start
,
1231 (unsigned long long)pr
->end
,
1232 (unsigned int)pr
->flags
);
1233 /* We'll assign a new address later */
1234 r
->flags
|= IORESOURCE_UNSET
;
1240 static void __init
pcibios_allocate_resources(int pass
)
1242 struct pci_dev
*dev
= NULL
;
1247 for_each_pci_dev(dev
) {
1248 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
1249 for (idx
= 0; idx
<= PCI_ROM_RESOURCE
; idx
++) {
1250 r
= &dev
->resource
[idx
];
1251 if (r
->parent
) /* Already allocated */
1253 if (!r
->flags
|| (r
->flags
& IORESOURCE_UNSET
))
1254 continue; /* Not assigned at all */
1255 /* We only allocate ROMs on pass 1 just in case they
1256 * have been screwed up by firmware
1258 if (idx
== PCI_ROM_RESOURCE
)
1260 if (r
->flags
& IORESOURCE_IO
)
1261 disabled
= !(command
& PCI_COMMAND_IO
);
1263 disabled
= !(command
& PCI_COMMAND_MEMORY
);
1264 if (pass
== disabled
)
1265 alloc_resource(dev
, idx
);
1269 r
= &dev
->resource
[PCI_ROM_RESOURCE
];
1271 /* Turn the ROM off, leave the resource region,
1272 * but keep it unregistered.
1275 pci_read_config_dword(dev
, dev
->rom_base_reg
, ®
);
1276 if (reg
& PCI_ROM_ADDRESS_ENABLE
) {
1277 pr_debug("PCI: Switching off ROM of %s\n",
1279 r
->flags
&= ~IORESOURCE_ROM_ENABLE
;
1280 pci_write_config_dword(dev
, dev
->rom_base_reg
,
1281 reg
& ~PCI_ROM_ADDRESS_ENABLE
);
1287 static void __init
pcibios_reserve_legacy_regions(struct pci_bus
*bus
)
1289 struct pci_controller
*hose
= pci_bus_to_host(bus
);
1290 resource_size_t offset
;
1291 struct resource
*res
, *pres
;
1294 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus
));
1297 if (!(hose
->io_resource
.flags
& IORESOURCE_IO
))
1299 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
1300 res
= kzalloc(sizeof(struct resource
), GFP_KERNEL
);
1301 BUG_ON(res
== NULL
);
1302 res
->name
= "Legacy IO";
1303 res
->flags
= IORESOURCE_IO
;
1304 res
->start
= offset
;
1305 res
->end
= (offset
+ 0xfff) & 0xfffffffful
;
1306 pr_debug("Candidate legacy IO: %pR\n", res
);
1307 if (request_resource(&hose
->io_resource
, res
)) {
1309 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1310 pci_domain_nr(bus
), bus
->number
, res
);
1315 /* Check for memory */
1316 for (i
= 0; i
< 3; i
++) {
1317 pres
= &hose
->mem_resources
[i
];
1318 offset
= hose
->mem_offset
[i
];
1319 if (!(pres
->flags
& IORESOURCE_MEM
))
1321 pr_debug("hose mem res: %pR\n", pres
);
1322 if ((pres
->start
- offset
) <= 0xa0000 &&
1323 (pres
->end
- offset
) >= 0xbffff)
1328 res
= kzalloc(sizeof(struct resource
), GFP_KERNEL
);
1329 BUG_ON(res
== NULL
);
1330 res
->name
= "Legacy VGA memory";
1331 res
->flags
= IORESOURCE_MEM
;
1332 res
->start
= 0xa0000 + offset
;
1333 res
->end
= 0xbffff + offset
;
1334 pr_debug("Candidate VGA memory: %pR\n", res
);
1335 if (request_resource(pres
, res
)) {
1337 "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1338 pci_domain_nr(bus
), bus
->number
, res
);
1343 void __init
pcibios_resource_survey(void)
1347 /* Allocate and assign resources */
1348 list_for_each_entry(b
, &pci_root_buses
, node
)
1349 pcibios_allocate_bus_resources(b
);
1350 pcibios_allocate_resources(0);
1351 pcibios_allocate_resources(1);
1353 /* Before we start assigning unassigned resource, we try to reserve
1354 * the low IO area and the VGA memory area if they intersect the
1355 * bus available resources to avoid allocating things on top of them
1357 if (!pci_has_flag(PCI_PROBE_ONLY
)) {
1358 list_for_each_entry(b
, &pci_root_buses
, node
)
1359 pcibios_reserve_legacy_regions(b
);
1362 /* Now, if the platform didn't decide to blindly trust the firmware,
1363 * we proceed to assigning things that were left unassigned
1365 if (!pci_has_flag(PCI_PROBE_ONLY
)) {
1366 pr_debug("PCI: Assigning unassigned resources...\n");
1367 pci_assign_unassigned_resources();
1370 /* Call machine dependent fixup */
1371 if (ppc_md
.pcibios_fixup
)
1372 ppc_md
.pcibios_fixup();
1375 /* This is used by the PCI hotplug driver to allocate resource
1376 * of newly plugged busses. We can try to consolidate with the
1377 * rest of the code later, for now, keep it as-is as our main
1378 * resource allocation function doesn't deal with sub-trees yet.
1380 void pcibios_claim_one_bus(struct pci_bus
*bus
)
1382 struct pci_dev
*dev
;
1383 struct pci_bus
*child_bus
;
1385 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1388 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
1389 struct resource
*r
= &dev
->resource
[i
];
1391 if (r
->parent
|| !r
->start
|| !r
->flags
)
1394 pr_debug("PCI: Claiming %s: "
1395 "Resource %d: %016llx..%016llx [%x]\n",
1397 (unsigned long long)r
->start
,
1398 (unsigned long long)r
->end
,
1399 (unsigned int)r
->flags
);
1401 pci_claim_resource(dev
, i
);
1405 list_for_each_entry(child_bus
, &bus
->children
, node
)
1406 pcibios_claim_one_bus(child_bus
);
1410 /* pcibios_finish_adding_to_bus
1412 * This is to be called by the hotplug code after devices have been
1413 * added to a bus, this include calling it for a PHB that is just
1416 void pcibios_finish_adding_to_bus(struct pci_bus
*bus
)
1418 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1419 pci_domain_nr(bus
), bus
->number
);
1421 /* Allocate bus and devices resources */
1422 pcibios_allocate_bus_resources(bus
);
1423 pcibios_claim_one_bus(bus
);
1424 if (!pci_has_flag(PCI_PROBE_ONLY
))
1425 pci_assign_unassigned_bus_resources(bus
);
1428 eeh_add_device_tree_late(bus
);
1430 /* Add new devices to global lists. Register in proc, sysfs. */
1431 pci_bus_add_devices(bus
);
1433 /* sysfs files should only be added after devices are added */
1434 eeh_add_sysfs_files(bus
);
1436 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus
);
1438 int pcibios_enable_device(struct pci_dev
*dev
, int mask
)
1440 if (ppc_md
.pcibios_enable_device_hook
)
1441 if (ppc_md
.pcibios_enable_device_hook(dev
))
1444 return pci_enable_resources(dev
, mask
);
1447 resource_size_t
pcibios_io_space_offset(struct pci_controller
*hose
)
1449 return (unsigned long) hose
->io_base_virt
- _IO_BASE
;
1452 static void pcibios_setup_phb_resources(struct pci_controller
*hose
,
1453 struct list_head
*resources
)
1455 struct resource
*res
;
1456 resource_size_t offset
;
1459 /* Hookup PHB IO resource */
1460 res
= &hose
->io_resource
;
1463 printk(KERN_WARNING
"PCI: I/O resource not set for host"
1464 " bridge %s (domain %d)\n",
1465 hose
->dn
->full_name
, hose
->global_number
);
1467 offset
= pcibios_io_space_offset(hose
);
1469 pr_debug("PCI: PHB IO resource = %08llx-%08llx [%lx] off 0x%08llx\n",
1470 (unsigned long long)res
->start
,
1471 (unsigned long long)res
->end
,
1472 (unsigned long)res
->flags
,
1473 (unsigned long long)offset
);
1474 pci_add_resource_offset(resources
, res
, offset
);
1477 /* Hookup PHB Memory resources */
1478 for (i
= 0; i
< 3; ++i
) {
1479 res
= &hose
->mem_resources
[i
];
1482 printk(KERN_ERR
"PCI: Memory resource 0 not set for "
1483 "host bridge %s (domain %d)\n",
1484 hose
->dn
->full_name
, hose
->global_number
);
1487 offset
= hose
->mem_offset
[i
];
1490 pr_debug("PCI: PHB MEM resource %d = %08llx-%08llx [%lx] off 0x%08llx\n", i
,
1491 (unsigned long long)res
->start
,
1492 (unsigned long long)res
->end
,
1493 (unsigned long)res
->flags
,
1494 (unsigned long long)offset
);
1496 pci_add_resource_offset(resources
, res
, offset
);
1501 * Null PCI config access functions, for the case when we can't
1504 #define NULL_PCI_OP(rw, size, type) \
1506 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1508 return PCIBIOS_DEVICE_NOT_FOUND; \
1512 null_read_config(struct pci_bus
*bus
, unsigned int devfn
, int offset
,
1515 return PCIBIOS_DEVICE_NOT_FOUND
;
1519 null_write_config(struct pci_bus
*bus
, unsigned int devfn
, int offset
,
1522 return PCIBIOS_DEVICE_NOT_FOUND
;
1525 static struct pci_ops null_pci_ops
=
1527 .read
= null_read_config
,
1528 .write
= null_write_config
,
1532 * These functions are used early on before PCI scanning is done
1533 * and all of the pci_dev and pci_bus structures have been created.
1535 static struct pci_bus
*
1536 fake_pci_bus(struct pci_controller
*hose
, int busnr
)
1538 static struct pci_bus bus
;
1541 printk(KERN_ERR
"Can't find hose for PCI bus %d!\n", busnr
);
1545 bus
.ops
= hose
? hose
->ops
: &null_pci_ops
;
1549 #define EARLY_PCI_OP(rw, size, type) \
1550 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1551 int devfn, int offset, type value) \
1553 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1554 devfn, offset, value); \
1557 EARLY_PCI_OP(read
, byte
, u8
*)
1558 EARLY_PCI_OP(read
, word
, u16
*)
1559 EARLY_PCI_OP(read
, dword
, u32
*)
1560 EARLY_PCI_OP(write
, byte
, u8
)
1561 EARLY_PCI_OP(write
, word
, u16
)
1562 EARLY_PCI_OP(write
, dword
, u32
)
1564 extern int pci_bus_find_capability (struct pci_bus
*bus
, unsigned int devfn
, int cap
);
1565 int early_find_capability(struct pci_controller
*hose
, int bus
, int devfn
,
1568 return pci_bus_find_capability(fake_pci_bus(hose
, bus
), devfn
, cap
);
1571 struct device_node
*pcibios_get_phb_of_node(struct pci_bus
*bus
)
1573 struct pci_controller
*hose
= bus
->sysdata
;
1575 return of_node_get(hose
->dn
);
1579 * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus
1580 * @hose: Pointer to the PCI host controller instance structure
1582 void pcibios_scan_phb(struct pci_controller
*hose
)
1584 LIST_HEAD(resources
);
1585 struct pci_bus
*bus
;
1586 struct device_node
*node
= hose
->dn
;
1589 pr_debug("PCI: Scanning PHB %s\n", of_node_full_name(node
));
1591 /* Get some IO space for the new PHB */
1592 pcibios_setup_phb_io_space(hose
);
1594 /* Wire up PHB bus resources */
1595 pcibios_setup_phb_resources(hose
, &resources
);
1597 hose
->busn
.start
= hose
->first_busno
;
1598 hose
->busn
.end
= hose
->last_busno
;
1599 hose
->busn
.flags
= IORESOURCE_BUS
;
1600 pci_add_resource(&resources
, &hose
->busn
);
1602 /* Create an empty bus for the toplevel */
1603 bus
= pci_create_root_bus(hose
->parent
, hose
->first_busno
,
1604 hose
->ops
, hose
, &resources
);
1606 pr_err("Failed to create bus for PCI domain %04x\n",
1607 hose
->global_number
);
1608 pci_free_resource_list(&resources
);
1613 /* Get probe mode and perform scan */
1614 mode
= PCI_PROBE_NORMAL
;
1615 if (node
&& ppc_md
.pci_probe_mode
)
1616 mode
= ppc_md
.pci_probe_mode(bus
);
1617 pr_debug(" probe mode: %d\n", mode
);
1618 if (mode
== PCI_PROBE_DEVTREE
)
1619 of_scan_bus(node
, bus
);
1621 if (mode
== PCI_PROBE_NORMAL
) {
1622 pci_bus_update_busn_res_end(bus
, 255);
1623 hose
->last_busno
= pci_scan_child_bus(bus
);
1624 pci_bus_update_busn_res_end(bus
, hose
->last_busno
);
1627 /* Platform gets a chance to do some global fixups before
1628 * we proceed to resource allocation
1630 if (ppc_md
.pcibios_fixup_phb
)
1631 ppc_md
.pcibios_fixup_phb(hose
);
1633 /* Configure PCI Express settings */
1634 if (bus
&& !pci_has_flag(PCI_PROBE_ONLY
)) {
1635 struct pci_bus
*child
;
1636 list_for_each_entry(child
, &bus
->children
, node
)
1637 pcie_bus_configure_settings(child
);
1641 static void fixup_hide_host_resource_fsl(struct pci_dev
*dev
)
1643 int i
, class = dev
->class >> 8;
1644 /* When configured as agent, programing interface = 1 */
1645 int prog_if
= dev
->class & 0xf;
1647 if ((class == PCI_CLASS_PROCESSOR_POWERPC
||
1648 class == PCI_CLASS_BRIDGE_OTHER
) &&
1649 (dev
->hdr_type
== PCI_HEADER_TYPE_NORMAL
) &&
1651 (dev
->bus
->parent
== NULL
)) {
1652 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
1653 dev
->resource
[i
].start
= 0;
1654 dev
->resource
[i
].end
= 0;
1655 dev
->resource
[i
].flags
= 0;
1659 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA
, PCI_ANY_ID
, fixup_hide_host_resource_fsl
);
1660 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE
, PCI_ANY_ID
, fixup_hide_host_resource_fsl
);
1662 static void fixup_vga(struct pci_dev
*pdev
)
1666 pci_read_config_word(pdev
, PCI_COMMAND
, &cmd
);
1667 if ((cmd
& (PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
)) || !vga_default_device())
1668 vga_set_default_device(pdev
);
1671 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID
, PCI_ANY_ID
,
1672 PCI_CLASS_DISPLAY_VGA
, 8, fixup_vga
);